JP2010114153A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which connects each of laminated memory cells, respectively, with the peripheral circuit. <P>SOLUTION: The nonvolatile semiconductor memory device includes a semiconductor substrate having a memory cell region, and a peripheral circuit region provided contiguously to the memory cell region, a memory cell string having a plurality of memory cells connected in series in the direction perpendicular to the main surface of the semiconductor substrate in the memory cell region, a transfer gate transistor provided in the semiconductor substrate in the peripheral circuit region, and the extension of a first conductive layer becoming the control gate of the memory cell to the peripheral circuit region, i.e. the first interconnect passing above the gate electrode of the transfer gate transistor when viewed from the semiconductor substrate. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  For example, a NAND flash memory using a floating gate as a memory layer, or a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type nonvolatile semiconductor memory device using silicon nitride or the like as a memory layer, in order to increase the memory density It is conceivable to stack the parts. Patent Document 1 discloses a technique related to a stacked nonvolatile semiconductor memory device having a plurality of memory cell strings in which a columnar semiconductor is formed perpendicular to a semiconductor substrate and a plurality of memory cells are connected in series.

In a nonvolatile semiconductor memory device, a control gate of a memory cell is connected to a word line, and this word line is drawn out to a peripheral circuit region and a predetermined operation is performed. The word lines are provided at a density corresponding to the arrangement density of the memory cells. On the other hand, a transfer gate transistor is provided in the peripheral circuit region. Generally, the size of the transfer gate transistor is larger than the distance between word lines. In a stacked nonvolatile semiconductor memory device having a multilayer memory cell, a word line connected to the control gate of each cell is also a multilayer wiring. A technique for connecting each to the transfer transistor in the peripheral circuit region is not known. For this reason, in the prior art, the space between the stacked word lines has to be widened, which has been a factor in hindering the reduction in size and density of the nonvolatile semiconductor memory device.
JP 2007-180389 A

  The present invention provides a nonvolatile semiconductor memory device that allows each of stacked memory cells to be connected to a peripheral circuit.

  According to one embodiment of the present invention, a semiconductor substrate having a memory cell region and a peripheral circuit region provided adjacent to the memory cell region, and a main surface of the semiconductor substrate in the memory cell region A memory cell string having a plurality of memory cells connected in series in the vertical direction; a transfer gate transistor provided on the semiconductor substrate in the peripheral circuit region; and a first conductive layer serving as a control gate of the memory cell. A non-volatile semiconductor memory device comprising: a first wiring that extends to the peripheral circuit region and passes above the gate electrode of the transfer gate transistor as viewed from the semiconductor substrate Is done.

  According to another aspect of the present invention, a semiconductor substrate having a memory cell region and a peripheral circuit region provided adjacent to the memory cell region, and a main surface of the semiconductor substrate in the memory cell region A memory cell string having a plurality of memory cells connected in series in the vertical direction, a transfer gate transistor provided on the semiconductor substrate in the peripheral circuit region, and provided on the semiconductor substrate in the peripheral circuit region. The peripheral circuit region of the conductive layer that extends in a direction non-parallel to the main surface and is electrically connected to the diffusion layer of the transfer gate transistor and the control layer of the memory cell Extending in a first direction parallel to the main surface of the semiconductor substrate in the peripheral circuit region, and extending to the main surface. And a peripheral circuit region wiring that protrudes in a second direction that is non-parallel to the first direction and has a connection portion that is electrically connected to the interlayer connector. A semiconductor memory device is provided.

  According to the present invention, there is provided a nonvolatile semiconductor memory device that enables each of the stacked memory cells to be connected to a peripheral circuit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Further, in the present specification and each drawing, the same reference numerals are given to the same elements as those described above with reference to the previous drawings, and detailed description thereof will be omitted as appropriate.

(First embodiment)
FIG. 1 is a schematic plan view illustrating the configuration of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
2, 3, 4, 5, and 6 are respectively a cross-sectional view taken along line AA ′, a cross-sectional view taken along line BB ′, a cross-sectional view taken along line CC ′, and a line DD ′ in FIG. 1. It is sectional drawing and EE 'line sectional drawing.
FIG. 7 is a schematic perspective view illustrating the configuration of a part of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
As shown in FIG. 1, in the nonvolatile semiconductor memory device 10 according to the first embodiment of the present invention, the semiconductor substrate 110 includes a memory cell region 120 and a peripheral circuit region 130 adjacent to the memory cell region 120. Have.
Here, as shown in FIG. 1, the direction perpendicular to the main surface 111 of the semiconductor substrate 110 is taken as the Z axis and is in a plane perpendicular to the Z axis. A direction in which the memory cells 210 connected by the common word line WL are arranged is an X axis, and a direction perpendicular to the Z axis and the X axis is a Y axis. That is, the X axis and the Y axis are parallel to the main surface 111.

  As shown in FIG. 2, a plurality of memory cells 210 arranged in a direction perpendicular to the main surface 111 of the semiconductor substrate 110 (Z-axis direction) are formed on the semiconductor substrate 110 in the memory cell region 120. Is provided. The memory cells 210 are connected in series in a direction perpendicular to the main surface 111 to form a memory cell string 212. The memory cell 210 includes a semiconductor layer 250 provided on the main surface 111 of the semiconductor substrate 110 and extending in a direction perpendicular to the main surface 111, and an insulating layer 260 adjacent to the semiconductor layer 250. In one memory cell 210, a control gate 220 is provided on the surface of the insulating layer 260 opposite to the semiconductor layer 250. That is, the insulating layer 260 is provided between the semiconductor layer 250 and the control gate 220.

A plurality of control gates 220 are stacked in a direction perpendicular to main surface 111 with an insulating layer (not shown) interposed therebetween.
As described above, the memory cell 210 is formed by being connected in series in a direction perpendicular to the main surface 111.
The control gate 220 is stacked in four layers in the direction perpendicular to the main surface 111 (Z-axis direction), but the number of stacks is arbitrary. That is, the control gate 220 is stacked in a plurality of layers of two or more layers.

For example, an n ⁻ type SOI (Silicon On Insulator) can be used for the semiconductor layer 250, and a three-layered film of SiO ₂ —SiN—AlO can be used for the insulating layer 260, for example. For the control gate 220, for example, n-type polysilicon can be used. However, these materials are examples, and various modifications are possible.

A drain-side selection gate line 370 is provided at the top of the memory cell string 212, and the top of the semiconductor layer 250 is connected to the bit line 380. For example, n-type polysilicon can be used for the drain side select gate line 370, and Cu can be used for the bit line 380, for example. However, these materials are examples, and various modifications are possible. In FIG. 1, the bit line 380 is omitted.
A diffusion layer 331 in the memory cell region is provided at the bottom of the memory cell 212.

  As already described with reference to FIG. 1, a plurality of memory cells 210, that is, memory cell strings 212 are juxtaposed in the X-axis direction. As shown in FIG. 2, in the juxtaposed memory cell strings 212, the conductive layer 230 constituting the control gate 220 of the memory cell 210 at the same distance from the main surface 111 is formed of the same layer. As shown in FIG. 1, the conductive layer 230 constituting each control gate 220 of each memory cell 210 extends in the X-axis direction, and the control gates 220 juxtaposed at the same distance from the main surface 111 are mutually connected. Connected to.

  The conductive layer 230 functions as the word line WL. That is, the word line WL including the conductive layer 230 commonly connects the memory cells 210 formed at the same height from the main surface 111 of the semiconductor substrate 110 in the X-axis direction.

  That is, the word line WL including the conductive layer 230 to be the control gate 220 and extending in the X-axis direction (first direction) is within the plane parallel to the main surface 111 of the semiconductor substrate 110 in the Y-axis direction ( A plurality are arranged in the second direction). Then, the word line WL commonly connects the memory cells 210 formed at the same height from the semiconductor substrate 110. A plurality of memory cell strings 212 are arranged in the X-axis direction. A plurality of groups of memory cell strings 212 connected in common by a common word line WL and arranged in the X-axis direction are juxtaposed at different positions in the Y-axis direction.

  Further, the conductive layer 230 constituting the control gate 220 extends to the peripheral circuit region 130. That is, the word line WL connected to each memory cell 210 extends to the peripheral circuit region 130.

  On the other hand, as shown in FIGS. 1 and 3 to 6, the transfer gate transistor 310 is provided on the main surface 111 of the semiconductor substrate 110 in the peripheral circuit region 130. The transfer gate transistor 310 has a gate electrode 320 and a diffusion layer 330 formed so as to sandwich the gate electrode 320.

  As shown in FIGS. 3 to 6, the gate electrode 320 of the transfer gate transistor 310 is provided closer to the semiconductor substrate 110 than the conductive layer 230 that becomes the control gate 220 of the memory cell 210. Above the gate electrode 320, a first wiring 350, which is an extension portion of the conductive layer (first conductive layer) 230 that becomes the control gate 220 of the memory cell 210 to the peripheral circuit region 130 passes. . Note that the first wiring 350 is a word line WL.

That is, the nonvolatile semiconductor memory device 10 includes a semiconductor substrate 110 having a memory cell region 120 and a peripheral circuit region 130 provided adjacent to the memory cell region 120.
The nonvolatile semiconductor memory device 10 includes a plurality of memory cells 210 provided in the memory cell region 120 of the semiconductor substrate 110 and connected in series in the vertical direction with respect to the main surface 111 of the semiconductor substrate 110. 212 and a transfer gate transistor 310 provided in the peripheral circuit region 130 of the semiconductor substrate 110.
In the nonvolatile semiconductor memory device 10, the conductive layer 230 that becomes the control gate 220 of the memory cell 210 extends to the peripheral circuit region 130, and the upper side of the gate electrode 320 of the transfer gate transistor 310 is viewed from the semiconductor substrate 110. A first wiring 350 passing therethrough is further provided.

That is, the conductive layer 230 that becomes the control gate 220 of the memory cell 210 is the word line WL, and a part of the word line WL passes through the upper side of the gate electrode 320 of the transfer gate transistor 310 as viewed from the semiconductor substrate 110. Wiring 350 is formed.
Note that the conductive layer (second conductive layer) 230 serving as the control gate 220 of the memory cell 210, that is, the other part of the word line WL does not pass over the gate electrode 320. As described above, the other part (second conductive layer) of the word line WL extends to the peripheral circuit region 130, and the extended part does not pass over the gate electrode 320 of the transfer gate transistor 310. Wiring 352 is formed.

  At this time, as shown in FIGS. 1 and 3 to 6, in the peripheral circuit region 130, the space between the word lines WL (first wirings 350) above the gate electrode 320 of the transfer gate transistor 310. Can be set narrowly.

  That is, the distance between the first wirings 350 in the plane parallel to the main surface 111 of the semiconductor substrate 110 above the gate electrode 320 is the distance between the conductive layers 230 in the plane parallel to the main surface 111 in the memory cell region 120. Can be set narrower.

  In addition, above the gate electrode 320 other than the gate electrode 320 on the same X axis, the distance between the second wiring 352 and the first wiring 350 may be set wider than the distance between the first wirings 350. it can.

  As a result, the contact electrode (interlayer connector) 360 and the contact electrode 361 are provided between the word lines WL in a region other than the upper portion of the gate electrode 320, that is, between the first wiring 350 and the second wiring 352. Each of the stacked conductive layers 230 to be the control gates 220 of the stacked memory cells 210 can be easily connected to the peripheral circuit (for example, the transfer gate transistor 310).

  That is, as illustrated in FIG. 3, a contact electrode 361 connected to the diffusion layer 330 of the transfer gate transistor 310 is provided between the stacked first wiring 350 and the stacked second wiring 352. The contact electrode 361 is connected to a part of the upper layer electrode 390, for example. Another part of the upper layer electrode 390 is provided on the lowermost word line WL among the stacked word lines WL (first wiring 350) by another contact electrode (interlayer connection body) 360. Connected to the connecting portion 392. For example, the connection portion 392 includes the conductive layer 230 protruding in the Y-axis direction.

  Then, as shown in FIG. 4, a part of the upper layer electrode 390 connected to the diffusion layer 330 of the transfer gate transistor 310 is connected to the second word line WL (first wiring 350) from the bottom by the contact electrode 360. It is connected to the provided connection portion 392.

  Then, as shown in FIG. 5, a part of the upper layer electrode 390 connected to the diffusion layer 330 of the transfer gate transistor 310 is connected to the third word line WL (first wiring 350) from the bottom by the contact electrode 360. It is connected to the provided connection portion 392.

  Then, as shown in FIG. 6, a part of the upper layer electrode 390 connected to the diffusion layer 330 of the transfer gate transistor 310 is formed by the contact electrode 360, the fourth word line from the bottom (first in this example). It is connected to a connection portion 392 provided in WL (first wiring 350).

Thus, each of the stacked word lines WL (first wiring 350) is electrically connected to the diffusion layer 330. That is, each of the stacked word lines WL (first wiring 350) is connected to the peripheral circuit.
Thus, a plurality of contact electrodes 360 are provided at different positions in a plane parallel to the main surface of the semiconductor substrate 110, and the stacked word lines WL (first wiring 350) are connected to the peripheral circuit. Is done. That is, each of the stacked word lines WL (first wiring 350) has a connecting portion 392 (a protruding portion in which the conductive layer 230 protrudes in the Y-axis direction) provided at a different plane position. In addition, a contact electrode 360 connected to the upper layer electrode 390 is connected.

  In the above description, the contact electrode 360 is connected to the first wiring 350. However, as will be described later, the contact electrode 360 may be connected to the second wiring 352. That is, the contact electrode 360 is connected to at least one of the first wiring 350 and the second wiring 352.

  As described above, in the nonvolatile semiconductor memory device 10, the conductive layer 230 that becomes the control gate 220 of the memory cell 210 extends to the peripheral circuit region 130, and is connected to the first wiring 350 above the gate electrode 320. The distance between the first wiring 350 and the second wiring 352 is larger than the distance between the first wirings 350 in the plane above the gate electrode 320. And an interlayer connection body (contact electrode 360) that extends in a direction non-parallel to the main surface 111 and is connected to at least one of the first wiring 350 and the second wiring 352.

  By repeatedly arranging the word lines WL having such a structure in the Y-axis direction, in the nonvolatile semiconductor memory device 10 having stacked memory cells, the stacked word lines WL are drawn out one by one to the peripheral circuit region. In addition, all the word lines WL can be connected to the transfer gate transistor 310.

  As described above, the nonvolatile semiconductor memory device 10 according to this embodiment can provide a nonvolatile semiconductor memory device with high storage density that enables each of the stacked memory cells to be connected to the peripheral circuit.

  In the nonvolatile semiconductor memory device 10, the extending direction of the word line WL (the first wiring 350 and the second wiring 352) is bent (curved in the Y-axis direction) at the boundary between the memory cell region 120 and the peripheral circuit region 130. The word line WL can bypass the contact electrode 360 and extend in the X-axis direction.

  The first wiring 350 that is part of the word line WL passes above the gate electrode 320 of the transfer gate transistor 310, and the second wiring 352 that is another part of the word line WL is connected to the gate electrode 320. Do not pass above.

  In the nonvolatile semiconductor memory device 10, the word line WL (in this case, for example, the first wiring 350) in which the conductive layer 230 that becomes the control gate 220 of the memory cell 210 extends to the peripheral circuit region 130 is: It passes between the interlayer connectors (in this case, for example, the contact electrodes 360) of the semiconductor substrate 110.

That is, in this example, the contact electrode 360 is not disposed on any of the first wiring 350 and the second wiring 352 which are the word lines WL.
However, the contact electrode 360 is not disposed on all of the first wiring 350 and the second wiring 352, but the contact electrode 360 is at least one of the stacked first wiring 350 and the stacked second wiring 352. It may be arranged on the part. Another part of the first wiring 350 and the second wiring 352 may pass between the contact electrodes 360.

  As illustrated in FIG. 7, the nonvolatile semiconductor memory device 10 according to this embodiment includes a semiconductor substrate 110 including a memory cell region 120 and a peripheral circuit region 130 provided adjacent to the memory cell region 120. A memory cell string 212 having a plurality of memory cells 210 provided in the memory cell region 120 of the semiconductor substrate 110 and connected in series in a direction perpendicular to the main surface 111 of the semiconductor substrate 110, and a peripheral circuit of the semiconductor substrate 110 An interlayer connector (contact electrode 360) provided in region 130, extending in a direction non-parallel to main surface 111 and electrically connected to diffusion layer 330 of transfer gate transistor 310, and memory cell 210 The main surface of the semiconductor substrate 110 is formed of a conductive layer 230 to be the control gate 220, and extends in the first direction (X-axis direction). 11 is a peripheral circuit region wiring having a connection portion 392 that protrudes in a second direction (for example, the Y-axis direction) non-parallel to the first direction in a plane parallel to 11 and is electrically connected to the interlayer connector. A word line WL, that is, at least one of the first wiring 350 and the second wiring 352).

  As described above, the interlayer connection body (contact electrode 360) is connected to the diffusion layer 330 of the transfer gate transistor 310 provided in the peripheral circuit region 130 of the semiconductor substrate 110 by the upper layer electrode 390 and the contact electrode 361. ing.

  By repeatedly arranging the word lines WL having such a structure in the Y-axis direction, in the nonvolatile semiconductor memory device 10 having stacked memory cells, the stacked word lines WL are drawn out one by one to the peripheral circuit region. In addition, all the word lines WL can be connected to the transfer gate transistor 310.

  As described above, the nonvolatile semiconductor memory device 10 according to this embodiment can provide a nonvolatile semiconductor memory device in which each of the stacked memory cells can be connected to the peripheral circuit.

  The contact electrode 361 connected to the transfer gate transistor 310 is further connected to a row decoder (not shown). As illustrated in FIGS. 3 to 6, according to the structure of the nonvolatile semiconductor memory device 10, The contact electrode 361 can be connected to the upper electrode 390 that is higher than the word line WL (further from the main surface 111 of the semiconductor substrate 110 than the word line WL), and the wiring resistance can be reduced.

  Further, as shown in FIGS. 1 and 2, in the memory cell region 120 of the nonvolatile semiconductor memory device 10, the conductive layer 230 that becomes the control gate 220 extends along the extending direction of the conductive layer 230, and the control gate 220. And a silicide portion 240 provided on a side surface opposite to the side.

  As shown in FIGS. 1 and 3 to 6, in the peripheral circuit region 130, the conductive layer 230 serving as the control gate 220 is both along the extending direction (X-axis direction) of the first wiring 350. The silicide portion 240 is provided on the side surface of the substrate.

For example, NiSi _x can be used for these silicide portions 240. In addition, MoSi _x , NbSi _x , TaSi _x , VSi _x , WSi _x , TiSi _x , CoSi _x , PdSi _{x and the} like can also be used.

  Thereby, the resistance of the word line WL (at least one of the first wiring 350 and the second wiring 352) including the conductive layer 230 that becomes the control gate 220 can be lowered.

  In the memory cell region 120, the silicide portion 240 is provided on the side surface opposite to the control gate 220 of the conductive layer 230 to be the control gate 220. In the peripheral circuit region 130, the silicide portion 240 is connected to the control gate 220. The silicide portion 240 having such a structure is formed on the side of the control gate 220 of the conductive layer 230 after forming the memory cell 210 on the side of the conductive layer 230 that extends in the X-axis direction. An insulating layer is provided so as to cover the cell 210, and then the conductive layer 230 is patterned into a strip shape extending in the X-axis direction, and then the side surface of the conductive layer 230 is silicided. Thus, the silicide portion 240 can be provided without adversely affecting the memory cell 210 such as reliability.

  As described above, in the memory cell region 120, the conductive layer 230 that becomes the control gate 220 has the silicide portion 240 provided on the side surface opposite to the control gate 220, and in the peripheral circuit region 130, the control gate 220. The conductive layer 230 to be used employs a structure having the silicide portions 240 on both side surfaces extending in the X-axis direction, whereby the memory cell 210 is highly reliable and can be manufactured by a simple method, and has a low resistance. A nonvolatile semiconductor memory device having the word line WL can be realized.

  However, in some cases, the silicide portion 240 in the memory cell region 120 is not limited to the side surface opposite to the control gate 220 of the conductive layer 230, but may be provided on the side surface of the conductive layer 230 on the same side as the control gate 220. Further, silicide portions 240 may be provided on the side surfaces on both sides of the conductive layer 230. Also in these cases, the resistance of the word line WL made of the conductive layer 230 that becomes the control gate 220 can be lowered.

  Further, in the peripheral circuit region 130, the conductive layer 230 to be the control gate 220 has the silicide portion 240 on both side surfaces extending in the X-axis direction, but one side surface extending in the X-axis direction. May include a silicide portion 240. For example, the conductive layer 230 in the peripheral circuit region 130 may be provided on the side surface opposite to the control gate 220 of the conductive layer 230 that becomes the control gate 220, or the control gate 220 of the conductive layer 230 that becomes the control gate 220. It may be provided on the same side surface. Also in this case, the resistance of the word line WL made of the conductive layer 230 that becomes the control gate 220 can be lowered.

  As shown in FIG. 7, in the nonvolatile semiconductor memory device 10 according to this embodiment, the circuit region wiring (word line WL, that is, at least one of the first wiring 350 and the second wiring 352) is Projecting in a second direction (for example, the Y-axis direction) non-parallel to the first direction (X-axis direction) within a plane parallel to the main surface 111 of the semiconductor substrate 110, the interlayer connector (contact electrode 360) Although each has a connection portion 392 having an independent shape, the shape of the connection portion 392 is arbitrary.

FIG. 8 is a schematic perspective view illustrating the configuration of a part of another nonvolatile semiconductor memory device according to the first embodiment of the invention.
As shown in FIG. 8, in another nonvolatile semiconductor memory device according to the first embodiment of the present invention, the connection portion 392 includes circuit region wirings (word lines WL, that is, the first wiring 350 and the second wirings). The wiring 352 extends on the side surface of the wiring 352 and has a continuous shape extending in the X-axis direction while corresponding to the interlayer connector (contact electrode 360).
Also in this case, a nonvolatile semiconductor memory device that can connect each of the stacked memory cells to a peripheral circuit can be provided.

(Second Embodiment)
FIG. 9 is a schematic plan view illustrating the configuration of the nonvolatile semiconductor memory device according to the second embodiment of the invention.
10, 11, 12, and 13 are a cross-sectional view taken along line BB ′, a cross-sectional view taken along line CC ′, a cross-sectional view taken along line DD ′, and a cross-sectional view taken along line EE ′ of FIG. is there.
As shown in FIGS. 9 to 13, in the nonvolatile semiconductor memory device 20 according to the second embodiment of the present invention, in the peripheral circuit region 130, a word is formed above the gate electrode 320 of the transfer gate transistor 310. The interval between the lines WL (first wiring 350) is set to be narrow, the interval between the second wiring 352 and the first wiring 350 is set to be wider than the interval between the first wirings 350, and the gate electrode 320 is set. A contact electrode (interlayer connection body) 360 is provided between the word lines WL, ie, between the first wiring 350 and the second wiring 352 in a region other than the upper portion of the first wiring 350, and the second wiring 352 is connected to the peripheral circuit. To do.

  In other words, the nonvolatile semiconductor memory device 10 has a structure in which the contact electrode (interlayer connection body) 360 is connected to the first wiring 350 and the first wiring 350 is connected to the peripheral circuit. The semiconductor memory device 20 has a structure in which a contact electrode (interlayer connection body) 360 is connected to a second wiring 352 and the second wiring 352 is connected to a peripheral circuit. Other than this, the configuration is the same as that of the non-volatile semiconductor memory device 10, and a description thereof will be omitted.

  That is, as illustrated in FIG. 10, a contact electrode (interlayer connection body) 361 connected to the diffusion layer 330 of the transfer gate transistor 310 between the stacked first wiring 350 and the stacked second wiring 352. The contact electrode 361 is connected to, for example, a part of the upper layer electrode 390. Another part of the upper layer electrode 390 is provided on the lowermost word line WL among the stacked word lines WL (second wiring 352) by another contact electrode (interlayer connection body) 360. Connected to the connecting portion 392.

  As shown in FIG. 11, a part of the upper layer electrode 390 connected to the diffusion layer 330 of the transfer gate transistor 310 is connected to the second word line WL (second wiring 352) from the bottom by the contact electrode 360. It is connected to the provided connection portion 392.

  Then, as shown in FIG. 12, a part of the upper layer electrode 390 connected to the diffusion layer 330 of the transfer gate transistor 310 is connected to the third word line WL (second wiring 352) from the bottom by the contact electrode 360. It is connected to the provided connection portion 392.

  Then, as shown in FIG. 13, a part of the upper layer electrode 390 connected to the diffusion layer 330 of the transfer gate transistor 310 is the fourth (from the top in this example) word line from the bottom by the contact electrode 360. It is connected to a connection portion 392 provided in WL (second wiring 352).

In this way, each of the stacked word lines WL (second wiring 352) is electrically connected to the diffusion layer 330. That is, each of the stacked word lines WL (second wiring 352) is connected to the peripheral circuit.
As described above, a plurality of contact electrodes 360 are provided at different positions in a plane parallel to the main surface of the semiconductor substrate 110, and all the word lines WL (second wiring 352) of the stacked layers are connected to the peripheral circuit. Connected. That is, each of the stacked word lines WL (second wiring 352) has a connecting portion 392 (a protruding portion in which the conductive layer 230 protrudes in the Y-axis direction, for example) provided at a different plane position. A contact electrode 360 connected to the upper layer electrode 390 is connected to 392.

  Note that the connection portion 392 of the second wiring 352 has the structure illustrated in FIGS. 7 and 8, that is, the first direction (X-axis direction) in a plane parallel to the main surface 111 of the semiconductor substrate 110. Projecting in a second non-parallel direction (for example, the Y-axis direction) and extending to an independent shape corresponding to each of the interlayer connectors (contact electrodes 360) or the side surface of the word line WL (second wiring 352) In addition, it can have a continuous shape extending in the X-axis direction while corresponding to the interlayer connector (contact electrode 360).

  Thus, according to the nonvolatile semiconductor memory device 20 according to the present embodiment, a nonvolatile semiconductor memory device that can connect each of the stacked memory cells to the peripheral circuit can be provided.

(Third embodiment)
FIG. 14 is a schematic plan view illustrating the configuration of the nonvolatile semiconductor memory device according to the third embodiment of the invention.
As shown in FIG. 14, in the nonvolatile semiconductor memory device 30 according to the third embodiment of the present invention, in the peripheral circuit region 130, the word line WL ( The interval between the first wirings 350) is set to be narrow, and the interval between the second wiring 352 and the first wiring 350 is set to be wider than the interval between the first wirings 350. An interlayer connector (contact electrode 360) is provided between the first wiring 350 and the second wiring 352 in a region other than the upper portion of the gate electrode 320 in the same region on the X axis with respect to the gate electrode 320. It has been.
The contact electrode 360 is connected to the connection portion 392 of the second wiring 352 and the upper layer electrode 390, and the upper layer electrode 390 is connected to the diffusion layer 330 of the transfer gate transistor 310 by another contact electrode 361. Thereby, the second wiring 352 is connected to the peripheral circuit (transfer gate transistor 310).

  That is, each of the stacked second wirings 352 has a connecting portion 392 (a protruding portion in which the conductive layer 230 protrudes in the Y-axis direction, for example) provided at a different planar position, and the connecting portion 392 includes an upper layer electrode. The contact electrode 360 connected to 390 is connected, and all the second wirings 352 of the stacked layers are connected to the peripheral circuit.

  Further, in the peripheral circuit region 130, the distance between the first wirings 350 is wider on the peripheral region side in the X-axis direction than the transfer gate transistor 310 (on the side opposite to the memory cell region 120 as viewed from the transfer gate transistor 310). The distance between the second wiring 352 and the first wiring 350 is set to be narrower than the distance between the first wirings 350. An interlayer connection body (contact electrode 360) is provided between the first wirings 350 that are spaced apart from each other. The contact electrode 360 is connected to the connection portion 392 of the first wiring 350 and the upper layer electrode 390, and the upper layer electrode 390 is connected to the diffusion layer 330 of the transfer gate transistor 310 by another contact electrode 361. Thereby, each of the stacked first wirings 350 is connected to the peripheral circuit (transfer gate transistor 310).

  That is, each of the stacked first wirings 350 has a connecting portion 392 (a protruding portion in which the conductive layer 230 protrudes in the Y-axis direction, for example) provided at a different plane position. The contact electrode 360 connected to 390 is connected, and all the first wirings 350 of the stacked layers are connected to the peripheral circuit.

  As described above, the nonvolatile semiconductor memory device 30 has a portion where the distance between the first wirings 350 is narrow, and in this part, the distance between the first wiring 350 and the second wiring is wide. An interlayer connector (contact electrode 360) is provided between the first wiring 350 and the second wiring 352. Further, in another part of the first wiring 350 having a narrow interval between the first wirings 350, there is a part where the first wirings 350 are widely spaced, and an interlayer connection is provided between the first wirings 350. A body (contact electrode 360) is provided.

  This interlayer connection body connects each of the connected first wiring 350 and second wiring 352 to a peripheral circuit. A portion where the distance between the first wirings 350 is narrow passes above the gate electrode 320 of the transfer gate transistor 310.

  As described above, in the nonvolatile semiconductor memory device 30, each of the stacked first wiring 350 and second wiring 352 can be connected to the peripheral circuit. According to the nonvolatile semiconductor memory device 30 according to the present embodiment, a nonvolatile semiconductor memory device that can connect each of the stacked memory cells to a peripheral circuit can be provided.

FIG. 15 is a schematic plan view illustrating the configuration of another nonvolatile semiconductor memory device according to the third embodiment of the invention.
As shown in FIG. 15, in another nonvolatile semiconductor memory device 31 according to the third embodiment of the present invention, in the peripheral circuit region 130, a word line is formed above the gate electrode 320 of the transfer gate transistor 310. An interval between WLs (first wirings 350) is set to be narrow, and an interval between the second wirings 352 and the first wirings 350 is set to be wider than an interval between the first wirings 350. An interlayer connector (contact electrode 360) is provided between the first wiring 350 and the second wiring 352 in a region other than the upper portion of the gate electrode 320 in the same region on the X axis with respect to the gate electrode 320. It has been.
The contact electrode 360 is connected to the connection portion 392 of the first wiring 350 and the upper layer electrode 390, and the upper layer electrode 390 is connected to the diffusion layer 330 of the transfer gate transistor 310 by another contact electrode 361. Thereby, each of the stacked first wirings 350 is connected to the peripheral circuit (transfer gate transistor 310).

  That is, each of the stacked first wirings 350 has a connecting portion 392 (a protruding portion in which the conductive layer 230 protrudes in the Y-axis direction, for example) provided at a different plane position. The contact electrode 360 connected to 390 is connected, and all the first wirings 350 of the stacked layers are connected to the peripheral circuit.

Further, in the peripheral circuit region 130, the second wiring 352 and another wiring 353 are connected on the peripheral region side in the X-axis direction from the transfer gate transistor 310 (on the side opposite to the memory cell region 120 as viewed from the transfer gate transistor 310). The interval between is set wide. In addition, an interlayer connection body (contact electrode 360) is provided in a portion where the distance from another wiring 353 is wide. The contact electrode 360 is connected to the connection portion 392 of the second wiring 352 and the upper layer electrode 390, and the upper layer electrode 390 is connected to the diffusion layer 330 of the transfer gate transistor 310 by another contact electrode 361. Thereby, each of the stacked second wirings 352 is connected to the peripheral circuit (transfer gate transistor 310).
That is, each of the stacked second wirings 352 has a connecting portion 392 (a protruding portion in which the conductive layer 230 protrudes in the Y-axis direction, for example) provided at a different planar position, and the connecting portion 392 includes an upper layer electrode. The contact electrode 360 connected to 390 is connected, and all the second wirings 352 of the stacked layers are connected to the peripheral circuit.

  As described above, the nonvolatile semiconductor memory device 31 has a portion where the distance between the first wiring 350 and the second wiring 352 is wide, and the portion between the first wiring 350 and the second wiring 352 in this portion. On the other hand, there is a portion where the interval between the second wiring 352 and another wiring 353 is wide, and the interlayer connection is provided in this portion.

  This interlayer connection body connects each of the connected first wiring 350 and second wiring 352 to a peripheral circuit. Note that the part where the distance between the first wiring 350 and the second wiring 352 is wide is formed by providing a part where the distance between the first wirings 350 is narrow, and the part where the distance between the first wirings 350 is narrow. Passes over the gate electrode 320 of the transfer gate transistor 310.

  Thus, in the nonvolatile semiconductor memory device 31, each of the stacked first wiring 350 and second wiring 352 can be connected to a peripheral circuit. According to the nonvolatile semiconductor memory device 31 according to the present embodiment, a nonvolatile semiconductor memory device that can connect each of the stacked memory cells to a peripheral circuit can be provided.

FIG. 16 is a schematic plan view illustrating the configuration of another nonvolatile semiconductor memory device according to the third embodiment of the invention.
As shown in FIG. 16, in another nonvolatile semiconductor memory device 32 according to the third embodiment of the present invention, the upper part of the gate electrode 320 of the transfer gate transistor 310 is arranged in the fourth circuit region in the peripheral circuit region 130. One wiring 350 passes.

  That is, in the nonvolatile semiconductor memory device 30 illustrated in FIG. 14, the two first wirings 350 pass over the gate electrode 320 of the transfer gate transistor 310, but in the nonvolatile semiconductor memory device 32, the gate electrode Four first wires 350 pass through the upper portion of 320. Thus, in the present embodiment, the number of word lines WL (first wiring 350) passing through the upper part of the gate electrode 320 is arbitrary.

In the nonvolatile semiconductor memory device 32, the interval between the word lines WL (first wiring 350) is set narrow above the gate electrode 320 of the transfer gate transistor 310, and the second wiring 352 and the first wiring are set. The distance from 350 is set wider than the distance between the first wirings 350. An interlayer connector (contact electrode 360) is provided between the first wiring 350 and the second wiring 352 in a region other than the upper portion of the gate electrode 320 in the same region on the X axis with respect to the gate electrode 320. It has been.
The contact electrode 360 is connected to the two connection portions 352 on the second wiring 352 side of the first wiring 350 and the upper layer electrode 390, and the upper layer electrode 390 is transferred to the transfer gate by another contact electrode 361. The diffusion layer 330 of the transistor 310 is connected.
Thereby, each of the two stacked conductive layers 230 on the second wiring 352 side of the first wiring 350 is connected to the peripheral circuit (transfer gate transistor 310).

  That is, with respect to two of the first wirings 350 on the second wiring 352 side, the stacked first wirings 350 are connected to the connection portions 392 provided at different plane positions (the conductive layer 230 is, for example, in the Y-axis direction). The contact electrode 360 connected to the upper layer electrode 390 is connected to the connection portion 392, and all the first wirings 350 of the stacked layers are connected to the peripheral circuit.

Further, in the peripheral circuit region 130, two on the peripheral region side in the X-axis direction from the transfer gate transistor 310 (on the side opposite to the memory cell region 120 as viewed from the transfer gate transistor 310), which is far from the second wiring 352. The interval between the first wirings 350 is set wide. A contact electrode (interlayer connection body) 360 is provided between the first wirings 350 having a wide interval. The contact electrode 360 is connected to the connection portion 392 of the two first wirings 350 on the side far from the second wiring 352 and the upper layer electrode 390, and the upper layer electrode 390 is connected to the transfer gate by another contact electrode 361. The diffusion layer 330 of the transistor 310 is connected.
As a result, each of the stacked conductive layers 230 to be the two first wirings 350 on the side far from the second wiring 352 is connected to the peripheral circuit (transfer gate transistor 310).

  That is, with respect to the two first wirings 350 on the side far from the second wiring 352, the stacked first wirings 350 are connected to the connection portions 392 (the conductive layer 230 is provided in, for example, the Y-axis direction) provided at different plane positions. The contact electrode 360 connected to the upper layer electrode 390 is connected to the connection portion 392, and all the first wirings 350 of the stacked layers are connected to the peripheral circuit.

  As described above, the nonvolatile semiconductor memory device 32 has a portion where the interval between the first wirings 350 is narrow, and the first wiring 350 and the second wiring 352 are adjacent to this portion in the Y-axis direction. The interval between the first wiring 350 and the second wiring 352 is provided between the first wiring 350 and the second wiring 352. This interlayer connection body connects the second wiring 352 to the peripheral circuit.

  On the other hand, at a position different from the gate electrode 320 of the transfer gate transistor 310 on the X axis, there is a portion where the distance between the first wirings 350 is wide, and an interlayer connection body is provided between the first wirings 350. Yes. This interlayer connection body connects the first wiring 350 to the peripheral circuit.

  A portion where the distance between the first wirings 350 is narrow passes above the gate electrode 320 of the transfer gate transistor 310.

  As described above, in the nonvolatile semiconductor memory device 32, each of the stacked first wirings 350 can be connected to the peripheral circuit. According to the nonvolatile semiconductor memory device 32 according to the present embodiment, a nonvolatile semiconductor memory device that can connect each of the stacked memory cells to a peripheral circuit can be provided.

FIG. 17 is a schematic plan view illustrating the configuration of another nonvolatile semiconductor memory device according to the third embodiment of the invention.
As shown in FIG. 17, in another nonvolatile semiconductor memory device 33 according to the third embodiment of the present invention, four upper portions of the gate electrode 320 of the transfer gate transistor 310 are arranged in the peripheral circuit region 130. One wiring 350 passes.

  In the nonvolatile semiconductor memory device 33, the interval between the word lines WL (first wiring 350) is set narrow above the gate electrode 320 of the transfer gate transistor 310, and the second wiring 352 and the first wiring are set. The distance from 350 is set wider than the distance between the first wirings 350. An interlayer connector (contact electrode 360) is provided between the first wiring 350 and the second wiring 352 in a region other than the upper portion of the gate electrode 320 in the same region on the X axis with respect to the gate electrode 320. It has been.

  The contact electrode 360 is connected to the two connection portions 392 on the second wiring 352 side of the first wiring 350 and the upper layer electrode 390, and the upper layer electrode 390 is transferred to the transfer gate by another contact electrode 361. The diffusion layer 330 of the transistor 310 is connected. Thus, each of the two stacked conductive layers 230 on the second wiring 352 side of the first wiring 350 is connected to the peripheral circuit (transfer gate transistor 310).

Furthermore, in the peripheral circuit region 130, two on the peripheral region side in the Y-axis direction from the transfer gate transistor 310 (on the side opposite to the memory cell region 120 as viewed from the transfer gate transistor 310), which is far from the second wiring 352. The interval between the first wirings 350 is set wide. A contact electrode (interlayer connection body) 360 is provided between the first wirings 350 having a wide interval. The contact electrode 360 is connected to the connection portion 392 of the two first wirings 350 on the side far from the second wiring 352 and the upper layer electrode 390, and the upper layer electrode 390 is connected to the transfer gate by another contact electrode 361. The diffusion layer 330 of the transistor 310 is connected.
As a result, each of the stacked conductive layers 230 to be the two first wirings 350 on the side far from the second wiring 352 is connected to the peripheral circuit (transfer gate transistor 310).

  Further, the first wiring 350 and the second wiring 352 at different positions in the Y direction with respect to the contact electrode 360 that connects the two first wirings 350 on the side far from the second wiring 352 to the peripheral circuit. Another contact electrode 360 is provided therebetween, and this other contact electrode 360 is connected to the second wiring 352. That is, each of the stacked second wirings 352 can be connected to the peripheral circuit.

  Thus, in the nonvolatile semiconductor memory device 33, each of the stacked first wiring 350 and second wiring 352 can be connected to a peripheral circuit. According to the nonvolatile semiconductor memory device 33 according to the present embodiment, a nonvolatile semiconductor memory device that can connect each of the stacked memory cells to a peripheral circuit can be provided.

  As described above, the nonvolatile semiconductor memory device according to the embodiment of the present invention relates to the structure of the stacked nonvolatile semiconductor memory device, and is characterized by the layout of the word line WL on the transfer gate transistor 310. In a nonvolatile semiconductor memory device having stacked memory cells, stacked word lines WL can be drawn out one by one to the peripheral circuit region, and all the word lines WL can be connected to the transfer gate transistor 310. To do.

  In the nonvolatile semiconductor memory devices 10, 20, 30, 31, 32, and 33, all WLs are connected to the same transfer gate transistor 310 for the sake of simplicity. Each WL is connected to an individual transfer gate transistor corresponding to each WL.

FIG. 18 is a schematic plan view illustrating the configuration of the nonvolatile semiconductor memory device 34 according to the embodiment of the invention.
As shown in FIG. 18, in the nonvolatile semiconductor memory device 34 according to the embodiment of the present invention, a part of WL is connected to the transfer gate transistor 320 shown in the figure, and another part of WL is For example, the transfer gate transistor 320 is connected to another transfer gate transistor (not shown) arranged in the positive direction of the X axis. As described above, in the nonvolatile semiconductor memory devices 10, 20, 30, 31, 32, and 33, each WL can be connected to a different transfer gate transistor corresponding to each WL.

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, regarding the specific configuration of each element constituting the nonvolatile semiconductor memory device, as long as a person skilled in the art can implement the present invention in a similar manner by appropriately selecting from a well-known range and obtain the same effect, It is included in the scope of the present invention.

  Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all nonvolatile semiconductor memory devices that can be implemented by a person skilled in the art based on the nonvolatile semiconductor memory device described above as an embodiment of the present invention as appropriate include the gist of the present invention. It belongs to the scope of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

1 is a schematic plan view illustrating the configuration of a nonvolatile semiconductor memory device according to a first embodiment of the invention. FIG. 2 is a cross-sectional view taken along line A-A ′ of FIG. 1. FIG. 2 is a sectional view taken along line B-B ′ of FIG. 1. FIG. 2 is a cross-sectional view taken along line C-C ′ in FIG. 1. FIG. 2 is a sectional view taken along line D-D ′ in FIG. 1. It is the E-E 'sectional view taken on the line of FIG. 1 is a schematic perspective view illustrating the configuration of a part of a nonvolatile semiconductor memory device according to a first embodiment of the invention; FIG. 6 is a schematic perspective view illustrating the configuration of a part of another nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 6 is a schematic plan view illustrating the configuration of a nonvolatile semiconductor memory device according to a second embodiment of the invention. FIG. 10 is a sectional view taken along line B-B ′ of FIG. 9. FIG. 10 is a sectional view taken along line C-C ′ of FIG. 9. FIG. 10 is a sectional view taken along line D-D ′ in FIG. 9. FIG. 10 is a cross-sectional view taken along line E-E ′ of FIG. 9. FIG. 7 is a schematic plan view illustrating the configuration of a nonvolatile semiconductor memory device according to a third embodiment of the invention. FIG. 6 is a schematic plan view illustrating the configuration of another nonvolatile semiconductor memory device according to the third embodiment of the invention. FIG. 6 is a schematic plan view illustrating the configuration of another nonvolatile semiconductor memory device according to the third embodiment of the invention. FIG. 6 is a schematic plan view illustrating the configuration of another nonvolatile semiconductor memory device according to the third embodiment of the invention. 1 is a schematic plan view illustrating the configuration of a nonvolatile semiconductor memory device according to an embodiment of the invention.

Explanation of symbols

10, 20, 30, 31, 32, 33, 34 Nonvolatile semiconductor memory device 110 Semiconductor substrate 111 Main surface 120 Memory cell region 130 Peripheral circuit region 210 Memory cell 212 Memory cell string 220 Control gate 230 Conductive layer 240 Silicide portion 250 Semiconductor Layer 260 Insulating layer 310 Transfer gate transistor 320 Gate electrode 330, 331 Diffusion layer 350 First wiring 352 Second wiring 353 wiring 360 Contact electrode (interlayer connection body)
361 Contact electrode 370 Drain side selection gate line 380 Bit line 390 Upper layer electrode 392 Connection portion WL Word line

Claims (5)

A semiconductor substrate having a memory cell region and a peripheral circuit region provided adjacent to the memory cell region;
A memory cell string having a plurality of memory cells connected in series in a direction perpendicular to the main surface of the semiconductor substrate in the memory cell region;
A transfer gate transistor provided on the semiconductor substrate in the peripheral circuit region;
A first wiring that extends to the peripheral circuit region of the first conductive layer to be a control gate of the memory cell and passes above the gate electrode of the transfer gate transistor as viewed from the semiconductor substrate;
A nonvolatile semiconductor memory device comprising: The second conductive layer serving as a control gate of the memory cell extends to the peripheral circuit region, and the distance between the second conductive layer and the first wiring in the peripheral circuit region is higher than the first of the gate electrode. A second wiring wider than the distance between the wirings;
An interlayer connector that is provided between the first wiring and the second wiring, extends in a direction non-parallel to the main surface, and is connected to at least one of the first wiring and the second wiring. When,
The nonvolatile semiconductor memory device according to claim 1, further comprising:   3. The nonvolatile semiconductor memory device according to claim 1, wherein an interval between the first wirings above the gate electrode is narrower than an interval between the first conductive layers in the memory cell region. The conductive layer in the memory cell region has a silicide portion provided on a side surface opposite to the memory cell,
4. The nonvolatile semiconductor memory device according to claim 1, wherein the first wiring in the peripheral circuit region has a silicide portion provided on both side surfaces. 5. A semiconductor substrate having a memory cell region and a peripheral circuit region provided adjacent to the memory cell region;
A memory cell string having a plurality of memory cells connected in series in a direction perpendicular to the main surface of the semiconductor substrate in the memory cell region;
A transfer gate transistor provided on the semiconductor substrate in the peripheral circuit region;
An interlayer connector provided on the semiconductor substrate in the peripheral circuit region, extending in a direction non-parallel to the main surface, and electrically connected to a diffusion layer of the transfer gate transistor;
A conductive layer serving as a control gate of the memory cell, which extends to the peripheral circuit region, and extends in a first direction parallel to the main surface of the semiconductor substrate in the peripheral circuit region. A peripheral circuit region wiring that has a connection portion that is parallel to the main surface and protrudes in a second direction that is not parallel to the first direction and is electrically connected to the interlayer connector;
A nonvolatile semiconductor memory device comprising:

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