JP2017098356A - Semiconductor module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor module capable of improving a balance of a current flowing to each semiconductor chip and performing a stable operation.SOLUTION: A semiconductor module 1 comprises: a semiconductor chip 3 in which a first electrode (a drain electrode) 50 is formed to a back surface, and in which a plurality of semiconductor chips in which a second electrode (a source electrode)60 and a third electrode (a gate electrode) are formed on a front surface is arranged in a first direction; a ceramic substrate to which first electrode pattern (a drain pattern) 300 and 400 and third electrode patterns (a gate pattern) 301 and 401 are formed in the first direction; a first electrode lead flame 5 which is formed on an upstream of the ceramic substrate 2, and has a first electrode lead out part connected to the first electrode pattern; and a second electrode lead flame 7 which has a beam part formed in the first direction on the upstream of the semiconductor chip, and has a second electrode lead out part to which the second electrode of the plurality of semiconductor chips is connected. The first electrode lead out part and the second electrode lead out part are oppositely arranged while sandwiching the beam part.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor module in which electrodes are formed on both front and back surfaces of a semiconductor chip, the back electrode is directly soldered to a substrate on which a wiring pattern is formed, and the front electrode is soldered to a lead frame.

  A semiconductor module with a structure in which a plurality of semiconductor chips are mounted on a ceramic substrate formed by directly bonding a copper circuit board to a ceramic substrate, and the whole is sealed with a resin, can be reduced in size and heat dissipation. Since it can be used, it is widely used especially in power semiconductor modules.

  For example, as an example of a plurality of semiconductor chips made of IGBTs or FETs used in a semiconductor module, an FET will be described. A drain electrode is formed on the entire back surface of a semiconductor chip, and a source electrode and a gate electrode are formed on the surface. A plurality of drain electrodes on the back surface of the semiconductor chip are directly soldered on the copper circuit pattern of the ceramic substrate, and the source electrode and gate electrode on the surface of each semiconductor chip are provided with input / output terminals drawn to the outside. It is known that a circuit is formed by soldering a lead frame, and a portion excluding the exposed portion of the terminal is sealed with a resin to form a semiconductor module (Patent Document 1).

JP 2013-171870 A

  However, when the capacity is increased by connecting a plurality of semiconductor chips in parallel, since the current flowing between the semiconductor chips is large, the impedance distribution of the current path to each semiconductor chip may be a problem. For example, when three semiconductor chips are connected in parallel to form one switching unit, the current supplied from the drain terminal flows from the drain electrode on the back surface of each semiconductor chip to the source terminal through the source electrode on the front surface. . At this time, if the total lengths of the current paths flowing through the respective semiconductor chips (hereinafter referred to as wiring distances) are different, there is a difference in the magnitude of impedance caused by the length of the wiring distance in the current path of each semiconductor chip. Occurs. If there is a difference in the size of the impedance, for example, the current flowing through a semiconductor chip with a short wiring distance, that is, a small impedance, becomes large, the current balance flowing through the semiconductor chip in one switching unit becomes poor, and the operation becomes unstable. There is a disadvantage that leads to destruction of the semiconductor chip due to current concentration. Even when two semiconductor chips are connected in parallel, the same inconvenience can be considered. However, a converter composed of a plurality of switching units using three semiconductor chips connected in parallel as one switching unit, In a semiconductor module having a large number of semiconductor chips used, such as an inverter, the wiring path is complicated, and therefore a difference in impedance due to a difference in wiring distance is likely to occur. However, in the conventional semiconductor modules, the current balance inside has not been considered.

  The present invention provides a highly reliable semiconductor module that improves the balance of current flowing through each semiconductor chip and enables stable operation when a plurality of semiconductor chips are connected in parallel to form one switching unit. With the goal.

The semiconductor module of the present invention is
A plurality of semiconductors in which an input-side first electrode is formed on the back surface, an output-side second electrode is formed on the surface, and a third electrode for controlling a current between the first electrode and the second electrode is formed on the surface A semiconductor chip array in which chips are arranged in a first direction;
A ceramic substrate in which a first electrode pattern to which the first electrodes of the plurality of semiconductor chips are connected and a third electrode pattern to which the third electrodes of the plurality of semiconductor chips are connected are formed in the first direction. When,
A first electrode lead frame formed above the ceramic substrate and having a first electrode lead portion connected to the first electrode pattern;
A second electrode lead frame having a beam portion formed in the first direction above the semiconductor chip and having a second electrode lead portion to which the second electrodes of the plurality of semiconductor chips are connected;
A first electrode terminal to which the first electrode lead portion is connected;
A second electrode terminal to which the second electrode lead portion is connected;
A third electrode terminal to which the third electrode pattern is connected;
Comprising a semiconductor module section comprising
The first electrode lead portion and the second electrode lead portion face each other across the beam portion, and the first electrode lead frame, the first electrode pattern, and the second electrode lead frame from the first electrode terminal. The wiring distance passing through to the second electrode terminal is the same length in each of the plurality of semiconductor chips.

  In the present invention, the semiconductor chip is typically a MOSFET chip, in which case the first electrode is a drain electrode, the second electrode is a source electrode, and the third electrode is a gate electrode.

  The plurality of semiconductor chips arranged in the first direction on the ceramic substrate have their first electrodes connected to the first electrode pattern on the ceramic substrate, and the second electrodes are formed in the first direction. Connected to the second electrode lead frame including the beam portion. The first electrode terminal is connected to the first electrode lead portion of the first electrode lead frame, and the second electrode terminal is connected to the second electrode lead portion of the second electrode lead frame. The main current is: path of first electrode terminal → first electrode lead frame → first electrode pattern → first electrode of a plurality of semiconductor chips → second electrode of a plurality of semiconductor chips → second electrode lead frame → second electrode terminal It flows in.

  There is an impedance in the path through which the main current flows, and the path is different for each semiconductor chip. In the present invention, the first electrode lead frame including the first electrode lead portion from the first electrode terminal by causing the first electrode lead portion and the second electrode lead portion to face each other across the beam portion; A wiring distance passing through the first electrode pattern and the second electrode lead frame including the second electrode lead portion to the second electrode terminal is set to the same length in each of the plurality of semiconductor chips. To do. By performing such an arrangement, the addition distance between the distance from the first electrode terminal to the semiconductor chip and the distance from the second electrode terminal to the semiconductor chip is the same for each semiconductor chip, and as a result, The magnitudes of the flowing main currents are the same.

  In the present invention, when a plurality of semiconductor chips arranged in a row are connected in parallel to form a semiconductor chip row, the magnitude of the main current flowing through each semiconductor chip can be made the same, so that the current balance is improved and stable. Enable proper operation.

Schematic plan view of a semiconductor module according to an embodiment of the present invention Schematic perspective view of semiconductor module Schematic perspective view of semiconductor module Circuit diagram of semiconductor module Detailed plan view of the first semiconductor module section 1a Partial schematic sectional view of the first semiconductor module part 1a The figure explaining the electric current which flows into the semiconductor chip row | line | column 3 of the 1st semiconductor module part 1a

  FIG. 1 is a schematic plan view of a semiconductor module according to an embodiment of the present invention, FIGS. 2 and 3 are schematic perspective views with different viewing angles, and FIG. 5 is a detailed plan view of a first semiconductor module portion 1a. .

  The semiconductor module 1 includes a first semiconductor module part 1a and a second semiconductor module part 1b (see FIG. 1). The first semiconductor module portion 1 a includes a first semiconductor chip row 3, and the second semiconductor module portion 1 b includes a second semiconductor chip row 4. In FIG. 1, the first semiconductor chip row 3 is disposed in the front, and the second semiconductor chip row 4 is disposed in the rear. The first semiconductor chip row 3 and the second semiconductor chip row 4 have substantially the same configuration, and these semiconductor chip rows 3 and 4 are provided on one ceramic substrate 2 in parallel in the longitudinal direction (first direction). ing.

  The first semiconductor chip row 3 is composed of three MOSFET semiconductor chips 3a, 3b, and 3c arranged in the longitudinal direction (first direction) of the ceramic substrate 2.

  The first semiconductor module unit 1a further includes a drain (first electrode) pattern 300, a gate (third electrode) pattern 301, and a source sense pattern 302 formed on the ceramic substrate 2. The drain (first electrode) pattern 300 corresponds to the first electrode pattern, and the gate pattern 301 corresponds to the third electrode pattern. These patterns 300, 301, and 302 are formed in parallel to the longitudinal direction (first direction) of the ceramic substrate 2 as a whole, and in order from the outside of the substrate 2, the gate pattern 301, the source sense pattern 302, and the drain pattern. The positional relationship is 300.

  Further, the drain pattern 300 is located on the lower surface of the first semiconductor chip row 3, and the drain electrode 30D (see FIG. 6) of the semiconductor chip 3a of the chip row 3 is directly soldered. As will be described later in detail (FIG. 5), the gate electrode 30G and the source sense electrode 30SS of the first semiconductor chip row 3 are soldered to the gate pattern 301 and the source sense pattern 302 by wires.

  The first semiconductor module unit 1 a further includes a first electrode lead frame 5 and a second electrode lead frame 7. The first electrode lead frame 5 includes a drain lead portion (first electrode lead portion) 51 connected to the drain terminal (first electrode terminal) 50, and a first joint portion 52 connected to the drain lead portion 51. . The second electrode lead frame 7 has a source / drain lead portion (second junction) (first electrode lead portion / second electrode lead portion) connected to a source / drain terminal (first electrode terminal / second electrode terminal) 70. ) 71 and a first beam portion 72 connected to the source / drain lead portion 71.

  The drain terminal 50 and the first electrode lead frame 5 constituting the drain lead portion 51 and the first joint portion 52 are formed by bending and cutting a single elongated metal plate. As shown in FIGS. 2 and 3, the shape is such that the end of the drain terminal 50 is cut thinly and bent downward to form a drain lead portion 51. Further, the drain lead portion 51 The first joint portion 52 is formed by bending the tip portion downward. The first joint portion 52 is soldered to the drain pattern 300 formed on the ceramic substrate 2.

  Further, the source / drain terminal 70, the source / drain lead portion 71 constituting the second electrode lead frame 7 and the first beam portion 72 are also formed by bending and cutting one metal plate. The metal plate to be used is an elongated, substantially L-shaped. As shown in FIGS. 2 and 3, the end of the source / drain terminal 70 is bent downward to form the source / drain lead portion 71, and the plate extends perpendicularly from the tip of the source / drain lead portion 71. The first beam portion 72 is formed by bending the portion upward.

  The arrangement of the drain terminal 50 and the source / drain terminal 70 is determined so as to be located on one side of the ceramic substrate 2 (the rear side in FIG. 1).

  The first beam portion 72 is a plate-like frame having a shape standing vertically above the first semiconductor chip row 3, and is directly on the source electrode of each semiconductor chip 3 a, 3 b, 3 c of the semiconductor chip row 3. Soldered.

  With the above configuration, the drain lead portion 51 and the source / drain lead portion 71 are in a positional relationship facing each other with the first beam portion 72 interposed therebetween. With this positional relationship, as will be described later, the drain terminal 50 passes through the first electrode lead frame 5, the drain pattern 300, and the second electrode lead frame 7 to reach the source / drain terminal 70. The wiring distance can be the same length for each of the plurality of semiconductor chips.

  The second semiconductor chip row 4 of the second semiconductor module section 1b is composed of three MOSFET semiconductor chips 4a, 4b, 4c arranged in the longitudinal direction (first direction) of the ceramic substrate 2. The second semiconductor chip row 4 is formed adjacent to the first semiconductor chip row 3 as a whole, and is formed behind the first semiconductor chip row 3 in FIG.

  The second semiconductor module unit 1 b further includes a drain pattern 400 formed on the ceramic substrate 2, a gate pattern 401, and a source sense pattern 402. The drain pattern 400 corresponds to the first electrode pattern, and the gate pattern 401 corresponds to the third electrode pattern. These patterns 400, 401, 402 are formed in parallel to the longitudinal direction (first direction) of the ceramic substrate 2 as a whole, and in order from the rear outside of the substrate 2, the gate pattern 401, the source sense pattern 402, The positional relationship of the drain pattern 400 is obtained.

  The drain pattern 400 is located on the lower surface of the semiconductor chip row 4 and the drain electrode 40D of the chip row 4 is directly soldered. A gate electrode and a source sense electrode of each semiconductor chip are soldered to the gate pattern 401 and the source sense pattern 402 by wires. These soldering structures are the same as those of the semiconductor chip row of the first semiconductor chip row 3.

  The second semiconductor module portion 1b further includes a first electrode lead frame and a second electrode lead frame. The first electrode lead frame has a source / drain lead portion 71 (first electrode lead portion) connected to a source / drain terminal 70 (which serves as both the drain terminal of the second semiconductor module portion 1b and the source terminal of the first semiconductor module portion 1a). (The second joint portion is also used). The second electrode lead frame includes a source lead portion (second electrode lead portion) 61 connected to the source terminal 60 and a second beam portion 62 connected to the source lead portion 61.

  The source lead-out portion 61 is L-shaped when viewed from above, and its front end is connected to the left end portion of the second beam portion 62. Therefore, the source terminal 60 is located at the center of the second beam portion 62 in the first direction.

  The back surface of the source / drain lead portion 71 is directly soldered to the drain pattern 400 formed on the ceramic substrate 2. In this way, the source / drain lead portion 71 also serves as a joint (second joint) for soldering and connecting to the drain pattern 400.

  The arrangement of the source / drain terminal 70 and the source terminal 60 is determined so as to be located on one side of the ceramic substrate 2 (the rear side in FIG. 1).

  With the above configuration, in the second semiconductor module section 1b, the source / drain terminal 70 is the first electrode terminal, the source terminal 60 is the second electrode terminal, the drain pattern 400 is the first electrode pattern, and the gate pattern 401 is the third electrode. Corresponding to the electrode pattern, the first electrode lead frame includes a source / drain lead portion 71 (second junction), and the second electrode lead frame includes a source lead wire 61 and a second beam portion 62.

  Similar to the first semiconductor module portion 1a, the second semiconductor module portion 1b has a positional relationship in which the source / drain lead portion 71 and the source lead portion 61 face each other across the second beam portion 62. With such a positional relationship, as will be described later, the source / drain terminal 70 passes through the source / drain lead portion 71, the drain pattern 400, the second beam portion 62, and the source lead portion 61, thereby supplying the source. The wiring distance to the terminal 60 can be set to the same length in each of the plurality of semiconductor chips.

  As can be seen from FIG. 3, the second beam portion 62 of the second semiconductor chip row 4 is a plate-like frame that is erected on the front side of the substrate above the semiconductor chip row, and the source of each semiconductor chip. Soldered directly to the electrode. The second beam portion 62 is connected to the front end of the L-shaped source lead portion 61 in the vicinity of the left end portion of the semiconductor chip row. The source terminal 60, the source lead wire 61, and the second beam portion 62 are formed by appropriately cutting and bending a single metal plate.

  Since the second beam portion 62 is inclined and erected on the front side of the substrate, the second beam portion 62 is close to the first beam portion 72 of the first semiconductor chip row 3. The reason for this structure will be described later.

  As described above, each of the first semiconductor chip row 3 and the second semiconductor chip row 4 is arranged in the first direction which is the longitudinal direction of the ceramic substrate 2, and three semiconductors constituting each chip row Since the chip is connected to a common drain pattern and a common beam portion, a plurality of semiconductor chips in each semiconductor chip row are connected in parallel. The source / drain terminal 70 is a common (shared) terminal that serves as both the source terminal of the first semiconductor chip row 3 and the drain terminal of the second semiconductor chip row 4. As a result, the semiconductor module has a circuit configuration as shown in FIG.

  In FIG. 4, the first semiconductor chip row 3 is composed of three MOSFET semiconductor chips 3a, 3b, and 3c, and the second semiconductor chip row 4 is composed of three MOSFET semiconductor chips 4a, 4b, and 4c. In addition, the drain terminal 50 and the source / drain terminal 70 of the first semiconductor chip row 3, and the source / drain terminal 70 and the source terminal 60 of the second semiconductor chip row 4 are shown. The source / drain terminal 70 is used as a shared terminal for the source terminal of the first semiconductor chip row 3 and the drain terminal of the second semiconductor chip row 4. The semiconductor module having such a circuit configuration is used in a control method for alternately turning on and off the first semiconductor chip row 3 and the second semiconductor chip row 4.

  Next, a detailed configuration of the first semiconductor chip row 3 will be described with reference to FIG. As described above, the first semiconductor chip row 3 includes the three semiconductor chips 3a, 3b, and 3c. Since each semiconductor chip has the same configuration, only the semiconductor chip 3a will be described below. .

  The semiconductor chip 3a has a source electrode 30S, a gate electrode 30G, and a source sense electrode 30SS formed on the surface thereof. The source electrode 30S is formed in two places with a relatively large area, and the source electrode 30S is directly soldered to a leg portion 73a formed at the end of the first beam portion 72. The gate electrode 30G is soldered and connected to the gate pattern 301 with a wire, and the source sense electrode 30SS connected in the chip so as to be electrically at the same potential as the source electrode 30S is soldered to the source sense pattern 302 with a wire. Are connected.

  The gate pattern 301 is formed on the outermost front side of the substrate 2 in parallel with the first direction, and is bent vertically rearward in the vicinity of the left end portion of the substrate to form an end portion. Thus, the gate terminal 80 is soldered and connected.

  The source sense pattern 302 is formed along the pattern 301 inside the gate pattern 301. The source sense pattern 302 is arranged inside the gate pattern 301 and inside the drain pattern 300. The potential of the source sense pattern 302 is the same as the potential of the source electrode 30S that is the reference potential. Therefore, the source sense pattern 302 exhibits a shielding effect with respect to the drain pattern 300.

  Next, a semiconductor chip soldering structure will be described.

  FIG. 6 is a partial cross-sectional view of the semiconductor chip 3a in the first direction.

  A drain pattern 300 is formed on the ceramic substrate 2, and a drain electrode 30 </ b> D on the back surface of the semiconductor chip 3 a is soldered thereon with a solder 31. Further, the two source electrodes 30S and 30S on the surface of the semiconductor chip 3a are soldered to the first beam portion 72 with solders 32 and 32, respectively. The same applies to the other semiconductor chips 3b and 3c, and also to the respective semiconductor chips 4a, 4b and 4c of the semiconductor chip row 4 of the second semiconductor module section 1b, and the description thereof will be omitted.

  In the semiconductor module having the above-described configuration, the first semiconductor switch row 3 is turned on at the first timing to cause the main current to flow, and the first semiconductor switch row 3 is turned off at the next second timing, instead of the second semiconductor switch row. Row 4 is turned on to pass the main current. Repeat this cycle.

  FIG. 7 is a diagram for explaining the current flowing through each of the semiconductor chips 3a, 3b, 3c in the first semiconductor switch array 3, and is a schematic diagram when the configuration of FIG. 5 is viewed from the path through which the main current flows. . The same applies to the second semiconductor switch row 4.

When the first semiconductor switch row 3 is on, the main current I is supplied from the drain terminal 50 to the semiconductor chips 3a, 3b, and 3c, but the distance X1 from the drain terminal 50 to the semiconductor chip 3a, and from the drain terminal 50 The relationship between the distance X2 to the semiconductor chip 3b and the distance X3 from the drain terminal 50 to the semiconductor chip 3c is as follows:
X1 <X2 <X3
It is.

On the other hand, the relationship between the distance Y1 from the source / drain terminal 70 to the semiconductor chip 3a, the distance Y2 from the source / drain terminal 70 to the semiconductor chip 3b, and the distance Y3 from the source / drain terminal 70 to the semiconductor chip 3c is
Y1>Y2> Y3
It is.

Therefore,
X1 + Y1 = X2 + Y2 = X3 + Y3
It has become a relationship.

  As described above, even if there is a difference in current path (wiring distance) between each semiconductor chip 3a, 3b, 3c and the drain terminal 50 or between each semiconductor chip 3a, 3b, 3c and the source / drain terminal 70, the drain terminal Since the distance between 50 and the source / drain terminal 70 is the same for each chip, the magnitude of the main current flowing for each chip is also the same. For this reason, the balance of the current flowing through each semiconductor chip is improved.

  Further, as shown in FIG. 3, in the second semiconductor module portion 1b, the second beam portion 62 is erected and inclined to the front side of the substrate, and the second beam portion 62 is the first beam of the first semiconductor module portion 1a. The structure is close to the portion 72. For this reason, the inductance inside the semiconductor module unit 1 is reduced, and an abnormal voltage during high-speed switching can be suppressed.

  Further, the gate pattern 301 is formed on the outermost side of the ceramic substrate 2, the source sense pattern 302 is formed on the inner side, and the drain pattern 300 on which the main current flows is formed on the inner side. If so, the source sense pattern 302 acts as a shield against the drain pattern 300 having a large current change, and the current change flowing through the drain pattern 300 can be prevented from acting on the gate pattern 301. The same applies to the second semiconductor module 1b.

  Further, as shown in FIG. 6, each semiconductor chip has double-sided soldering in which the drain electrode 30D and the source electrode 30S formed on the front and back surfaces thereof are directly soldered to the drain pattern 300 and the first beam portion 72, respectively. With this structure, it is possible to improve the reliability of the semiconductor module, promote compactness, and increase heat dissipation.

  Further, since all of the terminals 50, 60, and 70 are arranged on the rear side of the substrate 2, electrical connection with an external circuit is easy, and the module device can be easily manufactured and made compact.

1-semiconductor module 1a-first semiconductor module part 1b-second semiconductor module part 2-ceramic substrate 3-first semiconductor chip row 4-second semiconductor chip row 5-first electrode lead frame 7-second electrode lead frame 300, 400-Drain (first electrode) pattern 301, 401-Gate (third electrode) pattern 302, 402-Source sense pattern 50-Drain (first electrode) terminal 60-Source (second electrode) terminal

Claims (6)

A plurality of semiconductors in which an input-side first electrode is formed on the back surface, an output-side second electrode is formed on the surface, and a third electrode for controlling a current between the first electrode and the second electrode is formed on the surface A semiconductor chip array in which chips are arranged in a first direction;
A ceramic substrate in which a first electrode pattern to which the first electrodes of the plurality of semiconductor chips are connected and a third electrode pattern to which the third electrodes of the plurality of semiconductor chips are connected are formed in the first direction. When,
A first electrode lead frame formed above the ceramic substrate and having a first electrode lead portion connected to the first electrode pattern;
A second electrode lead frame having a beam portion formed in the first direction above the semiconductor chip and a second electrode lead portion to which the second electrodes of the plurality of semiconductor chips are connected;
A first electrode terminal to which the first electrode lead portion is connected;
A second electrode terminal to which the second electrode lead portion is connected;
A third electrode terminal to which the third electrode pattern is connected;
Comprising a semiconductor module section comprising
The first electrode lead portion and the second electrode lead portion face each other across the beam portion, pass through the first electrode lead frame and the first electrode pattern from the first electrode terminal, and further, the second electrode lead A semiconductor module, wherein a wiring distance passing through a frame and reaching the second electrode terminal has the same length in each of the plurality of semiconductor chips.   The semiconductor module according to claim 1, wherein the third electrode pattern is formed on the outermost side of the ceramic substrate.   The plurality of semiconductor chips have sense electrodes on their surfaces, and the ceramic substrate has a sense electrode pattern formed at the same potential as the second electrode between the first electrode pattern and the third electrode pattern. The semiconductor module according to claim 2.   The semiconductor module unit includes a first semiconductor module unit and a second semiconductor module unit each having a configuration of the semiconductor module unit, and a semiconductor chip row of the first semiconductor module unit and a semiconductor chip of the second semiconductor module unit The semiconductor module according to claim 1, wherein the rows are arranged in parallel on the ceramic substrate.   The semiconductor module according to claim 4, wherein the second electrode terminal of the first semiconductor module unit is used as the first electrode terminal of the second semiconductor module unit.   The semiconductor module according to claim 1, wherein the first electrode is a drain electrode, the second electrode is a source electrode, and the third electrode is a gate electrode.

Images