JP2017092308A - Wiring forming method and wiring structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of wiring by depositing Cu only in an opening for wiring formation while improving adhesiveness of the wiring and a resin film.SOLUTION: A sulfur compound is deposited on a resin film and in a region where wiring is formed on the resin film with the sulfur compound deposited thereon, a mask layer including a first opening is formed. While covering the mask layer, a first metal film containing Cu and a second metal film is laminated successively and on the resin film with which the first metal film and the second metal film have been formed, heat treatment is performed under an oxygen containing atmosphere. A surface of the second metal film is oxidized and Cu in a part of the first metal film that is formed on the sulfur compound is floated on the second metal film that is formed on the bottom of the first opening. Electric plating treatment is implemented with Cu that is floated on the bottom of the first opening defined as an electrode, wiring is formed in the first opening and after the wiring is formed, the second metal film and the first metal film that are formed on a surface of the mask layer are removed.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a wiring formation method and a wiring structure.

  A semi-additive method and a damascene method are known as methods for forming wiring on a printed circuit board or an interposer. In the semi-additive method, after a seed layer (conductive thin film) is formed on an electrically insulating substrate, a photoresist is selectively formed in a region where no wiring is formed, and the seed layer is not covered with the photoresist. In addition, it is a method of forming wiring by electroplating or the like. In the semi-additive method, after the wiring is formed by electroplating or the like, the seed layer not covered with the wiring is removed by an etching process or the like.

  In the damascene method, after a photoresist is selectively formed on a substrate, a seed layer is formed on the photoresist, and metal is deposited by electroplating or the like until it completely covers the opening of the photoresist. Thereafter, the metal is shaved by CMP (Chemical Mechanical Polishing) until the photoresist is exposed to form wiring.

  When wiring is formed on a resin substrate using the semi-additive method, a seed layer is formed using palladium sulfide or the like, and the surface of the resin substrate is dissolved after the electroplating process. A method for removing the layer has been proposed (see, for example, Patent Document 1). Moreover, when forming a glass epoxy board | substrate etc., the method of laminating resin in the atmosphere containing sulfur trioxide is proposed (for example, refer patent document 2). Furthermore, in the case of forming a wiring on a substrate using the damascene method, a method of forming a wiring without leaving the photoresist as an insulating layer by removing the photoresist after the CMP process has been proposed (for example, And Patent Document 3).

JP-A-10-22612 JP 62-114294 A JP 2009-117438 A

  In the damascene method in which the seed layer is formed on the photoresist, the excess seed layer is removed together with the metal covering the upper portion of the opening of the photoresist by the CMP process, so that the process for removing the seed layer is not provided. However, CMP is performed until a photoresist (resin) having a lower rigidity than silicon or the like is exposed. For this reason, when the photoresist bends due to the stress applied to the photoresist by CMP, there is a possibility that a short circuit or disconnection of the wiring may occur. For example, when the wiring width and the wiring interval are 2 μm (microns) or less and a stress that causes scratches is applied to the surface of the photoresist, the wiring is likely to be short-circuited or disconnected.

  On the other hand, in the semi-additive method in which the seed layer is formed before forming the photoresist, a part of the wiring is cut and thinned by the process of removing the seed layer not covered with the wiring. The influence of the wiring cut when removing the seed layer becomes larger as the wiring becomes finer.

  In one aspect, the wiring forming method and wiring structure disclosed in the present disclosure improve the adhesion between the wiring and the resin film, and deposit Cu only in the opening for forming the wiring, thereby improving the reliability of the wiring. The purpose is to improve.

  According to one aspect, a wiring forming method includes a step of attaching a sulfur compound on a resin film, and a mask having a first opening in a region where the wiring is formed on the resin film to which the sulfur compound is attached. A step of forming a layer, a step of sequentially stacking a first metal film containing Cu and a second metal film covering the mask layer, and a first metal film and a second metal film are formed. The resin film is heat-treated in an atmosphere containing oxygen to oxidize the surface of the second metal film, and to remove Cu from the first metal film formed on the sulfur compound in the first opening. A step of floating on the second metal film formed on the bottom, a step of forming a wiring in the first opening by performing an electroplating process using Cu floating on the bottom of the first opening as an electrode, and After forming the wiring, the second metal film formed on the surface of the mask layer and the first And a step of removing the metal film.

  According to another aspect, the wiring structure includes a wiring including Cu provided on the resin film, a layer including S sequentially stacked between the resin film and the wiring, and a first metal film including Cu. A second metal film is provided between the wiring and the first metal film and on the side wall of the wiring.

  The wiring forming method and wiring structure disclosed in the present disclosure can improve the reliability of wiring by improving the adhesion between the wiring and the resin film and by depositing Cu only in the opening for forming the wiring. it can.

It is a figure which shows one Embodiment of the formation method and wiring structure of wiring. It is a figure which shows the continuation of FIG. FIG. 3 is a diagram showing a continuation of FIG. 2. It is a figure which shows the cross-section of the bottom of the opening part before and behind the heat processing shown to FIG. 2 (A). It is a figure which shows an example of the wiring for evaluation used for evaluation of the adhesiveness of the wiring shown in FIG. It is a figure which shows the evaluation result of the adhesiveness of the wiring using the wiring for evaluation shown in FIG. It is a figure which shows an example of the sample for measuring peel strength. It is a figure which shows the measurement result of the peel strength using the sample shown in FIG. It is a figure which shows an example of the process of forming wiring by a semi-additive method. It is a figure which shows an example of the process of forming wiring by a damascene method. It is a figure which shows another example of the process of forming wiring by a damascene method. It is a figure which shows an example of the electronic device containing the wiring structure formed in another embodiment of the formation method of wiring. It is a figure which shows an example of the formation method of the chip package board | substrate containing the interposer shown in FIG. It is a figure which shows the continuation of FIG. It is a figure which shows the continuation of FIG. It is a figure which shows the continuation of FIG. It is a figure which shows the continuation of FIG. It is a figure which shows the continuation of FIG. It is a figure which shows the continuation of FIG. FIG. 20 is a diagram showing a continuation of FIG. 19. It is a figure which shows the continuation of FIG. It is a figure which shows another example of an electronic device. It is a figure which shows another example of an electronic device. It is a figure which shows another example of an electronic device. It is a figure which shows another example of an electronic device. It is a figure which shows another example of an electronic device. It is a figure which shows another example of an electronic device.

  Hereinafter, embodiments will be described with reference to the drawings.

  1 to 3 show an embodiment of a wiring formation method and a wiring structure. 1 to 3 are sectional views showing a manufacturing process for forming a wiring in a wiring layer for rewiring provided on a chip package substrate, a multichip package, and the like. For example, the wiring layer for rewiring is used for mutually connecting an LSI chip and a substrate such as a mother board, or is used for mutually connecting a plurality of LSI chips. A substrate including a wiring layer for rewiring is also referred to as an interposer. In FIG. 1 and other drawings, the thickness and aspect ratio of each element are different from the thickness and aspect ratio of elements formed on an actual substrate.

  First, in FIG. 1A, a sulfur compound 12 is attached on a resin film 10 such as polyimide or phenol resin. For example, thiol compounds such as triazine thiols are used as the sulfur compound 12. The sulfur compound 12 is deposited on the resin film 10 by immersing the resin film 10 in an aqueous solution of 0.01 wt% to 4.0 wt% (weight percent concentration) of the thiol compound for a predetermined time (1 to 10 minutes). Done in Alternatively, the sulfur compound 12 is attached to the resin film 10 by spraying an aqueous solution of a thiol compound on the resin film 10. The resin film 10 to which the sulfur compound 12 is attached is lightly washed and then dried.

  Next, in FIG. 1B, a mask layer 16 having an opening 14 in a region where a wiring is to be formed is formed on the resin film 10 coated with the sulfur compound 12 by using a photolithography method. For example, after forming a photoresist 18 on the resin film 10, the mask layer 16 selectively irradiates the photoresist 18 with light using a photomask (exposure), and the photoresist 18 positioned in the opening 14 is removed. It is formed by removing by development. For example, a TMAH (Tetramethyl Ammonium Hydroxide) solution is used as the developer. In this example, the aspect ratio (ratio between the depth and the inner diameter (depth / inner diameter)) of the opening 14 is set to approximately “1”, but should be set between “1” and “3”. Is desirable. The photoresist 18 may be formed by applying a liquid photoresist onto the resin film 10, or may be formed by applying a film-like photoresist to the resin film 10.

  Next, in FIG. 1C, a first metal film 20 (hereinafter referred to as Cu film 20) containing Cu (copper) covering the photoresist 18 on the resin film 10 on which the mask layer 16 is formed; And a second metal film 22 containing Ni (nickel) (hereinafter referred to as Ni film 22). The Cu film 20 is formed with a thickness of 20 nm to 100 nm, and the Ni film 22 is formed with a thickness of 20 nm to 100 nm. The Cu film 20 and the Ni film 22 are formed by sputtering, but may be formed by electroless plating. Note that the second metal film 22 may be formed of a metal containing Co (cobalt) or Sn (tin).

  Next, in FIG. 2A, atmospheric annealing is performed in which the resin film 10 on which the Cu film 20 and the Ni film 22 are formed is heat-treated in an atmosphere containing oxygen. Atmospheric annealing is performed at 150 ° C. for about 10 to 60 minutes, for example. Note that when the atmospheric annealing is performed at a low temperature of about 80 ° C., the annealing time may exceed 60 minutes.

  By the atmospheric annealing, the Ni film 22 is oxidized, and an oxide film 22a is formed on the surface, which is electrically insulated. However, at the bottom of the opening 14, due to the interaction between the atmospheric annealing and the sulfur compound 12, a part of Cu 20 a of the Cu film 20 penetrates the Ni film 22 and is exposed to the surface of the Ni film 22. That is, Cu 20 a contained in the Cu film 20 floats on the Ni film 22 at the bottom of the opening 14. The Ni film 22 at the bottom of the opening 14 oxidized by the atmospheric annealing is destroyed by the rising of the Cu 20a. Further, since Cu 20a constantly floats on the Ni film 22, the surface of Cu 20a is not covered with the oxide film. Therefore, the Ni film 22 at the bottom of the opening 14 and the Cu 20a floating on the Ni film 22 maintain conductivity, and function as a seed layer in the subsequent electroplating process.

  Note that the Cu 20a is lifted onto the Ni film 22 at a place where the Cu film 20 and the sulfur compound 12 are in contact with each other. For this reason, the Ni film 22 located on the side wall of the opening 14 and the surface of the photoresist 18 does not raise Cu, and the electrical insulation by the Ni oxide film 22a is maintained. Accordingly, the mask layer 16 is formed on the resin film 10 to which the sulfur compound 12 is adhered, and the seed layer is exposed only at the bottom of the opening 14 by performing atmospheric annealing after forming the Cu film 20 and the Ni film 22. Can be made. As a result, Cu can be deposited locally only in the opening 14 by electroplating, and the CMP process can be omitted.

  Furthermore, the resin film 10 at the bottom of the opening 14, the sulfur compound 12, and the Cu film 20 react with each other and are firmly adhered by atmospheric annealing. Thereby, the adhesiveness of the wiring 24 and the resin film 10 which are subsequently formed in the opening 14 can be improved as compared with the case where the sulfur compound 12 is not attached.

  Next, in FIG. 2B, electroplating is performed using Cu floating on the bottom of the opening 14 as an electrode (seed layer), and Cu is deposited inside the opening 14. That is, the wiring 24 is formed inside the opening 14.

  For example, the wiring 24 is a signal wiring through which a signal is transmitted and extends in the depth direction of FIG. 2, and is the ratio of the width (L) of the wiring 24 and the interval (S) between the wirings 24 adjacent to each other. The line L / space S is 2 μm / 2 μm. In this case, the electroplating process is performed so that the height of Cu embedded in the opening 14 is in the range of 2 μm to 2.5 μm. In other words, in order to prevent Cu from protruding from the opening 14, the height of the photoresist 18 is set to be higher than the height of Cu deposited by plating. The line L / space S of the wiring 24 may be 1 μm / 1 μm or 3 μm / 3 μm.

  The electroplating process is performed by immersing the resin film 10 shown in FIG. 2A in an electrolytic solution that is an aqueous solution of sulfuric acid and copper sulfate, and energizing the Cu film 20 and the Ni film 22. The seed layer (Cu film 20 + Ni film 22) other than the bottom of the opening 14 is electrically insulated from the electrolytic solution for plating by the Ni oxide film 22a. For this reason, Cu is not deposited on the seed layer (Cu film 20 + Ni film 22) other than the bottom of the opening 14. As a result, the electroplating process is completed before Cu protrudes from the opening 14, and as described above, after forming the wiring 24, a process of removing excess Cu other than the wiring 24 by CMP or the like. Can be omitted.

  Next, in FIG. 2C, the Ni film 22 (including the oxide film 22a) exposed on the surface of the mask layer 16 and the Cu film 20 are sequentially removed. The Ni film 22 is removed by wet etching using a mixed solution of phosphoric acid, sulfuric acid, and nitric acid. The Cu film 20 is removed by wet etching using any one of potassium persulfate, potassium sulfate, or sulfuric acid perwater. Since the wiring 24 having the same amount as the etching amount of the Cu film 20 is etched, the wiring 24 is formed with a thickness in consideration of the etching amount.

  The removal of the Ni film 22 and the Cu film 20 is performed not by a physical process such as CMP but by a chemical process. Since the CMP process can be omitted, the photoresist 18 can be prevented from being bent by the stress applied to the photoresist 18 by CMP, and the wiring 24 can be prevented from being bent together with the photoresist 18 to be short-circuited or disconnected. Can do. That is, the reliability of the wiring 24 can be improved. Further, since the Cu film 20 functioning as the seed layer is removed in a state where the wiring 24 is covered inside the opening 14 of the photoresist 18, the side wall of the wiring 24 is scraped when the Cu film 20 is removed. There is nothing. For this reason, it is possible to prevent the wiring 24 from being thinned by removing the Cu film 20. Furthermore, since the Ni film 22 and the Cu film 20 are removed by simple chemical treatment compared with CMP, the manufacturing cost can be reduced.

  Next, in FIG. 3A, a NiP film 26 (P is phosphorus) is formed on the surface of the wiring 24 formed in the opening 14. For example, the NiP film 26 is formed by an electroless plating method. Note that, on the surface of the wiring 24, instead of the NiP film 26, a Ni film, a NiB film (B is boron), a NiWP film (W is tungsten), a NiWB film, a CoP film, a CoP film, a CoB film, a CoWP film, or A CoWB film may be formed. Furthermore, instead of the NiP film 26, a NiCoWP film, a NiCoWB film, a NiCoP film, or a NiCoB film may be formed on the surface of the wiring 24. 3A, since the periphery of the wiring 24 is covered with a so-called metal barrier, the reliability of the wiring 24 can be improved as compared with the case where it is not covered with a metal barrier. Note that the step of FIG. 3B may be performed after the step of FIG. 2C without covering the surface of the wiring 24 with a barrier such as NiP.

  Next, in FIG. 3B, the photoresist 18 is removed. For removing the photoresist 18, a stripping solution such as NMP (N-methylpyrrolidone) is used. Here, since the wiring 24 and the resin film 10 are firmly bonded via the sulfur compound 12 by the atmospheric annealing performed in FIG. 2A, the photoresist 18 is removed from the resin film 10. The wiring 24 can be prevented from peeling off. That is, the reliability of the wiring 24 is ensured.

  Next, in FIG. 3C, the Cu film 20 formed around the side wall of the wiring 24 is removed by wet etching using any of potassium persulfate, potassium sulfate, or sulfuric acid perwater. Then, a wiring structure in which a metal barrier of Ni and NiP is provided around the wiring 24 and the bottom of the wiring 24 is in close contact with the resin film 10 via the Ni film 22, the Cu film 20, and the sulfur compound 12 is completed. Note that the wiring structure may be completed with the Cu film 20 left around the side wall of the wiring 24. Further, although the electrical characteristics of the wiring 24 are not affected, the wiring structure shown in FIG. 3C has a Ni oxide film 22 a at the interface between the side wall of the wiring 24 and the Ni film 22.

  Thereafter, a resin film such as polyimide or phenol resin is formed on the resin film 10 so as to cover the wiring 24. When the next wiring layer is formed on the wiring layer including the wiring 24, a photosensitive resin film is formed on the resin film 10.

  FIG. 4 shows a cross-sectional structure (electron micrograph) of the bottom of the opening 14 before and after the heat treatment shown in FIG. 4A and 4B show cross-sectional structures before and after heat treatment when the sulfur compound 12 is deposited on the resin film 10. 4C and 4D are cross sections before and after heat treatment when the steps of FIGS. 1B to 1C are performed without attaching the sulfur compound 12 on the resin film 10. The structure is shown.

  When the sulfur compound 12 is deposited on the resin film 10, it can be seen that a part of Cu 20 a of the Cu film 20 penetrates the Ni film 22 and is exposed to the surface of the Ni film 22. On the other hand, when the sulfur compound 12 is not deposited on the resin film 10, the Cu 20 a is not exposed on the surface of the Ni film 22. In this case, the surface of the Ni film 22 is oxidized.

  FIG. 5 shows an example of the evaluation wiring EW used for evaluating the adhesion of the wiring 24 shown in FIG. In FIG. 5, the process shown in FIGS. 1 to 3 and the process of forming a conventional wiring structure are performed, and each has four types of lines L / spaces S (hereinafter referred to as L / S). The evaluation wiring EW having a shape was produced. Each evaluation wiring EW is formed so that ten wirings having a length L of 1000 μm are engaged with each other. Note that in the process of forming the conventional wiring structure, the sulfur compound shown in FIG. 1A is not attached to the resin film. In FIG. 1C, the Ti (titanium) film and the Cu film are sequentially exposed. It is laminated on the resist. Further, the heat treatment shown in FIG.

  FIG. 6 shows the evaluation results of the adhesion of the wiring 24 using the evaluation wiring EW shown in FIG. In the wiring structure shown in FIG. 3C, no peeling of the wiring occurred when the L / S was “5 μm / 5 μm”, “3 μm / 3 μm”, “2 μm / 2 μm”, or “1 μm / 1 μm”. . On the other hand, in the conventional wiring structure, when L / S is “3 μm / 3 μm”, two wires are peeled off, and when L / S is “2 μm / 2 μm”, ten wires are peeled off, and L When / S was “1 μm / 1 μm”, 19 wires were peeled off. Wiring peeling occurs when the photoresist 18 shown in FIG. 3B is removed. As described above, the wiring structure shown in FIG. 3C is superior in adhesion to the conventional wiring structure particularly when L / S is “2 μm / 2 μm” and “1 μm / 1 μm”.

  FIG. 7 shows an example of a sample for measuring peel strength. FIG. 7 shows a cross-sectional structure of the sample. In the measurement of peel strength, a sample in which a laminated structure simulating the wiring portion shown in FIG. 3C and a laminated structure simulating the wiring portion of the conventional wiring structure is formed on a substrate such as a glass epoxy substrate is used. It was done.

  The stacked structure illustrated in FIG. 3C is formed using a process similar to the process illustrated in FIGS. However, the step of forming the mask layer 16 with the photoresist 18 shown in FIG. 1B is omitted, and the heat treatment shown in FIG. 2A is performed on the first group of samples, and is performed on the second group of samples. Not. When the stacked structure shown in FIG. 3C is formed, for example, a resin is applied to a thickness of 5 μm on a substrate, and an aqueous solution of a sulfur compound such as triazine thiols is applied by spraying or the like. Thereafter, Cu (50 nm) and Ni (100 nm) are formed by sputtering, respectively, and further Cu having a thickness of 20 μm is formed by electroplating or the like.

  On the other hand, when forming a conventional laminated structure, for example, a resin is applied on a substrate to a thickness of 5 μm, Ni (100 nm) is formed by sputtering, and further, Cu having a thickness of 20 μm is formed by electroplating or the like. Is done.

  The peel strength is obtained by picking the end of the laminated film (two or three layers formed on the resin) indicated by arrows in FIG. 7 with a clip or the like and pulling the picked laminated film perpendicular to the surface of the substrate. Measured.

  FIG. 8 shows the measurement results of peel strength using the sample shown in FIG. As a result of the measurement, the peel strength of the first group in which the heat treatment of FIG. 2A was performed in the stacked structure of FIG. 3C was 0.4 kgf / cm. In contrast, in the laminated structure of FIG. 3C, the peel strength of the second group that does not perform the heat treatment of FIG. 2A and the peel strength of the conventional laminated structure are both less than 0.1 kgf / cm. Met. In FIG. 7, the same measurement results as in FIG. 8 were obtained even in the sample in which NiP was formed instead of Ni. Thus, also in the measurement of peel strength, it was found that the wiring structure shown in FIG. 3C is superior in adhesion compared to the conventional wiring structure.

  FIG. 9 shows an example of a process for forming a wiring by a semi-additive method. First, in FIG. 9A, a metal film 2 such as Ti (hereinafter referred to as Ti film 2) and a metal film 3 such as Cu (hereinafter referred to as Cu film 3) are sequentially formed on the resin film 1 by sputtering or the like. It is formed. The Ti film 2 and the Cu film 3 function as seed layers in the electroplating process. Next, in FIG. 9B, using a photolithography method, a photoresist 4 is formed on the resin film 1 on which the Ti film 2 and the Cu film 3 are formed, except for a region for forming a wiring. .

  Next, in FIG. 9C, electroplating is performed using the seed layer (Ti film 2 and Cu film 3) exposed in the opening of the photoresist 4 as an electrode, and Cu is deposited inside the opening. . That is, the wiring 5 is formed inside the opening. Next, in FIG. 9D, after the photoresist 4 is removed, in FIG. 9E, the Cu film 3 and the Ti film 2 that are not covered with the wiring 5 are removed by wet etching or the like.

  Next, in FIG. 9F, a metal film 6 such as NiP (hereinafter referred to as NiP film 6) is formed on the wiring 5 and the periphery of the Cu wiring 5 is covered with a Ti film and a NiP film (metal barrier). Is called. Next, in FIG. 9G, the resin film 7 is formed on the wiring 5 covered with the metal barrier, and the wiring structure is completed.

  The electron microscope photograph of the wiring 5 produced using the process shown in FIG. 9 is shown in the lower left of FIG. When the wiring 5 is formed on the resin film 1 by the semi-additive method, as shown in the electron micrograph, if a gap is generated between the resin film 1 and the Ti film 2, the adhesion between the resin film 1 and the wiring 5 is achieved. However, there is a possibility that it may become weaker than when the wiring 5 is formed on an inorganic material.

  FIG. 10 shows an example of a process for forming wiring by the damascene method. The same elements as those in FIG. 9 are denoted by the same reference numerals, and detailed description thereof is omitted. First, in FIG. 10A, a photoresist 8 is formed in a region on the resin film 1 excluding a region where a wiring is formed, using a photolithography method. The photoresist 8 is a so-called permanent resist and remains in the completed wiring structure. Next, in FIG. 10B, a Ti film 2 and a Cu film 3 are sequentially stacked on the photoresist 8 by sputtering or the like. The Ti film 2 and the Cu film 3 function as seed layers in the electroplating process.

  Next, in FIG. 10C, electroplating is performed using the seed layer (Ti film 2 and Cu film 3) as electrodes, and Cu is deposited in the openings of the photoresist 8 and on the top of the photoresist 8. Next, in FIG. 10D, a CMP process is performed, Cu is scraped until the upper surface of the photoresist 4 is exposed, and the wiring 5 is formed. Next, in FIG. 10E, a NiP film 6 is formed on the wiring 5 and the periphery of the Cu wiring 5 is covered with the Ti film 2 and the NiP film 6 (metal barrier). Next, in FIG. 10F, the resin film 7 is formed on the wiring 5 covered with the metal barrier, and the wiring structure is completed.

  The lower right of FIG. 10 shows an optical micrograph of a sample in which a plurality of wires having L / S of 1 μm / 1 μm are produced using the process shown in FIG. In the process shown in FIG. 10, since the photoresist 8 used to form the wiring 5 is not removed after the CMP, the adhesion between the resin film 1 and the wiring 5 is higher than that of the wiring structure shown in FIG. . However, as shown in the optical micrograph, when stress that causes scratches (scratches) is applied to the photoresist 8 by the CMP process, the wiring 5 may bend together with the photoresist 8, and the adjacent wiring 5 may be short-circuited. There is. Since the abrasive grains used for CMP are harder than the photoresist 8 which is a resin material, scratches are likely to occur.

  FIG. 11 shows another example of a process for forming a wiring by the damascene method. The same elements as those in FIGS. 9 and 10 are denoted by the same reference numerals, and detailed description thereof is omitted. In the step shown in FIG. 11, the photoresist 4 removed after the formation of the wiring 5 is used instead of the photoresist 8 (permanent resist) used in the step shown in FIG.

  The process shown in FIGS. 11A to 11E is the same as the process shown in FIGS. 10A to 10E except that the photoresist 4 is used instead of the photoresist 8. is there. In FIG. 11F, the photoresist 4 is removed, and the wiring 5 covered with the metal barrier is exposed on the resin film 1. Next, in FIG. 11G, the resin film 7 is formed on the wiring 5 covered with the metal barrier, and the wiring structure is completed.

  An optical micrograph of a sample in which a plurality of wirings having L / S of 1 μm / 1 μm are produced using the steps shown in FIGS. 11A to 11F is shown in the lower right of FIG. In the wiring formation method shown in FIG. 11, the adhesion between the wiring 5 and the resin film 1 is weaker than that of the wiring structure shown in FIG. 3C, so that the photoresist 4 is removed as shown in the optical micrograph. At times, the wiring 5 may be peeled off from the resin film 1. In the optical micrograph, a plurality of straight lines extending in the vertical direction in FIG. 11 are traces of the wiring 5 formed on the resin film 1.

  As described above, in the embodiment shown in FIGS. 1 to 8, the adhesion between the wiring 24 formed in the opening 14 and the resin film 10 is improved as compared with the case where the sulfur compound 12 is not attached on the resin film 10. Can do. In addition, the mask layer 16 is formed on the resin film 10 to which the sulfur compound 12 is adhered, and the seed layer is exposed only at the bottom of the opening 14 by performing atmospheric annealing after the Cu film 20 and the Ni film 22 are formed. Can be made. As a result, Cu can be deposited locally only in the opening 14 by electroplating, and the CMP process can be omitted.

  Since the CMP process can be omitted, it is possible to prevent the photoresist 18 from being bent due to the stress applied to the photoresist 18 by CMP. Therefore, it is possible to prevent the wiring 24 from being bent together with the photoresist 18 to be short-circuited or disconnected, and the reliability of the wiring 24 can be improved as compared with the wiring structures of FIGS. 9 to 11. Further, the Cu film 20 functioning as a seed layer is removed in a state where the wiring 24 is covered inside the opening 14 of the photoresist 18. For this reason, the side wall of the wiring 24 is not scraped when the Cu film 20 is removed, and the wiring 24 can be prevented from being thinned by the removal of the Cu film 20. As described above, Cu is deposited only in the opening 14 for forming the wiring 24 while improving the adhesion between the wiring 24 and the resin film 10, so that the wiring 24 can be compared with the wiring structures of FIGS. 9 to 11. Reliability can be improved. Furthermore, since the Ni film 22 and the Cu film 20 are removed by simple chemical treatment compared to CMP, the manufacturing cost can be reduced compared to the case where CMP is performed.

  FIG. 12 shows an example of an electronic device including a wiring structure formed in another embodiment of a wiring forming method. Elements that are the same as or similar to those described in the embodiment shown in FIGS. 1 to 8 are given the same reference numerals, and detailed descriptions thereof are omitted. FIG. 12 shows a cross section of the electronic device. The electronic device 100 shown in FIG. 12 is formed by connecting a plurality of LSI (Large Scale Integration) chips 110 a and 110 b and a mother board (printed circuit board) 120 to each other via an interposer 130 and a package substrate 140. The interposer 130 includes a substrate 150 that secures the rigidity of the interposer 130 and has a connection interface with the package substrate 140, and a rewiring layer 160. In the example shown in FIG. 12, the substrate 150 and the rewiring layer 160 are each formed using a resin as a base material.

  The pads 111a of the LSI chip 110a are connected to electrodes formed on the surface of the rewiring layer 160 on the LSI chip 110a side via bumps BP1a (so-called micro bumps). The pad 111b of the LSI chip 110b is connected to an electrode formed on the surface of the rewiring layer 160 on the LSI chip 110b side via the bump BP1b. A gap between the LSI chips 110a and 110b and the rewiring layer 160 is filled with an underfill agent UF1 (sealing resin).

  In the example shown in FIG. 12, the rewiring layer 160 has a wiring layer W1 (electrode layer E1) in which electrodes connected to the electrodes of the substrate 150 are formed and signal wiring and power supply wiring are formed. The wiring layer W1 and the electrode layer E1 may be formed using different layers. The rewiring layer 160 is provided between the electrode layer E2 on which the electrodes connected to the pads 111a and 111b of the LSI chips 110a and 110b are formed, and between the wiring layer W1 and the electrode layer E2. And a wiring layer W2 formed thereon.

  The rewiring layer 160 and the substrate 150 are connected via electrodes facing each other. The electrode on the package substrate 140 side of the substrate 150 is connected to the electrode of the package substrate 140 via the bump BP2. A gap between the substrate 150 and the package substrate 140 is filled with an underfill agent UF2. The electrode on the motherboard 120 side of the package substrate 140 is connected to the terminal TM of the motherboard 120 via the bump BP3. The gap between the package substrate 140 and the motherboard 120 is filled with an underfill agent UF3.

  The structure in which the LSI chips 110a and 110b, the interposer 130, and the package substrate 140 are connected to each other is also referred to as a chip package substrate. 12, the structure in which the LSI chips 110a and 110b are two-dimensionally arranged on the interposer 130 and the interposer 130 and the package substrate 140 are independent from each other is also referred to as 2.5D-IC (Integrated Circuit). Is done. Furthermore, when the base material of the board | substrate 150 is resin, it is also called 2.3D-IC.

  13 to 21 show an example of a method for forming a chip package substrate including the interposer 130 shown in FIG. That is, FIG. 13 to FIG. 21 show another embodiment of a method for forming a wiring. The same elements as those in FIGS. 1 to 3 are denoted by the same reference numerals, and detailed description of the same steps is omitted.

  First, in FIG. 13A, a plurality of openings 30a are formed at intervals in a plate-like base material 30 such as Si (silicon), glass, or resin. For example, the inner diameter of the opening 30a is 90 μm, and the depth of the opening 30a is 100 μm to 150 μm. The opening 30a is formed using a dry etching method or the like.

  Next, in FIG. 13B, a Ti film 32 (for example, a thickness of 30 nm) and a Cu film 34 (for example, a thickness of 100 nm) are sequentially formed on the surface of the base material 30 and the opening 30a by sputtering or the like. The The Ti film 32 and the Cu film 34 function as seed layers in the electroplating process. Next, in FIG. 13C, electroplating is performed using the seed layer as an electrode, and Cu 36 is deposited in the opening 30 a and on the surface of the substrate 30.

  Next, in FIG. 13D, a CMP process or a grinding process is performed, and the Cu 36 is shaved until the upper surface of the substrate 30 is exposed. Next, in FIG. 13E, until the Cu 36 is exposed on the lower surface of the base material 30, the back surface side of the base material 30 is subjected to CMP treatment or grinding treatment, and is covered with the metal barrier of the Ti film 32. A structure in which the column of Cu 36 penetrates from the front surface to the back surface of the base material 30 is formed. For example, the thickness of the base material 30 is 100 μm. Note that the structure illustrated in FIG. 13D may be formed using another method. Next, in FIG. 13F, a Ti film 32 (for example, a thickness of 20 nm) and a Cu film 34 (for example, a thickness of 100 nm) are sequentially formed on the surface of the substrate 30.

  Next, in FIG. 14A, a photosensitive material having an opening 18a at a position corresponding to a pillar of Cu 36 on the base material 30 on which the Ti film 32 and the Cu film 34 are formed by using a photolithography method. A photoresist 18 is formed. For example, the photoresist 18 is applied to a thickness of 10 μm, and the inner diameter of the opening 18a is 200 μm.

  Next, in FIG. 14B, electroplating is performed using the seed layer (Ti film 32 and Cu film 34) exposed to the opening 18a as an electrode, and Cu 34 is deposited inside the opening 18a. For example, the thickness of Cu 34 inside the opening 18a is 5 μm. Next, in FIG. 14C, the photoresist 18 is removed.

  Next, in FIG. 14D, a photoresist 18 having openings 18b at positions corresponding to the columns of Cu 36 on both the left and right sides on the base material 30 is formed by photolithography. For example, the photoresist 18 is applied to a thickness of 10 μm, and the inner diameter of the opening 18b is 50 μm. Next, in FIG. 14E, electroplating is performed using the seed layer (Cu film 34) exposed in the opening 18b as an electrode, and new Cu 34 is deposited in the opening 18b, for example, 6 μm. . As a result, the thickness of the Cu 34 inside the opening 18b becomes 11 μm.

Next, in FIG. 15A, the photoresist 18 is removed. Next, in FIG. 15B, the Cu film 34 and the Ti film 32 functioning as a seed layer are sequentially removed. The Cu film 34 is removed by wet etching using any one of potassium persulfate, potassium sulfate, or sulfuric acid perwater. The Ti film 32 is removed by wet etching using ammonium fluoride or by dry etching using a mixed gas of CF ₄ (carbon tetrafluoride) and O ₂ (oxygen).

  Next, in FIG. 15C, the resin film 10 is formed on the resin film 30 so as to cover the Cu film 34. For example, the resin film 10 is formed to a thickness of 11 μm by spin-coating polyimide or phenol resin. Next, in FIG. 15D, the CMP process is performed, and the resin film 10 is scraped until the left and right Cu films 34 on the base material 30 are exposed. For example, the CMP process is performed using a slurry containing alumina abrasive grains. Then, the substrate 150 shown in FIG. 12 is completed.

  Next, in FIG. 15E, the sulfur compound 12 is attached on the resin film 10 as in FIG. For example, thiol compounds such as triazine thiols are used as the sulfur compound 12. Next, in FIG. 15F, as in FIG. 1B, a photoresist 18 having an opening 18c in a region where a wiring is to be formed is applied with the sulfur compound 12 using a photolithography method. It is formed on the resin film 10. That is, using the photoresist 18, a mask layer having an opening 18c in a region where wiring is to be formed is formed on the resin film 10 to which the sulfur compound 12 is applied. For example, the photoresist 18 is formed with a thickness of 3 μm.

  Next, in FIG. 16A, similarly to FIG. 1C, a Cu film 20 having a thickness of 20 nm to 100 nm and a thickness of 20 nm to 100 nm are covered with the photoresist 18 on the resin film 10. The Ni film 22 is sequentially stacked. Next, in FIG. 16B, as in FIG. 2A, atmospheric annealing is performed in which the resin film 10 on which the Cu film 20 and the Ni film 22 are formed is heat-treated in an atmosphere containing oxygen. By the atmospheric annealing, the surface of the Ni film 22 is oxidized to form an oxide film 22a (FIG. 2), which is electrically insulated. However, at the bottom of the opening 18c, a portion of the Cu 20a of the Cu film 20 penetrates the Ni film 22 and is exposed to the surface of the Ni film 22 by atmospheric annealing. The Ni film 22 at the bottom of the opening 18c and the Cu 20a floating on the Ni film 22 maintain conductivity and function as a seed layer in the subsequent processing. By the atmospheric annealing, the resin film 10, the sulfur compound 12 and the Cu film 20 at the bottom of the opening 18c react with each other and are firmly adhered to each other.

  Next, in FIG. 16C, similarly to FIG. 2B, electroplating is performed using Cu floating on the bottom of the opening 18c as an electrode (seed layer), and Cu is formed inside the opening 18c. It is deposited. That is, the wiring 24 is formed inside the opening 18c. For example, the line L / space S of the wiring 24 is 2 μm / 2 μm, and the electroplating process is performed so that the height of Cu embedded in the opening 18 c is in the range of 2 μm to 2.5 μm. .

  Next, in FIG. 16D, as in FIG. 2C, the Ni film 22 and the Cu film 20 formed on the photoresist 18 are sequentially removed by wet etching or the like. Next, in FIG. 16E, a NiP film 26 is formed on the surface of the wiring 24 formed in the opening 18c, as in FIG. 3A. Note that the step of FIG. 17A may be performed after the step of FIG. 16D without covering the surface of the wiring 24 with a barrier such as NiP.

  Next, in FIG. 17A, the photoresist 18 is removed as in FIG. Next, in FIG. 17B, as in FIG. 3C, the Cu film 20 formed around the side wall of the wiring 24 is removed by wet etching or the like. Then, a wiring structure in which a metal barrier of Ni and NiP is provided around the wiring 24 and the bottom of the wiring 24 is in close contact with the resin film 10 via the Ni film 22, the Cu film 20, and the sulfur compound 12 is completed.

  Next, in FIG. 17C, a new photosensitive resin film 10 (permanent resist) such as polyimide or phenol resin is formed on the resin film 10 so as to cover the wiring 24 including the metal barrier. Next, in FIG. 17D, exposure processing and development processing of the resin film 10 are performed using a photolithography method, and an opening 10a is formed in a region in the resin film 10 where a through hole connected to the wiring 24 is formed. Is formed. Next, in FIG. 17 (E), the sulfur compound 12 is deposited on the resin film 10 as in FIGS. 1 (A) and 15 (E). The sulfur compound 12 is performed by immersing the resin film 10 in an aqueous solution of a thiol compound, or by spraying an aqueous solution of a thiol compound on the resin film 10. Thereby, the sulfur compound 12 adheres also to the inside of the opening part 10a.

  Next, in FIG. 18 (A), as in FIGS. 1 (B) and 15 (F), a photoresist 18 having an opening 18d in a region where a wiring is formed is applied to a resin in which a sulfur compound 12 is applied. It is formed on the film 10. That is, using the photoresist 18, a mask layer having an opening 18d in a region where wiring is to be formed is formed on the resin film 10 to which the sulfur compound 12 is applied. Next, in FIG. 18B, as in FIGS. 1C and 16A, the Cu film 20 and the Ni film 22 are sequentially stacked on the resin film 10 so as to cover the photoresist 18. The The Cu film 20 and the Ni film 22 are formed not only inside the opening 18d but also inside the opening 10a.

  Next, in FIG. 18C, similarly to FIGS. 2A and 16B, atmospheric annealing is performed, and an oxide film 22a (FIG. 2) is formed on the surface of the Ni film 22. In addition, at the bottom of the opening 18 d and the inner surface of the opening 10 a, a part of the Cu film 20 penetrates the Ni film 22 and is exposed to the surface of the Ni film 22. In FIG. 18C, it appears that the opening 10a formed in FIG. 17D is filled with Cu 20a, but in reality, Cu 20a is exposed on the inner surface of the opening 10a. Further, by the atmospheric annealing, the resin film 10, the sulfur compound 12, and the Cu film 20 react with each other at the bottom of the opening 18 d and are firmly adhered to each other, and the resin film 10, the sulfur compound 12, and the like are formed on the inner surface of the opening 10 a. The Cu film 20 reacts with each other and adheres firmly.

  Next, in FIG. 18 (D), similarly to FIGS. 2 (B) and 16 (C), an electroplating process is performed using Cu floating inside the openings 18d and 10a as an electrode (seed layer), Cu is deposited inside the openings 18c and 10a, and the wiring 24 is formed. For example, the line L / space S of the wiring 24 is 2 μm / 2 μm. In FIG. 18D, the left and right wirings 24 extend in the depth direction of FIG. 18D, and the central wiring 24 extends in the left and right direction of FIG.

  Next, in FIG. 19A, as in FIGS. 2C and 16D, the Ni film 22 and the Cu film 20 formed on the photoresist 18 are sequentially removed by wet etching or the like. The Next, similarly to FIGS. 3A and 16E, the NiP film 26 is formed on the surface of the wiring 24 formed in the opening 18d.

  Next, in FIG. 19B, the photoresist 18 is removed as in FIGS. 3B and 17A, and the wiring 24 is removed as in FIGS. 3C and 17B. The Cu film 20 formed around the side wall is removed. Next, in FIG. 19C, as in FIGS. 17C and 17D, a photosensitive resin film 10 is newly formed on the resin film 10 so as to cover the wiring 24. An opening 10b is formed in a region where a through hole connected to the wiring 24 is formed.

  Next, in FIG. 19D, similarly to FIG. 9A, the Ti film 28 and the Cu film 20 are sequentially stacked on the resin film 10 by sputtering or the like. The Ti film 28 and the Cu film 20 are also formed on the inner surface of the opening 10b.

  Next, in FIG. 20A, similarly to FIG. 9B, a region where an electrode is formed on the resin film 10 on which the Ti film 28 and the Cu film 20 are formed is removed using a photolithography method. A photoresist 18 is formed in the region. Next, in FIG. 20B, electroplating is performed in the same manner as in FIG. 9C, Cu is deposited inside the opening 18e, and the electrode 29 is formed. Next, in FIG. 20C, the photoresist 18 is removed as in FIG. 9D.

  Next, in FIG. 21A, as in FIG. 9E, the Cu film 20 and the Ti film 28 (that is, the seed layer) not covered with the electrode 29 are removed by wet etching or the like, and the substrate 150 and The interposer 130 including the rewiring layer 160 is completed.

  Next, in FIG. 21B, the electrode of the package substrate 140 and the electrode formed on the substrate 150 in the interposer 130 are connected via the bump BP2, and an underfill agent is provided in the gap between the substrate 150 and the package substrate 140. UF2 is filled. Thereafter, LSI chips 110a and 110b are mounted on the electrodes 29 of the interposer 130, and the chip package substrate shown in FIG. 12 is completed.

  22 to 27 show another example of the electronic device. Elements that are the same as or similar to those in the electronic device 100 shown in FIG. 12 are given the same reference numerals, and detailed descriptions thereof are omitted. 22 to 27 show cross sections of the electronic device.

  22 does not have the substrate 150 of the electronic device 100 shown in FIG. 12, and the interposer 130 is formed only by the rewiring layer 160. That is, the electrode formed on the electrode layer E1 of the rewiring layer 160 is connected to the electrode of the package substrate 140 via the bump BP2. Then, another 2.5D-IC form is formed by the chip package substrate having the LSI chips 110a and 110b, the redistribution layer 160, and the package substrate 140 shown in FIG. The structure of the rewiring layer 160 is the same as the structure of the rewiring layer 160 shown in FIG.

  In the interposer 130 shown in FIG. 22, the rewiring layer 160 is formed on a support substrate (not shown), then peeled off from the support substrate and bonded to the package substrate 140. For this reason, in the method for forming the interposer 130 shown in FIG. 22, the steps shown in FIGS. 13A to 17C are not performed, and the same steps as those in FIG. 9 are performed. In this case, a support substrate is used instead of the resin film 1 of FIG. 9, and a Ni film is formed instead of the Ti film. In FIG. 9G, after the resin film 7 is formed on the support substrate, not on the resin film 1, the steps from FIG. 17D to FIG. 21A are performed, and the interposer 130 is formed. The

  The electronic device 100B illustrated in FIG. 23 does not include the substrate 150 of the electronic device 100 illustrated in FIG. 12, and the interposer 130 is formed by only the rewiring layer 160, as in FIG. In addition, the electrode formed on the electrode layer E1 of the rewiring layer 160 is directly connected to the electrode of the package substrate 140 having a resin film on the surface without the bump BP2 shown in FIG. The chip package substrate in which the interposer 130 and the package substrate 140 shown in FIG. 23 are integrated is also referred to as 2.1D-IC. The structure of the rewiring layer 160 is the same as the structure of the rewiring layer 160 shown in FIG.

  In the interposer 130 shown in FIG. 23, the rewiring layer 160 is formed on the package substrate 140. Since the rewiring layer 160 is formed on the package substrate 140, the steps shown in FIGS. 13A to 15D are not performed in the method for forming the interposer 130 shown in FIG. When a resin film is formed on the surface of the package substrate 140, the same steps as those shown in FIGS. 15E to 21A are performed. That is, in FIG. 15E, the sulfur compound 12 is attached on the resin film on the surface of the package substrate 140. On the other hand, when an inorganic material such as silicon is formed on the surface of the package substrate 140, a process similar to that shown in FIG. 9 is performed instead of the processes shown in FIGS.

  In the electronic device 100C shown in FIG. 24, LSI chips 110c and 110d are stacked on the LSI chip 110b in the electronic device 100A shown in FIG. For this reason, pads connected to the LSI chip 110c are formed on the upper surface of the LSI chip 110b. The chip package substrate having the rewiring layer 160 and the package substrate 140 shown in FIG. 24 and having the LSI chips 110a-110d mounted in two dimensions and three dimensions is also referred to as 2.5D / 3D-IC. . The interposer 130 shown in FIG. 24 is formed in the same manner as the interposer 130 shown in FIG.

  In the electronic device 100D shown in FIG. 25, LSI chips 110c and 110d are stacked on the LSI chip 110b in the electronic device 100B shown in FIG. The chip package substrate in which the rewiring layer 160 and the package substrate 140 shown in FIG. 25 are integrally formed and the LSI chips 110a to 110d are mounted in two dimensions and three dimensions is also referred to as 2.1D / 3D-IC. Is done. The interposer 130 shown in FIG. 25 is formed in the same manner as the interposer 130 shown in FIG.

  An electronic device 100E illustrated in FIG. 26 includes LSI chips 110a and 110b integrated with a sealing resin 170 instead of the individual LSI chips 110a and 110b provided in the electronic device 100A illustrated in FIG. A multi-chip package MCP is formed by the resin-sealed LSI chips 110 a and 110 b and the rewiring layer 160. For example, in the multi-chip package MCP, a large number of LSI chips 110a and 110b are resin-sealed in the shape of a semiconductor wafer, a rewiring layer 160 is formed on the LSI chips 110a and 110b using a semiconductor manufacturing apparatus, and then dicing is performed. It is manufactured by doing. The area in which the wiring is formed in the rewiring layer 160 is larger than the area of each of the LSI chips 110a and 110b. As described above, the method of forming the redistribution layer 160 in a region of the semiconductor wafer larger than the area of the LSI chips 110a and 110b is also referred to as a Fan Out WLP (Wafer Level Package) technique.

  In the method for forming the interposer 130 shown in FIG. 26, the steps shown in FIGS. 13A to 17C are not performed, and the same steps as those in FIG. 9 are performed. In this case, LSI chips 110a and 110b resin-sealed in the shape of a semiconductor wafer are used instead of the resin film 1 of FIG. 9, and the steps of FIGS. 9A to 9F are performed. However, a Ni film is formed instead of the Ti film. 9G, after forming the resin film 7 on the LSI chips 110a and 110b, the steps from FIG. 17D to FIG. 21A are performed, and the interposer 130 is formed.

  However, the rewiring layer 160 shown in FIG. 26 is formed in the order of the electrode layer E2, the wiring layer W2, and the electrode layer E1 (wiring layer W1). For this reason, the electrode layer E2 is formed by performing the same steps as in FIG. 9, the wiring layer W2 is formed by the steps shown in FIGS. 17C to 19B, and FIGS. The electrode layer E1 is formed by the process shown in A).

  As in FIG. 26, the electronic device 100F shown in FIG. 27 has LSI chips 110a and 110b integrated by resin sealing instead of the individual LSI chips 110a and 110b. Then, similarly to the rewiring layer 160 shown in FIG. 26, the rewiring layer 160 is formed on the resin-sealed LSI chips 110a and 110b by the Fan Out WLP technology, and then dicing is performed, so that the multichip package MCP is formed. Is formed. Further, the multi-chip package MCP shown in FIG. 27 is directly connected to the mother board 120 via the bumps BP3 without going through the package substrate 140 shown in FIG. Similarly to the rewiring layer 160 illustrated in FIG. 26, the rewiring layer 160 illustrated in FIG. 27 is formed in the order of the electrode layer E2, the wiring layer W2, and the electrode layer E1 (wiring layer W1).

  As described above, also in the embodiment shown in FIGS. 12 to 27, the same effect as the embodiment shown in FIGS. 1 to 8 can be obtained. That is, the adhesion between the wiring 24 formed on the resin film 10 and the resin film 10 can be improved as compared with the case where the sulfur compound 12 is not attached on the resin film 10. By electroplating, Cu can be deposited locally only inside the opening 18c, the CMP process can be omitted, and the wiring 24 can be prevented from being bent and short-circuited or disconnected together with the photoresist 18. can do. Further, since the Cu film 20 functioning as the seed layer is removed in a state where the wiring 24 is covered with the opening 14 of the photoresist 18, the removal of the Cu film 20 prevents the wiring 24 from being thinned. be able to. As a result, the reliability of the wiring 24 can be improved as compared with the wiring structures of FIGS.

  Furthermore, in the embodiment shown in FIGS. 12 to 27, when forming a through hole connected to the lower wiring 24, the reliability of the wiring 24 is improved by attaching the sulfur compound 12 to the resin film 10 in which the through hole is formed. Can be improved as compared with the wiring structures of FIGS. In other words, even when the rewiring layer 160 has a plurality of wiring layers, the reliability of the wiring 24 of each wiring layer can be ensured.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

  DESCRIPTION OF SYMBOLS 10 ... Resin film; 10a, 10b ... Opening; 12 ... Sulfur compound; 14 ... Opening; 16 ... Mask layer; 18 ... Photoresist; 18a, 18b, 18c, 18d ... Opening; 20a ... Cu; 22 ... Metal film (Ni film); 22a ... Oxide film; 24 ... Wiring; 26 ... NiP film; 28 ... Ti film; 29 ... Electrode; 30 ... Substrate; 30a ... Opening; 34 ... Cu film; 36 ... Cu100 ... electronic device; 110a, 110b ... LSI chip; 111a, 111b ... pad; 120 ... motherboard; 130 ... interposer; 140 ... package substrate; 150 ... substrate; 160 ... redistribution layer 170 ... Sealing resin; BP1a, BP1b, BP2, BP3 ... Bump; E1, E2 ... Electrode layer; EW ... Wiring for evaluation; TM ... Terminal; UF1, UF2, UF3 ... A Dafiru agent; W1, W2 ... wiring layer

Claims (9)

Attaching a sulfur compound on the resin film;
Forming a mask layer having a first opening in a region where wiring is formed on the resin film to which the sulfur compound is attached;
Covering the mask layer and sequentially laminating a first metal film containing Cu and a second metal film;
The resin film on which the first metal film and the second metal film are formed is heat-treated in an atmosphere containing oxygen to oxidize the surface of the second metal film and to form on the sulfur compound. A part of the Cu of the first metal film is floated on the second metal film formed on the bottom of the first opening;
Performing an electroplating process using Cu floating on the bottom of the first opening as an electrode to form the wiring in the first opening;
And a step of removing the second metal film and the first metal film formed on the surface of the mask layer after forming the wiring.   When connecting the wiring to another wiring formed in the resin film, before attaching a sulfur compound on the resin film, a second opening that penetrates to the other wiring is formed in the resin film. The wiring forming method according to claim 1, further comprising a forming step. Removing the mask layer after removing the second metal film and the first metal film;
The method of forming a wiring according to claim 1, further comprising: removing the first metal film remaining on the side wall of the wiring after removing the mask layer.   The wiring formation method according to claim 1, wherein the sulfur compound is a thiol-based compound.   5. The wiring formation method according to claim 1, wherein the second metal film includes at least one of Ni, Co, and Sn.   6. The method for forming a wiring according to claim 1, further comprising a step of covering a surface of the wiring formed in the first opening with a third metal film.   7. The composition of the third metal film is any one of Ni, NiP, NiB, NiWP, NiWB, CoP, CoB, CoWP, CoWB, NiCoWP, NiCoWB, NiCoP or NiCoB. Method for forming wiring. A wiring containing Cu provided on the resin film;
A layer containing S and a first metal film containing Cu, which are sequentially stacked between the resin film and the wiring;
A wiring structure comprising: a second metal film provided between the wiring and the first metal film and on a side wall of the wiring.   9. The wiring structure according to claim 8, further comprising an oxide film of a metal provided between the side wall of the wiring and the second metal film and contained in the second metal film.