JP2017092238A - Semiconductor substrate manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor substrate manufacturing method of removing a corner edge at an opening boundary of a hole by using a simple composition.SOLUTION: A semiconductor substrate manufacturing method comprises: a step of forming a first etching mask on one surface of a semiconductor substrate (silicon substrate 10); a step of forming a hole in the semiconductor substrate by using the first etching mask; a step of forming a second etching mask (photoresist layer 18) on the one surface side; and a step of performing edge trimming for forming a hole in such a manner that an angle between the one surface and a sidewall of the hole is larger at a lower part of the hole sidewall than at an upper part. In the step of forming the second etching mask, the second etching mask is coated when the edge trimming is in progress so as to expose a boundary 103 between the one surface and the hole sidewall.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a method for manufacturing a semiconductor substrate.

  In the semiconductor industry, along with miniaturization and weight reduction of electric precision devices such as mobile phones, integrated circuits (ICs) mounted thereon are also becoming smaller, lighter and more functional. As a technology that has recently attracted attention, there is a through silicon via (TSV). TSV forms a through-hole penetrating the front and back of a semiconductor substrate, and forms a through-electrode using this. Therefore, TSV enables miniaturization and weight reduction by realizing electrical connection between laminated substrates at the wafer level, and further contributes to speeding up functions by shortening the wiring distance.

  Various shapes are assumed for the holes (via holes) constituting the TSV, but a shape having a conical taper is often used. This is to improve the coverage when an insulating film and a conductive metal film are formed on the side wall (side surface) of the hole. For the formation of such holes, wet etching or dry etching is used. However, in the general non-Bosch process of wet etching or dry etching, the taper angle of the hole is limited by the silicon crystal orientation (for example, about 55 degrees), so that a via angle edge is formed at the opening boundary of the hole. . For this reason, in a film forming process of an insulating film, a conductive film, or the like, an electrical short, open, leak, or film formation failure occurs between vias.

In order to solve the above-described problem, for example, Patent Document 1 discloses a via structure and a via etching process for manufacturing the via structure. In this technique, a hard mask layer and a photoresist layer are sequentially formed on a semiconductor substrate, and a second opening is formed in the hard mask layer by using the first opening formed in the photoresist layer to expose a part of the semiconductor substrate. And vias are formed by etching. Thereafter, a trimming process is performed to smoothly connect the inclined surface of the second opening in the hard mask layer and the inner surface of the via, and etch the via sidewall and the via angle.
However, since the method disclosed in Patent Document 1 uses a multilayer structure for forming the tapered side wall, the manufacturing process is complicated.

  An object of the present invention is to provide a method of manufacturing a semiconductor substrate that removes a via angle edge at an opening boundary of a hole using a simple configuration.

  In order to solve the above-described problems, a method of manufacturing a semiconductor substrate according to the present invention includes a step of forming a first etching mask on one surface of a semiconductor substrate, and the semiconductor substrate using the first etching mask. Forming a hole in the surface, forming a second etching mask on the one surface side, and using the second etching mask, an angle formed between the one surface and the sidewall of the hole is: Performing edge trimming to form a hole in which the lower part is larger than the upper part of the side wall of the hole. In the step of forming the second etching mask, the second etching mask is applied so that a boundary between the one surface and the side wall of the hole is exposed during the edge trimming.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor substrate which removes the via angle edge of the opening boundary of a hole using a simple structure can be provided.

It is a flowchart showing the manufacturing method of the semiconductor substrate which concerns on one Embodiment. It is a figure explaining the photoresist application process in a via formation process. It is a figure explaining the pattern exposure process in a via formation process. It is a figure explaining the via etching process in a via formation process. It is a figure explaining the via hole formed by the via formation process. It is a figure explaining the covering property of the insulating film after a via formation process. (A) is a figure which shows via | veer coverage when the film thickness of an insulating film is thin, or the viscosity at the time of liquid phase film formation is low, (B) is a film thickness of an insulating film thick, or is a liquid phase It is a figure which shows the via | veer coverage in case the viscosity at the time of film-forming is high. It is a figure explaining the photoresist layer apply | coated to the via hole with the spray coater. (A) shows a cross-sectional profile of the photoresist layer, (B) shows a cross-sectional profile when the contact angle between the silicon substrate surface and the photoresist is large, and (C) shows a cross-section when the contact angle is small. It is a figure which shows a profile. It is a figure explaining the shape of the photoresist layer and via hole after via corner edge trimming execution. (A) is a figure showing the profile of a photoresist layer and a via hole, (B) is a figure explaining the angle | corner which the surface of a silicon substrate and a via side wall make. It is a figure explaining the coverage of the insulating film after a via corner edge trimming. (A) shows a state in which the photoresist is removed and an insulating film is formed in the via hole, and (B) is a diagram showing a state in which the insulating film is formed in the via hole with the photoresist remaining. .

  Hereinafter, embodiments will be described with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In the drawings, components having the same configuration or function and corresponding parts are denoted by the same reference numerals and description thereof is omitted.

  FIG. 1 is a flowchart showing a method for manufacturing a semiconductor substrate according to an embodiment. A method for manufacturing a semiconductor substrate according to an embodiment is a method for forming a hole (via hole) having a tapered side wall that constitutes a TSV. A via formation process (S31 to S33) for forming a hole in a semiconductor substrate, a via An edge trimming process (S34, S35) for removing a corner edge and a film forming process (S36) are included.

The semiconductor substrate manufacturing method of one embodiment has the following characteristics in the edge trimming process. The etching mask used in the edge trimming process is applied so that the boundary between one surface of the semiconductor substrate and the sidewall of the hole is exposed during the edge trimming process. This is because the contact angle between the semiconductor substrate and the photoresist at the via angle edge is reduced by the action of the surface tension when a photoresist as an etching mask is applied to the surface of the hole by a liquid phase film formation method such as a spray coater. The focus is on reducing the thickness of the photoresist only around the via corner edge. Thereafter, dry etching is performed on the applied etching mask to expose the semiconductor substrate only around the via corner edge.
This makes it possible to remove a via angle edge formed at the boundary between one surface of the semiconductor substrate and the side wall of the hole. In addition, an etching mask is formed only by applying a resist, and the exposure and development steps can be omitted. Details of the trimming process will be described later.

In this specification, the “hole” or “via hole” is a hole (hole) that becomes a through hole constituting the TSV, and has a tapered side wall whose hole diameter increases toward one surface (surface) of the semiconductor substrate. Has a shape. Further, “hole” or “via hole” are used without distinction.
“One surface of the semiconductor substrate” is the surface of the semiconductor substrate on which the etching mask is formed, and may be referred to as “the surface of the semiconductor substrate”.
The “via angle” is an angle formed by one surface (including a surface parallel to one surface) of the semiconductor substrate and the side wall of the hole, and is a right angle or an acute angle of less than 90 degrees.
The “via angle edge” is an edge formed at the boundary where one surface of the semiconductor substrate and the sidewall of the hole intersect, in other words, an opening edge of the hole formed in the surface of the semiconductor substrate.

Hereinafter, a method for manufacturing a semiconductor substrate according to an embodiment will be described with reference to the drawings. First, the via formation process will be described with reference to FIGS.
2 is a diagram for explaining a photoresist coating process (S31 in FIG. 1), FIG. 3 is for explaining a pattern exposure process (S32 in FIG. 1), and FIG. 4 is for explaining a via etching process (S33 in FIG. 1). . FIG. 5 is a diagram for explaining a via hole formed by a via formation process.
In one embodiment, a silicon substrate made of silicon (Si) will be described as an example of a semiconductor substrate, but the present invention is not limited to this. The semiconductor substrate may be made of gallium arsenide (GaAs), gallium arsenide phosphorus (GaAsP), indium phosphide (InP), gallium aluminum arsenide (GaAlAs), indium gallium phosphide (InGaP), or the like.

First, a photoresist coating process (S31 in FIG. 1) is performed.
FIG. 2 is a sectional view of the silicon substrate 10 and the photoresist layer 12 in the photoresist coating process. The photoresist layer 12 is formed on the silicon substrate 10 by, for example, uniformly applying a photoresist by a spin coater and solidifying the photoresist by pre-baking. At this time, the photoresist layer 12 is coated with a photoresist so as to have a film thickness of 5 to 15 micrometers (μm) in consideration of the selection ratio in the dry etching process. Note that a photoresist having a viscosity of 0.2 Pa · s (200 cp) or more is preferably used because it is thicker than a general resist film thickness.

Next, a pattern exposure / development step (S32 in FIG. 1) is performed.
FIG. 3 is a cross-sectional view of the silicon substrate 10, the photoresist layer 12, and the photomask 14 in the pattern exposure process. The photomask 14 on which the opening pattern of the via hole is drawn is brought into close contact with the photoresist layer 12, and the photoresist layer 12 is exposed by irradiating light. The exposure amount is appropriately adjusted according to the film thickness of the photoresist layer 12. Thereafter, the exposed photoresist is removed by a development process and post-baked to complete the lithography process (formation of a first etching mask).

After the pattern exposure / development process, a via etching process (S33 in FIG. 1) is performed.
FIG. 4 shows a cross-sectional view of the silicon substrate 10 and the photoresist layer 12 (first etching mask) in the via etching step (S33 in FIG. 1). In this embodiment, as an example, via etching uses dry etching with reactive ions. In addition, dry etching is not is a so-called Bosch process in which anisotropic etching is performed perpendicularly to the resist pattern in order to form a tapered via hole having an inclination angle as a via sidewall, and isotropic etching is performed. Use a non-Bosch process. The etching process uses an etching gas containing at least one of fluorocarbon C _x F _y (eg, cyclooctane octafluoride C ₄ F ₈ ), sulfur hexafluoride SF ₆ , and oxygen O _{2 in} an etching apparatus. Thus, dry etching is preferably performed. The pressure during etching is preferably 5 to 10 Pa, and the bias is preferably 2000 to 3000 W, for example. After the etching is completed, the etching opening surface recedes more than the opening pattern of the resist mask.

As described above, in the via etching process, taper etching with an inclined etching side wall is possible by isotropic etching by non-Bosch process etching. In addition, a protective film is formed on the side wall with fluorocarbon (C _x F _y ), the fluorocarbon polymer (C _x F _y polymer) is decomposed with oxygen (O ₂ ), and sulfur hexafluoride (SF ₆ ) The tape etching can be realized by performing the silicon etching process macroscopically with a mixed gas.

  FIG. 5 shows a cross-sectional view of the silicon substrate 10 with the via holes completed. By removing the remaining photoresist, the via formation process is completed. The via hole is etched so that the opening diameter of the via top is larger than the via bottom. The size of the via bottom is the size of the surface that becomes the bottom of the hole, and the opening diameter of the via top is the diameter of the opening edge formed on the surface of the semiconductor substrate. The depth of the via hole may be several tens to several hundreds of micrometers. The surface roughness of the via sidewall 101, which is the side surface of the via hole, is not particularly limited, but may be smooth to the extent that the coverage and adhesion of the insulating film and the conductive film are maintained.

Next, the edge trimming process (S34 and S35 in FIG. 1) will be described with reference to FIGS. First, a coating state when an insulating film is coated on a semiconductor substrate having a via corner edge will be described.
FIG. 6 shows a covering state of the insulating film when the insulating film is formed on the surface of the semiconductor substrate and the via sidewall after the via formation process. The method for forming the insulating film is not particularly limited, for example, a liquid phase film forming method such as spray coating or a vapor phase film forming method such as PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition). The insulating film may be made of any inorganic material such as SiO ₂ or SiOF, organic material such as parylene or polyallyl ether, organic / inorganic hybrid material, or other insulating materials.
FIG. 6A shows via coverage when the insulating film 16 is thin or has a low viscosity during liquid phase film formation. In this case, the thickness of the insulating film 16 tends to be thin at the via corner edge portion denoted by reference numeral 201 in the figure. When a conductive film is formed after such an insulating film formation process, an electrical short circuit or leakage between the silicon substrate 10 under the exposed insulating film 16 and the conductive film becomes a problem.
FIG. 6B shows the via coverage when the insulating film 16 is thick or has a high viscosity during liquid phase deposition. In this case, in the via corner edge portion indicated by reference numeral 202 in the drawing, the thickness of the insulating film 16 becomes thick, and there is a possibility that a protruding structure as shown in the drawing is formed. When a conductive film is formed after such an insulating film formation process, the coverage with the conductive film is not sufficient in the vicinity of the protrusion of the insulating film 16, and discontinuity of the conductive film may occur. Open is a problem.

As described above, when a via angle edge exists in a semiconductor substrate, there is a possibility that a problem occurs in a process after the via formation process, particularly in a film forming process. Therefore, it is desirable that the via angle edge is removed (trimmed) before starting the film forming process.
When trimming only the via angle by dry etching, a photoresist serving as an etching mask may be applied and the trimmed portion may be opened. However, in an ordinary photolithography process, when an opening pattern is formed in a photoresist, an exposure / development process (for example, the process of step S32 in FIG. 1) is performed. Therefore, a process for forming an opening is added. Then, the man-hour increases.
Therefore, in this embodiment, the etching mask (second etching mask) used in the trimming process (S35 in FIG. 1) is performed only in the photoresist (trimming resist) coating process (S34 in FIG. 1). Specifically, by applying a photoresist using a liquid phase film forming method such as a spray coater, the region to be trimmed is opened without taking the steps of exposure and development by utilizing the property of the surface tension of the liquid. By using the surface tension of the liquid phase deposition method, the etching mask profile is formed so that the silicon substrate near the opening of the via hole (near the boundary of the via opening) is exposed without using the exposure / development process. Is possible.

FIG. 7 is a diagram for explaining a photoresist layer applied to the surface of a silicon substrate including a via hole by a spray coater. FIG. 7A shows a cross-sectional profile of the photoresist layer. By applying the photoresist by spray coating, the photoresist is coated on the surface of the silicon substrate 10 and in the via hole (via side wall, bottom). At this time, since the photoresist landing on the silicon substrate 10 is in a liquid state, surface tension is applied to the photoresist at the boundary 103 between the surface of the silicon substrate 10 and the via sidewall (hereinafter also referred to as “via opening boundary” as appropriate). Work.
Here, the surface tension of the photoresist will be described with reference to FIGS. FIGS. 7B and 7C are partial cross-sectional views around the boundary of the via opening, showing the cross-sectional profile of the photoresist layer 18. FIG. 7B shows a case where the contact angle between the surface of the silicon substrate 10 and the photoresist layer 18 is large (for example, the contact angle θ1 is larger than 90 degrees), and FIG. 7C shows a small contact angle. (For example, the contact angle θ2 is 90 degrees or less).

  When attention is paid to the profile of the photoresist layer 18 in the vicinity of the boundary 103 between the surface of the silicon substrate 10 and the via sidewall, the following difference occurs in the film thickness of the photoresist layer 18 according to the size of the contact angle. When the contact angle is large (θ1> 90 °), the photoresist greatly rises in the vicinity of the via opening boundary, and the film thickness is much smaller than the photoresist layer 18 in the planar portion of the silicon substrate 10 other than the via opening boundary. no change. On the other hand, when the contact angle is small (θ2 ≦ 90 °), the surface of the silicon substrate 10 is in a so-called “wet state”, and the film thickness of the photoresist layer 18 in the vicinity of the via opening boundary is silicon other than the via opening boundary. Compared to the photoresist film thickness in the planar portion of the substrate 10, it is relatively very thin. That is, by adjusting the viscosity of the photoresist and reducing the contact angle, a difference in film thickness of the photoresist layer 18 occurs between the vicinity of the via opening boundary and the planar portion of the silicon substrate 10 other than the via opening boundary. As the process proceeds, the silicon substrate 10 is exposed only near the boundary of the via opening, and the via corner edge can be trimmed.

As described above, the photoresist coating process (second etching mask forming process) is performed so that the boundary between the surface of the silicon substrate 10 and the via sidewall is exposed during the subsequent trimming process. Apply resist. When the etching mask is formed, the mask profile is set so that the silicon substrate 10 in the vicinity of the via opening boundary is exposed, so that etching proceeds gradually from the vicinity of the via opening boundary and only the via corner edge is trimmed. .
The profile of the photoresist layer 18 when applied by a spray coater is not limited to the illustrated shape as long as the photoresist film thickness near the via opening boundary is very thin. The photoresist layer 18 may be applied so that the via corner edge is removed in the trimming process. For example, a part of the surface of the silicon substrate 10 near the boundary 103 (for example, a part of the boundary 103). May be applied so as to be exposed.

Next, in the trimming step (S35 in FIG. 1), the via corner edge is removed using the applied etching mask.
FIG. 8A shows a profile of the photoresist layer 18 and the via hole after trimming of the via corner edge. As with via etching, via corner edge trimming uses dry etching with reactive ions, and in the etching apparatus, fluorocarbon C _x F _y (for example, cyclobutane octafluoride C ₄ F ₈ ), sulfur hexafluoride SF ₆ , And an etching gas containing at least one of oxygen O ₂ .
When dry etching is started, the silicon substrate 10 is gradually exposed from the thin portion of the photoresist film thickness near the via opening boundary, and isotropic etching is performed around the via corner edge as the etching of the silicon substrate 10 proceeds. Is given. As shown as the trimming portion 105 in FIG. 8, the silicon substrate 10 is etched to remove only a part of the via corner edge.
By the trimming process, a hole is formed in which the angle formed between the surface of the silicon substrate 10 and the via sidewall is larger in the lower portion than in the upper portion of the via sidewall.

FIG. 8B is a partial cross-sectional view around the via hole, and is a diagram for explaining an angle (via angle) formed by the surface of the silicon substrate 10 and the via sidewall 101. The via angles α <b> 1 and α <b> 2 are angles formed between the surface of the silicon substrate 10 or a plane parallel to the surface and the via sidewall 101. As shown in FIG. 8B, the upper via angle α1 of the via sidewall 101 is smaller than the lower via angle α2. This is because if the via angle edge is removed by the trimming process, the inclination of the upper portion of the via sidewall 101 becomes smaller than that of the lower portion, resulting in an angle difference.
The profile of the photoresist and the trimmed via hole is not limited to the illustrated trimming shape as long as the inclination of the via hole changes stepwise after etching.

In the film forming step (S36 in FIG. 1), the formed via hole is coated with an insulating film, a conductive film, or the like.
FIG. 9 is a diagram illustrating the coverage of the insulating film after via corner edge trimming. FIG. 9A shows a state where the photoresist is removed by ashing and the insulating film 16 is formed in the via hole after the via formation process and the trimming process. Since the via sidewall and the surface of the silicon substrate 10 are connected more smoothly than before the via corner edge is trimmed, the insulating film 16 is also covered smoothly, as shown in FIGS. 6 (A) and 6 (B). Anomalies such as uneven coating and discontinuity of the insulating film 16 are less likely to occur. FIG. 9B shows a state in which after the via formation process and the trimming process, an insulating film is formed in the via hole with the photoresist remaining without being removed by ashing. In this way, the step of additionally forming an insulating film may be omitted without removing the photoresist by ashing.

  As described above, in the method of manufacturing a semiconductor substrate according to the present embodiment, a taper-like shape that removes the via corner edge near the via hole opening and smoothly connects the wafer surface and the via sidewall using the simple configuration. A via hole profile can be formed. In addition, since the development / exposure process can be omitted in forming the second etching mask used in the trimming process, it is possible to suppress an increase in manufacturing cost such as the number of processes and processing time.

In addition, recently attracted attention, a wafer level package using TSV realizes a mounting process including inter-chip wiring by high-precision alignment using a wafer level semiconductor process. As a result, the device is reduced in size and weight, and the cost is reduced by batch production.
Since the semiconductor substrate manufacturing method of the present embodiment uses a simple configuration that does not form a complex multilayer structure or the like, it can be easily applied to the semiconductor process, and trimming of a via corner edge is performed using an etching mask. Therefore, it can be expected to contribute to cost reduction.
Furthermore, in the wafer level package adopting TSV, the back and front of the substrate are connected by the shortest distance by the through electrode, and the wiring distance is shortened, thereby contributing to the speeding up of the function. The semiconductor substrate manufacturing method of the present embodiment realizes the trimming of the via angle edge with a simple configuration that does not use a multilayer structure or the like, and is therefore suitable for shortening the wiring distance.

  In addition, this invention is not limited to embodiment shown above. Within the scope of the present invention, it is possible to change, add, or convert each element of the above-described embodiment to a content that can be easily considered by those skilled in the art.

DESCRIPTION OF SYMBOLS 10 Silicon substrate 12, 18 Photoresist layer 14 Photomask 16 Insulating film 101 Via side wall 103 Boundary 105 Trimming part 201, 202 Via corner edge part

Japanese Patent No. 5560877

Claims (8)

Forming a first etching mask on one surface of the semiconductor substrate;
Forming a hole in the semiconductor substrate using the first etching mask;
Forming a second etching mask on the one surface side;
Performing edge trimming using the second etching mask to form a hole in which the angle formed between the one surface and the side wall of the hole is larger in the lower part than in the upper part of the side wall of the hole. ,
The step of forming the second etching mask includes applying the second etching mask so that a boundary between the one surface and the sidewall of the hole is exposed during the edge trimming. Production method.   The method of manufacturing a semiconductor substrate according to claim 1, wherein the step of forming the second etching mask does not include exposure and development processing.   3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the second etching mask is applied so that a film thickness of a region including the boundary is thinner than that of another region.   4. The method for manufacturing a semiconductor substrate according to claim 1, wherein the second etching mask is applied so that a part of the surface of the semiconductor substrate is exposed. 5.   5. The method of manufacturing a semiconductor substrate according to claim 1, wherein the second etching mask is applied so that at least a part of the boundary is exposed. 6.   The semiconductor substrate manufacturing method according to claim 1, wherein the second etching mask is formed by a liquid phase film forming method.   The method for manufacturing a semiconductor substrate according to claim 1, wherein the step of forming the hole and the step of performing edge trimming are performed by isotropic dry etching using an etching gas. The step of forming the hole and the step of performing edge trimming are performed by dry etching using an etching gas containing at least one of carbon fluoride, sulfur hexafluoride, and oxygen O _2. The method for manufacturing a semiconductor substrate according to any one of claims 1 to 7.