JP2016207991A - Semiconductor substrate manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a semiconductor substrate having a via hole without having a corner at an opening in a simple manufacturing method.SOLUTION: A semiconductor substrate manufacturing method includes a first step and a second step. The first step is a step of forming on a first surface T1 of a semiconductor substrate 10, a mask layer 12 having a first through hole 12A. The second step is a step of etching the semiconductor substrate 10 via the first through hole 12A of the mask layer 12 from the first surface T1 side of the semiconductor substrate 10 to form a via hole 14A in the semiconductor substrate 10. The mask layer 12 is a layer for forming the via hole 14A which forms an angle between the first surface T1 and a side wall S of the via hole 14A is larger on a second surface T2 side of the semiconductor substrate 10, which is opposite to the first surface T1 than on the first surface T1 side.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a semiconductor substrate.

  From the viewpoint of achieving high integration, a technique is disclosed that uses a through electrode (TSV: Through Silicon Via) penetrating a semiconductor substrate for connection between LSI (Large Scale Integration) chips. The TSV is formed by forming a via hole (through hole) penetrating the semiconductor substrate and embedding a conductive material in the via hole via an insulating film.

  As the shape of the via hole, a shape having a taper having a smaller lower diameter than the upper diameter is known. Etching of the surface of the semiconductor substrate is used for forming the via hole. However, since the taper angle is limited by the silicon crystal orientation (for example, about 55 °), the corner portion is formed in the opening of the via hole. When the corner portion is formed in the opening of the via hole, an electrical short, open, leak, or the like between the TSVs occurs when the conductive material is embedded through the insulating film. Therefore, a technique is disclosed in which after a via hole is formed by etching, a trimming process of a corner portion of the opening of the via hole is separately performed.

  However, conventionally, it is necessary to separately provide a step of trimming the corners of the opening of the via hole separately from the step of forming the via hole, and the via hole having no corner is formed in the opening by a simple manufacturing method. It was difficult to do.

  In order to solve the above-described problems and achieve the object, the present invention includes a first step of forming a mask layer having a first through hole on a first surface of a semiconductor substrate, and the first of the mask layer. And a second step of etching the semiconductor substrate from the first surface side of the semiconductor substrate through a through hole to form a via hole in the semiconductor substrate. The mask layer forms the via hole in which the angle formed between the first surface and the sidewall of the via hole is larger on the second surface side facing the first surface of the semiconductor substrate than on the first surface side. Layer.

  According to the present invention, there is an effect that it is possible to manufacture a semiconductor substrate having via holes that do not have corners in the openings by a simple manufacturing method.

FIG. 1 is an explanatory diagram of the manufacturing method of the present embodiment. FIG. 2 is an explanatory diagram of a semiconductor substrate. FIG. 3 is an explanatory diagram showing an example of the manufacturing method according to the present embodiment. FIG. 4 is an explanatory diagram of the arrangement of the second light transmission parts. FIG. 5 is an explanatory diagram of a conventional semiconductor substrate. FIG. 6 is an explanatory view of a semiconductor substrate manufactured by a conventional manufacturing method. FIG. 7 is a schematic view showing a state in which an insulating film is formed on the semiconductor substrate of the present embodiment. FIG. 8 is an explanatory diagram of the manufacturing method of the present embodiment. FIG. 9 is an explanatory diagram of a semiconductor substrate. FIG. 10 is an explanatory diagram showing an example of the manufacturing method of the present embodiment. FIG. 11 is an explanatory diagram of the arrangement of the second light transmission parts.

  Embodiments of the present invention will be described below.

  The method for manufacturing a semiconductor substrate of the present embodiment (hereinafter simply referred to as “manufacturing method”) includes a first step and a second step.

  The first step is a step of forming a mask layer having a first through hole on the first surface of the semiconductor substrate. The second step is a step of forming a via hole in the semiconductor substrate by etching the semiconductor substrate from the first surface side of the semiconductor substrate through the first through hole of the mask layer. In the manufacturing method of the present embodiment, the mask layer has the via hole in which the angle formed between the first surface and the side wall of the via hole is larger on the second surface side facing the first surface of the semiconductor substrate than on the first surface side. It is a layer for forming.

  That is, in the manufacturing method of the present embodiment, a semiconductor substrate having via holes that do not have corners in the opening on the first surface side can be manufactured by one process such as the second process. Details will be described below.

(First embodiment)
Hereinafter, the manufacturing method of the present embodiment will be described in detail.

  FIG. 1 is an explanatory diagram of the manufacturing method of the present embodiment.

  The manufacturing method of the present embodiment includes a first step and a second step.

  The first step is a step of forming the mask layer 12 on the first surface T1 of the semiconductor substrate 10 (see FIG. 1A).

  The semiconductor substrate 10 is made of, for example, silicon (Si), gallium arsenide (GaAs), gallium arsenide phosphorus (GaAsP), indium phosphide (InP), gallium aluminum arsenide (GaAlAs), indium gallium phosphide (InGaP), or the like. The In the present embodiment, as an example, the case where the semiconductor substrate 10 is made of silicon will be described.

  In the first step, the mask layer 12 is formed on the first surface T1 of the semiconductor substrate 10. The first surface T1 is one of the two opposing surfaces of the semiconductor substrate 10. The surface facing the first surface T1 of the semiconductor substrate 10 will be referred to as the second surface T2.

  The mask layer 12 has a first through hole 12A. 12 A of 1st through-holes are holes which penetrate the mask layer 12 in the thickness direction (arrow X direction in FIG. 1). 12 A of 1st through-holes are provided in the position according to the via hole of the formation object in the plane parallel to 1st surface T1.

  The second step is a step of etching the semiconductor substrate 10 from the first surface T1 side of the semiconductor substrate 10 through the first through hole 12A of the mask layer 12 to form a via hole 14A in the semiconductor substrate 10 (FIG. 1). (See (B)).

  The via hole 14A formed by etching in the second step has a larger angle between the first surface T1 on the second surface T2 side and the side wall S of the via hole 14A than on the first surface T1 side. In the present embodiment, the via hole 14A is formed in the second step by using the mask layer 12 used in the present embodiment. That is, the mask layer 12 has a via hole 14A in which the angle formed between the first surface T1 and the sidewall S of the via hole 14A is larger on the second surface T2 side facing the first surface T1 of the semiconductor substrate 10 than on the first surface T1 side. It is a layer for forming.

  The angle formed by the first surface T1 and the side wall S of the via hole 14A is an angle formed by a plane parallel to the first surface T1 and the side wall S of the via hole 14A, and is a right angle or an acute angle (90 Less than °). Hereinafter, an angle formed by the first surface T1 and the side wall S may be referred to as a “via angle”.

  Specifically, as shown in FIG. 1B, in the via hole 14A, the via angle (α2) on the second surface T2 side is larger than the via angle (α1) on the first surface T1 side. That is, the relationship of α2> α1 is satisfied.

  FIG. 2 is an explanatory diagram of the semiconductor substrate 14 in which the via hole 14A is formed. As shown in FIG. 2, the via angle (α1, α2) of the via hole 14A formed by the second step is larger on the second surface T2 side (α2) than on the first surface T1 side (α1).

  For this reason, the opening on the first surface T1 side of the via hole 14A has no corner. In the present embodiment, the corner is an opening edge on the first surface T1 side by the via hole 14A in the semiconductor substrate 14, and the angle formed by the first surface T1 and the side wall S is the first edge of the via hole 14A. The part which is below the via angle | corner of the 2nd surface T2 side edge part is shown.

  As described above, in the manufacturing method of the present embodiment, the semiconductor substrate 14 having the via hole 14A having no corner in the opening on the first surface T1 side can be manufactured by one etching in the second step. .

  In the present embodiment, the cross-sectional shape in the thickness direction of the semiconductor substrate 14 at the opening edge of the via hole 14A is continuously via from the first surface T1 side to the second surface T2 side as shown in FIG. It is a shape with a large corner.

  In order to form the via hole 14A in the second step, the mask layer 12 prepared in the first step is continuous along the direction parallel to the first surface T1 with respect to the first through hole 12A in the mask layer 12. The thickness of the first region A1 only needs to be thinner as it is closer to the first through hole 12A.

  For example, as shown in FIG. 1A, in the mask layer 12, the thickness of the first region A1 continuous along the direction parallel to the first surface T1 with respect to the first through hole 12A in the mask layer 12 is set. It is preferable that the closer to the first through hole 12A is, the thinner continuously.

  The first region A1 is a region in the mask layer 12 that is continuous in a direction parallel to the first surface T1 with respect to the first through hole 12A, and with respect to the side wall S portion of the via hole 14A formed in the semiconductor substrate 10. Any region corresponding to the thickness direction (arrow X direction) may be used. For this reason, the region between the first regions A1 (the region where the first through holes 12A are not disposed) in the mask layer 12 may be an intermediate region A2 having a constant thickness.

The mask layer 12 may be made of a material having a lower etching rate than that of the semiconductor substrate 10 by the etching in the second step. The mask layer 12 may be made of, for example, SiO ₂ or may be formed using a resist.

  When the mask layer 12 is formed using a resist, the first process includes a third process, a fourth process, and a fifth process.

  FIG. 3 is an explanatory diagram showing an example of the manufacturing method of the present embodiment when the mask layer 12 is formed using a resist.

  First, the first step is performed. In the third step of the first step, a photoresist layer 17 is formed over the semiconductor substrate 10 (see FIG. 3A). In the present embodiment, a positive photoresist whose solubility in a developer is increased by exposure is used as the photoresist layer 17. As the photoresist layer 17, a known positive type photoresist may be used.

  The photoresist layer 17 may be formed, for example, by uniformly applying a photoresist with a spin coater and solidifying the photoresist by pre-baking. In the third step, it is preferable to apply a photoresist so that the layer thickness is 5 μm to 15 μm in consideration of the selectivity in the second step of etching. Moreover, it is preferable to use a photoresist having a viscosity of 200 cp or more.

  Next, the 4th process in the 1st process is performed. In the fourth step, a photomask 20 is disposed on the photoresist layer 17 (see FIG. 3B). The photomask 20 has a first light transmission part 20A. 20 A of 1st light transmissive parts are provided in the position corresponding to the 1st through-hole 12A (namely, via hole 14A) in the surface parallel to the 1st surface T1 of the photomask 20. As shown in FIG.

  The photomask 20 includes a first light transmission portion 20A and a first light shielding region P along a plane parallel to the first surface T1 of the photomask 20. The first light shielding region P is a region that shields the exposure light used for exposing the photoresist layer 17 in the fifth step.

  The first light transmitting portion 20A is a region in the photomask 20 that transmits the exposure light used for exposing the photoresist layer 17 in the fifth step.

In the second light-shielding region P1 in the first light-shielding region P, which is continuous in the direction parallel to the first surface T1 with respect to the first light-transmissive portion 20A, a plurality of second light beams having an opening width smaller than that of the first light-transmissive portion 20A. Light transmissive portions 20B _{1 to} 20B ₃ are provided. The plurality of second light transmission portions 20B _{1 to} 20B ₄ have different opening widths. Although four types of second light transmission parts 20B _{1 to} 20B ₄ are shown in FIG. 3, it is not limited to four types. In the following, when describing generically second light transmitting portion _20B 1 _{~20B 4} of the plurality, are referred to as a second light transmitting portion 20B. The second light transmission portion 20B is a region that transmits exposure light. A region between the second light shielding regions P1 is a third light shielding region P2 that shields the exposure light.

  The opening width indicates the length of a region having the smallest opening in a cross section parallel to the first surface T1 in each of the first light transmitting portion 20A and the second light transmitting portion 20B.

In the example illustrated in FIG. 3, the second light transmission unit 20B ₁ to the second light transmission unit 20B ₄ are arranged in this order in the second light shielding region P1 in a direction away from a position close to the first light transmission unit 20A. Has been.

  That is, the photomask 20 is provided with a plurality of second light transmission portions 20B in the second light shielding region P1 around the first light transmission portion 20A.

  The opening widths of the plurality of second light transmission portions 20B provided in the second light shielding region P1 may be the same as each other as long as the opening width is smaller than the first light transmission portion 20A. Good.

  In the present embodiment, the opening widths of the plurality of second light transmission portions 20B are different from each other. Specifically, in the present embodiment, the second light-shielding region P1 has a plurality of second light-shielding regions P1 that have a smaller opening width than the first light transmission unit 20A and a larger opening width closer to the first light transmission unit 20A. Two light transmission parts 20B are arranged.

  Each of the plurality of second light transmission portions 20B may be arranged around the first light transmission portion 20A (that is, the second light shielding region P1 in the first light shielding region P), and the arrangement position is not limited.

  For example, the arrangement positions of the plurality of second light transmission parts 20B may be arranged concentrically around the first light transmission part 20A, or may be arranged radially. FIG. 4 is an explanatory diagram of the arrangement of the second light transmission unit 20B.

In the example shown in FIG. 4A, the plurality of second light transmission portions 20B are concentrically arranged in the second light shielding region P1 around the first light transmission portion 20A. In the example shown in FIG. 4A, the second light transmission part 20B (second light transmission part 20B ₁ to second light transmission part 20B ₃ ) has a larger opening width as it is closer to the first light transmission part 20A. As the distance from the one light transmitting portion 20A increases, the opening width decreases. In FIG. 4, it is omitted second light transmitting portion 20B _4.

In the example shown in FIG. 4B, the second light transmission portion 20B has a circular cross section parallel to the first surface T1, and the opening width (that is, the diameter) is smaller than that of the first light transmission portion 20A. . And the 2nd light transmissive part 20B is radially arrange | positioned in the 2nd light-shielding area | region P1 around 20 A of 1st light transmissive parts. In the example shown in FIG. 4B, the second light transmission unit 20B (second light transmission unit 20B ₁ to second light transmission unit 20B ₄ ) has a larger opening width as it is closer to the first light transmission unit 20A. The opening width decreases as the distance from the first light transmission portion 20A increases.

  The first light shielding region P of the photomask 20 may be made of a material that shields the exposure light. Further, the first light transmitting portion 20A and the second light transmitting portion 20B may be configured to transmit the exposure light. For example, the photomask 20 has a first light shielding region P, a region other than the second light transmitting portion 20B of the second light shielding region P1, and a third light shielding region P2 on a glass or quartz substrate that transmits exposure light. What is necessary is just to produce by sputtering with light-shielding films, such as chromium.

  In addition, the pattern by the light-shielding area | region of the 2nd light-shielding area | region P1 in the photomask 20 is not limited to the pattern shown in FIG. It may be. In other words, the second light-shielding region P1 is a region that reduces the exposure amount of the region corresponding to the periphery of the first light transmission portion 20A of the photomask 20 in the photoresist layer 17 and does not completely expose the photoresist layer 17. That's fine.

  Returning to FIG. 3B, next, in the fifth step, the photoresist layer 17 is exposed through the photomask 20. The photomask 20 is provided with a first light transmission portion 20A and a second light transmission portion 20B. For this reason, the photoresist layer 17 is exposed by the exposure light transmitted through the first light transmission portion 20A and the second light transmission portion 20B of the photomask 20. That is, the areas corresponding to the first light transmission part 20A and the second light transmission part 20B in the photoresist layer 17 are exposed. The exposure amount may be adjusted according to the layer thickness of the photoresist layer 17.

  And the exposure area | region exposed with exposure light is removed by developing the photoresist layer 17 with an alkaline solution. Then post bake. Thus, in the fifth step, the mask layer 12 is formed as the photoresist layer 17 from which the exposed region has been removed (see FIG. 3C).

  As shown in FIG. 3C, the photoresist layer 17 is exposed through a photomask 20 and developed, whereby the mask layer 12 having the above-described shape having the first through-holes 12A is obtained.

  That is, when the photoresist layer 17 is exposed through the photomask 20, an area corresponding to the first light transmission portion 20A is exposed. At the same time, in the second light-shielding region P1 around the first light transmission part 20A, the photoresist layer 17 passes through the plurality of second light transmission parts 20B whose opening width becomes smaller as the distance from the first light transmission part 20A increases. Are exposed.

  For this reason, the first through hole 12A corresponding to the first light transmitting portion 20A is formed in the photoresist layer 17, and the thickness of the mask layer 12 that is the photoresist layer 17 in which the first through hole 12A is formed. The cross-sectional shape in the direction (arrow X direction) becomes thinner as it is closer to the first through hole 12A. That is, the cross-sectional shape of the first through hole 12A in the thickness direction (arrow X direction) is such that the opening on the photomask 20 side is the widest and the opening continuously decreases toward the semiconductor substrate 10 side.

  Next, in the second step, the semiconductor substrate 10 is etched from the first surface T1 side of the semiconductor substrate 10 through the first through holes 12A of the mask layer 12 to form via holes 14A in the semiconductor substrate 10 (FIG. 3). (See (D)). Since the via hole 14A has been described above, the description thereof is omitted.

  Here, as described above, the cross-sectional shape in the thickness direction (arrow X direction) of the first through hole 12A in the mask layer 12 has the widest opening on the photomask 20 side, and the opening toward the semiconductor substrate 10 side. Continuously small shape.

  For this reason, during the etching in the second step, the receding speed of the mask layer 12 changes at an accelerated speed, and the etching speed also changes accordingly. Finally, the opening edge of the via hole 14A on the mask layer 12 side has a smaller angle (via angle) formed between the side wall S and the first surface T1, and the second surface T2 from the first surface T1 side. The via angle continuously increases toward the side. For this reason, when etching the via hole 14A, the corner of the opening edge of the via hole 14A is also removed at the same time.

  Note that the pattern of the photomask 20 by the first light transmitting portion 20A and the second light transmitting portion 20B may be any pattern that provides the mask layer 12 capable of forming the via hole 14A in the second step. It is not limited to the form shown in FIG.

  The etching conditions in the second step are constant in the second step. The constant etching conditions indicate that the etching recipes such as the gas composition, gas flow rate, pressure, and bias are constant when dry etching is used as the etching. In the case where wet etching is used as the etching, the composition of the etching solution, the supply condition of the etching solution, and the like are made constant.

  That is, in the present embodiment, in the second step, the via hole 14A is formed by continuously performing etching under a constant etching condition without changing or changing the etching recipe during the etching.

  In the second step, the via hole 14A is preferably formed by dry etching using reactive ions. Further, the via hole 14A is preferably formed by dry etching and isotropic etching. By adopting isotropic etching, the via hole 14A having a taper can be formed. Further, the opening surface of the via hole 14A becomes wider than the first through hole 12A of the mask layer 12 by isotropic etching.

When dry etching is used as the second step, dry etching is performed using an etching gas containing at least one of fluorocarbon (eg, cyclooctane octafluoride C ₄ F ₈ ), sulfur hexafluoride SF ₆ , and oxygen O _2. It is preferable to do so. The pressure during etching is preferably 5 Pa to 10 Pa, for example, and the bias is preferably RF bias power of 2000 W to 3000 W, for example.

  The depth (the length in the thickness direction (arrow X direction)) of the via hole 14A is, for example, several tens μm to several hundreds μm. The surface roughness of the sidewall S of the via hole 14A is not particularly limited as long as the surface roughness of the insulating film and the conductive material covering the via hole 14A is maintained.

  As described above, the manufacturing method of the present embodiment includes the first step and the second step. The first step is a step of forming the mask layer 12 having the first through holes 12A on the first surface T1 of the semiconductor substrate 10. The second step is a step of forming the via hole 14 </ b> A in the semiconductor substrate 10 by etching the semiconductor substrate 10 from the first surface T <b> 1 side of the semiconductor substrate 10 through the first through hole 12 </ b> A of the mask layer 12. The mask layer 12 forms a via hole 14A in which the angle formed between the first surface T1 and the sidewall S of the via hole 14A is larger on the second surface T2 side facing the first surface T1 of the semiconductor substrate 10 than on the first surface T1 side. It is a layer to do.

  Thus, in the manufacturing method of the present embodiment, the via angle of the via hole 14A formed in the second step is larger on the second surface T2 side than on the first surface T1 side. That is, in the manufacturing method of the present embodiment, the semiconductor substrate 14 having the via holes 14A having no corners in the opening on the first surface T1 side can be manufactured by one etching in the second step.

  Therefore, in the manufacturing method of the present embodiment, there is an effect that the semiconductor substrate 14 having the via hole 14A having no corners in the opening can be manufactured by a simple manufacturing method.

  Here, a via hole formed in a conventional semiconductor substrate will be described. FIG. 5 is an explanatory diagram of a conventional semiconductor substrate 100.

  In the conventional via hole 100A formed in the semiconductor substrate 100, the angle (β1) formed between the first surface T1 and the sidewall S of the via hole 100A is constant in the thickness direction of the semiconductor substrate 100 (see the arrow X direction). For this reason, a corner is formed in the opening edge of the via hole 100A on the first surface T1 side.

  When a conductive material is buried in the via hole 100A having a corner at the opening edge on the first surface T1 side through an insulating film, an electrical short, open, leak, etc. between TSVs occurs.

  FIG. 6 is an explanatory view of a semiconductor substrate 100 manufactured by a conventional manufacturing method. 6A shows a state in which the first surface T1 side of the semiconductor substrate 100 and the inner wall (including the side wall S) of the via hole 100A are covered with an insulating film 104 having a small film thickness or low viscosity during liquid phase film formation. It is explanatory drawing which shows. As shown in FIG. 6A, when the semiconductor substrate 100 manufactured by the conventional manufacturing method is covered with the insulating film 104, the insulating film 104 at the opening edge C forming the corner of the opening of the via hole 100A. The layer thickness becomes smaller than other regions. For this reason, when a conductive material is filled into the via hole 100A through the insulating film 104, a short circuit or a leak due to conduction between the semiconductor substrate 100 and the conductive material occurs.

  FIG. 6B shows a state in which the first surface T1 side of the semiconductor substrate 100 and the inner wall (including the side wall S) of the via hole 100A are covered with a thick or highly viscous insulating film 105 during liquid phase film formation. It is explanatory drawing which shows. As shown in FIG. 6B, when the semiconductor substrate 100 manufactured by the conventional manufacturing method is covered with the insulating film 105, the insulating film 105 is formed at the opening edge C of the opening of the via hole 100A that forms the corner. As a result, the protrusion 105A is formed. For this reason, when the via hole 100A is filled with the conductive material via the insulating film 105, the coverage with the conductive material in the vicinity of the protrusion 105A is lowered, and a discontinuous portion may be generated in the conductive layer of the conductive material.

  On the other hand, as described above, in the semiconductor substrate 14 manufactured by the manufacturing method of the present embodiment, the via angle of the via hole 14A formed by the second process is larger on the second surface T2 side than on the first surface T1 side. . That is, in the manufacturing method of the present embodiment, the semiconductor substrate 14 having the via holes 14A having no corners in the opening on the first surface T1 side can be manufactured by one etching in the second step.

  For this reason, in the manufacturing method of the present embodiment, it is possible to manufacture the semiconductor substrate 14 having the via holes 14A that do not have the corners in the openings by a simple manufacturing method.

FIG. 7 is a schematic diagram showing a state in which the insulating film 30 is formed on the semiconductor substrate 14 of the present embodiment. A method for forming the insulating film 30 is not particularly limited. For example, there are a liquid phase film forming method such as spray coating, and a vapor phase film forming method such as PVD and CVD. The constituent material of the insulating film 30 may be an insulating material. The constituent material of the insulating film 30 is, for example, inorganic such as SiO ₂ or SiOF, organic such as parylene or polyallyl ether, or organic / inorganic hybrid.

  The via hole 14A manufactured by the manufacturing method of the present embodiment does not have a corner at the opening. For this reason, the thickness of the insulating film 30 in the region from the first surface T1 to the side wall S is suppressed from being different from that of other regions. For this reason, it is possible to suppress a short circuit and a leak due to conduction between the semiconductor substrate 14 and the conductive material filled in the via hole 14A and a discontinuous portion in the conductive layer of the conductive material.

  Further, in the mask layer 12, the thickness of the first region A1 continuous along the direction parallel to the first surface T1 with respect to the first through hole 12A may be gradually reduced as the thickness is closer to the first through hole 12A. preferable.

  In the second step, the semiconductor substrate 10 is etched from the first surface T1 side through the first through hole 12A of the mask layer 12 under a certain etching condition, and a via hole 14A is formed in the semiconductor substrate 10. preferable.

  In the second step, the semiconductor substrate 10 is etched from the first surface T1 side through the first through hole 12A of the mask layer 12 by isotropic etching to form a via hole 14A in the semiconductor substrate 10. preferable.

  In the second step, the first surface T1 is formed through the first through-hole 12A of the mask layer 12 by dry etching using an etching gas containing at least one of fluorocarbon, sulfur hexafluoride, and oxygen. It is preferable to etch the semiconductor substrate 10 from the side to form a via hole 14 </ b> A in the semiconductor substrate 10.

  Further, the first process may include a third process, a fourth process, and a fifth process. The third step is a step of forming a positive photoresist layer 17 on the first surface T1 of the semiconductor substrate 10. The fourth step is a step of disposing the photomask 20 having the first light transmission portion 20A on the photoresist layer 17 at a position corresponding to the first through hole 12A in a plane parallel to the first surface T1. The fifth step is a step of exposing the photoresist layer 17 through the photomask 20 to form the mask layer 12 as the photoresist layer 17 from which the exposed region has been removed.

  Further, the photomask 20 includes a first light transmission portion 20A and a first light shielding region P other than the first light transmission portion 20A along a plane parallel to the first surface T1 of the photomask 20. In the first light shielding region P, the second light shielding region P1 continuous to the first light transmitting portion 20A includes a plurality of second light transmitting portions 20B having an opening width smaller than that of the first light transmitting portion 20A.

  For example, the second light-shielding region P1 includes a plurality of second light transmission portions 20B having an opening width smaller than that of the first light transmission portion 20A and having a larger opening width closer to the first light transmission portion 20A.

  For example, each of the plurality of second light transmission portions 20B is concentrically arranged in the second light shielding region P1 with the first light transmission portion 20A as the center.

  For example, each of the plurality of second light transmission portions 20B has a circular shape whose cross-sectional shape parallel to the first surface T1 is smaller in opening width than the first light transmission portion 20A. The plurality of second light transmission portions 20B are arranged radially in the second light shielding region P1 outside the first light transmission portion 20A with the first light transmission portion 20A as the center.

(Second Embodiment)
In the first embodiment, the cross-sectional shape in the thickness direction of the semiconductor substrate 14 at the opening edge of the via hole 14A manufactured by the manufacturing method of the first embodiment is as shown in FIG. 2 from the first surface T1 side. The case where the via angle continuously increases toward the second surface T2 side has been described (see FIG. 2).

  In the present embodiment, the cross-sectional shape in the thickness direction of the semiconductor substrate 15 at the opening edge of the via hole 15A has a via angle that gradually increases from the first surface T1 side to the second surface T2 side as shown in FIG. A case where the shape becomes larger will be described.

  FIG. 8 is an explanatory diagram of the manufacturing method of the present embodiment.

  The manufacturing method of the present embodiment includes a first step and a second step.

  The first step is a step of forming a mask layer 13 on the first surface T1 of the semiconductor substrate 10 (see FIG. 8A). The first step of the present embodiment is the same as the first step of the first embodiment except that the mask layer 13 is used instead of the mask layer 12.

  The mask layer 13 has a first through hole 13A. 13 A of 1st through-holes are holes which penetrate the mask layer 13 in the thickness direction (arrow X direction in FIG. 8). 13 A of 1st through-holes are provided in the position according to the via hole of formation object. The first through hole 13A is the same as the first through hole 12A of the first embodiment.

  The second step is a step of etching the semiconductor substrate 10 from the first surface T1 side of the semiconductor substrate 10 through the first through hole 13A of the mask layer 13 to form a via hole 15A in the semiconductor substrate 10 (FIG. 8). (See (B)).

  The via hole 15A formed by the etching in the second step, like the via hole 14A, is an angle formed between the first surface T1 and the side wall S of the via hole 15A on the second surface T2 side compared to the first surface T1 side ( That is, the via angle is large.

  Specifically, as shown in FIG. 8B, in the via hole 15A, the via angle (α2) on the second surface T2 side is larger than the via angle (α1) on the first surface T1 side. That is, the relationship of α2> α1 is satisfied.

  FIG. 9 is an explanatory diagram of the semiconductor substrate 15 in which the via hole 15A is formed. As shown in FIG. 9, the via angle of the via hole 15A formed by the second step is larger on the second surface T2 side than on the first surface T1 side. For this reason, the opening on the first surface T1 side of the via hole 15A has no corner. The corners are the same as those in the first embodiment.

  In the present embodiment, the cross-sectional shape in the thickness direction of the semiconductor substrate 15 at the opening edge of the via hole 15A has a via angle that gradually increases from the first surface T1 side to the second surface T2 side as shown in FIG. It is a shape that grows.

  In order to form the via hole 15A in the second step, the mask layer 13 prepared in the first step is continuous in the mask layer 13 along the direction parallel to the first surface T1 with respect to the first through hole 13A. The thickness of the first region A1 only needs to be thinner stepwise as it is closer to the first through hole 13A.

  For example, as shown in FIG. 8A, in the mask layer 13, the thickness of the first region A1 continuous along the direction parallel to the first surface T1 with respect to the first through hole 13A in the mask layer 13 is set. It is preferable that the closer to the first through hole 13A, the thinner it is in steps.

  The first region A1 is a region in the mask layer 13 that is continuous in a direction parallel to the first surface T1 with respect to the first through hole 13A, and with respect to the side wall S portion of the via hole 15A formed in the semiconductor substrate 10. Any region corresponding to the thickness direction (arrow X direction) may be used. For this reason, the region between the first regions A1 (the region where the first through holes 13A are not disposed) in the mask layer 13 may be an intermediate region A2 having a constant thickness.

The constituent material of the mask layer 13 is the same as that of the mask layer 12. The mask layer 13 may be made of, for example, SiO ₂ or may be formed using a resist.

  When the mask layer 13 is formed using a resist, the first step includes a third step, a fourth step, and a fifth step.

  FIG. 10 is an explanatory diagram showing an example of the manufacturing method of the present embodiment when the mask layer 13 is formed using a resist.

  First, the first step is performed. In the third step of the first step, a photoresist layer 17 is formed over the semiconductor substrate 10 (see FIG. 10A). The third step is the same as the third step of the first embodiment.

  Next, the 4th process in the 1st process is performed. In the fourth step, a photomask 22 is disposed on the photoresist layer 17 (see FIG. 10B). The photomask 22 has a first light transmission portion 22A. 22 A of 1st light transmissive parts are provided in the position corresponding to the 1st through-hole 13A (namely, via hole 15A) in the surface parallel to the 1st surface T1 of the photomask 22. As shown in FIG.

  The photomask 22 includes a first light transmission portion 22A and a first light shielding region P ′ along a surface parallel to the first surface T1 of the photomask 22.

  22 A of 1st light transmissive parts are the areas | regions which transmit the exposure light used for exposure of the photoresist layer 17 in the 5th process in the photomask 22. FIG. The first light shielding region P ′ is a region that shields the exposure light. The first light shielding region P ′ may be made of a material that shields the exposure light.

In the first light-shielding region P ′, the second light-shielding region P′1 continuous in the direction parallel to the first surface T1 with respect to the first light-transmitting portion 22A has a plurality of opening widths smaller than those of the first light-transmitting portion 22A. Second light transmitting portions 22B _{1 to} 22B ₃ are provided. FIG. 10 shows three types of second light transmission portions 22B _{1 to} 22B ₃ , but is not limited to three types. In the following description, when the plurality of second light transmission portions 22B _{1 to} 22B ₃ are collectively described, they are referred to as second light transmission portions 22B. The second light transmission portion 22B is a region that transmits exposure light. The opening width indicates the length of the region having the smallest opening in the cross section parallel to the first surface T1 in each of the first light transmitting portion 22A and the second light transmitting portion 22B. A region between the second light shielding regions P′1 is a third light shielding region P′2 that shields the exposure light.

In the example shown in FIG. 10, in the second light-shielding region P′1, the second light transmitting portion 22B ₁ to the second light transmitting portion 22B ₃ are arranged in the direction away from the position close to the first light transmitting portion 20A. Arranged in order. That is, in the photomask 22, a plurality of second light transmission portions 22B are provided in the second light shielding region P′1 around the first light transmission portion 22A.

  In the present embodiment, the opening widths of the plurality of second light transmission portions 22B provided in the second light shielding region P′1 are smaller than the opening width of the second through hole 22A and the same opening width.

  Each of the plurality of second light transmission portions 22B only needs to be disposed around the first light transmission portion 22A (that is, the second light shielding region P′1 in the first light shielding region P ′), and the arrangement position thereof is It is not limited.

  For example, the arrangement positions of the plurality of second light transmission parts 22B may be arranged concentrically around the first light transmission part 22A, or may be arranged radially. FIG. 11 is an explanatory diagram of the arrangement of the second light transmission portion 22B.

  In the example shown in FIG. 11A, the second light transmission part 22B is concentrically arranged in the second light-shielding region P′1 around the first light transmission part 22A. In the example shown in FIG. 11A, the plurality of second light transmission portions 20B have the same opening width.

  In the example shown in FIG. 11B, the second light transmission portion 22B has a circular shape in the direction along the first surface T1, and the opening width (that is, the diameter) is larger than that of the first light transmission portion 22A. small. The plurality of second light transmission portions 22B have the same opening width (that is, the same diameter). The second light transmission part 22B is radially arranged in the second light shielding region P′1 around the first light transmission part 22A.

  Returning to FIG. 10B, next, in the fifth step, the photoresist layer 17 is exposed through the photomask 22. The photomask 22 is provided with a first light transmission portion 22A and a second light transmission portion 22B. For this reason, the photoresist layer 17 is exposed by the exposure light transmitted through the first light transmission part 22A and the second light transmission part 22B of the photomask 22. That is, the areas corresponding to the first light transmission part 22A and the second light transmission part 22B in the photoresist layer 17 are exposed.

  And the exposure area | region exposed with exposure light is removed by developing the photoresist layer 17 with an alkaline solution. Thus, in the fifth step, the mask layer 13 is formed as the photoresist layer 17 from which the exposed region has been removed (see FIG. 10C).

  As shown in FIG. 10C, the photoresist layer 17 is exposed through a photomask 22 and developed to obtain the mask layer 13 having the above shape.

  That is, when the photoresist layer 17 is exposed through the photomask 22, an area corresponding to the first light transmission portion 22A is exposed. At the same time, the photoresist layer 17 is exposed through the plurality of second light transmission portions 22B having the same opening width in the second light-shielding region P′1 around the first light transmission portion 22A. Therefore, the first through hole 13A corresponding to the first light transmission portion 22A is formed in the photoresist layer 17, and the thickness of the mask layer 13 that is the photoresist layer 17 in which the first through hole 13A is formed. The cross-sectional shape in the direction (arrow X direction) becomes thinner as it is closer to the first through hole 13A. That is, the cross-sectional shape of the first through hole 13A in the thickness direction (arrow X direction) is such that the opening on the photomask 22 side is the widest and the opening gradually decreases toward the semiconductor substrate 10 side.

  Next, in the second step, the semiconductor substrate 10 is etched from the first surface T1 side of the semiconductor substrate 10 through the first through hole 13A of the mask layer 13 to form a via hole 15A in the semiconductor substrate 10 (FIG. 10). (See (D)). Since the via hole 15A has been described above, the description thereof is omitted.

  Here, as described above, the cross-sectional shape of the first through hole 13A in the mask layer 13 in the thickness direction (arrow X direction) has the widest opening on the photomask 22 side, and the opening toward the semiconductor substrate 10 side. It is a small shape step by step.

  For this reason, during the etching in the second process, the opening width of the first through hole 13A of the mask layer 13 changes stepwise in a certain time. Accordingly, the opening edge on the mask layer 13 side of the via hole 15A is gradually reduced in angle (via angle) formed by the side wall S and the first surface T1. For this reason, when etching the via hole 15A, the corner of the opening edge of the via hole 15A is also removed at the same time.

  Note that the pattern of the photomask 22 by the first light transmitting portion 22A and the second light transmitting portion 22B may be any pattern that provides the mask layer 13 capable of forming the via hole 15A in the second step. It is not limited to the form shown in FIG.

  Next, in the second step, the semiconductor substrate 10 is etched from the first surface T1 side of the semiconductor substrate 10 through the first through holes 13A of the mask layer 13 to form via holes 15A in the semiconductor substrate 10. Since the via hole 15A has been described above, the description thereof is omitted.

  The etching conditions in the second step are the same as those in the first embodiment.

  That is, in the present embodiment, in the second step, the via hole 15A is formed by continuously performing etching under certain etching conditions without switching or changing the etching recipe during the etching.

  As described above, in the present embodiment, the cross-sectional shape in the thickness direction of the semiconductor substrate 15 at the opening edge of the via hole 15A is from the first surface T1 side to the second surface T2 side as shown in FIG. This is a shape in which the via angle gradually increases. Also in this case, the present embodiment provides the same effects as those of the first embodiment.

  Further, the via hole 15A manufactured by the manufacturing method of the present embodiment does not have a corner at the opening. For this reason, as shown in FIG. 7, the thickness of the insulating film 30 in the region from the first surface T <b> 1 to the side wall S is suppressed from being different from the other regions. For this reason, it is possible to suppress a short circuit and a leak due to conduction between the semiconductor substrate 15 and the conductive material filled in the via hole 15A, and a discontinuous portion in the conductive layer of the conductive material.

  As mentioned above, although embodiment for implementing invention was described, this invention is not limited to embodiment mentioned above. Modifications can be made without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 12, 13 Mask layer 12A, 13A 1st through-hole 14, 15 Semiconductor substrate 14A, 15A Via hole 17 Photoresist layer 20, 22 Photomask 20A, 22A 1st light transmission part 20B, 22B 2nd light transmission part

Japanese Patent No. 5560877

Claims (10)

A first step of forming a mask layer having a first through hole on a first surface of a semiconductor substrate;
A second step of etching the semiconductor substrate from the first surface side of the semiconductor substrate through the first through hole of the mask layer to form a via hole in the semiconductor substrate;
Including
The mask layer is for forming the via hole in which the angle formed between the first surface and the sidewall of the via hole is larger on the second surface side facing the first surface of the semiconductor substrate than on the first surface side. A method for manufacturing a semiconductor substrate, which is a layer.   The thickness of the first region in the mask layer that is continuous along the direction parallel to the first surface with respect to the first through hole is thinner stepwise or continuously as the thickness is closer to the first through hole. Item 12. A method for manufacturing a semiconductor substrate according to Item 1.   The said 2nd process etches the said semiconductor substrate from the said 1st surface side through the said 1st through-hole of the said mask layer on fixed etching conditions, The said via hole is formed in the said semiconductor substrate. A method for manufacturing a semiconductor substrate according to claim 1.   The said 2nd process etches the said semiconductor substrate from the said 1st surface side through the said 1st through-hole of the said mask layer by isotropic etching, The said via hole is formed in the said semiconductor substrate. The manufacturing method of the semiconductor substrate of any one of Claims 1-3.   In the second step, the first surface side is formed through the first through hole of the mask layer by dry etching using an etching gas containing at least one of fluorocarbon, sulfur hexafluoride, and oxygen. The method of manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor substrate is etched to form the via hole in the semiconductor substrate. The first step includes
A third step of forming a positive photoresist layer on the first surface of the semiconductor substrate;
A fourth step of disposing a photomask having a first light transmission portion on the photoresist layer at a position corresponding to the first through hole in a plane parallel to the first surface;
A fifth step of exposing the photoresist layer through the first light transmission portion of the photomask to form the mask layer as the photoresist layer from which an exposed region has been removed;
The manufacturing method of the semiconductor substrate of any one of Claims 1-4 containing this. The photomask has the first light transmission portion and a first light shielding region other than the first light transmission portion along a plane parallel to the first surface of the photomask,
7. The semiconductor substrate according to claim 6, wherein the second light shielding region that is continuous with the first light transmitting portion in the first light shielding region includes a plurality of second light transmitting portions having an opening width smaller than that of the first light transmitting portion. Manufacturing method.   8. The second light-shielding region according to claim 7, wherein the second light-shielding region includes a plurality of second light transmission parts having an opening width smaller than that of the first light transmission part and having a larger opening width closer to the first light transmission part. A method for manufacturing a semiconductor substrate.   9. The method of manufacturing a semiconductor substrate according to claim 7, wherein each of the plurality of second light transmission portions is disposed in the second light shielding region concentrically with the first light transmission portion as a center. . Each of the plurality of second light transmission parts has a circular shape with a cross-sectional shape parallel to the first surface and an opening width smaller than that of the first light transmission part,
The plurality of second light transmission parts are arranged radially in the second light-shielding region outside the first light transmission part with the first light transmission part as a center. A method for manufacturing a semiconductor substrate according to claim 1.