JP2017085064A - Mounting structure of integrated circuit element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a mounting structure of an integrated circuit element which allows for easy arrangement of a thin film element having an inductor and one capacitor electrode, between an integrated circuit element and a mounting board, while configuring a circuit of an inductor and a capacitor between the integrated circuit element and mounting board.SOLUTION: A mounting structure of an integrated circuit element includes an integrated circuit element 1 having an external terminal 51, a mounting board 2 on which a first capacitor electrode CP1 is formed, and a thin film element 101 having a first principal surface S1 and a second principal surface S2. The thin film element 101 has an insulating board, a thin fil inductor formed by thin film process, a second capacitor electrode formed on the insulating board, and connection terminals P11, P12 formed on the first principal surface S1 of the thin film element 101. The connection terminals P11, P12 of the thin film element 101 are connected with the external terminal 51, and the first capacitor electrode CP1 and a second capacitor electrode CP2 face at least partially.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an integrated circuit element mounting structure, and more particularly to an integrated circuit element mounting structure in which, for example, a thin film element formed by a thin film process is disposed between an integrated circuit element and a mounting substrate.

  Conventionally, when an integrated circuit element is mounted on a mounting substrate via a solder ball, a surface mounting in which connection terminals are formed on five surfaces at both ends, such as a multilayer ceramic capacitor, between the integrated circuit element and the mounting substrate A method of arranging parts is known (Patent Document 1).

  In the mounting structure of the integrated circuit element, the surface-mounted component can be connected to one or both of the integrated circuit element and the mounting substrate.

JP 2005-150283 A

  However, when the integrated circuit element is mounted on the mounting board via the solder balls, the gap between the integrated circuit element and the mounting board is very small. Therefore, it is not realistic to arrange the surface mount component between the integrated circuit element and the mounting substrate.

  In addition, even when the above surface mount components can be arranged between the integrated circuit element and the mounting substrate, the mounting of the surface mount components depends on the amount of conductive bonding material (solder) used to connect the connection terminals. The state may vary.

  An object of the present invention is to provide an integrated circuit element mounting structure in which a thin film element can be easily disposed between an integrated circuit element and a mounting substrate, and the thin film element can be stably mounted. .

(1) The mounting structure of the integrated circuit element of the present invention is as follows:
An integrated circuit element;
A mounting board having mounting terminals;
An integrated circuit element mounting structure comprising:
A thin film element having a first main surface and a second main surface facing the first main surface;
A first capacitor electrode formed on the integrated circuit element;
Further comprising
The thin film element is
An insulating substrate having a first surface and a second surface;
A thin film inductor formed by a thin film process on either the first surface or the second surface of the insulating substrate;
A second capacitor electrode formed on the second surface of the insulating substrate;
A connection terminal formed on the first main surface of the thin film element and connected to at least one of the thin film inductor and the second capacitor electrode;
Have
The connection terminal is connected to the mounting terminal,
The first capacitor electrode and the second capacitor electrode are at least partially opposed to each other.

  With this configuration, a thin film element that can be easily arranged in the gap between the integrated circuit element and the mounting substrate can be realized. Further, since it is not necessary to provide a connection terminal on the second main surface of the thin film element and connect it to the external terminal of the integrated circuit element, the thickness of the thin film element can be further reduced as compared with the case where a capacitor is provided inside the thin film element. . Furthermore, with this configuration, the number of passive elements mounted on the mounting substrate can be reduced, and high density and high integration can be achieved.

(2) The integrated circuit element mounting structure of the present invention has the following structure:
An integrated circuit element having an external terminal;
A mounting board;
An integrated circuit element mounting structure comprising:
A thin film element having a first main surface and a second main surface facing the first main surface;
A first capacitor electrode formed on the mounting substrate;
Further comprising
The thin film element is
An insulating substrate having a first surface and a second surface;
A thin film inductor formed by a thin film process on either the first surface or the second surface of the insulating substrate;
A second capacitor electrode formed on the second surface of the insulating substrate;
A connection terminal formed on the first main surface of the thin film element and connected to at least one of the thin film inductor and the second capacitor electrode;
Have
The connection terminal is connected to the external terminal,
The first capacitor electrode and the second capacitor electrode are at least partially opposed to each other.

  With this configuration, a thin film element that can be easily arranged in the gap between the integrated circuit element and the mounting substrate can be realized. Further, since it is not necessary to provide a connection terminal on the second main surface of the thin film element and connect it to the mounting terminal of the mounting substrate, the thickness of the thin film element can be further reduced as compared with the case where a capacitor is provided inside the thin film element. Furthermore, with this configuration, the number of passive elements mounted on the mounting substrate can be reduced, and high density and high integration can be achieved.

(3) In the above (1) or (2), the thin film element further includes a dielectric member, and at least a part of the dielectric member is between the first capacitor electrode and the second capacitor electrode. You may arrange in.

(4) In any one of (1) to (3), the thin film inductor is formed on the first surface of the insulating substrate, and the thin film inductor and the second capacitor electrode are formed on the insulating substrate. It is preferable to connect via an interlayer connection conductor provided. With this configuration, the area of the thin film inductor and capacitor formation region in plan view can be reduced.

(5) In the above (4), the number of the thin film inductors may be plural.

(6) In any one of the above (2) to (5), the integrated circuit element further includes a power supply circuit, the mounting substrate further includes a ground, the thin film inductor is connected to the power supply circuit, The first capacitor electrode is preferably connected to ground. With this configuration, the thin film inductor and the capacitor constitute a low pass filter or a smoothing circuit.

  ADVANTAGE OF THE INVENTION According to this invention, the mounting structure of the integrated circuit element which can arrange | position a thin film element easily between an integrated circuit element and a mounting substrate, and enabled the thin film element to be mounted stably is realizable.

FIG. 1 is a front view showing a part in which a thin film element 101 is arranged between an integrated circuit element 1 and a mounting substrate 2 in an electronic apparatus 201 according to the first embodiment. FIG. 2 is an enlarged view of a portion Z1 in FIG. FIG. 3 is a cross-sectional view of the thin film element 101 according to the first embodiment. FIG. 4 is an exploded perspective view of a part of the mounting substrate 2 and the thin film element 101. FIG. 5A is a circuit diagram of a portion where the thin film element 101 is disposed between the integrated circuit element 1 and the mounting substrate 2 in the electronic apparatus 201, and FIG. 3 is a circuit diagram of the thin film element 101. FIG. FIG. 6A is a front view showing a state in which the integrated circuit element 1 is mounted on the mounting substrate 2 using the thin film element 101, and FIG. 6B is a diagram of the integrated circuit element 1 mounted on the mounting substrate 2. It is a front view which shows the state after reflow. FIG. 7 is a cross-sectional view of the thin film element 102 according to the second embodiment. FIG. 8 is an exploded perspective view of a part of the mounting substrate 2 and the thin film element 102. FIG. 9A is a circuit diagram of a portion in which the thin film element 102 is disposed between the integrated circuit element 1 and the mounting substrate 2 in the second embodiment, and FIG. 3 is a circuit diagram of a part and a thin film element 102. FIG. FIG. 10 is a front view showing a portion in which the thin film element 103 is arranged between the integrated circuit element 1 and the mounting substrate 2 in the electronic apparatus 203 according to the third embodiment. FIG. 11 is an enlarged view of a portion Z2 in FIG. FIG. 12 is a cross-sectional view of the thin film element 103 according to the third embodiment. FIG. 13A is a bottom view of the microprocessor chip 3 such as an APU according to the fourth embodiment, and FIG. 13B is a front view of the microprocessor chip 3. FIG. 14 is a front view showing a state after the reflow of the microprocessor chip 3 mounted on the mounting board 2. FIG. 15 is a conceptual diagram showing a connection structure of a smoothing circuit to the microprocessor chip 3 according to the fourth embodiment.

  Hereinafter, several specific examples will be given with reference to the drawings to show a plurality of modes for carrying out the present invention. In each figure, the same reference numerals are assigned to the same portions. In consideration of ease of explanation or understanding of the main points, the embodiments are shown separately for convenience, but the components shown in different embodiments can be partially replaced or combined. In the second and subsequent embodiments, description of matters common to the first embodiment is omitted, and only different points will be described. In particular, the same operation effect by the same configuration will not be sequentially described for each embodiment.

<< First Embodiment >>
FIG. 1 is a front view showing a part in which a thin film element 101 is arranged between an integrated circuit element 1 and a mounting substrate 2 in an electronic apparatus 201 according to the first embodiment. FIG. 2 is an enlarged view of a portion Z1 in FIG. 1 and 2, the thickness of each part is exaggerated, and the same applies to front views and cross-sectional views in the following embodiments. Moreover, in FIG. 1 and FIG. 2, illustration of the connection terminal P15 is abbreviate | omitted in order to avoid complication of a figure, and it is the same also about the front view in each subsequent embodiment. The thin film element 101 is an electronic component that is disposed between the integrated circuit element and the mounting substrate and includes a thin film inductor and a part of the capacitor electrode.

  The electronic device 201 includes an integrated circuit element 1, a mounting substrate 2, and a thin film element 101. A plurality of external terminals 51 and 53 are formed on the lower surface of the integrated circuit element 1, and a first capacitor electrode CP 1 and a plurality of mounting terminals 43 are formed on the upper surface of the mounting substrate 2. The integrated circuit element 1 is, for example, a semiconductor microprocessor chip or a semiconductor IC chip, and the mounting board 2 is, for example, a printed wiring board.

  The thin film element 101 is an insulating thin plate having a first main surface S1 and a second main surface S2 facing the first main surface S1 and having a square shape in plan view. On the first main surface S1 of the thin film element 101, connection terminals P11, P12 and the like having a square planar shape are formed. The connection terminals P11, P12, and the like are obtained by coating a conductive pattern mainly composed of Cu with a plating film such as Ni or Au.

  As shown in FIGS. 1 and 2, the connection terminals P <b> 11 and P <b> 12 of the thin film element 101 are connected to the external terminals 51 of the integrated circuit element 1 through the conductive bonding material 31, respectively. The surface S2 is in contact with the first capacitor electrode CP1 of the mounting substrate 2. In addition, the external terminal 53 of the integrated circuit element 1 is connected to the mounting terminal 43 of the mounting substrate 2 via the conductive bonding material 33. As will be described in detail later, the thin film element 101 includes a second capacitor electrode CP2 therein. The first capacitor electrode CP1 and the second capacitor electrode CP2 are at least partially opposed to each other to form a capacitor C1. The conductive bonding materials 31 and 33 are, for example, solder. In the present embodiment, the first capacitor electrode CP1 is connected to the ground of the mounting substrate 2.

  FIG. 3 is a cross-sectional view of the thin film element 101 according to the first embodiment. FIG. 4 is an exploded perspective view of a part of the mounting substrate 2 and the thin film element 101. In FIG. 3, the first thin film insulator layer 11 and the second thin film insulator layer 12 are not shown.

  The thin film element 101 includes an insulating substrate 21, a first thin film insulator layer 11, a second thin film insulator layer 12, a dielectric member 13, a plurality of thin film inductors L1, L2, L3, L4, a second capacitor electrode CP2, and a plurality of capacitor elements CP2. Interlayer connection conductors V11, V12, V13, V14, V15, V21, V22, V23, and V24.

  The insulating substrate 21 is an insulating thin plate having a square planar shape and has a first surface PS1 and a second surface PS2. The insulating substrate 21 is, for example, a high resistance Si substrate.

  Thin film inductors L <b> 1 to L <b> 4 are formed on the first surface PS <b> 1 of the insulating substrate 21. The thin film inductors L1 to L4 are passive elements formed by a thin film process, and are a loop-shaped conductor pattern of about 1 turn. The thin film inductors L1 to L4 are, for example, Cu films.

  A second capacitor electrode CP2 is formed on the second surface PS2 of the insulating substrate 21 with the second thin film insulator layer 12 interposed therebetween. The second thin film insulator layer 12 is formed on the entire second surface PS2 of the insulating substrate 21, and the second capacitor electrode CP2 is formed on the entire lower surface of the second thin film insulator layer 12. The second thin film insulator layer 12 is, for example, a polyimide resin or an epoxy resin. The second capacitor electrode CP2 is a conductor film formed by a thin film process, and for example, a material such as Pt, Au, or Ru that has oxidation resistance against heat treatment is preferable.

A dielectric member 13 is formed on the lower surface of the second capacitor electrode CP2. The dielectric member 13 is a material having a high dielectric constant, such as barium strontium titanate ((Ba _x , Sr _1-x ) TiO ₃ , hereinafter referred to as “BST”).

  The first thin film insulator layer 11 is formed on the first surface PS1 of the insulating substrate 21. The thin film inductors L1 to L4 are entirely covered with a first thin film insulator layer 11 as shown in FIG. The first thin film insulator layer 11 is preferably magnetic ferrite, for example, in order to obtain a predetermined large inductance value.

  Connection terminals P11, P12, P13, P14, and P15 are formed in an island shape on the surface of the first thin film insulator layer 11 (the first main surface S1 of the thin film element 101). The connection terminals P11 to P14 are connected to the first ends of the thin film inductors L1 to L4 via the interlayer connection conductors V11, V12, V13, and V14, respectively. The second ends of the thin film inductors L1 to L4 are connected to the second capacitor electrode CP2 via interlayer connection conductors V21, V22, V23, and V24 provided on the insulating substrate 21, respectively.

  As shown in FIG. 2 and FIG. 4, the thin film element 101 is disposed between the integrated circuit element 1 and the mounting substrate 2, so that the first capacitor electrode CP <b> 1 and the second capacitor electrode CP <b> 2 serve as the dielectric member 13. Opposite each other with a sandwich. For this reason, a capacitance is formed in a portion where the first capacitor electrode CP1 and the second capacitor electrode CP2 are opposed to each other. Therefore, the capacitor C1 is configured by the first capacitor electrode CP1, the second capacitor electrode CP2, and the dielectric member 13 disposed between the first capacitor electrode CP1 and the second capacitor electrode CP2.

  FIG. 5A is a circuit diagram of a portion where the thin film element 101 is disposed between the integrated circuit element 1 and the mounting substrate 2 in the electronic apparatus 201, and FIG. 3 is a circuit diagram of the thin film element 101. FIG.

  The integrated circuit element 1 has a power supply circuit 80 such as a DC / DC converter. The power supply circuit 80 is connected to the power supply input terminal Vin and the connection terminals P11, P12, P13, and P14 of the thin film element 101, respectively. The connection terminal P15 of the thin film element 101 is connected to the integrated circuit element 1. The first capacitor electrode of the mounting substrate 2 is connected to the ground. The power input terminal Vin is an input terminal connected to a power circuit on the mounting board 2 side, for example.

  As shown in FIG. 5A, the inductor L of the thin film element 101 is connected to the power supply circuit 80, and the capacitor C of the thin film element 101 is connected to the ground of the mounting substrate. Therefore, in this embodiment, the inductor L and the capacitor C constitute a low-pass filter or a smoothing circuit.

  Specifically, as shown in FIG. 5B, the first ends of the four thin film inductors L1, L2, L3, and L4 are conducted to the connection terminals P11, P12, P13, and P14, and the thin film inductors L1, L2, and L4 are electrically connected. The second ends of L3 and L4 are commonly connected and conducted to the connection terminal P15. The first end of the capacitor C1 is conducted to the ground, and the second end of the capacitor C1 is conducted to the connection terminal P15.

  With this structure, the time constant of the thin film element 101 can be switched by selectively connecting the power supply circuit 80 and the connection terminals P11, P12, P13, and P14. Further, when the power supply circuit 80 and the four thin film inductors L1, L2, L3, and L4 are connected in parallel, the direct current resistance (DCR) can be reduced.

  Next, a mounting structure of the integrated circuit element 1 using the thin film element 101 will be described with reference to the drawings. FIG. 6A is a front view showing a state in which the integrated circuit element 1 is mounted on the mounting substrate 2 using the thin film element 101, and FIG. 6B is a diagram of the integrated circuit element 1 mounted on the mounting substrate 2. It is a front view which shows the state after reflow.

  As shown in FIG. 6A, the integrated circuit element 1 is mounted on the upper surface of the mounting substrate 2. The integrated circuit element 1 is a BGA (Ball grid array) type package, and solder bumps 33 </ b> B are formed on the external terminals 53 of the integrated circuit element 1. The integrated circuit element 1 is mounted face-down on the mounting substrate 2 via solder bumps 33B. The solder bump 33 </ b> B is in contact with the mounting terminal 43 of the mounting substrate 2.

  A thin film element 101 is disposed between the integrated circuit element 1 and the mounting substrate 2. Solder bumps 31 </ b> B are formed on the connection terminals P <b> 11 to P <b> 15 of the thin film element 101. The solder bump 31B is in contact with the external terminal 51 of the integrated circuit element 1, and the second main surface S2 of the thin film element 101 is in contact with the first capacitor electrode CP1 of the mounting substrate 2.

  Thereafter, as shown in FIG. 6B, the integrated circuit element 1 is mounted on the mounting substrate 2 by a reflow process.

  More specifically, the solder bump 31B is melted into the solder 31S by the reflow process. The solder 31S is electrically connected between the connection terminals P11 to P15 of the thin film element 101 and the external terminal 51 and is structurally joined. The second main surface S2 of the thin film element 101 is in contact with the first capacitor electrode CP1 of the mounting substrate 2 even after the reflow process. By the reflow process, the solder bumps 33B are melted to become solder 33S. The solder 33S is electrically connected between the external terminal 53 and the mounting terminal 43 and is structurally joined.

  As shown in FIG. 6A, the total height Ta of the thin film element 101 and the solder bump 31B (the total length in the Z direction of the thin film element 101 and the solder bump 31B in FIG. 6A) is If the height Tb of the solder bumps 33B before the reflow process (the length in the Z direction of the solder bumps 33B in FIG. 6A) is less than (Ta ≦ Tb), the gap between the integrated circuit element 1 and the mounting substrate 2 The thin film element 101 can be easily arranged. Considering that the solder bump 33B is reduced after the reflow process, the total height Ta of the thin film element 101 and the solder bump 31B is 0.7 times the height Tb of the solder bump 33B before the reflow process. As described above, it is preferably 1 time or less (0.7 Tb ≦ Ta ≦ Tb), and more preferably 0.75 time or more and 0.85 time or less (0.75 Tb ≦ Ta ≦ 0.85 Tb).

  The solder bump 31B may be formed on the external terminal 51 of the integrated circuit element 1, and the solder bump 33B may be formed on the mounting terminal 43 of the mounting substrate 2. Further, instead of the solder bumps 31B and 33B, solder balls may be disposed between the external terminals 53 and the mounting terminals 43, or between the external terminals 51 and the connection terminals P11 to P15. Also in this case, the total height Tc of the thin film element 101 and the solder ball is 0.7 times or more the height Td of the solder ball disposed between the external terminal 53 and the mounting terminal 43 before the reflow process, It is preferable that it is 1 time or less (0.7Td ≦ Tc ≦ Td).

  According to the mounting structure of the integrated circuit element 1 according to the present embodiment, the following effects are obtained.

(A) The thin film element 101 according to the present embodiment includes thin film inductors L1 to L4 and a second capacitor electrode CP2 formed by a thin film process on the first surface PS1 and the second surface PS2 of the insulating substrate 21. With this configuration, the thin film element 101 that can be easily disposed in the gap between the integrated circuit element 1 and the mounting substrate 2 can be realized.

(B) In the present embodiment, the first connection terminals P <b> 11 to P <b> 15 formed on the first main surface S <b> 1 of the thin film element 101 are connected to the external terminal 51 of the integrated circuit element 1. In this configuration, the connection terminal is not formed on the end face of the thin film element 101, and the conductive bonding material 31 is prevented from spreading on the end face of the thin film element 101, so that the mounting state of the thin film element 101 is stable.

(C) Further, in the present embodiment, the first capacitor electrode CP1 constituting a part of the capacitor C1 is formed on the upper surface of the mounting substrate 2, and the second main surface S2 of the thin film element 101 is in contact with the first capacitor electrode CP1. It touches. In this configuration, since it is not necessary to provide a connection terminal on the second main surface S2 of the thin film element 101 and connect it to the mounting terminal of the mounting substrate 2, compared to the case where the first capacitor electrode CP1 is provided inside the thin film element 101. Further, the thickness of the thin film element can be further reduced. Also, with this configuration, the capacitor C1 can be disposed in the shortest distance to the circuit formed on the mounting substrate 2, so that the parasitic inductance of the capacitor C1 can be reduced and a circuit with excellent high frequency characteristics can be realized. When a low-pass filter or a smoothing circuit is configured with the thin film inductors L1 to L4 and the capacitor C1 as in this embodiment, it is unnecessary if a large parasitic inductance is given to the shunt-connected capacitor C1. A pole is generated and the desired low-pass filter function is not achieved. Therefore, the above configuration is particularly useful when the low-pass filter or the smoothing circuit is configured by the thin film inductors L1 to L4 and the capacitor C1.

(D) In this embodiment, the thin film element 101 is connected between the integrated circuit element 1 and the mounting substrate 2. In general, when no thin film element is disposed between the integrated circuit element 1 and the mounting substrate 2, the amount of the conductive bonding material (large) for bonding between the external terminal of the integrated circuit element 1 and the mounting terminal of the mounting substrate. The gap between the integrated circuit element 1 and the mounting substrate 2 varies due to the difference in the difference in height). On the other hand, in the present embodiment, since the thin film element 101 is disposed between the integrated circuit element 1 and the mounting substrate 2, a certain gap can be secured between the integrated circuit element 1 and the mounting substrate 2. That is, the thin film element 101 functions as a spacer. Furthermore, with this configuration, the number of passive elements mounted on the mounting substrate 2 can be reduced, and high density and high integration can be achieved. Moreover, according to this embodiment, compared with the case where a passive element is mounted on the mounting substrate 2, the number of connection points by the conductive bonding material can be reduced, and thus connection reliability is improved.

(E) In the thin film element 101, thin film inductors L1 to L4 are formed on the first surface PS1 of the insulating substrate 21, and a capacitor C1 is formed on the second surface PS2 of the insulating substrate 21. Therefore, the area in plan view of the formation region of the thin film inductors L1 to L4 and the capacitor C1 can be reduced.

(F) In the thin film element 101, the second thin film insulator layer 12 and the insulating substrate 21 are disposed between the first thin film insulator layer 11 made of magnetic ferrite and the first capacitor electrode CP1. . In general, when a coiled inductor is formed inside a magnetic material, if a conductor pattern such as an electrode is formed on the surface of the magnetic material, the magnetic field generated in the inductor is affected by the conductor pattern (eddy currents). The Q value of the inductor tends to decrease due to generation and the conductor pattern contributing to magnetic field radiation. On the other hand, in the present embodiment, the second thin film insulator layer 12 having a low magnetic permeability and the insulating substrate 21 are sandwiched between the first thin film insulator layer 11 having a high magnetic permeability and the second capacitor electrode CP2. Thus, the thin film inductors L1 to L4 and the capacitor C1 are magnetically separated. Therefore, the magnetic field generated in the thin film inductors L1 to L4 is suppressed from being affected by the capacitor C1, and a decrease in the Q value of the thin film inductors L1 to L4 can be suppressed.

<< Second Embodiment >>
In the second embodiment, an example in which the shape and number of thin film inductors and capacitors included in the thin film element are different from those in the first embodiment will be described.

  FIG. 7 is a cross-sectional view of the thin film element 102 according to the second embodiment. FIG. 8 is an exploded perspective view of a part of the mounting substrate 2 and the thin film element 102. In FIG. 8, the first thin film insulator layer 11 and the second thin film insulator layer 12 are not shown.

  The thin film element 102 includes an insulating substrate 21, a first thin film insulator layer 11, a second thin film insulator layer 12, a dielectric member 13, a plurality of thin film inductors L1 and L2, a plurality of second capacitor electrodes CP21 and CP22, and a plurality of thin film elements. Interlayer connection conductors V11, V12, V13, V14, V23, and V24.

  Thin film inductors L 1 and L 2 are formed on the first surface PS 1 of the insulating substrate 21. The thin film inductors L1 and L2 are passive elements formed by a thin film process, and are spiral conductor patterns of about 1.5 turns.

  Second capacitor electrodes CP21 and CP22 are formed on the second surface PS2 of the insulating substrate 21 with the second thin film insulator layer 12 interposed therebetween. The second thin film insulator layer 12 is formed on the entire second surface PS2 of the insulating substrate 21, and the second capacitor electrodes CP21 and CP22 are formed on the lower surface of the second thin film insulator layer 12. A dielectric member 13 is formed on the lower surface of the second capacitor electrodes CP21 and CP22.

  Connection terminals P <b> 11 to P <b> 14 are formed on the surface of the first thin film insulator layer 11. The connection terminals P11 and P12 are connected to the first ends of the thin film inductors L1 and L2 via the interlayer connection conductors V11 and V12, respectively. The connection terminals P13 and P14 are connected to the second ends of the thin film inductors L1 and L2 via the interlayer connection conductors V13 and V14, respectively. The second ends of the thin film inductors L1 and L2 are connected to the second capacitor electrodes CP21 and CP22 via interlayer connection conductors V23 and V24 provided on the insulating substrate 21, respectively.

  As shown in FIG. 8, by disposing the thin film element 102 between the integrated circuit element 1 and the mounting substrate 2, a part of the first capacitor electrode CP <b> 1 and the second capacitor electrode CP <b> 21 are formed on the dielectric member 13. Opposing each other across a part. For this reason, a capacitance is formed in a portion where the first capacitor electrode CP1 and the second capacitor electrode CP21 are opposed to each other. Therefore, the capacitor C1 is configured by the first capacitor electrode CP1, the second capacitor electrode CP21, and the dielectric member 13 disposed between the first capacitor electrode CP1 and the second capacitor electrode CP21.

  Further, since the thin film element 102 is disposed between the integrated circuit element 1 and the mounting substrate 2, a part of the first capacitor electrode CP 1 and a part of the second capacitor electrode CP 22 sandwich a part of the dielectric member 13. Facing each other. For this reason, a capacitance is formed in a portion where the first capacitor electrode CP1 and the second capacitor electrode CP22 are opposed to each other. Accordingly, the capacitor C2 is configured by the first capacitor electrode CP1, the second capacitor electrode CP22, and the dielectric member 13 disposed between the first capacitor electrode CP1 and the second capacitor electrode CP22.

  FIG. 9A is a circuit diagram of a portion in which the thin film element 102 is disposed between the integrated circuit element 1 and the mounting substrate 2 in the second embodiment, and FIG. 3 is a circuit diagram of a part and a thin film element 102. FIG.

  In this embodiment, a power supply circuit 81 and a thin film element 102 are provided. The power supply circuit 81 is connected to the power input terminal Vin and the connection terminals P11 and P12 of the thin film element 102, respectively. The power supply circuit 81 is, for example, a step-down DC / DC converter included in an integrated circuit element.

  The power supply circuit 81 includes a plurality of control circuits 71 and 72 and a plurality of switch elements T1a, T1b, T2a, and T2b. The switch elements T1a, T1b, T2a, T2b are three-terminal active elements, for example, power MOS-FETs.

  The first ends of the switch elements T1a and T2a are connected to the power input terminal Vin, respectively, and the second ends of the switch elements T1a and T2a are connected to the first ends of the switch elements T1b and T2b, respectively. The second ends of the switch elements T1b and T2b are respectively connected to the ground. The third ends of the switch elements T1a and T2a are connected to the control circuits 71 and 72, respectively, and the third ends of the switch elements T1b and T2b are connected to the control circuits 71 and 72, respectively. The connection point between the second end of the switch element T1a and the first end of the switch element T1b is connected to the connection terminal P11 of the thin film element 102, and the connection between the second end of the switch element T2a and the first end of the switch element T2b. The point is connected to the connection terminal P12 of the thin film element 102.

  As shown in FIGS. 9A and 9B, the first ends of the two thin film inductors L1 and L2 are electrically connected to the connection terminals P11 and P12, and the second ends of the thin film inductors L1 and L2 are connected to the connection terminal P13. , P14. Both ends of the capacitor C1 are electrically connected to the connection terminal P13 and the ground of the mounting substrate, and both ends of the capacitor C2 are electrically connected to the connection terminal P14 and the ground of the mounting substrate. In the present embodiment, the connection terminals P13 and P14 are connected to the output terminals Vout1 and Vout2.

  Therefore, the thin film inductor L1 and the capacitor C1 constitute a smoothing circuit, and the thin film inductor L2 and the capacitor C2 constitute a smoothing circuit. With this configuration, a 1-input 2-output circuit including a DC / DC converter is configured, and the voltage input to the power input terminal Vin is converted to output two individual power supply voltages from the output terminals Vout1 and Vout2. it can.

  As shown in the present embodiment, the first capacitor electrode and the second capacitor electrode constituting the capacitors C1 and C2 may be configured to face each other at least partially.

  Further, as shown in the present embodiment, it is sufficient that at least a part of the dielectric member 13 is disposed in a facing portion between the first capacitor electrode and the second capacitor electrode. That is, the dielectric member 13 may be formed at a portion other than the facing portion between the first capacitor electrode and the second capacitor electrode. In addition, the dielectric member 13 may be formed only at a part of the facing portion between the first capacitor electrode and the second capacitor electrode. As described in detail later, the dielectric member 13 is not essential in the present invention.

<< Third Embodiment >>
In the third embodiment, an example is shown in which a thin film element not provided with a second thin film insulator layer is disposed between an integrated circuit element and a mounting substrate.

  FIG. 10 is a front view showing a portion in which the thin film element 103 is arranged between the integrated circuit element 1 and the mounting substrate 2 in the electronic apparatus 203 according to the third embodiment. FIG. 11 is an enlarged view of a portion Z2 in FIG.

  The electronic device 203 includes an integrated circuit element 1, a mounting substrate 2, and a thin film element 103. A first capacitor electrode CP1 and a plurality of external terminals 51 and 53 are formed on the lower surface of the integrated circuit element 1, and a plurality of mounting terminals 41 and 43 are formed on the upper surface of the mounting substrate 2.

  The thin film element 103 is an insulating thin plate having a square planar shape. The first main surface S1 of the thin film element 103 is formed with connection terminals P11, P12 and the like having a square planar shape, and the second main surface S2 of the thin film element 103 is a second capacitor electrode having a square planar shape. CP2 is formed.

  As shown in FIGS. 10 and 11, the connection terminals P <b> 11 and P <b> 12 of the thin film element 103 are connected to the mounting terminal 41 of the mounting substrate 2 through the conductive bonding material 31, respectively.

  FIG. 12 is a cross-sectional view of the thin film element 103 according to the third embodiment.

  The thin film element 103 includes an insulating substrate 21, a first thin film insulator layer 11, a dielectric member 13, a plurality of thin film inductors L1, L2, etc., a second capacitor electrode CP2, and a plurality of interlayer connection conductors V11, V22.

  Thin film inductors L1, L2 and the like are formed on the first surface PS1 of the insulating substrate 21. A second capacitor electrode CP2 is formed on the second surface PS2 of the insulating substrate 21. The second capacitor electrode CP2 is formed on the second surface PS2 of the insulating substrate 21. A dielectric member 13 is formed on the lower surface of the second capacitor electrode CP2.

  As shown in FIG. 11, by mounting the thin film element 103 on the mounting substrate 2, the thin film element 103 is disposed between the integrated circuit element 1 and the mounting substrate 2. At this time, the first capacitor electrode CP1 and the second capacitor electrode CP2 face each other, and a capacitance is formed between the first capacitor electrode CP1 and the second capacitor electrode CP2. Therefore, the capacitor C1 is configured by the first capacitor electrode CP1, the second capacitor electrode CP2, and the dielectric member 13 disposed between the first capacitor electrode CP1 and the second capacitor electrode CP2. In the present embodiment, a gap is formed between the first capacitor electrode CP1 and the second capacitor electrode CP2.

  Thus, the second thin film insulator layer is not essential in the present invention. Since the thin film element 103 does not include the second thin film insulator layer, the thickness can be further reduced as compared with the thin film element 101 according to the first embodiment including the second thin film insulator layer.

  As shown in the present embodiment, the first capacitor electrode CP1 may be formed in the integrated circuit element 1. The second capacitor electrode CP2 may be directly formed on the second surface PS2 of the insulating substrate 21.

  In the present invention, the dielectric member 13 is not essential. A gap may be formed between the first capacitor electrode CP1 and the second capacitor electrode CP2, and another member may be disposed between the first capacitor electrode CP1 and the second capacitor electrode CP2.

<< Fourth Embodiment >>
The fourth embodiment shows an example in which the thin film element of the present invention is applied to a microprocessor including a circuit that operates with a plurality of power supply voltages.

  FIG. 13A is a bottom view of the microprocessor chip 3 such as an APU according to the fourth embodiment, and FIG. 13B is a front view of the microprocessor chip 3. In FIG. 13A, illustration of the solder bumps 33B is omitted.

  A plurality of external terminals 51 and 53 are formed on the lower surface of the microprocessor chip 3, and solder bumps 31B and 33B are formed on the plurality of external terminals 51 and 53, respectively. A plurality of thin film elements 101a, 101b, 101c, and 101d are mounted on the lower surface of the microprocessor chip 3. The thin film elements 101a to 101d are the same as the thin film element 101 shown in the first embodiment.

  Solder bumps 31B formed on the lower surface of the microprocessor chip 3 are temporarily fixed to connection terminals P11 to P15 included in the thin film elements 101a to 101d by a flux or the like. As shown in FIG. 13A, the thin film elements 101a to 101d are arranged at the four corners (near each corner) of the microprocessor chip 3 having a rectangular planar shape. As shown in FIG. 13B, the height of the solder bump 33B is higher than that of the thin film elements 101a to 101d.

  The microprocessor chip 3 is mounted face-down on the mounting substrate via the thin film elements 101a to 101d and the solder bumps 33B.

  FIG. 14 is a front view showing a state after the reflow of the microprocessor chip 3 mounted on the mounting board 2.

  As shown in FIG. 14, since the thin film elements 101a to 101d are arranged in the gap between the microprocessor chip 3 and the mounting substrate 2, the thin film elements 101a to 101d function as spacers. That is, the gap between the microprocessor chip 3 and the mounting substrate 2 is defined by the height dimensions of the thin film elements 101 a to 101 d arranged at the four corners of the microprocessor chip 3.

  Although the thin film elements 101a to 101d are in contact with the first capacitor electrode CP1 of the mounting substrate 2, they are not joined (fixed) to the mounting substrate 2. Therefore, when the microprocessor chip 3 is mounted on the mounting substrate 2 using the thin film elements 101a to 101d, the stress concentration at the four corners of the microprocessor chip 3 is alleviated, and the impact resistance is improved.

  FIG. 15 is a conceptual diagram showing a connection structure of a smoothing circuit to the microprocessor chip 3 according to the fourth embodiment.

  The microprocessor chip 3 includes a plurality of circuit blocks having different operating power supply voltages. In each circuit block, individual power supply circuits 80a, 80b, 80c, and 80d corresponding to the power supply voltage are formed. The thin film elements 101a, 101b, 101c, and 101d of the power supply circuits 80a, 80b, 80c, and 80d are provided outside the microprocessor chip 3 and are connected via a wiring pattern on the substrate.

<< Other Embodiments >>
In the above-described embodiment, an example in which the planar shape of the thin film element is a square is shown, but the present invention is not limited to this configuration. The shape of the thin film element can be changed as appropriate within the range where the functions and effects of the present invention are exhibited. For example, the planar shape may be a thin plate such as a rectangle, a polygon, a circle, an ellipse, an L shape, or a T shape. Similarly, the shape of the insulating substrate 21 can be changed as appropriate within the range where the functions and effects of the present invention can be achieved. For example, the planar shape is a thin plate such as a rectangle, polygon, circle, ellipse, L-shape, T-shape, It may be.

  In the above-described embodiment, an example in which the thin film inductor is formed on the first surface PS1 of the insulating substrate 21 and the capacitor is formed on the second surface PS2 of the insulating substrate 21 has been described. However, the present invention is limited to this configuration. is not. A thin film inductor may be formed on the second surface PS2 of the insulating substrate 21. That is, both the thin film inductor and the capacitor may be formed on the second surface PS2 of the insulating substrate 21. The thin film inductor may be formed on both the first surface PS1 and the second surface PS2 of the insulating substrate 21.

In the above-described embodiment, an example in which the thin film inductor is formed directly on the first surface PS1 of the insulating substrate 21 has been described. However, the present invention is not limited to this configuration. The thin film inductor may be formed on the surface of the insulating substrate 21 with an SiO ₂ film or the like interposed therebetween. That is, the thin film inductor and the second capacitor electrode “formed on the first surface of the insulating substrate” in the present invention are not limited to those formed directly on the first surface PS1 of the insulating substrate 21, but are thin film inductors. Also included are those in which the second capacitor electrode is formed on the first surface PS1 of the insulating substrate 21 with another member interposed therebetween. Similarly, the thin film inductor and the second capacitor electrode “formed on the second surface of the insulating substrate” in the present invention are not limited to those formed directly on the second surface PS2 of the insulating substrate 21, but are thin films. This includes an inductor and a second capacitor electrode formed on the second surface PS2 of the insulating substrate 21 with another member interposed therebetween.

  In the above-described embodiment, an example in which the thin film inductor is a loop-shaped conductor pattern of about 1 turn or a spiral-shaped conductor pattern of about 1.5 turns is shown, but the present invention is not limited to this. The number of turns of the thin film inductor can be changed as appropriate, and may be, for example, 1 turn or less or 1 turn or more. Further, the thin film inductor may be a helical conductor.

  In the above-described embodiment, the example in which the winding axis of the thin film inductor is in the direction (Z direction) perpendicular to the first surface PS1 and the second surface PS2 of the insulating substrate 21 has been described. However, the present invention is not limited to this. Absent. The winding axis of the thin film inductor may be a direction parallel to the first surface PS1 and the second surface PS2 of the insulating substrate 21 (for example, the X direction or the Y direction). With this configuration, it is possible to suppress the magnetic flux generated in the thin film inductor from being obstructed by the capacitor when the formation regions of the thin film inductor and the capacitor overlap in plan view.

  In the above-described embodiment, an example in which a low-pass filter or a smoothing circuit is configured by a thin film inductor and a capacitor is shown, but the present invention is not limited to this. The circuit composed of the integrated circuit element 1, the mounting substrate 2 and the thin film element can be appropriately changed. For example, a high-pass filter may be configured, a circuit in which a thin film inductor and a capacitor are connected in series, a π-type circuit, Alternatively, a T-type circuit or the like may be used. Further, the numbers of thin film inductors and capacitors are not limited to those in the above-described embodiment, and can be appropriately changed depending on the circuit constituted by the integrated circuit element 1, the mounting substrate 2, and the thin film element.

  In the above-described embodiment, the example in which the planar shape of the connection terminal is a square is shown, but the present invention is not limited to this configuration. The shape of the connection terminal can be changed as appropriate, and may be, for example, polygonal, circular, elliptical, L-shaped, T-shaped, or the like. Also, the number of connection terminals can be appropriately changed depending on the circuit configuration of the thin film element. Furthermore, the arrangement of the connection terminals formed on the first main surface S1 of the thin film element can be changed as appropriate.

C1, C2 ... capacitors L1, L2, L3, L4 ... thin film inductor CP1 ... first capacitor electrodes CP2, CP21, CP22 ... second capacitor electrodes P11, P12, P13, P14, P15 ... connection terminal PS1 ... first of the insulating substrate 1 surface PS2 2nd surface S1 of insulating substrate 1st main surface S2 of thin film element 2nd main surface T1a, T1b, T2a, T2b of thin film element Switch elements V11, V12, V13, V14, V15, V21 , V22, V23, V24 ... interlayer connection conductor Vin ... power input terminals Vout1, Vout2 ... output terminal 1 ... integrated circuit element 2 ... mounting substrate 3 ... microprocessor chip 11 ... first thin film insulator layer 12 ... second thin film insulator Layer 13 ... Dielectric member 21 ... Insulating substrates 31 and 33 ... Conductive bonding materials 31B and 33B ... Solder bumps 41 and 43 ... Mounting terminals 5 , 53 ... external terminals 71 and 72 ... control circuit 80, 80a, 80b, 80c, 80d, 81 ... power supply circuit 101 or 101a, 101b, 101c, 101d, 102 and 103 ... thin film element 201, 203 ... electronic device

Claims (6)

An integrated circuit element;
A mounting board having mounting terminals;
An integrated circuit element mounting structure comprising:
A thin film element having a first main surface and a second main surface facing the first main surface;
A first capacitor electrode formed on the integrated circuit element;
Further comprising
The thin film element is
An insulating substrate having a first surface and a second surface;
A thin film inductor formed by a thin film process on at least one of the first surface and the second surface of the insulating substrate;
A second capacitor electrode formed on the second surface of the insulating substrate;
A connection terminal formed on the first main surface of the thin film element and connected to at least one of the thin film inductor and the second capacitor electrode;
Have
The connection terminal is connected to the mounting terminal,
The integrated circuit element mounting structure, wherein the first capacitor electrode and the second capacitor electrode are at least partially opposed to each other. An integrated circuit element having an external terminal;
A mounting board;
An integrated circuit element mounting structure comprising:
A thin film element having a first main surface and a second main surface facing the first main surface;
A first capacitor electrode formed on the mounting substrate;
Further comprising
The thin film element is
An insulating substrate having a first surface and a second surface;
A thin film inductor formed by a thin film process on at least one of the first surface and the second surface of the insulating substrate;
A second capacitor electrode formed on the second surface of the insulating substrate;
A connection terminal formed on the first main surface of the thin film element and connected to at least one of the thin film inductor and the second capacitor electrode;
Have
The connection terminal is connected to the external terminal,
The integrated circuit element mounting structure, wherein the first capacitor electrode and the second capacitor electrode are at least partially opposed to each other. The thin film element further includes a dielectric member,
The integrated circuit device mounting structure according to claim 1, wherein at least a part of the dielectric member is disposed between the first capacitor electrode and the second capacitor electrode. The thin film inductor is formed on the first surface of the insulating substrate,
The integrated circuit element mounting structure according to claim 1, wherein the thin film inductor and the second capacitor electrode are connected via an interlayer connection conductor provided on the insulating substrate.   The integrated circuit element mounting structure according to claim 4, wherein the number of the thin film inductors is plural. The integrated circuit element further comprises a power supply circuit;
The mounting board further includes a ground,
The thin film inductor is connected to the power supply circuit;
The integrated circuit device mounting structure according to claim 2, wherein the first capacitor electrode is connected to a ground.

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