JP2017063230A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a semiconductor device manufacturing method, which can improve reliability of the semiconductor device.SOLUTION: A semiconductor device comprises: a front-surface device structure of a trench IGBT provided on a top face of a semiconductor substrate, which serves as an ntype drift region 1; and an interlayer insulation film 7 which is provided on a surface of a top face of the semiconductor surface and has a contact hole 11. The contact hole 11 is composed of a first opening 12 provided in a surface layer of an interlayer insulation film 7 on the side of an interface 8 between a metal electrode layer and the interlayer insulation film 7 and a second opening 13 connected to the first opening 12 on the side of the semiconductor substrate. In the first opening 12, a first opening width w1 on the side of the interface between the interlayer insulation film 7 and the metal electrode layer 8 in a direction where trenches 6 of the trench IGBT are laid is larger than a second opening width w2 on the semiconductor substrate side in the direction where the trenches 6 are laid. The metal electrode layer 8 is connected with a p type channel region 4 and an ntype source region 5 via the contact hole 11.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Conventionally, as an insulated gate semiconductor device, for example, an insulated gate bipolar transistor (IGBT) employing a trench gate structure as a front surface element structure is known. Hereinafter, a conventional trench gate structure IGBT (hereinafter, referred to as a trench IGBT) manufacturing method will be described by taking, for example, a vertical trench IGBT having metal electrodes on both sides of a semiconductor substrate.

  11 and 12 are cross-sectional views showing a cross-sectional structure during the manufacture of a conventional semiconductor device. 11 and 12, only the active region of the trench gate type IGBT is illustrated, and the breakdown voltage structure formed so as to surround the active region is not shown (hereinafter also in FIGS. 1, 4 to 9, and 13 to 15). Similarly, only the active region is illustrated). The active region is a region where current flows when the semiconductor device is turned on. The breakdown voltage structure is a structure that realizes a desired breakdown voltage by relaxing the electric field strength on the surface of the pn junction constituting the semiconductor device.

  First, as shown in FIG. 11, the gate electrode 2, the gate insulating film 3, the channel region 4, the source region 5, and the like are formed on the front surface of the active region of the semiconductor substrate that becomes the drift region 1 by a general manufacturing process. The front surface element structure of the trench IGBT is formed. At this time, the front surface element structure of the trench IGBT is formed in the active region, and the front surface element structure (not shown) of the breakdown voltage structure portion is formed so as to surround the active region. Next, an interlayer insulating film 107 is formed on the front surface of the semiconductor substrate by a CVD (Chemical Vapor Deposition) method.

  Next, a contact hole 111 is formed in the interlayer insulating film 107 by photolithography. Thereby, the channel region 4 provided with the source region 5 and a part of the source region 5 provided in the channel region 4 are exposed in the contact hole 111. The contact hole 111 is an opening for connecting a metal electrode layer formed on the front surface of the semiconductor substrate in a later step to the channel region 4 and the source region 5.

  Next, as shown in FIG. 12, a metal electrode layer 108 made of, for example, aluminum (Al) is deposited on the surface of the interlayer insulating film 107 by sputtering. As a result, the metal electrode layer 108 is embedded in the contact hole 111 and connected to the channel region 4 and the source region 5 through the contact hole 111. Next, after the metal electrode layer 108 is patterned by photolithography, a thermal annealing process is performed in order to obtain a stable bondability and good electrical characteristics of the metal electrode layer 108.

  Next, a passivation film (not shown) is formed on the front surface of the semiconductor substrate. Next, the passivation film is patterned by photolithography to expose the metal electrode layer 108. Next, after performing pretreatment and zincate treatment for forming a metal plating layer on the surface of the metal electrode layer 108, a metal plating layer (not shown) is formed on the surface of the metal electrode layer 108 by electroless plating. To do. Thereafter, a collector region and a back electrode (not shown) are formed on the back surface of the semiconductor substrate to complete the vertical trench IGBT.

  As described above, as a method for manufacturing a semiconductor device having a metal electrode layer on the front surface of a semiconductor substrate, a pattern is formed with a resist on an oxide film stacked on the semiconductor substrate, and then the oxide film is formed by isotropic dry etching. Etching is performed halfway, and etching is performed until the semiconductor substrate is reached by anisotropic dry etching, and aluminum is sequentially laminated on the contact hole to form an aluminum electrode, and further over the aluminum electrode. A method of forming the coat film 5 has been proposed (see, for example, Patent Document 1 below).

JP 2003-152075 A

  However, as a result of intensive studies by the inventor, it has been newly found that the following problems occur in the conventional technology described above. 13 to 15 are cross-sectional views showing a cross-sectional structure in the middle of manufacturing a conventional semiconductor device. 13 to 15 are cross-sectional structures of the semiconductor device in the manufacturing process subsequent to FIG. In the conventional semiconductor device manufacturing method described above, a step having the same dimension as the thickness of the interlayer insulating film 107 is formed between the interlayer insulating film 107 and the semiconductor substrate exposed in the contact hole 111.

  When the thickness of the interlayer insulating film 107 is as thick as 0.5 μm or more, for example, a step generated between the interlayer insulating film 107 and the semiconductor substrate exposed to the contact hole 111 becomes large, and the step coverage of the interlayer insulating film 107 is deteriorated. . For this reason, when the metal electrode layer 108 is formed by sputtering, the growth of the metal electrode layer 108 on the side wall of the contact hole 111 is delayed. As a result, voids 112 are locally formed in the metal electrode layer 108 as shown in FIG. The void 112 is a recess generated on the surface of the metal electrode layer 108 or a cavity generated inside the metal electrode layer 108. In FIG. 12, a concave portion generated on the surface of the metal electrode layer 108 is illustrated.

  When the void 112 is generated in the metal electrode layer 108, a resist mask used for patterning the metal electrode layer 108 enters the void 112. The resist that has entered the void 112 cannot be removed by ashing (ashing). For this reason, as shown in FIG. 13, an organic residue 113 remains in the void 112. The residue 113 remaining in the void 112 is carbonized by a thermal annealing process after the patterning of the metal electrode layer 108 is formed. Then, as shown in FIG. 14, the carbonized residue 114 adheres to the surface around the void 112 of the metal electrode layer 108.

  The residue of the passivation film formed on the surface of the metal electrode layer 108 after the patterning of the metal electrode layer 108 remains on the surface of the metal electrode layer 108 similarly to the residue 114 of the resist. When the residue 114 remains on the surface of the metal electrode layer 108 as described above, as shown in FIG. 15, the metal plating layer 109 is not formed on the portion of the surface of the metal electrode layer 108 where the residue 114 is attached. For this reason, when the metal plating layer 109 and a wire (not shown) are soldered together, the solder reaches the portion of the surface of the metal electrode layer 108 that is not covered with the metal plating layer 109, and the semiconductor device is destroyed. There is a risk of reaching.

  Even when the metal electrode layer 108 and the wire are directly solder-bonded without forming the metal plating layer 109 (not shown), the electrical characteristics deteriorate due to the organic residue 114 remaining on the surface of the metal electrode layer 108. For example, the bonding strength between the metal electrode layer 108 and the wire is reduced by the organic residue 114 remaining on the surface of the metal electrode layer 108. Therefore, it is conceivable to avoid the generation of the residue 114 by improving the step coverage of the metal electrode layer 108 and suppressing the generation of the void 112. However, in this case, the following problem occurs.

  As a method for improving the step coverage of the metal electrode layer 108 to such an extent that the generation of the void 112 can be suppressed, for example, the metal electrode layer 108 is formed on the front surface of the semiconductor substrate by sputtering with the temperature of the semiconductor substrate raised. The method of depositing is mentioned. However, when the metal electrode layer 108 made of aluminum or the like is formed on the surface of the semiconductor substrate made of silicon (Si) without a barrier film, the semiconductor substrate and the metal electrode layer 108 are in direct contact with each other.

  For this reason, when the temperature of the semiconductor substrate is raised, alloy spikes are generated in the semiconductor substrate, or silicon is deposited at the interface between the semiconductor substrate and the metal electrode layer 108 to increase the contact resistance. In order to avoid such an increase in contact resistance due to alloy spikes or silicon deposition, the temperature of the semiconductor substrate cannot be raised to 400 ° C. or higher where the reflow effect of the metal electrode layer 108 can be expected. The above-described problem occurs similarly even when a void is generated inside the metal electrode layer 108. The reason is that, for example, the surface layer of the metal electrode layer 108 is removed by pretreatment for plating the metal plating layer 109 on the surface of the metal electrode layer 108, and voids inside the metal electrode layer 108 are removed from the metal electrode layer 108. This is because it may appear on the surface.

  Further, in the technique shown in Patent Document 1 described above, a method for improving the step coverage of the metal electrode layer has been proposed, but the relationship between the shape of the contact hole and the thickness of the interlayer insulating film is disclosed. Absent. Since the void generated in the metal electrode layer is not mentioned, there is a possibility that the above-described problem may occur when a void occurs in the metal electrode layer.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing a semiconductor device in order to solve the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention includes a second conductivity type semiconductor region provided in a surface layer of a front surface of a first conductivity type semiconductor substrate. A trench that penetrates the second conductive type semiconductor region and reaches the first conductive type semiconductor region made of the semiconductor substrate, a first electrode embedded in the trench through a gate insulating film, and the second conductive type Interlayer insulating film provided on the surface of the type semiconductor region opposite to the surface in contact with the first conductivity type semiconductor region, and a contact provided on the surface of the interlayer insulating film and provided on the interlayer insulating film A second electrode having a thickness of 2 μm or more and made of a material mainly composed of aluminum embedded in the hole, wherein the contact hole is formed between the interlayer insulating film and the second electrode. Front side, front side A first opening width in a direction in which the trenches are arranged is connected to a first opening portion wider than a second opening width in the direction in which the trenches are arranged on the semiconductor substrate side, and the semiconductor substrate side of the first opening portion, A second opening having an opening width in the direction in which the trenches are arranged equal to the second opening width of the first opening, the thickness of the interlayer insulating film being 0.5 μm or more, and the first opening It is 0.6 times or more of the second opening width of the opening.

  In the semiconductor device according to the present invention as set forth in the invention described above, the thickness of the interlayer insulating film is 0.28 times or less the first opening width of the first opening.

  In the semiconductor device according to the present invention, in the above-described invention, the contact hole has a rectangular planar shape, and the plurality of contact holes are in a direction perpendicular to the direction in which the trenches are arranged and the direction in which the trenches are arranged. Are arranged in a matrix.

  In the semiconductor device according to the present invention, in the above-described invention, the plurality of contact holes arranged in parallel along the direction in which the trenches are arranged are arranged in stripes in parallel with each other extending in a direction perpendicular to the direction in which the trenches are arranged. It is characterized by being.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, an electroless plating layer is provided on the surface of the second electrode.

  In order to solve the above-described problems and achieve the object of the present invention, a method of manufacturing a semiconductor device according to the present invention includes a second conductivity type on a surface layer of a front surface of a first conductivity type semiconductor substrate. A step of forming a semiconductor region, a step of forming a trench penetrating the second conductive type semiconductor region and reaching the first conductive type semiconductor region formed of the semiconductor substrate, and a gate insulating film in the trench. Embedding one electrode, forming an interlayer insulating film having a thickness of 0.5 μm or more on the surface of the second conductivity type semiconductor region, forming a resist on the surface of the interlayer insulating film, Selectively opening, performing isotropic etching using the resist as a mask to form a first opening having a depth shallower than the thickness of the interlayer insulating film in the interlayer insulating film, and the resist The mask Performing anisotropic etching to form a second opening connected to the first opening and exposing the front surface of the semiconductor substrate to the interlayer insulating film; and to the interlayer insulating film Embedding a second electrode made of a material containing aluminum as a main component and having a thickness of 2 μm or more on the surface of the interlayer insulating film in the provided contact hole, and the interlayer insulating film The thickness of the second opening is formed to be not less than 0.6 times the second opening width of the second opening in the direction in which the trenches are arranged.

  The method for manufacturing a semiconductor device according to the present invention includes the step of connecting the second conductive type semiconductor region and the second electrode through the first opening and the second opening in the above-described invention. It is further characterized by including.

  In the semiconductor device manufacturing method according to the present invention, in the above-described invention, the thickness of the interlayer insulating film is 0.28 times or less the first opening width of the first opening in the direction in which the trenches are arranged. It is characterized by forming in.

  The semiconductor device manufacturing method according to the present invention is characterized in that, in the above-described invention, a plurality of the resist are opened in a matrix in a direction in which the trenches are arranged and a direction orthogonal to the direction in which the trenches are arranged.

  In the semiconductor device manufacturing method according to the present invention, the resist is opened in a stripe shape extending in a direction orthogonal to a direction in which the trenches are arranged.

  Also, the method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-described invention, the interlayer insulating film is formed with a thickness of 0.5 μm or more.

  The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-described invention, the method further includes a step of electroless plating the surface of the second electrode by electroless plating.

  Further, the semiconductor device manufacturing method according to the present invention is characterized in that, in the above-described invention, after the zincate process is performed, the electroless plating process is performed.

  According to the above-described invention, the step generated between the interlayer insulating film and the semiconductor substrate exposed in the contact hole is relaxed as compared with the conventional semiconductor device. Thereby, since the step coverage of the interlayer insulating film is improved as compared with the conventional case, no void is generated in the metal electrode layer formed on the interlayer insulating film. Therefore, the resist mask for patterning the metal electrode layer can be removed without leaving a resist residue on the surface of the metal electrode layer. Therefore, a metal plating film can be uniformly formed on the surface of the metal electrode layer.

  According to the semiconductor device and the semiconductor device manufacturing method of the present invention, there is an effect that the reliability of the semiconductor device can be improved.

1 is a cross-sectional view showing a semiconductor device according to an embodiment. It is a top view which shows the principal part of the semiconductor device concerning embodiment. It is a top view which shows another example of the principal part of the semiconductor device concerning embodiment. It is sectional drawing which shows the cross-sectional structure in the middle of manufacture of the semiconductor device concerning embodiment. It is sectional drawing which shows the cross-sectional structure in the middle of manufacture of the semiconductor device concerning embodiment. It is sectional drawing which shows the cross-sectional structure in the middle of manufacture of the semiconductor device concerning embodiment. It is sectional drawing which shows the cross-sectional structure in the middle of manufacture of the semiconductor device concerning embodiment. It is sectional drawing which shows the cross-sectional structure in the middle of manufacture of the semiconductor device concerning embodiment. It is sectional drawing which shows the cross-sectional structure in the middle of manufacture of the semiconductor device concerning embodiment. It is a characteristic view which shows the relationship between the contact hole shape of the semiconductor device concerning an Example, and a void generation rate. It is sectional drawing which shows the cross-sectional structure in the middle of manufacture of the conventional semiconductor device. It is sectional drawing which shows the cross-sectional structure in the middle of manufacture of the conventional semiconductor device. It is sectional drawing which shows the cross-sectional structure in the middle of manufacture of the conventional semiconductor device. It is sectional drawing which shows the cross-sectional structure in the middle of manufacture of the conventional semiconductor device. It is sectional drawing which shows the cross-sectional structure in the middle of manufacture of the conventional semiconductor device.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment)
FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment. The semiconductor device according to the embodiment will be described by taking, for example, a vertical trench IGBT as an example. As shown in FIG. 1, the semiconductor device according to the embodiment has an active region of an n-type (first conductivity type) semiconductor substrate that becomes an n ⁻ -type drift region (first conductivity type semiconductor region) 1. The front surface element structure of the trench IGBT such as the gate electrode 2, the gate insulating film 3, the p-type channel region (p-type base region: second conductivity type semiconductor region) 4 and the n ⁺ -type source region 5 is provided on the surface. It has been.

Specifically, the p-type channel region 4 is provided on the surface layer of the front surface of the semiconductor substrate. A trench 6 that penetrates the p-type channel region 4 and reaches the n ⁻ -type drift region 1 is provided. The plurality of trenches 6 are arranged in stripes in parallel in the short direction of the trenches. A gate electrode (first electrode) 2 is buried inside the trench 6 with a gate insulating film 3 interposed therebetween. The n ⁺ type source region 5 is selectively provided in the surface layer of the p type channel region 4.

The n ⁺ -type source region 5 is in contact with the gate insulating film 3 formed on the sidewall of the trench 6. An interlayer insulating film 7 is provided on the front surface of the semiconductor substrate, that is, the surface of the p-type channel region 4 opposite to the surface in contact with the n ⁻ -type drift region 1. The interlayer insulating film 7 may be an oxide film or a nitride film, for example. The thickness t1 of the interlayer insulating film 7 may be 0.5 μm or more, for example. For example, a contact hole 11 for a source contact is provided in the interlayer insulating film 7. A metal electrode layer (second electrode) 8 is provided on the surface of the interlayer insulating film 7 and inside the contact hole 11.

Metal electrode layer 8 is connected to p-type channel region 4 and n ⁺ -type source region 5 through contact hole 11. The metal electrode layer 8 is made of, for example, a material mainly composed of aluminum. Specifically, the metal electrode layer 8 may be made of, for example, aluminum or an aluminum alloy. The thickness t2 of the metal electrode layer 8 may be 2 μm or more. The surface of the metal electrode layer 8 is plated, and a metal plating layer 9 is formed. The metal plating layer 9 may be a plating film made of nickel, for example.

  A breakdown voltage structure (not shown) of the semiconductor substrate is provided so as to surround the active region. On the front surface of the breakdown voltage structure portion of the semiconductor substrate, for example, the front surface of the breakdown voltage structure portion such as a floating p-type semiconductor region (field limiting ring) or a field plate electrode in contact with the p-type semiconductor region An element structure, a passivation film, and the like are provided.

  Next, the cross-sectional shape of the contact hole 11 will be described. The contact hole 11 is formed by connecting the first opening 12 and the second opening 13. The first opening 12 is provided on the interface side of the interlayer insulating film 7 with the metal electrode layer 8. The first opening 12 has a first opening width w1 in the direction in which the trenches 6 are arranged on the interface side between the interlayer insulating film 7 and the metal electrode layer 8, and a second opening in the direction in which the trenches 6 on the semiconductor substrate side are arranged. It is wider than the width w2. Therefore, the first opening 12 has a trapezoidal cross-sectional shape in which the interface side between the interlayer insulating film 7 and the metal electrode layer 8 is an upper base and the semiconductor substrate side is a lower base.

  The second opening 13 is connected to the semiconductor substrate side of the first opening 12 and penetrates the interlayer insulating film 7 to selectively expose the front surface of the semiconductor substrate. The second opening 13 is provided with the same opening width from the interface side between the interlayer insulating film 7 and the metal electrode layer 8 to the semiconductor substrate side. The opening width of the second opening 13 in the direction in which the trenches 6 are arranged is equal to the second opening width w2 of the first opening 12. For this reason, the second opening 13 has a rectangular cross-sectional shape.

  Next, the relationship between the first and second opening widths w1 and w2 of the first opening 12 of the contact hole 11 and the thickness t1 of the interlayer insulating film 7 will be described. The thickness t1 of the interlayer insulating film 7 is preferably 0.28 times or less the first opening width w1 of the first opening 12 as shown in the following formula (1). The reason is that no void is generated in the metal electrode layer 8 by providing the interlayer insulating film 7 and the first opening 12 of the contact hole 11 with dimensions satisfying the following expression (1).

  t1 / w1 ≦ 0.28 (1)

  Further, as shown in the following formula (2), the thickness t1 of the interlayer insulating film 7 may be 0.6 times or more the second opening width w2 of the first opening 12. In the conventional semiconductor device, when a contact hole is provided in the interlayer insulating film with a size satisfying the following expression (2), voids are likely to be generated in the metal electrode layer. On the other hand, in the semiconductor device according to the embodiment, when the contact hole 11 is provided in the interlayer insulating film 7 with a size satisfying the following expression (2), no void is generated in the metal electrode layer 8.

  t1 / w2 ≧ 0.6 (2)

  The reason why no void is generated in the metal electrode layer 8 is that the contact hole 11 having the above-described shape and size is used above the contact hole on the surface of the metal electrode layer even when the metal electrode layer 8 is thicker than 2 μm. This is because the level difference in the portion 20 does not become so large that voids are generated.

  Next, the planar shape and arrangement of the contact hole 11 will be described. FIG. 2 is a plan view illustrating a main part of the semiconductor device according to the embodiment. 2, only the trench 6, the interlayer insulating film 7, and the contact hole 11 are shown in order to clarify the planar shape and arrangement of the contact hole 11 (only the same configuration is shown in FIG. 3). As shown in FIG. 2, the contact hole 11 has, for example, a rectangular planar shape. Specifically, both the first opening 12 and the second opening 13 have a rectangular planar shape.

The plurality of contact holes 11 are arranged in a matrix in the direction in which the trenches 6 are arranged and in the direction orthogonal to the direction in which the trenches 6 are arranged. Specifically, the plurality of contact holes 11 are regularly arranged in an island shape at regular intervals in the longitudinal direction and the short direction of the trench 6 (hereinafter referred to as a cell structure). Each contact hole 11 exposes a portion of the semiconductor substrate sandwiched between the trenches 6. Specifically, each contact hole 11, n ⁺ -type source region and p-type channel region 4 (not shown) is provided, one n ⁺ -type source region provided in the p-type channel region 4 Part is exposed.

  When the contact holes 11 are arranged in a cell structure, a plurality of rectangular trenches are exposed by the contact holes 11 arranged in a matrix instead of the trenches 6 arranged in parallel in the short direction of the trenches 6. Alternatively, the p-type channel regions 4 may be arranged in a matrix so as to sandwich the p-type channel region 4.

  FIG. 3 is a plan view illustrating another example of the main part of the semiconductor device according to the embodiment. As shown in FIG. 3, a plurality of contact holes 31 arranged in parallel along the direction in which the trenches 6 are arranged in the interlayer insulating film 37 may be arranged in a stripe shape extending in a direction perpendicular to the direction in which the trenches 6 are arranged ( Hereinafter, a stripe structure is used. That is, the first opening 32 and the second opening 33 are arranged in a stripe shape extending in the longitudinal direction of the trench 6. The contact hole 31 is disposed between the adjacent trenches 6. Then, the contact hole 31 exposes the portion of the p-type channel region 4 sandwiched between the trenches 6 in a stripe shape in parallel in the lateral direction of the trench.

  The configuration other than the planar shape of the contact hole 31 shown in FIG. 3 is the same as that of the contact hole 11 shown in FIG. In FIG. 3, only the planar shape of the first opening 32 is shown, but a second opening (not shown) whose width in the short direction is the second opening width w2 in the short direction of the first opening 32 is also shown. The first opening 32 is disposed on the semiconductor substrate side.

Next, a method for manufacturing the semiconductor device according to the embodiment will be described. 4-9 is sectional drawing which shows the cross-sectional structure in the middle of manufacture of the semiconductor device concerning Embodiment. First, as shown in FIG. 4, the gate electrode 2, the gate insulating film 3, the p-type channel region 4 and the n ^{+ are} formed on the front surface of the semiconductor substrate to be the n ⁻ -type drift region 1 by a general manufacturing process. A front surface element structure of the active region of the trench IGBT such as the type source region 5 is formed. At this time, the front surface element structure of the trench IGBT is formed in the active region, and the front surface element structure (not shown) of the breakdown voltage structure portion is formed so as to surround the active region.

For example, after forming the p-type channel region 4 in the surface layer of the front surface of the semiconductor substrate, the trench 6 that penetrates the p-type channel region 4 and reaches the n ⁻ -type drift region 1 is formed. Next, the gate electrode 2 is embedded in the trench 6 via the gate insulating film 3. Then, an n ⁺ type source region 5 is formed on the surface layer of the front surface of the semiconductor substrate.

  Next, as shown in FIG. 5, an interlayer insulating film 7 is formed on the front surface of the semiconductor substrate by a CVD (Chemical Vapor Deposition) method. Next, as shown in FIG. 6, a resist mask 41 having an opening 42 through which the contact hole 11 formation region is exposed is formed on the surface of the interlayer insulating film 7. The opening width w3 of the opening 42 is substantially the same as the second opening width w2 of the first opening 12 formed using the resist mask 41 as a mask in a later step.

  Further, the opening 42 of the resist mask 41 is formed so that a contact hole formed in a later step using the resist mask 41 as a mask has a cell structure or a stripe structure. Specifically, when forming the contact holes 11 arranged in the cell structure, the openings 42 are arranged in a matrix in the direction in which the trenches 6 are arranged and in the direction perpendicular to the direction in which the trenches 6 are arranged (see FIG. 2). ). On the other hand, when forming the contact holes 31 arranged in a stripe structure, a plurality of openings 42 arranged in parallel along the direction in which the trenches 6 are arranged are arranged in a stripe shape extending in a direction orthogonal to the direction in which the trenches 6 are arranged. (See FIG. 3).

  Next, as shown in FIG. 7, isotropic etching is performed using the resist mask 41 as a mask, and the interlayer insulating film 7 exposed in the opening 42 of the resist mask 41 is removed. As a result, the first opening 12 is formed in the surface layer of the interlayer insulating film 7 with a depth shallower than the thickness of the interlayer insulating film 7. Specifically, the interlayer insulating film 7 is removed by isotropic etching so that the depth of the first opening 12 is about 50% to 60% of the thickness of the interlayer insulating film 7. By setting the first and second opening widths w1 and w2 of the first opening 12 to satisfy the above expressions (1) and (2), the thickness of the interlayer insulating film 7 is about 50% to 60%. The first opening 12 can be formed with a depth.

  In forming the first opening 12, since the interlayer insulating film 7 is removed by isotropic etching, the etching of the interlayer insulating film 7 proceeds in the same way in all directions. For this reason, the opening width (first opening width w1) of the first opening 12 on the resist mask 41 side becomes wider than the opening width of the opening 42 of the resist mask 41, and the opening of the first opening 12 on the semiconductor substrate side. The width (second opening width w2) can be made substantially equal to the opening width of the opening 42 of the resist mask 41. Thereby, the cross-sectional shape of the 1st opening part 12 becomes trapezoid. For the isotropic etching, for example, a chemical dry etching (CDE) apparatus may be used.

  Next, anisotropic etching is performed using the same resist mask 41 used for forming the first opening 12 as a mask, and the interlayer insulating film 7 exposed in the opening 42 of the resist mask 41 is removed. The anisotropic etching for forming the second opening 13 is performed until the front surface of the semiconductor substrate is exposed. As a result, the interlayer insulating film 7 exposed to the first opening 12 is removed, and the second opening 13 connected to the first opening 12 is formed.

  In forming the second opening 13, since the interlayer insulating film 7 is removed by anisotropic etching, the etching of the interlayer insulating film 7 proceeds selectively only in the depth direction of the interlayer insulating film 7. For this reason, the second opening 13 is formed in the depth direction of the interlayer insulating film 7 with the same opening width as the opening width of the opening 42 of the resist mask 41, that is, the second opening width w 2 of the first opening 12. The Thereby, the cross-sectional shape of the 2nd opening part 13 becomes a rectangular shape.

In this way, by performing isotropic etching and anisotropic etching in order using the same resist mask 41, as shown in FIG. 8, a contact hole made up of the first opening 12 and the second opening 13 is obtained. 11 is formed. In the contact holes 11, and the p-type channel region 4 n ⁺ -type source region 5 is provided, a part of the n ⁺ -type source region 5 provided on the p-type channel region 4 is exposed.

Next, the resist mask 41 is removed by ashing, for example, with plasma. Then, as shown in FIG. 9, a metal electrode layer 8 made of, for example, aluminum is deposited on the surface of the interlayer insulating film 7 by, for example, sputtering. Metal electrode layer 8 is embedded in contact hole 11 and connected to p-type channel region 4 and n ⁺ -type source region 5 through contact hole 11.

  Next, a resist mask (not shown) in which the pattern of the metal electrode layer 8 is formed is formed on the surface of the metal electrode layer 8. Next, using this resist mask as a mask, the metal electrode layer 8 exposed in the opening of the resist mask is removed, and a desired metal electrode layer 8 pattern is formed. Then, after removing the resist mask used for patterning the metal electrode layer 8 by, for example, ashing with plasma or the like, thermal annealing is performed to obtain stable bondability and good electrical characteristics of the metal electrode layer 8. Process.

  Next, a passivation film (not shown) is formed on the front surface of the semiconductor substrate. Next, the passivation film is patterned by photolithography to expose the metal electrode layer 8. Next, pretreatment and zincate treatment for forming the metal plating layer 9 on the surface of the metal electrode layer 8 are performed. Then, a metal plating layer 9 made of nickel, for example, is formed on the surface of the metal electrode layer 8 by an electroless plating method. Thereafter, a collector region and a back electrode (not shown) are formed on the back surface of the semiconductor substrate, thereby completing a vertical trench IGBT as shown in FIG.

  Thus, the first opening width w1 on the interface side between the interlayer insulating film 7 and the metal electrode layer 8 of the first opening 12 constituting the contact hole 11 is formed wider than the second opening width w2 on the semiconductor substrate side. Is done. As a result, the angle formed between the side wall of the first opening 12 and the front surface of the semiconductor substrate exposed in the contact hole 11 becomes an obtuse angle. Therefore, the step formed between the interlayer insulating film 7 and the semiconductor substrate exposed in the contact hole 11 is inclined at an angle at which the side wall of the first opening 12 forms an obtuse angle with respect to the front surface of the semiconductor substrate. Therefore, it is more relaxed than the conventional semiconductor device.

  Since the step generated between the interlayer insulating film 7 and the semiconductor substrate exposed in the contact hole 11 is relaxed, atoms jumping out of the target material when the metal electrode layer 8 is sputtered adhere to the sidewall of the contact hole 11. Cheap. For this reason, no void is generated in the metal electrode layer 8 even when the thickness t1 of the interlayer insulating film 7 is as thick as 0.5 μm or more, or when the thickness of the metal electrode layer 8 is as thick as 2 μm. Since no void is generated in the metal electrode layer 8, no resist residue is generated on the surface of the metal electrode layer 8.

  As described above, according to the semiconductor device of the embodiment, the semiconductor exposed to the interlayer insulating film 7 and the contact hole 11 by forming the first opening 12 so as to satisfy the expression (1). The level difference between the substrate and the substrate is reduced as compared with the conventional semiconductor device. Thereby, since the step coverage of the interlayer insulating film 7 is improved as compared with the conventional case, no void is generated in the metal electrode layer 8 formed on the interlayer insulating film 7. Therefore, the resist mask for patterning the metal electrode layer 8 can be removed without leaving a resist residue on the surface of the metal electrode layer 8. Therefore, the metal plating film 9 can be uniformly formed on the surface of the metal electrode layer 8, and the reliability of the semiconductor device is improved.

(Example)
Next, the void generation rate is verified. FIG. 10 is a characteristic diagram illustrating the relationship between the contact hole shape and the void generation rate of the semiconductor device according to the example. According to the embodiment, the first opening width w1 was variously changed, and a plurality of semiconductor devices (hereinafter referred to as samples) including contact holes 31 arranged in a stripe structure were manufactured (manufactured). In each sample, the first opening width w1 of the first opening 32 is such that the thickness t1 of the interlayer insulating film 37 is 0.25 to 0.32 times the first opening width w1 of the first opening 32 ( = T1 / w1, hereinafter referred to as a thickness / aperture width ratio).

  In each sample, the second opening width w2 of the first opening 32 is formed so that the thickness t1 of the interlayer insulating film 37 is 0.6 times the second opening width w2 of the first opening 32. Yes. In each sample, the depths of the first opening 32 and the second opening of the contact hole 31 differ depending on the dimension of the first opening width w1 of the first opening 32 formed by isotropic etching. And the presence or absence of the void generation | occurrence | production in each sample produced on such conditions was investigated.

  From the results shown in FIG. 10, by setting the thickness t1 of the interlayer insulating film 37 and the first opening width w1 of the first opening 32 so that the thickness / opening width ratio is 0.28 or less, It was confirmed that the generation of voids can be suppressed (void generation rate = 0%). In addition, the depth of the first opening 32 of the sample measured at the measurement point A (shown by a white arrow) at which the thickness / opening width ratio is 0.28 is the thickness t1 of the interlayer insulating film 37. It was confirmed that the size was about 60%.

  Also in the semiconductor device including the contact hole 11 arranged in the cell structure, the thickness t1 of the interlayer insulating film 7 and the first opening 12 are set so that the thickness / opening width ratio is 0.28 or less. By setting the opening width w 1, it is possible to obtain the same effect as that of the semiconductor device of the above-described embodiment having the contact holes 31 arranged in a stripe structure.

  In the above description, the vertical trench IGBT is described as an example in the present invention. However, the present invention is not limited to the above-described embodiment, and is applied to semiconductor devices having various configurations having a metal electrode layer on the front surface of a semiconductor substrate. Is possible. In the embodiment described above, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is the same even if the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a semiconductor device having a thick aluminum electrode on the front surface of a semiconductor substrate.

1 n ⁻ type drift region 2 gate electrode 3 gate insulating film 4 p type channel region 5 n ⁺ type source region 6 trench 7 interlayer insulating film 8 metal electrode layer 9 metal plating layer 11 contact hole 12 first opening 13 second opening Part 20 Part above the contact hole on the surface of the metal electrode layer

Claims (12)

A second conductivity type semiconductor region provided on the front surface layer of the first conductivity type semiconductor substrate;
A trench that penetrates through the second conductive semiconductor region and reaches the first conductive semiconductor region formed of the semiconductor substrate;
A first electrode embedded in the trench through a gate insulating film;
An interlayer insulating film provided on a surface of the second conductivity type semiconductor region opposite to a surface in contact with the first conductivity type semiconductor region;
A second electrode having a thickness of 2 μm or more, made of a material mainly composed of aluminum, provided on a surface of the interlayer insulating film and embedded in a contact hole provided in the interlayer insulating film; ,
With
The contact hole is
A first opening in which the first opening width in the direction in which the trenches are arranged on the interface side between the interlayer insulating film and the second electrode is wider than the second opening width in the direction in which the trenches are arranged on the semiconductor substrate side; ,
A second opening connected to the semiconductor substrate side of the first opening and having an opening width in a direction in which the trenches are arranged equal to the second opening width of the first opening;
The thickness of the said interlayer insulation film is 0.5 micrometer or more, and is 0.6 times or more of the said 2nd opening width of the said 1st opening part, The semiconductor device characterized by the above-mentioned.   2. The semiconductor device according to claim 1, wherein the thickness of the interlayer insulating film is 0.28 times or less the width of the first opening of the first opening. The contact hole has a rectangular planar shape,
3. The semiconductor device according to claim 1, wherein the plurality of contact holes are arranged in a matrix in a direction in which the trenches are arranged and a direction orthogonal to the direction in which the trenches are arranged.   The semiconductor device according to claim 1, wherein the plurality of contact holes arranged in parallel along the direction in which the trenches are arranged are arranged in a stripe shape extending in a direction orthogonal to the direction in which the trenches are arranged. .   The semiconductor device according to claim 1, further comprising an electroless plating layer on a surface of the second electrode. Forming a second conductivity type semiconductor region on the front surface layer of the first conductivity type semiconductor substrate;
Forming a trench that penetrates through the second conductive type semiconductor region and reaches the first conductive type semiconductor region made of the semiconductor substrate;
Burying a first electrode in the trench through a gate insulating film;
Forming an interlayer insulating film having a thickness of 0.5 μm or more on the surface of the second conductivity type semiconductor region;
Forming a resist on the surface of the interlayer insulating film, and selectively opening the resist;
Performing isotropic etching using the resist as a mask to form a first opening having a depth shallower than the thickness of the interlayer insulating film in the interlayer insulating film;
Performing anisotropic etching using the resist as a mask, and forming a second opening in the interlayer insulating film connected to the first opening and exposing a front surface of the semiconductor substrate; and the interlayer Burying a second electrode made of a material mainly composed of aluminum and having a thickness on the surface of the interlayer insulating film of 2 μm or more in a contact hole provided in the insulating film;
Including
A method of manufacturing a semiconductor device, wherein the thickness of the interlayer insulating film is formed to be 0.6 times or more the second opening width of the second opening in the direction in which the trenches are arranged.   The method of manufacturing a semiconductor device according to claim 6, further comprising a step of connecting the second conductive semiconductor region and the second electrode through the first opening and the second opening. .   8. The semiconductor device according to claim 6, wherein the thickness of the interlayer insulating film is formed to be 0.28 times or less of the first opening width of the first opening in the direction in which the trenches are arranged. Manufacturing method.   9. The method of manufacturing a semiconductor device according to claim 6, wherein a plurality of the resist are opened in a matrix in a direction in which the trenches are arranged and a direction orthogonal to the direction in which the trenches are arranged.   9. The method of manufacturing a semiconductor device according to claim 6, wherein the resist is opened in a stripe shape extending in a direction orthogonal to a direction in which the trenches are arranged.   The method of manufacturing a semiconductor device according to claim 6, further comprising a step of performing electroless plating on a surface of the second electrode by an electroless plating process.   The method of manufacturing a semiconductor device according to claim 11, wherein a step of performing the electroless plating process is performed after the zincate process.

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