JP2017063129A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an inexpensive semiconductor device hardly causing discharge between electrodes during inspection.SOLUTION: In a semiconductor device 100, a floating electrode 50 is provided at an intermediate position between a drain electrode 12 and a source electrode 11 at a place adjacent to a source opening 40A that is formed in a protective film, and at an intermediate position between the source electrode 11 and the drain electrode 12 at a place adjacent to a drain opening 40B, in plan view. The floating electrode 50 is also formed along intermediate points of the source electrode 11 and the drain electrode 12 at a gap between the source electrode 11 and the drain electrode 12, in plan view.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a structure of a semiconductor device in which two electrodes through which an operating current flows are provided on the same surface side of a semiconductor layer.

  A semiconductor device (power semiconductor element) that performs a switching operation of a large current flowing between a source electrode (first main electrode) and a drain electrode (second main electrode) depends on the direction in which the operating current flows and the electrode configuration. It is roughly divided into a vertical semiconductor device and a horizontal semiconductor device. In a vertical semiconductor device, a source electrode and a drain electrode are respectively formed on two main surfaces (front surface and back surface) of a semiconductor layer, and an operating current flows in the film thickness direction of the semiconductor layer. On the other hand, in a horizontal semiconductor device, the source electrode and the drain electrode are both formed on one main surface (front surface) side of the semiconductor layer.

  As such a semiconductor device, a HEMT (High Electron Mobility Transistor) using a group III nitride semiconductor (GaN or the like) is known. The HEMT that allows an operating current to flow along the heterojunction interface is normally a lateral element, and is used for on / off control of the source electrode (first main electrode), the drain electrode (second main electrode), and the operating current. The gate electrodes are all provided on the surface side of the semiconductor layer.

  Here, in general, in order to flow a large current when turned on, a large number of HEMT elements (semiconductor elements) are arranged in a semiconductor layer, and small source electrodes, drain electrodes, and gates formed in the respective HEMT elements. The electrodes (individual source electrode, individual drain electrode, individual gate electrode) are connected to the large source electrode, drain electrode, and gate electrode formed in the upper layer, and the electrical connection between the outside is the source electrode of this upper layer, This is performed on the drain electrode and the gate electrode. Thereby, all the HEMT elements are connected in parallel and operate, and a large current can flow between the source electrode and the drain electrode.

  At this time, the individual source electrode and the individual drain electrode in the lower layer, the source electrode and the drain electrode in the upper layer are configured so that each HEMT element operates uniformly (operating current flows uniformly). On the other hand, during operation, the source electrode is normally set at a ground potential and the gate electrode is set at a low potential (10 V or less) according to on / off control, while the drain electrode is set at a high potential of several hundreds V or more. For this reason, when the source electrode and the drain electrode are formed on the same side of the semiconductor layer in this way, it is required that the withstand voltage between the drain electrode, the source electrode, and the gate electrode when off is sufficiently high.

  Patent Document 1 describes an electrode configuration that satisfies these requirements in a horizontal semiconductor device (power MOSFET). In this structure, the source electrode and the drain electrode are in a comb shape, and the pad portion to which the bonding wire is connected in the source electrode and the pad portion to which the bonding wire is connected in the drain electrode are separated from each other on the surface of the semiconductor layer. Thus, it is provided on a different end side. In practice, such a semiconductor device is mounted on a package, and the pad portion of the source electrode is connected to the source terminal of the package, and the pad portion of the drain electrode is connected to the drain terminal of the package by bonding wires.

  Here, the pad portion of the source electrode and the pad portion of the drain electrode are formed outside the active region (region where the operating current flows), and the area of the active region is set large in order to increase the operating current. When these pad portions are separated with the active region interposed therebetween, the source electrode and the drain electrode are elongated in the direction in which the pad portions are arranged. For this reason, the wiring resistance of the source electrode and the drain electrode itself increases, and it becomes difficult to operate each element uniformly in the plane. Further, the chip area is further increased by providing large pad portions at both ends. For this reason, if a configuration in which bonding wires can be connected to a plurality of locations on the active region without providing a large pad portion as described above, each element can be operated uniformly with an active region of the same area and a small chip area. Can be done. FIG. 4 is a plan view of the outermost surface of the semiconductor device 200 having such a configuration, FIG. 5A is a cross-sectional view in the BB direction, a cross-sectional view in the CC direction, and a cross-sectional view in the DD direction. ), (B), and (c), respectively.

  As shown in FIG. 4, a plurality of source electrodes 11 extending in the vertical direction (one direction) in the figure are formed in parallel on the surface of the semiconductor device 200. The extending comb-tooth portion and the source electrode 11 are formed to be intertwined with each other. For this reason, the part extended in the up-down direction in the source electrode 11 and the part extended in the up-down direction in the drain electrode face each other close to each other. The gate electrode 13 that maintains a low potential during operation is provided in a small area at the end of these arrays. In FIG. 4, each of the source electrode 11 and the drain electrode 12 has four comb-tooth portions, but in actuality, the number of these is set to be larger, and FIG. 4 simplifies this. Show.

  5A and 5B, in the semiconductor device 200, a non-doped GaN layer 21A and an AlGaN layer 21B are sequentially formed on the substrate 20 as the semiconductor layer 21. As the substrate 20, a silicon substrate can be used, and a buffer layer (not shown) made of GaN, AlGaN or the like is formed on the surface thereof. An individual source electrode 31 and an individual drain electrode 32 are formed on the AlGaN layer 21 </ b> B, and an individual gate electrode 33 is formed between the individual source electrode 31 and the individual drain electrode 32. A pair of adjacent individual source electrode 31, individual drain electrode 32, and individual gate electrode 33 constitute individual HEMT elements, and the interface between the AlGaN layer 21B / non-doped GaN layer 21A between the individual source electrode 31 and the individual drain electrode 32. ON / OFF of the two-dimensional electron gas flowing through the first and second electrodes is controlled by a voltage applied to the individual gate electrode 33. In FIG. 5C, the description of the structure below the semiconductor layer 21 is omitted.

  As shown in FIGS. 5A and 5B, as described above, a large number of sets of the individual source electrode 31, the individual drain electrode 32, and the individual gate electrode 33 are periodically arranged and formed of a silicon oxide film or the like. An insulating interlayer insulating layer 34 is formed so as to cover all the individual source electrodes 31, the individual drain electrodes 32, and the individual gate electrodes 33. As shown in FIG. 5A, all the individual drain electrodes 32 are connected to the upper drain electrode 12 via drain electrode connection via wiring (via wiring) 32A provided in the interlayer insulating layer 34. As shown in FIG. 5B, all the individual source electrodes 31 are connected to the upper layer source electrode 11 via the source electrode connection via wiring (via wiring) 31A provided in the interlayer insulating layer 34. Is done. Although not shown, all the individual gate electrodes 33 are similarly connected to the gate electrode 13 via via wirings or other wirings. With such a structure, the operation of all the HEMT elements formed in the region shown in FIG. 4 can be performed uniformly, and an operating current can be supplied uniformly. In an actual product, the semiconductor device 200 is mounted on a package, and the source terminal, drain terminal, and gate terminal of the package are connected to the source electrode 11, the drain electrode 12, and the gate electrode 13 through bonding wires, respectively. Is performed by electrical connection to the source terminal, drain terminal, and gate terminal.

  Here, as described above, it is required that dielectric breakdown (discharge) due to a high voltage does not occur between the source electrode 11 and the drain electrode 12 during operation (off). In the configuration of FIG. 4, the distance between the source electrode 11 and the drain electrode 12 that are closely opposed to each other (L in FIG. 5C) is generally several tens μm or more, and the interlayer insulating layer 34 having a thickness L. The breakdown voltage of the (silicon oxide film) is sufficiently higher than the high voltage applied between the source electrode 11 and the drain electrode 12. For this reason, the discharge to be suppressed here is not a discharge caused by a dielectric breakdown at a location where the source electrode 11 and the drain electrode 12 are closest to each other, but a creeping discharge in which a current flows through a path through the surface.

  In order to suppress this creeping discharge, most of the surfaces of the source electrode 11 and the drain electrode 12 are covered with a protective film 40 made of a thick insulating layer (silicon oxide film, silicon nitride film). Only the part for connecting to is opened. In FIG. 4, this opening is a source opening 40 </ b> A for the source electrode 11 and a drain opening 40 </ b> B for the drain electrode 12. In order to suppress the creeping discharge, it is preferable that the opening area of the source opening 40A and the drain opening 40B is small. Therefore, the opening area is set to be small as long as the bonding wires can be sufficiently connected. The Further, in this case, creeping discharge is likely to occur between the source opening 40A and the drain opening 40B, and therefore it is preferable that the distance between the source opening 40A and the drain opening 40B is wide. Therefore, in FIG. 4, the source opening 40A is uniformly provided on the lower side (one side) and the drain opening 40B is uniformly provided on the upper side (the other side). In FIG. 4, the protective film 40 is not described, and only the source opening 40A and the drain opening 40B provided in the protective film 40 are shown. Similarly, a gate opening 40C is also provided on the gate electrode 13, and the gate electrode 13 (gate opening 40C) having a small potential difference with the source electrode 11 is close to the source electrode 11 and from the drain electrode 12. Are provided separately.

  Bonding wires are connected between the source terminal and each source opening 40A in the package and between the drain terminal and each drain opening 40B in the package, respectively, so that the drain terminal The resistance between each drain electrode 12 can be made sufficiently small, and a large current can be passed through many bonding wires between the source terminal and the drain terminal for operation. A voltage can be similarly applied to the gate electrode 13.

  When the semiconductor device 200 is actually manufactured, a large number of the structures shown in FIGS. 4 and 5 (single semiconductor device 200) are arranged on a single large-diameter wafer constituting the substrate 20, and then the single device is formed. After the semiconductor devices 200 are cut and separated, each is mounted on a package. In order to perform an operation test of each semiconductor device 200 in the state of the wafer before the cutting and separation, as shown in FIG. 4, in the state of this wafer, the prober probe P is used as the source instead of the bonding wire. In general, an inspection is performed in which a voltage is applied to the opening 40A, the drain opening 40B, and the gate opening 40C and the operation is performed in the same manner as in use. In order to flow a large current, as shown in FIG. 4, a large number of probes P are simultaneously used for each of the source electrode 11 and the drain electrode 12 as in the case of the bonding wire. As a result, it is possible to determine whether each semiconductor device 200 in the wafer is a non-defective product or a defective product, and only the semiconductor device 200 determined to be a non-defective product can be mounted on a package after being cut and separated to obtain a product.

JP 2000-340580 A

  When an operation test was performed by actually applying a voltage through the probe P in the structure of FIG. 4 in the wafer state, the source opening 40A and the lateral direction were formed in the lateral direction despite the formation of the protective film 40. In many cases, discharges are generated between the drain electrode 12 and the drain opening 40B adjacent to each other and the source electrode 11 adjacent to the drain opening 40B in the lateral direction. In FIG. 4, this discharge path in plan view is indicated as Q. This discharge is not generated in the interlayer insulating layer 34 or the protective film 40 between the adjacent source electrode 11 and drain electrode 12 at the shortest distance, and the protective film in the source opening 40A and the drain opening 40B. It was confirmed that this was creeping discharge in which current flowed through the surface via 40 side walls and the like.

  It is presumed that the cause of the creeping discharge is that a portion where the breakdown voltage is locally lowered is formed in the protective film 40 first. In this case, a discharge is generated along a path through the portion having a low withstand voltage from the sidewall of the protective film 40 in the source opening 40A and the drain opening 40B through the surface of the protective film 40. Although shown in a simplified manner in FIG. 5C, the protective film 40 is actually thin locally on the ends of the patterned source electrode 11 and drain electrode 12. Further, since unevenness due to the source electrode connection via wiring 31A and drain electrode connection via wiring 32A is actually formed in the source electrode 11 and the drain electrode 12, the non-uniform film thickness due to the unevenness is also protected. Occurs in the film 40. Furthermore, not only the film thickness of the protective film 40 varies due to such steps and irregularities, but also film quality fluctuations such as the occurrence of voids in the protective film 40 occur. Thus, the location where the film thickness or the film quality of the protective film 40 is non-uniform is the location where the breakdown voltage is locally reduced, and the creeping discharge path includes the location where the breakdown voltage is reduced. Presumed. In addition, the electric field spreading outward from the source opening 40A and the drain opening 40B is not actually uniform, and the region where the electric field strength is relatively high and the region where the breakdown voltage is reduced overlap. It is considered that discharge occurs.

  The form of the bonding wire and the probe P that are connected when the semiconductor device 200 is mounted in a package as a product is the same. However, in the package, the entire structure including the bonding wire is sealed with a mold resin having a high withstand voltage, so that creeping discharge is less likely to occur. On the other hand, the operation test (inspection) using the probe P is performed in the atmosphere. For this reason, the above-described discharge is unlikely to occur in an actual product package, and is particularly likely to occur during an operation test (inspection) in a wafer state.

  It is difficult to form the protective film 40 composed of a silicon oxide film or a silicon nitride film on the source electrode 11 and the drain electrode 12 so as to be sufficiently thick and uniform so that such non-uniformity does not become a problem. For this reason, when the insulating polyimide which can be formed by application instead is formed thickly on the protective film 40, the discharge can be suppressed.

  However, in order to form such a polyimide layer, a polyimide coating process, a curing process, an exposure development process for patterning this to form an opening and the like are required, and thus the manufacturing process becomes complicated. It was difficult to manufacture this semiconductor device at a low cost.

  That is, it has been difficult to obtain an inexpensive semiconductor device that hardly generates a discharge between electrodes during inspection.

  The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.

In order to solve the above problems, the present invention has the following configurations.
The semiconductor device of the present invention includes a first main electrode extending in one direction on one main surface side of the semiconductor layer, and a second main electrode extending in the one direction and facing the first main electrode. And an insulating protective film covering the one main surface side of the semiconductor layer including the first main electrode and the second main electrode is formed, and the protective film is locally formed on the first main electrode. A current flows between the first main electrode and the second main electrode through the removed first opening and the second opening from which the protective film is locally removed on the second main electrode. The floating electrode made of a conductor insulated from the periphery under the protective film extends in the one direction adjacent to the first opening in a plan view. Between the second main electrode and the first main electrode, adjacent to the second opening and in the one direction Between the first main electrode and the second main electrode of Shin, characterized in that it is formed, respectively.
In the semiconductor device of the present invention, the maximum electric field strength in a region where the floating electrode is not formed between the first main electrode and the second main electrode in a plan view has an insulation of an insulating layer around the floating electrode. It is provided so as not to exceed the breaking strength.
In the semiconductor device of the present invention, the floating electrode is formed in a region including an intermediate point in a direction perpendicular to the one direction between the adjacent first main electrode and the second main electrode in plan view. It is characterized by that.
The semiconductor device of the present invention is characterized in that a plurality of the floating electrodes are formed between the adjacent first main electrode and the second main electrode in plan view.
The semiconductor device of the present invention includes a plurality of locations where the first main electrode and the second main electrode extend in the one direction and face each other, and the first opening and the second opening are A plurality of discs are formed discretely on the first main electrode at the location and on the second main electrode at the location.
The semiconductor device of the present invention is characterized in that the floating electrode is continuously formed from a region adjacent to the first opening to a region adjacent to the second opening in a plan view.
In the semiconductor device of the present invention, in plan view, the floating electrode is discretely formed in each of the regions adjacent to the plurality of first openings and each of the regions adjacent to the plurality of second openings. It is characterized by that.
In the semiconductor device of the present invention, the plurality of first openings are all formed on one side in plan view on the one main surface of the semiconductor layer, and the plurality of second openings are all the one. It is formed on the other side opposite to this side.
In the semiconductor device of the present invention, the semiconductor layer includes a plurality of semiconductor elements that are operated by a current flowing between the individual first electrode and the individual second electrode, and the plurality of the individual first electrodes and the plurality of the individual first electrodes. An interlayer insulating layer covering two electrodes, wherein the first main electrode, the second main electrode, the floating electrode, and the protective film are formed on the interlayer insulating layer, and the first main electrode, the first The two main electrodes are respectively connected to the plurality of individual first main electrodes and the plurality of individual second main electrodes via via wirings formed in the interlayer insulating layer.
In the semiconductor device of the present invention, the first main electrode, the second main electrode, and the floating electrode are formed on substantially the same plane, and each of the first main electrode, the second main electrode, and the floating electrode is formed. The thickness is substantially the same.
The semiconductor device of the present invention includes a gate electrode that controls on / off of a current flowing between the first main electrode and the second main electrode.
In the semiconductor device of the present invention, the semiconductor layer is made of a group III nitride semiconductor, the first main electrode is one of a source electrode and a drain electrode, and the second main electrode is a source electrode and a drain electrode. The other is a high electron mobility transistor (HEMT).
In the semiconductor device of the present invention, the gate electrode is formed below the protective film on the one main surface side of the semiconductor layer, and the floating electrode corresponds to the drain electrode in plan view. The gate electrode is formed between one main electrode and one of the second main electrodes and the gate electrode.

  Since the present invention is configured as described above, it is possible to obtain an inexpensive semiconductor device that hardly generates a discharge between electrodes during inspection.

1 is a top view of a semiconductor device according to an embodiment of the present invention. It is sectional drawing of the AA direction of the semiconductor device which concerns on embodiment of this invention. It is a top view of the modification of the semiconductor device which concerns on embodiment of this invention. It is a top view of an example of a conventional semiconductor device. It is sectional drawing of the BB direction (a), CC direction (b), and DD direction (c) of an example of the conventional semiconductor device.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. FIG. 1 is a top view of the semiconductor device 100, and FIG. 2 is a cross-sectional view in the AA direction. Moreover, the cross-sectional views in the BB direction and the CC direction in FIG. 1 are the same as those in FIGS. FIG. 2 corresponds to the structure of FIG. 5C in the conventional semiconductor device 200.

  The semiconductor device 100 is a horizontal type and is composed of a large number of HEMT elements (semiconductor elements). Similar to the semiconductor device 200, the semiconductor layer 21 in which the substrate 20, the non-doped GaN layer 21A, and the AlGaN layer 21B are sequentially formed is used. An individual source electrode 31 and an individual drain electrode 32 are formed on the AlGaN layer 21 </ b> B, and an individual gate electrode 33 is formed between the individual source electrode 31 and the individual drain electrode 32. The individual source electrode 31 and the individual drain electrode 32 are made of a material that is in ohmic contact with the AlGaN layer 21 </ b> B, and ON / OFF of the current between the individual source electrode 31 and the individual drain electrode 32 is determined by the voltage applied to the individual gate electrode 33. Be controlled. A single HEMT element is formed by a set of adjacent individual source electrode 31, individual drain electrode 32, and individual gate electrode 33, and all the individual source electrodes 31 are formed in the interlayer insulating layer 34. (Via wiring) 31A A drain electrode connecting via wiring (via wiring) connected to the upper layer source electrode (first main electrode) 11 and all the individual drain electrodes 32 provided in the interlayer insulating layer 34 The same applies to the connection to the upper drain electrode (second main electrode) 12 through 32A and the connection of all the individual gate electrodes 33 to the gate electrode 13. Further, a protective film 40 is formed so as to cover the source electrode 11, the drain electrode 12, and the gate electrode 13, and a source opening (first opening) 40 </ b> A and a protection on the drain electrode 12 are formed in the protective film 40 on the source electrode 11. Similarly, a drain opening (second opening) 40B is provided in the film 40, and a gate opening 40C is provided in the protective film 40 on the gate electrode 13. In FIG. 1, the description of the protective film 40 is omitted, and only the source opening 40A, the drain opening 40B, and the gate opening 40C are shown.

  However, as shown in FIGS. 1 and 2, unlike the semiconductor device 200 described above, in the semiconductor device 100, the source at a location adjacent to the source opening 40 </ b> A formed in the protective film 40 in plan view. A floating electrode 50 is provided at an intermediate position between the electrode 11 and the drain electrode 12 and between the drain electrode 12 and the source electrode 11 at a position adjacent to the drain opening 40B. Further, the floating electrode 50 is formed along an intermediate point between the source electrode 11 and the drain electrode 12 in a gap between the source electrode 11 and the drain electrode 12 in a plan view. For this reason, the floating electrode 50 is configured such that it surrounds the source electrode 11 and further the drain electrode 12 surrounds the outside of the floating electrode 50. Therefore, as shown in FIG. 1, the floating electrode 50 extends between the source electrode 11 and the drain electrode 12 facing each other in the vertical direction in the drawing so as to extend in parallel with the extending direction (one direction). Is formed perpendicular to the discharge path Q at the location where the discharge path Q in FIG. Unlike the source electrode 11, the drain electrode 12, and the gate electrode 13, the floating electrode 50 is always at a floating potential because its surroundings are all insulated by the interlayer insulating layer 34 and the protective film 40.

  The interlayer insulating layer 34 is a silicon oxide film having a thickness of about 4 μm, and is formed by CVD or the like so that the individual source electrode 31, the individual drain electrode 32, and the individual gate electrode 33 can be insulated from the upper layer. The source electrode connecting via wiring (via wiring) 31A and the drain electrode connecting via wiring (via wiring) 32A partially open the interlayer insulating layer 34 on the individual source electrode 31 and the individual drain electrode 32, and the inside It is formed by embedding with a metal layer made of tungsten (W) or the like.

  Further, since a bonding wire is directly connected to the source electrode 11 or the like, or the probe P is in direct contact with the wafer state during inspection, the source electrode 11, the drain electrode 12, and the gate electrode 13 are sufficiently thick, for example, thick It is made of Al of about 5 μm. However, a thin film layer made of Ti or the like is also provided at the lowermost portion in order to improve adhesion.

  In the conventional semiconductor device 200, the source electrode 11, the drain electrode 12, and the gate electrode 13 are patterned after a uniform thick metal layer is formed on the interlayer insulating layer 34 (after exposure and development of the photoresist). The metal layer is partially etched). At this time, since the floating electrode 50 can be formed at the same time, a special process for forming the floating electrode 50 is not necessary. When the semiconductor devices 200 and 100 are manufactured, only the mask pattern at this time is different. It becomes. Therefore, the semiconductor device 100 can be manufactured at the same cost as the conventional semiconductor device 200, and the semiconductor device 100 can be manufactured at low cost. In this case, the source electrode 11, the drain electrode 12, the gate electrode 13, and the floating electrode 50 are formed as the same layer. That is, these electrodes are formed on substantially the same plane, and their thicknesses are equal.

  The protective film 40 is a silicon oxide film, a silicon nitride film, or the like having a thickness of about 2 μm so as to cover these electrodes in order to suppress creeping discharge between the drain electrode 12 and the source electrode 11 and the gate electrode 13. Composed. As described above, since the source electrode 11 and the like are formed thick, the protective film 40 is formed by using a CVD method having particularly good coverage, and a material using TEOS (tetraethoxysilane) or the like as a raw material is preferably used. . The source opening 40A and the drain opening 40B are formed by partially etching the protective film 40 that is uniformly formed in the same manner as the patterning of the source electrode 11 and the like.

  The effect of the floating electrode 50 will be described. First, in the semiconductor device 200 having the structure shown in FIGS. 4 and 5 in which the floating electrode 50 is not formed, the distance L between the source electrode 11 and the drain electrode 12 is set to 50 μm, and the source electrode 11 and the drain electrode 12 are turned off via the probe P. When a voltage of 600 V was applied between them, it was confirmed that discharge (creeping discharge) occurred in the discharge path Q shown in FIG. At this time, the direct electric field strength (0.12 MV / cm) between the source electrode 11 and the drain electrode 12 is sufficiently lower than the dielectric breakdown strength of the silicon oxide film or the like constituting the interlayer insulating layer 34 or the protective film 40. . Further, as shown by the discharge path Q in FIG. 4, the discharge is caused by the source electrode 11 exposed in the source opening 40A, the drain electrode 12 exposed in the drain opening 40B, and the protective film 40 adjacent to these. Occurred between the covered drain electrode 12 and source electrode 11, respectively.

  When the above-described semiconductor device 100 in which the source electrode 11, the drain electrode 12, etc. have the same configuration and the floating electrode 50 (width 5 μm) is formed along the intermediate point between the source electrode 11 and the drain electrode 12 is manufactured, Even when a voltage of 600 V was applied between the source electrode 11 and the drain electrode 12 at the time of inspection, no discharge occurred.

  1 and 2, in the left-right direction (the direction perpendicular to the extending direction of the source electrode 11 and the like), the potential is constant during the width M of the floating electrode 50 by forming the floating electrode 50. It occurs only in the left and right regions of the floating electrode 50. For this reason, the electric field strength in the interlayer insulating layer 34 or the protective film 40 in the left and right width (LM) / 2) region of the floating electrode 50 is larger than that in the case where the floating electrode 50 does not exist (M = 0). Despite being high, discharge is suppressed. Therefore, it is clear that the discharge generated in the structure of FIG. 4 is a creeping discharge rather than a direct breakdown of the interlayer insulating layer 34 or the protective film 40 between the source electrode 11 and the drain electrode 12. This creeping discharge is considered to be suppressed in the semiconductor device 100.

  By forming the floating electrode 50 having the configuration shown in FIGS. 1 and 2, in the region between the source electrode 11 and the drain electrode 12 adjacent to the source opening 40A and the drain opening 40B, the intermediate between the source electrode 11 and the drain electrode 12 is provided. The potential in the vicinity of the point is constant over the longitudinal direction (the direction along the outer periphery of the source electrode 11). For this reason, on the sides of the source opening 40A and the drain opening 40B, the potential in the creeping direction is uniform over the longitudinal direction of the source electrode 11 and the drain electrode 12, and a region where the electric field strength is locally increased is generated. It is considered that the suppression of the occurrence of discharge is less likely to occur.

  It is also clear that when the floating electrode 50 is formed between the source electrode 11 and the drain electrode 12, the flatness of the protective film 40 or the protective film 40 itself is improved. For this reason, the thickness of the protective film 40 and the uniformity of the film quality are increased, and it becomes difficult to form a region where the breakdown voltage is locally lowered.

  Here, when the potential of the floating electrode 50 is the same as or interlocks with any of the source electrode 11, the drain electrode 12, and the gate electrode 13, a new discharge path through the floating electrode 50 may be formed. . For this reason, the floating electrode 50 needs to be insulated from the periphery thereof, and the periphery is preferably surrounded by the protective film 40 and the interlayer insulating layer 34.

  As described above, by providing the floating electrode 50, it is possible to suppress discharge at the time of inspection and to appropriately perform an operation test in a wafer state. On the other hand, as described above, the provision of the floating electrode 50 increases the electric field strength in the left and right regions of the floating electrode 50 in FIG. 2, so that a discharge occurs in the region between the source electrode 11 or the drain electrode 12 and the floating electrode 50. Is likely to occur. Therefore, L (interval between the source electrode 11 and drain electrode 12) and M (width of the floating electrode 50) in FIG. 2 indicate that the electric field strength in this region is the dielectric breakdown strength (dielectric breakdown) of the interlayer insulating layer 34 and the protective film 40. The electric field intensity that generates the electric field) may be set so as not to exceed. As described above, a silicon oxide film or a silicon nitride film is used as the material for the interlayer insulating layer 34 and the protective film 40. The dielectric breakdown strength of these materials largely depends on the film quality and the like, but is approximately over 8 MV / cm. In the configuration of FIG. 2, between the source electrode 11 and the drain electrode 12, the electric field strength is zero in the region where the floating electrode 50 exists, and the electric field strength is uniform in the region where the floating electrode 50 does not exist. If the maximum voltage at the time of operation applied between the source electrode 11 and the drain electrode 12 is Vmax, the operation in the region where the floating electrode 50 between the source electrode 11 and the drain electrode 12 does not exist in the configuration of FIG. The maximum electric field strength at that time is Vmax / (L−M), and this value is sufficiently smaller than the dielectric breakdown strength of the interlayer insulating layer 34 and the protective film 40, for example, so that it does not exceed 5 MV / cm. A width M of 50 is set.

  In FIG. 2, the floating electrode 50 is provided at an intermediate point between the source electrode 11 and the drain electrode 12. However, even when the floating electrode 50 is not located at the intermediate point, at least the side of the source opening 40A and the drain opening 40B. It is clear that there is an effect of making the potential distribution uniform over the longitudinal direction of the source electrode 11 and the drain electrode 12. For this reason, it is not necessary to provide the floating electrode 50 at an intermediate point between the source electrode 11 and the drain electrode 12. Even in this case, since the electric field strength in the region where the floating electrode 50 does not exist is uniform, the restriction on Vmax / (LM) is the same as described above.

  However, when the floating electrode 50 is provided at an intermediate point, the manufacturing is particularly easy, and the entire structure between the source electrode 11 and the drain electrode 12 is symmetrical in the horizontal direction in FIGS. Therefore, the protective film 40 and the like can be easily formed uniformly, and non-uniformity that causes local dielectric breakdown is particularly difficult to occur. For this reason, the structure of FIGS. 1 and 2 in which the floating electrode 50 is provided in a region including the intermediate point is particularly preferable.

  On the other hand, in the above example, only one floating electrode 50 is provided between the source electrode 11 and the drain electrode 12, but a plurality of floating electrodes are provided in parallel between the source electrode 11 and the drain electrode 12. It is clear that the same effect can be obtained. In this case, even if the floating electrode is not provided at an intermediate point between the source electrode and the drain electrode, the overall structure can be made symmetrical, and the uniformity of the protective film 40 can be further improved. Also, in this case, since the number of regions where the potential is constant between the source electrode and the drain electrode in plan view increases according to the number of floating electrodes, the effect of suppressing the generation of a region where the electric field strength is locally large is generated. Also particularly large. On the other hand, when the area occupied by the floating electrode (the total width of the floating electrode) increases, the maximum electric field strength during operation in the region where the floating electrode is not formed between the source electrode and the drain electrode is Therefore, the number and width of the floating electrodes are appropriately set within a range where the maximum electric field strength is allowed in the same manner as described above.

  Further, as described above, since the discharge path Q in FIG. 4 is formed only in the region adjacent to the source opening 40A and the drain opening 40B, the floating electrode 50 is adjacent to the source opening 40A and the drain opening 40B. It is sufficient to form it only in the region. However, as shown in FIG. 1, by continuously configuring the floating electrode 50 so as to surround the source electrode 11 along the outer periphery of the source electrode 11, the potential distribution becomes wider along the outer periphery of the source electrode 11. Since it can be made uniform in the range, the effect of preventing discharge becomes larger.

  On the other hand, when the floating electrode 50 is formed so long, defects are generated in the pattern of the source electrode 11, the drain electrode 12, and the floating electrode 50 due to, for example, dust at the time of manufacture. May occur easily. Therefore, as a configuration of a modified example of the semiconductor device 100 described above, as shown in a top view in FIG. 3, only a necessary minimum portion, that is, a region adjacent to the source opening 40A and the drain opening 40B is locally applied. Alternatively, the floating electrode 50 may be formed. In this case, a large number of divided floating electrodes 50 are formed. Even in such a case, the source electrode 11, the drain electrode 12, and the floating electrode 50 can be similarly formed by changing the etching pattern of the metal layer in the same manner as described above.

  1 and 3 and the like, even if the positional relationship between the source electrode (first main electrode) 11 and the individual source electrode 31, the drain electrode (second main electrode) 12 and the individual drain electrode 32 is changed, the same applies. It is clear that the effects of Also in this case, it is preferable that the gate electrode is provided apart from the drain electrode on the high potential side and close to the source electrode side on the low potential side.

  In the above configuration, the source electrode 11, the drain electrode 12, and the floating electrode 50 are formed in the same process using the same metal layer. For example, the floating electrode 50 is connected to the source electrode 11 and the drain electrode 11. Even if it is formed as a separate layer in a separate process, it is obvious that the discharge can be similarly suppressed as long as a similar structure can be realized. However, when the source electrode 11, the drain electrode 12, and the floating electrode 50 are formed in the same layer using the same metal pattern, the manufacturing cost is particularly low. Further, in this case, since the source electrode 11, the drain electrode 12, and the floating electrode 50 having the same thickness are arranged on the same plane, it is particularly effective in terms of improving the uniformity of the protective film.

  In addition, the semiconductor device 100 is a HEMT using a group III nitride semiconductor (GaN-based), but is also a horizontal semiconductor device and has a large current on the surface (one main surface) side in the semiconductor layer. It is clear that the above configuration is effective if two electrodes (first main electrode and second main electrode) through which current flows are provided. For this reason, the same configuration can be applied to a horizontal power MOSFET or an insulated gate bipolar transistor (IGBT) in which a semiconductor layer is formed of, for example, silicon (Si) or silicon carbide (SiC). At this time, the above configuration is effective regardless of the channel type (n-channel, p-channel) of the power MOSFET or IGBT.

  Alternatively, even if an electrode (gate electrode) used for controlling the operating current is not provided, the same configuration is effective as long as a current flows between the first main electrode and the second main electrode. For example, the above configuration is also effective in a pn junction diode, a Schottky barrier diode (SBD), or the like. When the gate electrode is used, as shown in FIGS. 1 and 3, a floating electrode is provided between the first main electrode and the second main electrode where the potential difference between the gate electrode and the gate electrode is large and the gate electrode. It is preferable to provide it.

100, 200 Semiconductor device (HEMT)
11 Source electrode (first main electrode)
12 Drain electrode (second main electrode)
13 Gate electrode 20 Substrate 21 Semiconductor layer 21A Non-doped GaN layer 21B AlGaN layer 31 Individual source electrode 31A Via wiring for connecting source electrode (via wiring)
32 Individual drain electrode 32A Drain electrode connection via wiring (via wiring)
33 Individual gate electrode 34 Interlayer insulating layer 40 Protective film 40A Source opening (first opening)
40B Drain opening (second opening)
40C Gate opening 50 Floating electrode P Probe Q Discharge path

Claims (13)

A first main electrode extending in one direction on one main surface side of the semiconductor layer; and a second main electrode extending in the one direction and facing the first main electrode, the first main electrode And an insulating protective film covering the one main surface side of the semiconductor layer including the second main electrode, and the first opening in which the protective film is locally removed on the first main electrode A semiconductor device which operates by passing a current between the first main electrode and the second main electrode through the second opening from which the protective film is locally removed on the second main electrode. There,
The second main electrode and the first main electrode, which are formed of a conductor insulated from the surroundings under the protective film, extend in the one direction adjacent to the first opening in a plan view. The semiconductor device is formed between the first main electrode and the second main electrode which are adjacent to the second opening and extend in the one direction.   The maximum electric field strength in a region where the floating electrode is not formed between the first main electrode and the second main electrode in plan view does not exceed the dielectric breakdown strength of the insulating layer around the floating electrode. The semiconductor device according to claim 1, wherein the semiconductor device is provided.   The planar electrode is characterized in that the floating electrode is formed in a region including an intermediate point in a direction perpendicular to the one direction between the adjacent first main electrode and the second main electrode. 3. The semiconductor device according to 1 or 2.   3. The semiconductor device according to claim 1, wherein a plurality of the floating electrodes are formed between the adjacent first main electrode and the second main electrode in plan view. A plurality of locations where the first main electrode and the second main electrode extend in the one direction and face each other;
2. The plurality of first openings and the second openings are discretely formed on the first main electrode at the location and on the second main electrode at the location, respectively. The semiconductor device according to claim 1.   6. The semiconductor device according to claim 5, wherein the floating electrode is continuously formed from a region adjacent to the first opening to a region adjacent to the second opening in a plan view.   The planar electrode is characterized in that the floating electrodes are discretely formed in each of a region adjacent to the plurality of the first openings and each of a region adjacent to the plurality of the second openings. Item 6. The semiconductor device according to Item 5.   On the one main surface of the semiconductor layer, the plurality of first openings are all formed on one side in a plan view, and the plurality of second openings are all on the other side opposite to the one side. The semiconductor device according to claim 5, wherein the semiconductor device is formed on a side. In the semiconductor layer, a plurality of semiconductor elements that are operated by passing a current between the individual first electrode and the individual second electrode are formed,
An interlayer insulating layer covering the plurality of individual first electrodes and the plurality of individual second electrodes;
The first main electrode, the second main electrode, the floating electrode, and the protective film are formed on the interlayer insulating layer,
The first main electrode and the second main electrode are respectively connected to the plurality of individual first main electrodes and the plurality of individual second main electrodes via via wirings formed in the interlayer insulating layer. The semiconductor device according to claim 1, wherein:   The first main electrode, the second main electrode, and the floating electrode are formed on substantially the same plane, and the thicknesses of the first main electrode, the second main electrode, and the floating electrode are substantially the same. The semiconductor device according to claim 9.   11. The semiconductor according to claim 1, further comprising a gate electrode that controls on / off of a current flowing between the first main electrode and the second main electrode. apparatus.   The semiconductor layer is made of a group III nitride semiconductor, and the first main electrode is one of a source electrode and a drain electrode, and the second main electrode is the other of the source electrode and the drain electrode. The semiconductor device according to claim 11, wherein the semiconductor device is a degree transistor (HEMT). The gate electrode is formed under the protective film on the one main surface side of the semiconductor layer;
13. The floating electrode according to claim 12, wherein the floating electrode is formed between one of the first main electrode and the second main electrode corresponding to the drain electrode and the gate electrode in plan view. The semiconductor device described.

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