JP2017059598A - Wafer and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wafer and a semiconductor device capable of suppressing cracks.SOLUTION: According to an embodiment, a wafer includes a base substance and a foundation part. The base substance includes a plurality of crystal grains. The foundation part includes an amorphous first foundation layer, and a second foundation layer containing silicon. The first foundation layer is provided between the second foundation layer and the base substance. A thickness of the first foundation layer is equal to or less than 140 nanometers. A thickness of the second foundation layer is equal to or less than 70 nanometers. An average grain diameter of the crystal grains is less than 3.1 micrometers.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a wafer and a semiconductor device.

  In a nitride semiconductor device, a nitride semiconductor is formed on a substrate. Cracks may occur due to the difference in thermal expansion coefficient between the substrate and the nitride semiconductor.

US Pat. No. 6,794,276B2

  Embodiments of the present invention provide a wafer and a semiconductor device capable of suppressing cracks.

  According to the embodiment of the present invention, the wafer includes a base and a base portion. The base includes a plurality of crystal grains. The foundation portion includes an amorphous first foundation layer and a second foundation layer containing silicon. The first underlayer is provided between the second underlayer and the base body. The first underlayer has a thickness of 140 nanometers or less. The second underlayer has a thickness of 70 nanometers or less. The average grain size of the crystal grains is 3.1 micrometers or less.

FIG. 1A to FIG. 1C are schematic views illustrating a wafer according to the first embodiment. 2A to 2C are schematic cross-sectional views in order of the processes, illustrating the method for manufacturing a substrate according to the first embodiment. FIG. 3A and FIG. 3B are schematic views illustrating experimental results of peeling that occurs on the substrate. It is a schematic diagram which illustrates the experimental result of the peeling which arises on a board | substrate. FIG. 5A and FIG. 5B are schematic views showing irregularities on the surface of the substrate. It is a graph which illustrates the characteristic of a substrate. It is a graph which illustrates the characteristic of a silicon film. It is a schematic diagram which illustrates another wafer which concerns on 1st Embodiment. FIG. 9A and FIG. 9B are schematic cross-sectional views illustrating another wafer according to the first embodiment. It is a graph which illustrates the characteristic of a wafer. FIG. 6 is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating a wafer according to a third embodiment. FIG. 6 is a schematic cross-sectional view illustrating a semiconductor device according to a fourth embodiment. FIG. 9 is a schematic cross-sectional view illustrating a semiconductor device according to a fifth embodiment. FIG. 15A and FIG. 15B are schematic views illustrating another semiconductor device according to the fifth embodiment. FIG. 10 is a schematic cross-sectional view illustrating another semiconductor device according to the fifth embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Even in the case of representing the same part, the dimensions and ratios may be represented differently depending on the drawings.
In the present specification and drawings, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
FIG. 1A to FIG. 1C are schematic views illustrating a wafer according to the first embodiment. FIG. 1A and FIG. 1B are schematic cross-sectional views. FIG. 1C is a scanning electron microscope SEM (Scanning Electron Microscope) image. FIG.1 (b) is the schematic diagram drawn based on FIG.1 (c).
As shown in FIG. 1A, the wafer 150 according to this embodiment includes a base body 60 and a base portion 65. The foundation portion 65 includes a first foundation layer 61 and a second foundation layer 62. The substrate 60 and the base portion 65 (the first base layer 61 and the second base layer 62) are included in the substrate 50. The first foundation layer 61 is provided between the second foundation layer 62 and the base body 60. The first foundation layer 61 is in contact with the base body 60.

  A direction from the base body 60 toward the base portion 65 (for example, a direction from the base body 60 toward the second base layer 62) is defined as a Z-axis direction (first direction). One direction perpendicular to the Z-axis direction is taken as an X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is taken as a Y-axis direction.

  In the present specification, the state in which the first element is provided on the second element is a state in which the first element and the second element are in contact with each other and a third element is provided between the first element and the second element. State.

  The base body 60 has a base surface 60s (for example, the main surface of the base body 60). The base surface 60s is substantially perpendicular to the Z-axis direction, for example. The base surface 60 s is in contact with the first base layer 61. The first foundation layer 61 is provided on the base surface 60s. The second foundation layer 62 is provided on the first foundation layer 61.

  The first foundation layer 61 is, for example, amorphous. The first foundation layer 61 includes, for example, silicon oxide. The first foundation layer 61 includes, for example, silicon dioxide. The first foundation layer 61 may include, for example, at least one of silicon oxide and silicon oxynitride. The first foundation layer 61 is, for example, a silicon oxide layer.

  The thickness t1 (length in the Z-axis direction) of the first base layer 61 is, for example, 140 nanometers (nm) or less. The thickness t1 is, for example, 15 nm or more. In order to suppress peeling, the thickness t1 is more desirably 35 nm or more. The thickness t1 is, for example, about 100 nm.

  The second underlayer 62 is crystalline. The second foundation layer 62 includes, for example, silicon. The second foundation layer 62 is, for example, a silicon layer. The thickness t2 (length in the Z-axis direction) of the second base layer 62 is, for example, 70 nm or less. The thickness t2 is, for example, 8 nm or more. In order to suppress peeling, the thickness t2 is more desirably 18 nm or more. The thickness t2 is, for example, about 50 nm.

  The substrate 60 has a back surface 60r in addition to the substrate surface 60s. The back surface 60r is a surface opposite to the base surface 60s. The thickness t0 (length in the Z-axis direction) of the base body 60 is, for example, about 0.7 mm (for example, 0.15 mm to 1.5 mm). The thickness t0 corresponds to the distance between the base surface 60s and the back surface 60r.

  The planar shape of the wafer 150 (planar shape of the substrate 50) is, for example, a substantially circular shape. The diameter of the substrate 50 is, for example, 200 mm or more. The diameter is, for example, 450 mm or less. In the embodiment, the upper limit of the diameter is arbitrary.

  As shown in FIG. 1B, the base 60 includes a plurality of crystal grains 60g. The plurality of crystal grains 60g include, for example, aluminum nitride (AlN). That is, the base body 60 includes, for example, polycrystal. The polycrystal includes AlN. The polycrystal includes, for example, a sintered body. The base 60 includes, for example, an AlN polycrystalline sintered body. The crystal grain 60g is surrounded by a grain boundary 60b.

For example, in the cross section of the base body 60, a plurality of crystal grains 60g are observed. For example, a cross section is observed by SEM. In the observation image, each of the plurality of crystal grains 60g is not necessarily spherical. The length of the crystal grain 60g in one direction is longer than the length of the crystal grain 60g in another one direction. In one crystal grain 60g, the length of the crystal grain 60g is the longest in one direction. In one crystal grain 60g, the longest length of the crystal grain 60g is L1. L2 is the longest length of the one crystal grain 60g along the direction orthogonal to the one direction. The geometric mean ((L1 × L2) ^1/2 ) of the length L1 and the length L2 is taken as the diameter of one crystal grain 60g. Each of the plurality of crystal grains 60g has such a diameter. The arithmetic average of the diameters of the plurality of crystal grains 60 g is defined as an average particle diameter d 60 in the base body 60.

Thus, the average particle diameter d60 of the crystal grains 60g is calculated from, for example, the SEM image of the cross section of the substrate 60. The area of the cross section for calculation is 50 μm ² .

  In the embodiment, the average particle diameter d60 of the crystal grains 60g is, for example, less than 3.1 μm (micrometer). The average particle diameter d60 is, for example, 2.5 μm or more.

  The substrate surface 60s of the substrate 60 has irregularities 60dp. The depth D60 (height) of the unevenness 60dp is, for example, not less than 50 nm and not more than 65 nm.

  The unevenness 60dp includes, for example, a plurality of concave portions or a plurality of convex portions. For example, unevenness 60 dp (a plurality of concave portions or a plurality of convex portions) is observed from a cross section of the base body 60 (a cross section including the Z-axis direction). The depth D60 of the unevenness 60dp is obtained from this cross section. The depth (or height) of each of the plurality of concave portions or the plurality of convex portions is obtained from the images (cross-sectional images) of the plurality of concave portions or the plurality of convex portions of the unevenness dp of the base surface 60s of the base body 60. The maximum value of the depth (or height) of each of the plurality of concave portions or the plurality of convex portions in the predetermined range is set as the depth D60 of the unevenness 60dp. The depth D60 of the unevenness 60dp is also the height of the unevenness 60dp. The unevenness dp of the base surface 60s may be obtained from a plurality of observation images.

  In the calculation of the depth D60 of the unevenness 60dp, the predetermined range is a range having a length of 7.5 μm. That is, in the SEM image of the cross section of the base body 60 (cross section including the Z-axis direction), the width of the base body surface 60s (the length in the direction perpendicular to the Z-axis direction) is 7.5 μm. It is said. The depth (maximum value) of the plurality of irregularities 60dp on the base surface 60s having this width is defined as the depth D60.

  The base surface 60s is formed by polishing, for example. The accuracy of polishing on the base surface 60s is higher than the accuracy of polishing on the back surface 60r. The back surface 60r may also have irregularities. The depth D60 of the unevenness 60dp on the base surface 60s is smaller than the depth of the unevenness on the back surface 60r.

  As illustrated in FIG. 1A, the functional unit 10 </ b> F is formed on the second base layer 62. The functional unit 10F includes, for example, a nitride semiconductor. The functional unit 10F includes, for example, GaN.

  In the substrate 50 according to the embodiment, the base body 60 includes, for example, AlN. On the other hand, the functional unit 10F includes a nitride semiconductor. The thermal expansion coefficient of the base body 60 is relatively close to the thermal expansion coefficient of the functional unit 10F. For this reason, the curvature of the board | substrate 50 when the functional part 10F is formed on the board | substrate 50 at high temperature and it returns to room temperature after that can be suppressed.

  For example, in a reference example in which a nitride semiconductor layer is formed on a silicon substrate, the substrate is greatly warped. This is because the difference in thermal expansion coefficient between silicon and nitride semiconductor is large.

  In the embodiment, the thermal expansion coefficient of the base body 60 is not less than 0.75 times and not more than 1.3 times the thermal expansion coefficient of the functional unit 10F. Thereby, curvature can be suppressed.

  When the functional unit 10F is formed on the substrate 50, the first base layer 61 and the second base layer 62 are provided between the base body 60 and the functional unit 10F. The difference between the thermal expansion coefficient of these underlayers and the thermal expansion coefficient of the substrate 60 is large. However, since two layers (base 60 and functional unit 10F) having relatively close thermal expansion coefficients are provided on both sides of the base layer, warping is suppressed.

  And even if the thermal expansion coefficient between these foundation layers and the base | substrate 60 differs greatly and the thermal expansion coefficients between these foundation layers and the function part 10F differ greatly, the thickness of these foundation layers is different. Since it is thin, the occurrence of cracks or the like in these underlayers is suppressed.

  For example, there is a first reference example in which a nitride semiconductor layer is formed on a sapphire substrate. In this case, the difference in thermal expansion coefficient between sapphire and the nitride semiconductor is relatively small, and the difference in lattice spacing is also relatively small. For this reason, in the first reference example, the nitride semiconductor layer is hardly cracked. However, the dislocation density in the nitride semiconductor layer is relatively high. This is considered to be because the crystal structure of sapphire (corundum structure) and the crystal structure of the nitride semiconductor layer (wurzeite structure) are different from each other.

  On the other hand, there is a second reference example in which a nitride semiconductor layer is formed on a silicon substrate. Since a silicon substrate having a large area can be obtained at a low cost, it is considered advantageous for cost reduction. However, there is a large difference in thermal expansion coefficient between silicon and nitride semiconductor. For this reason, in the second reference example, when the nitride semiconductor layer is formed at a high temperature and then returned to room temperature, the substrate is greatly warped. Cracks are likely to occur in the nitride semiconductor layer. The thermal expansion coefficient of silicon is smaller than the thermal expansion coefficient of nitride semiconductor, and the difference between the thermal expansion coefficient of silicon and the thermal expansion coefficient of nitride semiconductor is large. Nitride semiconductors are subject to tensile strain. For this reason, the substrate is likely to warp and cracks are likely to occur.

  On the other hand, there is a third reference example in which a nitride semiconductor layer is formed on a GaN single crystal substrate or an AlN single crystal substrate. In this case, since the difference in thermal expansion coefficient is small between the substrate and the nitride semiconductor layer, cracks are unlikely to occur. Since the crystal structure is the same, the dislocation density is low and high crystal quality can be obtained. However, it is difficult to obtain a large area in these single crystal substrates. For this reason, there is a limit to cost reduction.

  For example, in a polycrystalline substrate such as AlN, a large area can be obtained relatively easily. The difference between the thermal expansion coefficient of AlN or the like and the thermal expansion coefficient of the nitride semiconductor layer is small or no difference. For this reason, when a nitride semiconductor layer is provided on a polycrystalline substrate such as AlN, cracks due to differences in thermal expansion coefficients are unlikely to occur. However, when the nitride semiconductor layer is directly formed on the polycrystalline substrate, the nitride semiconductor layer is affected by the crystal orientation of each of the plurality of crystal grains included in the polycrystalline substrate. For this reason, it is difficult to obtain good crystallinity in the nitride semiconductor layer.

  In the embodiment, the wafer 150 (substrate 50) is formed on, for example, an AlN polycrystalline base 60, a silicon oxide first base layer 61 provided on the base 60, and the first base layer 61. And a second underlayer 62 containing silicon provided. By providing the second underlayer 62, when a nitride semiconductor layer is formed on the second underlayer 62, the influence of the respective crystal orientations of the plurality of crystal grains of the substrate 60 is suppressed in the nitride semiconductor layer. it can.

  At this time, if the second base layer 62 of silicon is directly provided on the polycrystalline base 60 of AlN, AlN and silicon react. For this reason, it is difficult to obtain a desired underlayer.

  In the embodiment, a first underlayer 61 containing silicon oxide is provided between a polycrystalline base 60 of AlN and a second underlayer 62 containing silicon. As a result, this reaction is suppressed, and a desired silicon layer (second base layer 62) is obtained.

  A functional unit 10F including a nitride semiconductor is formed on the substrate 50 (on the second base layer 62 of silicon). At the surface of silicon, the transition density is low. For this reason, a nitride semiconductor layer (functional unit 10F) having a low dislocation density is obtained by forming a nitride semiconductor layer on the second underlayer 62 of silicon. A favorable crystalline nitride semiconductor layer (functional portion 10F) is obtained. For example, a layer containing silicon nitride (SiN) may be formed on the second base layer 62 of silicon, and a nitride semiconductor layer may be further formed thereon. Thereby, a nitride semiconductor layer (functional part 10F) having a lower dislocation density is obtained.

  Since the difference in coefficient of thermal expansion is small between the base body 60 (AlN polycrystalline substrate) and the functional part 10F (nitride semiconductor), cracks are unlikely to occur. A large area can be obtained relatively easily by using a polycrystalline substrate.

  In the embodiment, the thickness of these foundation layers is reduced. As a result, when the stress due to the temperature change when the functional unit 10F (nitride semiconductor layer) is grown at a high temperature is applied to the underlayer, the deformation of these underlayers is prevented without causing a large number of cracks. Is possible. When stress is applied to the underlayer, the generation of cracks in the underlayer is suppressed.

  As will be described later, in the embodiment, when the average grain size d60 of the polycrystalline crystal grains 60g of the substrate 60 is a predetermined size, good characteristics can be obtained. Before describing the appropriate average particle diameter d60, an example of a method for manufacturing the substrate 50 according to the embodiment will be described.

2A to 2C are schematic cross-sectional views in order of the processes, illustrating the method for manufacturing a substrate according to the first embodiment.
As shown in FIG. 2A, a first structure S1 and a second structure S2 are prepared.

  The first structure S1 includes a base body 60 and a first silicon oxide film 61a. The first silicon oxide film 61 a becomes a part of the first base layer 61. The first silicon oxide film 61 a is provided on the base surface 60 s of the base 60. The thickness t11 of the first silicon oxide film 61a is, for example, not less than 7 nm and not more than 140 nm (for example, about 40 nm).

  The polycrystalline substrate to be the base 60 is formed by, for example, sintering. The substrate 60 is obtained by polishing the surface of the polycrystalline substrate.

  The second structure S2 includes a silicon substrate 62s and a second silicon oxide film 61b. The second silicon oxide film 61 b becomes a part of the first base layer 61. The silicon substrate 62s has a surface 62sa and a surface 62sb. The surface 62sb is a surface opposite to the surface 62sa. The second silicon oxide film 61b is provided on the surface 62sa. The thickness t21 of the silicon substrate 62s is, for example, not less than 0.28 mm and not more than 1.2 mm (for example, about 0.65 mm). The thickness t22 of the second silicon oxide film 61b is, for example, not less than 5 nm and not more than 50 nm (for example, about 30 nm).

  As shown in FIG. 2A, the first structure S1 and the second structure S2 are arranged to face each other. The first silicon oxide film 61a and the second silicon oxide film 61b are opposed to each other.

  As shown in FIG. 2B, the first silicon oxide film 61a and the second silicon oxide film 61b are joined. For example, the first silicon oxide film 61a and the second silicon oxide film 61b are brought into contact with each other and heated. Thereby, these silicon oxide films are bonded. Thereby, 1st structure S1 and 2nd structure S2 are joined. The first base layer 61 is formed by the bonded first silicon oxide film 61a and second silicon oxide film 61b.

  As shown in FIG. 2C, the thickness t21 of the silicon substrate 62s is decreased. Thereby, the second underlayer 62 is obtained from the silicon substrate 62s. Thereby, the substrate 50 is obtained.

  It has been found that in the substrate 50 obtained by such a method, the underlayer may be peeled off. The peeling of the underlayer depends on the surface state of the substrate 60. In particular, it is considered that the unevenness 60 dp on the surface of the substrate 60 (substrate surface 60 s) is related to peeling.

  As described above, the base 60 is obtained by polishing the surface of the polycrystalline substrate to be the base 60. At this time, irregularities 60dp are formed on the substrate surface 60s of the substrate 60 including the polycrystalline crystal grains 60g. The unevenness 60 dp on the substrate surface 60 s is affected by the grain size of the crystal grains 60 g. For example, when the substrate serving as the base 60 is amorphous or single crystal, the degree of unevenness on the surface of the substrate is determined by the polishing conditions. However, in the case of a polycrystalline substrate, irregularities remain on the surface of the substrate even if the surface of the substrate is polished with high accuracy. This unevenness is caused by the polycrystalline crystal grains 60 g. The depth D60 of the unevenness 60dp on the base surface 60s of the base body 60 is affected by the size (grain size) of the crystal grains 60g.

  Hereinafter, experiments conducted by the inventors will be described. In the experiment, the average particle diameter d60 (size) of the crystal grains 60g is changed in the base body 60 containing AlN polycrystals. The size is changed depending on the sintering conditions of the substrate 60. A first underlayer 61 of silicon oxide is formed on a base 60 having a different average grain size d60 of crystal grains 60g, thereby forming a first structure S1. Such a first structure S1 is joined to the second structure S2.

  According to experiments, when the average grain size d60 of 60 g of AlN crystal grains exceeds about 3.1 μm (for example, when 3.3 μm or 4.7 μm), the first silicon oxide of the first underlayer 61 is used. The film 61a is easily peeled off. When the first silicon oxide film 61a is formed on the base surface 60s of the base body 60, silicon oxide cannot fill the deep position of the concave portion of the base surface 60s, and a cavity remains in the deep position of the concave portion. It is thought to be the cause. When the first structure S1 (base 60 and first silicon oxide film 61a) and the second structure S2 in this state are joined, the first silicon oxide film 61a is easily peeled off from the base 60 after the joining process. In the heating step of bonding (for example, 100 ° C. or more and 300 ° C. or less), it is considered that the gas existing in the cavity of the recesses 60dp of the substrate surface 60s of the substrate 60 expands and peels off.

  When the average particle diameter d60 of the crystal grains 60g of the substrate 60 is 3.1 μm or less (for example, 2.9 μm or 2.5 μm), it is found that the first silicon oxide film 61a is difficult to peel off. It was.

FIG. 3A and FIG. 3B are schematic views illustrating experimental results of peeling that occurs on the substrate.
These drawings illustrate optical micrographs of the surface of the substrate 60 after the first structure S1 and the second structure S2 are joined. In FIG. 3A, the average particle diameter d60 of the crystal grains 60g of the substrate 60 is 2.9 μm. In FIG.3 (b), the average particle diameter d60 of the crystal grain 60g of the base | substrate 60 is 3.3 micrometers.

  As shown in FIG. 3B, when the average particle diameter d60 is 3.3 μm, a part (silicon) of the second underlayer 62 is observed, but a part of the second underlayer 62 is observed. The first base layer 61 (silicon oxide) and the base body 60 are exposed on the surface.

  As shown in FIG. 3A, when the average particle diameter d60 is 2.9 μm, the surface is covered with the second underlayer 62 (silicon), and peeling is suppressed.

  When a plurality of samples are evaluated, a sample with a relatively small average particle size d60 (average particle size d60 of 3.1 μm or less) may be partially peeled off on the substrate. I understood. When the area where peeling has occurred and the area where peeling has not occurred, the average particle diameter d60 in the part where peeling has occurred is smaller than the average particle diameter d60 in the part where peeling has not occurred. I understood.

FIG. 4 is a schematic view illustrating an experimental result of peeling occurring on the substrate.
These drawings illustrate optical micrographs of the surface of the substrate 60 after the first structure S1 and the second structure S2 are joined. In FIG. 4, the average particle diameter d60 of the crystal grains 60g of the substrate 60 is 2.4 μm.

  As shown in FIG. 4, when the average particle size d60 is 2.4 μm, the first base layer 61 (silicon oxide) and the second base layer 62 (silicon) are not observed, and only the base 60 is observed. . That is, the first ground layer 61 and the second ground layer 62 are all peeled off.

  Thus, when the average particle diameter d60 of the base 60 is excessively small, it is considered that the adhesion between the base 60 and the first underlayer 61 (silicon oxide) decreases. For example, when the average particle diameter d60 of the substrate 60 is excessively small (for example, 2.4 μm or less), the unevenness 60dp on the surface of the substrate 60 (substrate surface 60s) is excessively small, and the substrate surface 60s becomes flat. It is considered that the adhesive force between the base body 60 and the first base layer 61 is reduced by the base surface 60s being excessively flat.

  When the average grain size d60 of the polycrystalline crystal grains 60g of the base body 60 is excessively large or excessively small, the first base layer S1 and the second structural body S2 are joined and then the first underlayer 61 is easy to peel off. When the average particle diameter d60 is excessively large, the unevenness 60dp formed on the base surface 60s of the base body 60 is large, and the first underlayer 61 does not sufficiently fill the concave portions of the unevenness 60dp. Thereby, it is considered that a cavity is formed in the concave portion and peeling occurs due to generation of gas or the like. On the other hand, when the average particle diameter d60 is excessively small, the base surface 60s becomes excessively flat, and as a result, the contact area between the base surface 60s and the first underlayer 61 decreases. This is considered to cause peeling.

  In the substrate 60, when the average grain size d60 of the polycrystalline (Al polycrystalline) crystal grains 60g is 3.1 μm or less, peeling of the underlayer is suppressed. When the average particle size d60 is 2.5 μm or more and 3.1 μm or less, peeling of the underlayer can be more stably suppressed.

FIG. 5A and FIG. 5B are schematic views showing irregularities on the surface of the substrate.
In Fig.5 (a), the average particle diameter d60 is 1.7 micrometers. In FIG.5 (b), the average particle diameter d60 is 4.7 micrometers. FIG. 5A and FIG. 5B are schematic diagrams drawn based on a cross-sectional SEM image of a sample.

  As shown in FIG. 5A, when the average particle diameter d60 is 1.7 μm, the depth of the unevenness 60dp of the base surface 60s of the base body 60 is shallow, and the flatness of the base surface 60s is high. When the average particle diameter d60 is 1.7 μm, the depth D60 of the unevenness 60dp on the base surface 60s is about 40 nm.

  As shown in FIG. 5B, when the average particle diameter d60 is 4.7 μm, the depth of the unevenness 60dp on the base surface 60s of the base body 60 is deep, and the flatness of the base surface 60s is low. When the average particle diameter d60 is 4.7 μm, the depth D60 of the unevenness 60dp on the base surface 60s is about 250 nm. In this case, the concave portion of the unevenness 60 dp is large. For example, the width of the upper end (opening) of the concave portion of the unevenness 60 dp is about 3 μm. The ratio of the depth of the unevenness 60dp to the width (depth / width) is about 0.083.

  When the concave portion of the unevenness 60dp on the substrate surface 60s is large, it is considered that the filling (planarization) with silicon oxide serving as the first underlayer 61 is insufficient. When the recesses of the unevenness 60 dp on the base surface 60 s are small, it is considered that the recesses of the unevenness 60 dp are satisfactorily filled with silicon oxide that becomes the first base layer 61.

  In the embodiment, the ratio of the depth D60 of the unevenness 60dp on the base surface 60s of the base 60 to the width of the upper end (opening) of the concave portion of the unevenness 60dp is, for example, 0.05 or less. This ratio is, for example, 0.02 or less. This ratio is, for example, 0.015 or less. Thereby, satisfactory embedding by the first underlayer 61 is obtained. This ratio is preferably 0.015 or more. Thereby, appropriate irregularities 60dp are formed on the base surface 60s, and the contact area between the base 60 and the first underlayer 61 can be increased. High adhesion can be obtained.

  Hereinafter, the relationship between the average particle diameter d60 of the crystal grains 60g of the substrate 60 and the irregularities 60dp on the surface of the substrate 60 (substrate surface 60s) will be described.

FIG. 6 is a graph illustrating characteristics of the substrate.
The horizontal axis of FIG. 6 indicates the average particle diameter d60 (μm) of the crystal grains 60g included in the substrate 60. The vertical axis in FIG. 6 indicates the depth D60 (nm) of the unevenness 60 dp of the base surface 60 s of the base body 60.

  As shown in FIG. 6, the depth D60 of the unevenness 60dp on the base surface 60s of the base body 60 is large when the average particle diameter d60 is large. When the average particle diameter d60 is 3.3 μm, the depth D60 of the unevenness 60dp is about 100 nm. When the average particle diameter d60 is 3.1 μm, the depth D60 of the unevenness 60dp is about 50 nm. When the average particle size d60 is 2.9 μm, the depth D60 of the unevenness 60dp is about 65 nm. When the average particle size d60 is 2.5 μm, the depth D60 of the unevenness 60dp is about 65 nm. When the average particle diameter d60 is 2.4 μm, the depth D60 of the unevenness 60dp is 20 nm.

  When the average particle diameter d60 is 3.3 μm or more, the depth D60 is 100 nm or more and increases rapidly. When the average particle diameter d60 is between 3.1 μm and 2.5 μm, the depth D60 is between 50 nm and 65 nm. When the average particle diameter d60 is 2.4 μm or less, the depth D60 does not reach 50 nm.

  As already described, when the average particle diameter d60 of the substrate 60 exceeds 3.1 μm (region Re3), peeling occurs. When the particle size d60 is 3.1 μm or less (region Re1 and region Re2), peeling is suppressed. Furthermore, when the particle size d60 is 2.5 μm or more and 3.1 μm or less (region Re2), peeling of the underlayer can be more stably suppressed. That is, when the depth D60 of the unevenness 60dp on the base surface 60s of the base body 60 is 65 nm or less, peeling can be suppressed. When the depth D60 is 50 nm or more and 65 nm or less, peeling can be more stably suppressed.

FIG. 7 is a graph illustrating characteristics of the silicon film.
FIG. 7 illustrates the critical film thickness of the silicon film when a silicon film is provided on the substrate. The critical film thickness is a critical thickness related to thermal strain caused by a difference in thermal expansion between the silicon film and the substrate. The horizontal axis of FIG. 7 is the difference (thermal expansion coefficient difference dTE) between the thermal expansion coefficient of the substrate and the thermal expansion coefficient of silicon. The vertical axis represents the critical film thickness tc (nm). In this example, the silicon film corresponds to the second underlayer 62. In this example, for the sake of simplicity, the characteristics under conditions where the first underlayer 61 is omitted are shown. A laminate including the base and the silicon film corresponds to the first structure S1. After joining such 1st structure S1 and 2nd structure S2, it heats to 1000 degreeC (corresponding to the growth temperature of functional part 10F), and returns to room temperature. At this time, a crack may occur in the silicon film due to a difference in thermal expansion coefficient. If the silicon film is thinner than the critical film tc, the silicon film is likely to be deformed, so that even if there is a difference in thermal expansion coefficient, cracks are unlikely to occur. That is, the critical thickness tc is the maximum thickness at which cracks do not occur at a predetermined thermal expansion coefficient difference dTE.

As shown in FIG. 7, when the thermal expansion coefficient difference dTE increases, the critical film thickness tc decreases. For example, when the substrate is SiC, the thermal expansion coefficient difference dTE is 1.2 × 10 ⁻⁶ / ° C. (1 / K), and at this time, the critical film thickness tc is 75 nm. For example, when the substrate is AlN, the thermal expansion coefficient difference dTE is 1.3 × 10 ⁻⁶ / ° C. (1 / K), and at this time, the critical film thickness tc is 70 nm. For example, when the substrate is Al ₂ O ₃ (sapphire), the difference in thermal expansion coefficient dTE is 4.8 × 10 ⁻⁶ / ° C. (1 / K). At this time, the critical film thickness tc is 25 nm. It is.

  From the viewpoint of the critical film thickness tc shown in FIG. 7, when an AlN polycrystalline substrate is used as the substrate 60, the thickness t2 of the second underlayer 62 (silicon film) is preferably 70 nm or less. In consideration of practical tolerance, the thickness t2 may be about 85 nm or less.

  Therefore, in the present embodiment, the thickness t2 of the second underlayer 62 is set to 70 nm or less. In consideration of practical tolerance, the thickness t2 may be about 85 nm or less. Thereby, in the process in which the functional unit 10F (for example, a group nitride semiconductor layer) is formed on the substrate 50, the second underlayer 62 is elastically deformed. Thereby, a crack can be suppressed.

  On the other hand, in the present embodiment, the thickness t1 of the first foundation layer 61 is 140 nm or less. Thereby, in the process in which the functional unit 10F (for example, a group nitride semiconductor layer) is formed on the substrate 50, the first foundation layer 61 is deformed. At this time, cracks are suppressed. For example, when the temperature is returned to room temperature after the growth of the semiconductor layer at a high temperature, the occurrence of cracks in the first underlayer 61 and the second underlayer 62 is suppressed.

  In the embodiment, the ratio (t1 / t2) of the thickness t1 of the first foundation layer 61 to the thickness t2 of the second foundation layer 62 is preferably about 0.67 or more. The ratio of the elastic constant of silicon to the elastic constant of silicon oxide is about 2. On the other hand, the ratio of the yield strain of silicon to the yield strain of silicon oxide is about 1/3. Therefore, when the ratio (t1 / t2) of the thickness of the silicon oxide layer (thickness t1) to the thickness of the silicon layer (thickness t2) is about 2/3, the silicon oxide layer and the silicon layer are simultaneously Start surrendering. This effectively relieves stress in these layers. In the embodiment, the ratio (t1 / t2) of the thickness t1 of the first foundation layer 61 to the thickness t2 of the second foundation layer 62 is set in consideration of a practical tolerance value. 0.55 or more is preferable. The ratio (t1 / t2) is more preferably 0.67 or more. Thereby, generation | occurrence | production of a crack can be suppressed more effectively.

  For example, when the ratio (t1 / t2) is excessively low, the first underlayer 61 is likely to yield. That is, in the first underlayer 61, stress based on the difference in thermal expansion coefficient cannot be relieved, the first underlayer 61 does not elastically deform, and cracks are likely to occur.

  On the other hand, the ratio (t1 / t2) of the thickness t1 of the first foundation layer 61 to the thickness t2 of the second foundation layer 62 is preferably about 2 or less. In this case, the deformation amount of the first underlayer 61 (silicon oxide) when stress is applied is substantially the same as the deformation amount of the second underlayer 62 (silicon) when stress is applied. . For example, the thickness of the second foundation layer 62 is 70 nm or less. At this time, the thickness of the first underlayer 61 is preferably 140 nm. Considering a practical allowable value, the ratio (t1 / t2) may be 2.4 or less. The ratio (t1 / t2) is more preferably 2.0 or less.

  When the ratio (t1 / t2) is not less than 0.55 and not more than 2.4, cracks are unlikely to occur due to mutual strain between the first underlayer 61 and the second underlayer 62.

  As already described, in the embodiment, when the average particle diameter d60 of the polycrystalline substrate 60 is 2.5 μm or more and 3.1 μm or less, the depth D60 of the unevenness 60dp on the substrate surface 60s of the substrate 60 is reduced. it can. Thereby, peeling of the first underlayer 61 and the second underlayer 62 can be suppressed. For example, high flatness can be obtained on the surface of the first silicon oxide film 61 a that becomes a part of the first base layer 61. Thereby, it is considered that good bonding can be obtained between the first silicon oxide film 61a and the second silicon oxide film 61b.

  As already described with reference to FIG. 6, in the AlN polycrystalline substrate used for the substrate 60, the flatness after polishing depends on the average grain size d60 (size) of the crystal grains 60g of the crystal substrate. When the average particle diameter d60 of the crystal grains 60g is large, the depth D60 of the unevenness 60dp on the base surface 60s varies depending on the size of the crystal grains 60g (average particle diameter d60). If the size of the crystal grains 60g is large, a gap is formed between the crystal grains 60g, and it is difficult to flatten the substrate surface 60s even if polished, and irregularities 60dp corresponding to the average grain diameter d60 are formed. It is done.

  For example, when an AlN polycrystalline substrate is formed by sintering, the AlN material moves due to sublimation, and crystal grains 60g grow. When the crystal grains 60g are small, the gaps between the plurality of crystal grains 60g are small, so that the AlN material is easily embedded between the gaps due to the sublimation movement of the material. For this reason, high flatness is obtained on the surface of the polycrystalline substrate by polishing. On the other hand, when the crystal grains 60g are excessively large, the gaps between the plurality of crystal grains 60g are large, so that the gaps are not filled by movement during the sintering of the AlN material. For this reason, when the crystal grain 60g is excessively large, high flatness cannot be obtained on the surface of the polycrystalline substrate. For example, when the average particle diameter d60 of the crystal grains 60g is 3.1 μm or less, it is considered that gaps between the plurality of crystal grains 60g are filled by the sublimation movement of the material.

  When the depth D60 of the irregularities 60dp on the substrate surface 60s of the substrate 60 is deep, when the thickness t1 of the first underlayer 61 is increased, the gaps between the irregularities 60dp (gap between the plurality of crystal grains 60g) are the first lower There is also a possibility of being embedded with the material of the formation 61. However, when the thickness t1 of the first foundation layer 61 is thick like this, a crack is generated in the first foundation layer 61 when the functional unit 10F is formed on the substrate 50.

  When the temperature is increased to form the functional unit 10F, the base body 60 and the first underlayer 61 expand due to a temperature difference from room temperature. At this time, the degree of expansion differs depending on the difference in thermal expansion coefficient between the base 60 and the first underlayer 61. This is presumed to be a cause of cracks in the first underlayer 61 when the functional part 10F is formed.

  In the embodiment, the depth D60 of the unevenness 60dp on the surface of the substrate 60 is set to a predetermined range by setting the average particle diameter d60 of the substrate 60 to an appropriate range. As a result, the surface of the underlayer can be flattened by the thin underlayer in which cracks in the underlayer are suppressed. Thereby, it can suppress that a base layer peels from the base | substrate 60. FIG.

FIG. 8 is a schematic view illustrating another wafer according to the first embodiment.
As shown in FIG. 8, in another wafer 151 according to this embodiment, the base 60 may include or include a base portion 60p and a boundary portion 60q. The boundary portion 60q is provided between the base portion 60p and the first base layer 61. Except this, it is the same as the substrate 50 illustrated in FIG.

  In the example of FIG. 8, the base portion 60p is, for example, an AlN polycrystalline substrate. The surface of the polycrystalline substrate is uneven. A part of the material to be the first base layer 61 is embedded in the concave and convex portions. For example, when analysis is performed along the Z-axis direction, for example, silicon and oxygen are detected in the first underlayer 61. Nitrogen may be detected in the first underlayer 61. On the other hand, when an AlN polycrystalline substrate is used as the substrate 60, Al and nitrogen are detected in the substrate portion 60p of the substrate 60. On the other hand, in the boundary portion 60q, Al and nitrogen resulting from the uneven protrusion and silicon and oxygen (and nitrogen) resulting from the material embedded in the uneven recess are detected.

  The thickness of the boundary portion 60q is, for example, not less than 50 nm and not more than 65 nm. For example, the thickness of the boundary portion 60q corresponds to the unevenness depth 60dp of the base surface 60s. The boundary portion 60q may be regarded as a part of the base body 60. The boundary portion 60q may be regarded as a part of the first foundation layer 61.

  For example, the thickness of the boundary portion 60q is, for example, 50 nm or more and 65 nm or less, the thickness t1 of the first foundation layer 61 is 35 nm or more, and the thickness t2 of the second foundation layer 62 is 18 nm or more. Thereby, peeling of the 1st foundation layer 61 and peeling of the 2nd foundation layer 62 can be suppressed. For example, the thickness of the first foundation layer 61 is ½ or more of the thickness of the boundary portion 60q. Thereby, the unevenness 60 dp on the surface of the base body 60 is covered with the first underlayer 61. For example, the thickness of the second foundation layer 62 is desirably set to be 1/2 or more of the thickness of the first foundation layer 61.

FIG. 9A and FIG. 9B are schematic cross-sectional views illustrating another wafer according to the first embodiment.
FIG. 9A is a schematic cross-sectional view. FIG. 9B is a schematic cross-sectional view showing a part of the wafer.
As shown in FIG. 9A, another wafer 152 according to this embodiment includes a substrate 50 and a functional unit 10F. Hereinafter, in the wafer 152, the description of the same parts as the wafers 150 and 151 is omitted.

  The substrate 50 further includes an intermediate portion 55 in addition to the base body 60 and the base portion 65. A base portion 65 is disposed between the intermediate portion 55 and the base body 60. A base portion 65 is provided between the base body 60 and the functional portion 10F. An intermediate portion 55 is provided between the base portion 65 and the functional portion 10F. The base portion 65 is formed on the base body 60. The intermediate portion 55 is formed on the formed base portion 65.

  In this example, the substrate 50 further includes a third foundation layer 63. A third foundation layer 63 is provided on the second foundation layer 62. That is, the second base layer 62 is disposed between the first base layer 61 and the third base layer 63. The third foundation layer 63 includes, for example, a silicon nitride layer. The second foundation layer 62 is a silicon layer. That is, the concentration of nitrogen contained in the third foundation layer 63 is higher than the concentration of nitrogen contained in the second foundation layer 62. For example, the second underlayer 62 does not substantially contain nitrogen.

  For example, the third underlayer 63 can be formed by nitriding the surface of the silicon layer that becomes the second underlayer 62. The surface of the silicon layer that becomes the second underlayer 62 is nitrided at a low temperature (for example, 720 ° C. or higher and 1150 ° C. or lower). The nitrided portion of the surface of the second foundation layer 62 becomes the third foundation layer 63. A portion that is not nitrided or has a low degree of nitridation becomes the second underlayer 62. The thickness of the third foundation layer 63 is, for example, not less than 0.7 nm and not more than 20 nm.

  In nitriding the surface of the silicon layer, when the nitriding temperature is 720 ° C. or lower, the surface of the silicon layer is nitrided non-uniformly. This is presumed to be because the surface dependence becomes strong because the nitriding rate is low. On the other hand, when the nitriding temperature exceeds 1150 ° C., the crystallinity of the AlN layer (for example, a first intermediate layer described later) formed on the silicon layer (second underlayer 62) is lowered. For example, the full width at half maximum of the X-ray diffraction of the (0002) plane of the AlN layer suddenly increases.

  For example, when the thickness of the AlN layer (for example, a first intermediate layer described later) is 0.2 μm, the half-value width of the X-ray diffraction of the (0002) plane of the AlN layer exceeds 1200 ″ (arcsecond in angle units). For example, when the thickness of the AlN layer (for example, a first intermediate layer described later) is 0.5 μm, the half width of the X-ray diffraction of the (0002) plane of the AlN layer exceeds 800 ″. The full width at half maximum of X-ray diffraction is inversely proportional to the thickness of the layer being measured. The half width of the X-ray diffraction of the (0002) plane of the AlN layer having a thickness of 0.2 μm and the half width of the X-ray diffraction of the (0002) plane of the AlN layer having a thickness of 0.5 μm are It is wider than the half-value width of X-ray diffraction derived from the thickness. This indicates that the nitridation process at high temperature reduces the quality of the AlN layer.

  In this example, the intermediate portion 55 includes a first intermediate layer 51, a second intermediate layer 52, and a third intermediate layer 53. The first intermediate layer 51 is disposed between the third intermediate layer 53 and the base portion 65. The second intermediate layer 52 is disposed between the third intermediate layer 53 and the first intermediate layer 51.

  For example, the third foundation layer 63 is provided on the second foundation layer 62. A first intermediate layer 51 is provided on the third underlayer 63. A second intermediate layer 52 is provided on the first intermediate layer 51. A third intermediate layer 53 is provided on the second intermediate layer 52.

The first intermediate layer 51 includes aluminum nitride (AlN). The second intermediate layer 52 includes aluminum, gallium, and nitrogen. The third intermediate layer 53 includes gallium and nitrogen. The first intermediate layer 51 is, for example, an AlN layer. The second intermediate layer 52 is, for example, an AlGaN layer. The second intermediate layer 52 is an Al _x Ga _1-x N (0 <x <1) layer. The third intermediate layer 53 is, for example, a GaN layer. For example, the first intermediate layer 51 does not substantially contain Ga. The Ga composition ratio in the second intermediate layer 52 is higher than the Ga composition ratio in the first intermediate layer 51, and lower than the Ga composition ratio in the third intermediate layer 53. The first intermediate layer 51 does not substantially contain Al, for example. The Al composition ratio in the second intermediate layer 52 is lower than the Al composition ratio in the first intermediate layer 51 and higher than the Al composition ratio in the third intermediate layer 53.

  In this example, the first intermediate layer 51 (AlN layer) of the intermediate portion 55 is formed on the third foundation layer 63. According to experiments, when an AlN layer is formed directly on a silicon layer (second underlayer 62) at a high temperature, the crystal quality of the AlN layer tends to be low. This is thought to be due to the fact that aluminum reacts with silicon. On the other hand, when AlN is formed on the silicon layer (second base layer 62) at a low temperature and then AlN is formed at a high temperature, the crystal quality of the first intermediate layer 51 is improved. However, the dislocation density in the AlN layer is high.

  In the wafer 152, the surface of the silicon layer that becomes the second underlayer 62 is nitrided at a low temperature to form a third underlayer 63 (SiN layer). An AlN layer is formed on the third underlayer 63 at a high temperature. Thereby, it is easy to obtain an AlN layer (first intermediate layer 51) having high crystal quality and low dislocation density.

  The intermediate portion 55 (the first intermediate layer 51, the second intermediate layer 52, the third intermediate layer 53, and the like) is, for example, a crystal. When the dislocation density in the intermediate part 55 is low, the dislocation density in the functional part 10F formed on the intermediate part 55 can be lowered. Thereby, a high characteristic is obtained in the functional unit 10F. On the other hand, when stress due to a difference in thermal expansion coefficient or the like is applied to the base portion 65, if the dislocation density in the intermediate portion 55 is low, the stress is difficult to be relaxed. For this reason, if the dislocation density in the intermediate portion 55 is low, cracks are likely to occur.

In the embodiment, cracks are unlikely to occur in the base portion 65. For this reason, even if the dislocation density in the intermediate portion 55 is lowered, cracks are hardly generated. For example, the threading dislocation density in the first intermediate layer 51 is, for example, 1 × 10 ¹⁰ / cm ² or less. Thereby, a high characteristic is acquired, suppressing a crack. The threading dislocation density in the first intermediate layer 51 is, for example, 1 × 10 ¹⁰ / cm ² or more. The threading dislocation density is the sum of the spiral transition density and the edge transition density. The helical transition density and the edge transition density are determined by X-ray diffraction measurement on the (0002) plane, the (11-20) plane, and these high index planes of the nitride semiconductor.

By reducing the threading dislocation density in the first intermediate layer 51, the threading dislocation density in the second intermediate layer 52 can be reduced. The threading dislocation density in the second intermediate layer 52 is, for example, 3 × 10 ⁹ / cm ² or more and 0.5 × 10 ¹⁰ / cm ² or less. By reducing the threading dislocation density in the first intermediate layer 51, the threading dislocation density in the third intermediate layer 53 can be reduced. The threading dislocation density in the third intermediate layer 53 is, for example, 1 × 10 ⁹ / cm ² or more and 3 × 10 ⁹ / cm ² or less.

A second intermediate layer 52 is formed on the first intermediate layer 51, and a third intermediate layer 53 is formed on the second intermediate layer 52. Before forming the second intermediate layer 52, high concentration Si may be added to the surface of the first intermediate layer 51. Before forming the third intermediate layer 53, high concentration Si may be added to the surface of the second intermediate layer 52. For example, high concentration Si addition using monosilane (SiH ₄ ) is performed.

Thereby, the threading dislocation density of the second intermediate layer 52 can be made lower than the threading dislocation density of the first intermediate layer 51. Thereby, the threading dislocation density of the third intermediate layer 53 can be made lower than the threading dislocation density of the first intermediate layer 51. The threading dislocation density of the third intermediate layer 53 is, for example, 1/20 or less of the threading dislocation density of the first intermediate layer 51. The threading dislocation density of the third intermediate layer 53 can be set to 3 × 10 ⁸ cm ⁻² or less, for example.

  That is, a high-concentration Si-containing region (δ-doping) is present in at least one of the interface portion between the first intermediate layer 51 and the second intermediate layer 52 and the interface portion between the second intermediate layer 52 and the third intermediate layer 53. By providing the region, for example, the dislocation is bent. Thereby, the dislocation density (threading dislocation density) can be lowered in the layer provided on the high concentration Si-containing region.

For example, Si is added to the surface portion of the second intermediate layer 52 at a high concentration. A thick third intermediate layer 53 is provided thereon. Thereby, the surface of the third intermediate layer 53 is planarized. For example, the thickness of the third intermediate layer 53 is 1.5 μm or more and 10 μm or less. The threading dislocation density of the third intermediate layer 53 is, for example, 3 × 10 ⁸ cm ⁻² or less. The threading dislocation density of the third intermediate layer 53 is, for example, 1 × 10 ⁸ cm ⁻² or less.

The thickness of the first intermediate layer 51 is, for example, not less than 0.2 nm and not more than 3 μm.
The thickness of the second intermediate layer 52 is, for example, not less than 200 nm and not more than 1000 nm.
The thickness of the third intermediate layer 53 is not less than 1 μm and not more than 10 μm, for example.

  In this example, the functional unit 10 </ b> F includes the first semiconductor layer 10, the stacked body 40, the third semiconductor layer 30, and the second semiconductor layer 20.

  The first semiconductor layer 10 includes a first nitride semiconductor of a first conductivity type. The second semiconductor layer 20 includes a second nitride semiconductor of the second conductivity type. The third semiconductor layer 30 is provided between the first semiconductor layer 10 and the second semiconductor layer 20. A stacked body 40 is provided between the third semiconductor layer 30 and the first semiconductor layer 10.

  For example, the first conductivity type is n-type and the second conductivity type is p-type. In the embodiment, the first conductivity type may be p-type and the second conductivity type may be n-type. Hereinafter, the first conductivity type is n-type, and the second conductivity type is p-type. The third semiconductor layer 30 is, for example, a light emitting unit.

  The first semiconductor layer 10 includes, for example, an n-type GaN layer.

  In this example, the second semiconductor layer 20 includes a first p layer 21, a second p layer 22, and a third p layer 23. A first p layer 21 is provided between the third p layer 23 and the third semiconductor layer 30. A second p layer 22 is provided between the third p layer 23 and the first p layer 21. The first p layer 21 is, for example, a p-type AlGaN layer. The thickness of the first p layer 21 is, for example, 5 nm or more and 25 nm or less (for example, about 10 nm). The Al composition ratio in the first p layer 21 is, for example, 5% or more and 30% or less (for example, about 15%). The second p layer 22 is, for example, a p-type GaN layer. The thickness of the second p layer 22 is, for example, not less than 30 nm and not more than 250 nm (for example, about 100 nm). The thickness of the third p layer 23 is, for example, not less than 3 nm and not more than 10 nm (for example, about 5 nm). The third p layer 23 becomes, for example, a contact layer.

  As illustrated in FIG. 9B, the third semiconductor layer 30 includes a plurality of barrier layers 31 and a plurality of well layers 32. The plurality of barrier layers 31 and the plurality of well layers 32 are alternately arranged along the Z-axis direction. The barrier layer 31 is, for example, a GaN layer. The thickness of the barrier layer 31 is, for example, not less than 2 nm and not more than 20 nm (for example, about 5 nm). The well layer 32 is, for example, a GaInN layer. The thickness of the well layer 32 is 2 nm or more and 9 nm or less (for example, about 3 nm), for example. One barrier layer 31 and one well layer 32 are paired. In the third semiconductor layer 30, the number of pairs is, for example, 1 or more and 9 or less.

As illustrated in FIG. 9B, the stacked body 40 includes a plurality of first layers 41 and a plurality of second layers 42. The plurality of first layers 41 and the plurality of second layers 42 are alternately arranged along the Z-axis direction. The first layer 41 is, for example, a GaN layer. The Si concentration in the first layer 41 is, for example, 1 × 10 ¹⁷ cm ³ or more and 5 × 10 ¹⁹ cm ³ or less (for example, about 1 × 10 ¹⁸ cm ³ ). The thickness of the first layer 41 is, for example, not less than 0.5 nm and not more than 5 nm (for example, about 1 nm). The first layer 41 may be, for example, an AlGaInN layer or an AlGaN layer. The second layer 42 is, for example, a GaInN layer. The second layer 42 may contain Si. The thickness of the second layer 42 is, for example, not less than 0.3 nm and not more than 4 nm (for example, about 2 nm). One first layer 41 and one second layer 42 are paired. In the stacked body 40, the number of pairs is, for example, 10 or more and 30 or less.

  From such a wafer 152, for example, a semiconductor light emitting element (LED or the like) is obtained.

  As shown in FIG. 9A, the second underlayer 62 has a first surface 62l and a second surface 62u. The first surface 62l is a surface on the first base layer 61 side. The second surface 62u is a surface opposite to the first surface 62l. The second surface 62u is, for example, an upper surface.

  The second surface 62u is a (111) surface of silicon. The second surface 62u may be a (113) surface of silicon. The second surface 62u may be inclined at a small angle with respect to the (111) surface of silicon. The angle between the second surface 62u and the (111) surface of silicon is, for example, 1 degree or less. The second surface 62u may be inclined at a small angle with respect to the (113) surface of silicon. The angle between the second surface 62u and the (113) surface of silicon is, for example, 1 degree or less.

  For example, when the second surface 62u is a (111) plane, the plane orientation of the first intermediate layer 51 is a (0001) plane.

The angle between the second surface 62u and the (111) surface is preferably 1 degree or less (0.02 degrees or more and 0.06 degrees or less). For example, when the second underlayer 62 is heat-treated at 1100 ° C. or higher and 1350 ° C. or lower in an Ar (argon) atmosphere, atoms on the crystal surface of the second underlayer 62 move. This increases the flatness of the crystal plane. At this time, for example, a Bilayer crystal plane is obtained. Thereafter, the surface of the second underlayer 62 is nitrided using NH ₃ gas. Thereby, a thin and uniform third underlayer 63 is obtained. The third base layer 63 becomes a protective layer. By providing the third underlayer 63, the crystal disorder of the first intermediate layer 51 can be suppressed.

  By providing the first intermediate layer 51 on the third underlayer 63, the crystal quality of the first intermediate layer 51 can be improved. The width (for example, full width at half maximum) of the (0002) plane of the first intermediate layer 51 is as narrow as that of the second underlayer 62 (for example, full width at half maximum).

  On the other hand, when the second surface 62u of the second underlayer 62 is a (113) plane of silicon, the plane orientation of the first intermediate layer 51 is, for example, a (11-22) plane. In this case, the carrier recombination probability can be increased in the well layer 32 provided in the functional unit 10F. Thereby, a highly efficient semiconductor device can be obtained.

  A semiconductor light emitting device can be formed using the wafer 150 according to the present embodiment. In the semiconductor light emitting device, the emission color is, for example, green. In the embodiment, the plurality of polycrystals 60g of the base body 60 of the wafer 150 includes, for example, aluminum nitride. In this case, the stress applied to the semiconductor crystal with the difference in thermal expansion coefficient between the base 60 and the semiconductor layer after the growth of the semiconductor crystal (functional layer 10F) can be reduced as compared with the case where the Si single crystal substrate is used. Since the stress can be reduced, high luminous efficiency can be obtained. In particular, in a light-emitting layer that emits green light, a lattice mismatch is large and a lattice bond of the light-emitting layer is weak, so that defects such as dislocations are easily generated. According to the embodiment, even in the case of such a light emitting layer, dislocations in the light emitting layer can be suppressed, and a highly efficient semiconductor light emitting device can be provided.

The thermal expansion coefficient of the second underlayer 62 (for example, silicon) is, for example, 2.5 × 10 ⁻⁶ / ° C. (1 / K). On the other hand, the thermal expansion coefficient of the substrate 60 (for example, AlN) is 4.8 × 10 ⁻⁶ / ° C. (1 / K). For this reason, when the intermediate part 55 and the functional part 10F are formed at 1000 ° C. on the base part 65 including the second base layer 62 and then returned to room temperature, the space between the base 60 and the second base layer 62 is reached. In addition, distortion occurs. The strain exceeds 0.23%.

  In the embodiment, this strain (a strain exceeding 0.23%) can be elastically relaxed by setting the thickness t2 of the second underlayer 62 to 70 nm or less.

  On the other hand, when the thickness t2 of the second underlayer 62 is 70 nm or more and the crystal defects (dislocations) are present in the second underlayer 62, deformation due to distortion is caused by the dislocation, and the distortion can be alleviated. Therefore, when many crystal defects (dislocations) exist in the second underlayer 62, the second underlayer 62 is not cracked even when the thickness t2 of the second underlayer 62 is 70 nm or more. To deform.

FIG. 10 is a graph illustrating characteristics of the wafer.
FIG. 10 illustrates the relationship between the difference in thermal expansion coefficient between two layers (lower layer and upper layer) and the dislocation density. An upper layer is provided on the lower layer. The lower layer is, for example, the base body 60. The upper layer is the second underlayer 62, for example. In this example, for the sake of simplicity, the first underlayer 61 and the third underlayer 63 are ignored.

The horizontal axis in FIG. 10 represents the difference C2 (%) in the thermal expansion coefficient between the two layers. The thermal expansion coefficient of the lower layer is CTE1, and the thermal expansion coefficient of the upper layer is CTE2. The difference C2 is CTE1-CTE2. The vertical axis in FIG. 10 represents the dislocation density C1 (/ cm ² ) in the upper layer (second base layer 62). In the example of FIG. 10, the thickness of the upper layer is 100 nm. In FIG. 10, the upper layer includes a plurality of dislocation-free regions, and each of the plurality of regions is elastically deformed when the thickness of each of the plurality of regions is equal to or less than the critical thickness. And it is assumed that the dislocation can move freely within the range of the length of Burgers' vector. It is assumed that cracks occur when the deformation exceeds the range of the Burgers vector length. After forming the lower layer and the upper layer, the temperature is raised to 1000 ° C., which is a temperature for forming the functional layer 10F. At this time, there is a thermal expansion coefficient difference C2 between the upper layer and the lower layer. For this reason, the upper layer is deformed relative to the lower layer. Depending on the thermal expansion coefficient difference C2, cracks may or may not occur due to deformation.

  In the region R1 on the lower side (right side) of the curve in FIG. In the region R2 on the upper side (left side) of the curve in FIG. 10, no crack occurs.

For example, when the thickness of the upper layer exceeds the critical thickness, high density dislocations are introduced into the upper layer. For example, when the thickness of the upper layer (silicon) is 100 nm, the dislocation density in the upper layer is 1.5 × 10 ⁹ cm ⁻² . When dislocations are introduced into the upper layer (second base layer 62), the dislocations are also introduced into the intermediate portion 55 (and the functional portion 10F) formed thereon. By setting the thickness of the upper layer (second base layer 62) to 70 nm or less, the intermediate portion 55 and the functional portion 10F having a low dislocation density can be obtained.

In the embodiment, the second intermediate layer 52 may be omitted. In this case, for example, the third intermediate layer 53 is provided on the first intermediate layer 51. Prior to the formation of the third intermediate layer 53, a high concentration silicon-containing region may be provided on the first intermediate layer 51. The dislocation density can be reduced while suppressing the distortion. When the dislocation density of the first intermediate layer 51 is 3 × 10 ⁹ cm ⁻² or less, the dislocation density of the third intermediate layer 53 can be 1 × 10 ⁸ cm ⁻² or less, for example.

It is difficult to form such low dislocation GaN (third intermediate layer 53) on a thick silicon substrate. This is because when a GaN layer is formed on a thick silicon substrate, dislocation occurs in the GaN layer in order to relieve stress based on the difference in thermal expansion coefficient between silicon and GaN. On the other hand, even in the case of forming a GaN layer on a sapphire substrate, in addition to the difference in crystal structure, since a narrow degree of freedom in controlling the crystal growth process, the GaN layer, 1 × 10 ⁸ cm ^-2 or less threading dislocations It is difficult to obtain density.

In the present embodiment, the AlN layer (first intermediate layer 51) can be thickened, and the threading dislocation density in the first intermediate layer 51 can be reduced. Thereby, the threading dislocation density of the 3rd intermediate | middle layer 53 formed on the 1st intermediate | middle layer 51 can be made into 1 * 10 ^{< 8} > cm ^<-2> or less, for example. The size (diameter) of the base body 60 is, for example, 200 mm or more and 450 mm or less. A high-quality device can be formed on such a large-area substrate.

  When the wafer becomes larger, the influence of the physical properties of the wafer material on the thermal deformation becomes larger than the effect of warping of the wafer. In particular, an epitaxial film can be grown with a small warp on a large wafer, and an in-plane temperature distribution during the process and unintended temperature changes can be suppressed. For this reason, it is possible to grow a homogeneous epitaxial film. For example, in a well layer having a GaInN / GaN multiple quantum well structure (for example, including eight GaInN well layers), for example, the half width of the PL peak is 100 nm or less.

Hereinafter, an example of a method for manufacturing the wafer 152 will be described.
A second silicon oxide film 61b is formed on the silicon substrate 62s (see FIG. 2A). The thickness of the second silicon oxide film 61b is, for example, about 200 nm. After the heat treatment at a temperature of 1100 ° C. for 30 minutes, the surface of the second silicon oxide film 61b is polished. By this heat treatment, deaeration proceeds in the second silicon oxide film 61b. The surface roughness Ra of the second silicon oxide film 61b is set to 1 nm or less, for example. Thereby, the second structure S2 is obtained. The polishing may be omitted when the surface roughness Ra of the second silicon oxide film 61b is 3 nm or less.

  On the other hand, a first silicon oxide film 61 a is formed on the surface of the substrate 60. The thickness of the first silicon oxide film 61a is, for example, 1000 nm. Heat treatment is performed at 1200 ° C. for 30 minutes. The surface of the first silicon oxide film 61a is polished. The surface roughness Ra of the first silicon oxide film 61a is set to 2 nm or less, for example. Thereby, 1st structure S1 is obtained. For example, a silicon nitride region may be formed between the base 60 and the first silicon oxide film 61a. Thereby, for example, when the first structure body S1 and the second structure body S2 are joined, aluminum is suppressed from diffusing toward the silicon substrate 62s.

  The first structure S1 and the second structure S2 are joined in a reduced pressure. The pressure of the reduced pressure atmosphere in the bonding is, for example, 0.1 atmosphere. Bonding may be performed at normal pressure. The bonded first structure S1 and second structure S2 are heat-treated in a nitrogen atmosphere. The temperature rise and fall in this heating is, for example, 10 ° C./min or less. By raising and lowering the temperature at a low speed, the gas generated along with the bonding can be degassed and the peeling of the bonding can be suppressed.

  After returning to room temperature, the thickness of the silicon substrate 62s is decreased. The thickness is reduced by polishing, for example. The thickness reduction may be performed by a combination of grinding and polishing. Polishing is performed, for example, by CMP using a slurry. The pH of the slurry is 10, for example. The surface of the second silicon oxide film 61b whose thickness has been reduced is, for example, scrabble cleaned. Thereby, the base 60, the first underlayer 61, and the second underlayer 62 are formed.

When forming the third foundation layer 63 on the second foundation layer 62, after reducing the thickness of the silicon substrate 62s, the surface (surface 62sb) of the silicon substrate 62s is nitrided. For example, in a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, the surface of the silicon substrate 62s is brought into contact with ammonia (NH ₃ ) at a temperature of 1100 ° C. Thereby, the nitrided surface portion becomes the third underlayer 63. The portion that has not been nitrided becomes the second underlayer 62.

  The first intermediate layer 51 (AlN layer) is formed on the second underlayer 62 (on the third underlayer 63) at a temperature of 1200 ° C. The thickness of the first intermediate layer 51 is about 0.8 μm. The dislocation density of the first intermediate layer 51 is low. For example, the half width of the rocking curve of the (0002) plane in the first intermediate layer 51 is, for example, 600 seconds or less. This value is substantially the same as the half width of the rocking curve of AlN formed on a silicon single crystal substrate. When AlN having such a thickness is grown on a Si single crystal substrate, cracks occur in AlN when the temperature is lowered from the process temperature of AlN deposition to room temperature due to the difference in thermal expansion coefficient between Si and AlN.

  In the embodiment, the second underlayer 62 is thin. From the viewpoint of thermal expansion, it can be considered that the first intermediate layer 51 is directly provided on the AlN substrate 60. For this reason, the 1st intermediate | middle layer 51 can be thickened. Dislocation can be reduced by increasing the thickness of the first intermediate layer 51. For this reason, in the embodiment, a high-quality crystal can be obtained with lower dislocations than on a Si single crystal substrate.

A second intermediate layer 52 is formed on the first intermediate layer 51. The formation temperature is, for example, 1050 ° C. The second intermediate layer 52 may have a multilayer structure or a gradient composition structure. For example, an Al _0.5 Ga _0.5 N layer (thickness is 0.1 μm, for example) is formed on the first intermediate layer 51 as the first portion. On top of this, an Al _0.25 Ga _0.75 N layer (thickness is, for example, 2 μm) is formed as a second portion. The second portion may be an Al _0.2 Ga _0.8 N layer (thickness is, for example, 0.1 μm).

A GaN layer to be the third intermediate layer 53 is formed on the second intermediate layer 52. The temperature of formation is about 1000 ° C., for example. For example, the edge dislocation density in the third intermediate layer 53 is 9 × 10 ⁹ cm ⁻² . The screw dislocation density in the third intermediate layer 53 is, for example, 1 × 10 ⁹ cm ⁻² .

  By forming the second intermediate layer 52 having a lattice irregularity on the first intermediate layer 51 and forming the third intermediate layer 53 on the second intermediate layer 52, the dislocation is bent along with the lattice irregularity. The dislocation density in the layer provided on the intermediate portion 55 can be lowered.

  An n-type GaN layer to be the first semiconductor layer 10 is formed on the intermediate portion 55. A stacked body 40 is formed on the n-type GaN layer. A third semiconductor layer 30 is formed on the stacked body 40. The second semiconductor layer 20 is formed on the third semiconductor layer 30. Thereby, the wafer 152 is formed.

  In the wafer 152, the warpage is small. The third semiconductor layer 30 can be formed with a small warpage. Thereby, for example, the distribution in the wafer surface of the peak wavelength of the light emitted from the third semiconductor layer 30 can be made within 5 nm. The light intensity is highest at the peak wavelength.

  Furthermore, in the formation of the second semiconductor layer 20, the in-plane distribution of the p-type doping condition can be reduced. Thereby, the distribution of the driving voltage can be reduced. The distribution of contact resistance can be reduced. For example, the in-plane distribution of the operating voltage when the driving current is 350 mA can be set to 0.1 V or less.

In the embodiment, for example, a first underlayer 61 of SiO _{2 having} a thickness of 100 nm is provided on the substrate 60. A second base layer 62 of (113) plane Si is provided thereon. The first silicon oxide film 61a provided on the substrate 60 and the second silicon oxide film 61b provided on the (113) plane Si substrate are bonded to each other by raising the temperature to 150 ° C. under reduced pressure. Thereby, the first underlayer 61 is formed.

  The silicon substrate of the second structure S2 is thinned by grinding or polishing. Thereby, the second underlayer 62 is formed. Thinning may be performed by smart cut by ion implantation of hydrogen into the (113) Si substrate from the second silicon oxide film 61b side of the (113) plane Si substrate of the second structure S2. After the smart cut, the (113) Si surface may be polished.

  A first intermediate layer 51 of (11-22) plane AlN may be formed on the second underlayer 62. The thickness of the first intermediate layer 51 is, for example, 1 μm. A third base layer 63 made of SiN may be provided between the first intermediate layer 51 made of AlN and the second base layer 62.

The thickness of the third underlayer 63 is preferably, for example, not less than 0.6 nm and not more than 1 nm. In the second intermediate layer 52 provided on the first intermediate layer 51, for example, an Al _0.7 Ga _0.3 N layer having a thickness of 50 nm and an Al _0.1 GaN layer having a thickness of 70 nm are formed. It may be laminated. A third intermediate layer 53 of GaN may be provided on the second intermediate layer 52.

A GaN first semiconductor layer 10 is provided on the third intermediate layer 53. In the first semiconductor layer 10, the concentration of Si is, for example, 4 × 10 ¹⁸ cm ⁻³ . The thickness of the first semiconductor layer 10 is, for example, 2 μm.

  A stacked body 40 is provided on the first semiconductor layer 10. In the stacked body 40, 30 pairs of a 3 nm-thick GaN layer and a 1 nm GaInN layer are stacked. A third semiconductor layer 30 is provided on the stacked body 40. In the third semiconductor layer 30, a GaN layer having a thickness of 5 nm and a GaInN layer having a thickness of 3 nm are alternately stacked. In the third semiconductor layer 30, for example, a GaN layer having a thickness of 5 nm and a GaInN layer having a thickness of 2.5 to 9 nm and an In composition ratio of 25% are stacked to have a thickness of 500 to 550 nm. The emission wavelength (green) is obtained. The third semiconductor layer 30 has an MQW structure or an SQW structure.

  The second semiconductor layer 20 is provided on the third semiconductor layer 30. As the second semiconductor layer 20, an AlGaN layer and a GaN layer are provided. A light emitting element capable of current injection is obtained. In such a light-emitting element, stress from the substrate is small and high light emission efficiency can be obtained.

  Luminous efficiency is high, and in particular, a decrease in efficiency is suppressed when the current injection density is high. The light emission wavelength (for example, peak wavelength) in such a light emitting element is, for example, 510 nm or more and 540 nm or less.

  The GaInN layer of the third semiconductor layer 30 may include a first GaInN layer having a low In composition ratio and a second GaInN layer having a high In composition ratio. The first and second GaInN layers are stacked. In the first GaInN layer, for example, the thickness is 3 nm and the In composition ratio is 5%. In the second GaInN layer, the thickness is 2 nm, and the In composition ratio is 30% or more and 45% or less.

  When the GaInN layer of the third semiconductor layer 30 includes the first GaInN layer having a low In composition ratio and the second GaInN layer having a high In composition ratio, the In composition ratio of the first GaInN layer is set to 5% or less, The thickness of the first GaInN layer is 3 nm to 5 nm, and the thickness of the second GaInN layer is 0.7 nm to 1 nm. At this time, an LED having a blue emission wavelength is obtained. In the MQW having such a configuration, the energy of a band with a large Auger absorption shifts from twice the emission wavelength at a wavelength of 450 nm to 460 nm with a large Auger absorption in a normal blue LED. For this reason, Auger absorption can be suppressed in the MQW having such a configuration. As a result, a blue LED having a small light output drop at a high current injection density can be obtained. When a polycrystalline AlN substrate 60 is used, the difference in thermal expansion coefficient between the substrate 60 and the epitaxial growth layer is small, and stress is not easily applied to the epitaxial growth layer. This facilitates the growth of GaInN with a high In composition on such a substrate 60. This facilitates the formation of MQW as described above.

(Second Embodiment)
FIG. 11 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment.
The semiconductor device 110 according to the present embodiment is manufactured using the wafer according to the first embodiment (wafers 150, 151, 152, etc.). According to the semiconductor device 110, a semiconductor device capable of suppressing cracks can be obtained.

  As shown in FIG. 11, the semiconductor device 110 includes a first semiconductor layer 10, a stacked body 40, a third semiconductor layer 30, a second semiconductor layer 20, a first electrode 10e, a second electrode 20e, Have In the semiconductor device 110, after the functional unit 10F is formed on the substrate 50, a part of the substrate 50 is removed. In this example, the base body 60 and the base portion 65 are removed, and a part of the intermediate portion 55 is further removed. For the removal, for example, chlorine ion etching is used. A first electrode 10 e is provided on the surface of the first semiconductor layer 10 exposed by removing a part of the intermediate portion 55. A second electrode 20e is provided on the surface of the second semiconductor layer 20 (the surface of the third p layer 23). The first electrode 10 e is electrically connected to the first semiconductor layer 10. The second electrode 20 e is electrically connected to the second semiconductor layer 20. Other configurations are similar to those described with respect to wafers 150, 151 and 152.

  In the semiconductor device 110, the first semiconductor layer 10 includes a first semiconductor portion 10p and a second semiconductor portion 10q. The direction from the first semiconductor portion 10p toward the second semiconductor portion 10q is along the Z-axis direction.

The first semiconductor portion 10p includes n-type GaN and includes Si. The concentration of Si in the first semiconductor portion 10p is, for example, not less than 0.5 × 10 ¹⁸ cm ^{−3 and not} more than 8 × 10 ¹⁸ cm ⁻³ , for example, 3 × 10 ¹⁸ cm ⁻³ . The thickness of the first semiconductor portion 10p is, for example, 1 μm or less and 10 μm or less, for example, 1.5 μm.

The second semiconductor portion 10q includes n-type GaN. The carrier concentration in the second semiconductor portion 10q is, for example, 3 × 10 ¹⁸ cm ⁻³ or less, 12 × 10 ¹⁸ cm ⁻³ or less, for example, 8 × 10 ¹⁸ cm ⁻³ . The thickness of the second semiconductor portion 10q is, for example, not less than 0.2 μm and not more than 1.5 μm, for example, 0.5 μm. The first electrode 10e is in contact with the second semiconductor portion 10q.

  In the semiconductor device 110, light is emitted from the third semiconductor layer 30 by applying a voltage between the first electrode 10e and the second electrode 20e. The semiconductor device 110 is, for example, an LED.

  In the semiconductor device 110, the dislocation density in the third intermediate layer 53 is low. Thereby, a low dislocation density is obtained in the functional unit 10F. Thereby, high luminous efficiency is obtained.

  The difference in thermal expansion coefficient between the base body 60 and the first semiconductor layer 10 is small. The third semiconductor layer 30 can be formed with a small warpage. For this reason, the in-plane distribution of the formation conditions in the formation of the second semiconductor layer 20 can be reduced. For example, p-type dopant Mg can be added uniformly. The in-plane distribution of driving voltage can be reduced. The in-plane distribution of contact resistance can be reduced.

(Third embodiment)
FIG. 12 is a schematic cross-sectional view illustrating a wafer according to the third embodiment.
As shown in FIG. 12, in the wafer 160 according to the present embodiment, a hole 60 h is provided in the base body 60. On the other hand, each of the third semiconductor layer 30 and the stacked body 40 is provided with a plurality of regions. The rest is the same as the wafer 152.

  The hole 60h is, for example, a receding part. The hole 60h extends from the back surface 60r of the base body 60 in the Z-axis direction. The bottom 60hb of the hole 60h does not reach the first foundation layer 61, for example. In this example, a plurality of holes 60h are provided.

  The third semiconductor layer 30 includes a first low In composition ratio region 30a and a first high In composition ratio region 30b. The first low In composition ratio region 30a does not overlap with the hole 60h in the Z-axis direction. The first high In composition ratio region 30b overlaps the hole 60h in the Z-axis direction. The direction from the first low In composition ratio region 30a to the first high In composition ratio region 30b intersects the Z-axis direction. The direction from the first low In composition ratio region 30a to the first high In composition ratio region 30b is, for example, perpendicular to the Z-axis direction.

  The average In composition ratio in the first high In composition ratio region 30b is higher than the average In composition ratio in the first low In composition ratio region 30a.

  For example, the first low In composition ratio region 30a includes a plurality of barrier layers 31 (GaN layers) and a plurality of well layers 32 (GaInN layers) that are alternately stacked. The barrier layer 31 is, for example, an AlGaInN layer or an AlGaN layer. For example, the first high In composition ratio region 30b includes a plurality of barrier layers (GaN layers) and a plurality of well layers (GaInN layers) that are alternately stacked. The barrier layer included in the first high In composition ratio region 30b is continuous with the barrier layer 31 included in the first low In composition ratio region 30a. The composition ratio between the barrier layer included in the first high In composition ratio region 30b and the barrier layer included in the first low In composition ratio region 30a may be continuously changed. The well layer included in the first high In composition ratio region 30b is continuous with the well layer 32 included in the first low In composition ratio region 30a. The In composition ratio in the well layer (GaInN layer) included in the first high In composition ratio region 30b is higher than the In composition ratio in the well layer 32 (GaInN layer) included in the first low In composition ratio region 30a.

  The composition ratio between the well layer included in the first high In composition ratio region 30b and the well layer included in the first low In composition ratio region 30a may be continuously changed.

  The stacked body 40 includes a second low In composition ratio region 40a and a second high In composition ratio region 40b. The second low In composition ratio region 40a does not overlap with the hole 60h in the Z-axis direction. The second high In composition ratio region 40b overlaps the hole 60h in the Z-axis direction. The direction from the second low In composition ratio region 40a to the second high In composition ratio region 40b intersects the Z-axis direction. The direction from the second low In composition ratio region 40a to the second high In composition ratio region 40b is, for example, perpendicular to the Z-axis direction.

  The average In composition ratio in the second high In composition ratio region 40b is higher than the average In composition ratio in the second low In composition ratio region 40a.

  For example, the second low In composition ratio region 40a includes a plurality of first layers 41 (any of GaN layers, AlGaInN layers, and AlGaN layers) and a plurality of second layers 42 (GaInN layers) that are alternately stacked. For example, the second high In composition ratio region 40b includes a plurality of third layers (any of GaN layers, AlGaInN layers, and AlGaN layers) and a plurality of fourth layers (GaInN layers) that are alternately stacked. The third layer included in the second high In composition ratio region 40b is continuous with the first layer 41 included in the second low In composition ratio region 40a.

  The composition ratio of the third layer included in the first high In composition ratio region 40b and the first layer included in the first low In composition ratio region 40a may change continuously.

  The fourth layer included in the second high In composition ratio region 40b is continuous with the second layer 42 included in the second low In composition ratio region 40a. The In composition ratio in the fourth layer (GaInN layer) included in the second high In composition ratio region 40b is higher than the In composition ratio in the second layer 42 (GaInN layer) included in the second low In composition ratio region 40a. .

The composition ratio of the fourth layer included in the second high In composition ratio region 40b and the second layer included in the second low In composition ratio region 40a may change continuously.
The wafer 160 can be formed in the same manner as described with respect to the wafers 150, 151, and 152, for example. In the wafer 160, cracks can be suppressed.

  In the wafer 160, the base 60 is provided with a hole 60hb. The hole 60hb may be provided after the formation of the flat substrate 60. The hole 60hb is formed by cutting, for example. For example, the hole 60hb may be formed on the lower surface of the base 60 after a nitride semiconductor layer (functional unit 10F) or the like is formed on the base 60. For example, the hole 60hb can be formed by removing a part of the base body 60 using a mask having an opening. The hole 60hb may be formed by putting a material (base material of a sintered body) to be the base 60 into a mold and sintering it. The mold is provided with a convex portion corresponding to the hole 60hb.

  A semiconductor crystal layer (the first semiconductor layer 10, the stacked body 40, the third semiconductor layer 30, the second semiconductor layer 20, and the like) is formed on the substrate 50 including the base body 60 provided with the holes 60h. At this time, since the hole 60h is provided in the base 60, the temperature of the substrate 50 at a position overlapping with the hole 60h is lower than the temperature of the substrate 50 at a position not overlapping with the hole 60h when the semiconductor crystal layer is grown. . In general, In is easily taken in at a low temperature. For this reason, In is easy to be taken in a region that does not overlap with the hole 60h.

  Therefore, the In composition ratio in the first high In composition ratio region 30b that overlaps the hole 60h is different from the In composition ratio in the first low In composition ratio region 30a that does not overlap the hole 60h due to the temperature difference when forming the third semiconductor layer. It becomes higher than the composition ratio. The In composition ratio in the second low In composition ratio region 40a that does not overlap with the hole 60h is caused by the difference in temperature at the time of forming the stacked body 40, so that the In composition ratio in the second high In composition ratio region 40b that overlaps with the hole 60h. Higher than.

  Therefore, the band gap energy of the well layer in the first high In composition ratio region 30b in the third semiconductor layer 30 is lower than the band gap energy of the well layer 32 in the first low In composition ratio region 30a. For this reason, a potential difference is generated in the third semiconductor layer 30. That is, in the third semiconductor layer 30, an electric field (drive voltage) acting on carriers is applied in the direction from the first low In composition ratio region 30a to the first high In composition ratio region 30b. This drive voltage has a component in a direction crossing the Z-axis direction. Accordingly, in-plane uniformity of light emission in the third semiconductor layer 30 is increased during operation.

  The width (for example, the length along the X-axis direction) of the hole 60h is, for example, not less than 100 μm and not more than 350 μm (for example, about 150 μm). For example, the width of the hole 60h is not less than about 1/6 and not more than about 1/3 of the side length of the element. For example, the hole 60h is provided in the central portion of the element. The hole 60h is disposed between two regions where the hole 60h is not provided. When the width of the hole 60h is 1/3 or more of the side length, the width of each of the two regions is substantially the same as the width of the hole 60h. Thereby, a big temperature difference is obtained. A temperature difference is obtained when the width of the hole 60h is 1/2 or more of the side.

  The depth of the hole 60h (for example, the length along the Z-axis direction) is, for example, 200 μm or more and 600 μm or less (for example, about 350 μm).

  For example, the distance along the Z-axis direction between the base surface 60s of the base body 60 and the bottom 60hb of the hole 60h is equal to or smaller than the width of the hole 60h. In this case, even when the temperature difference between the region in which the hole 60h is provided in the base 60 and the region in which the hole 60h is not provided is reduced by thermal diffusion, the temperature difference on the base surface 60s. Occurs. For example, the distance between the base surface 60s and the bottom 60hb of the hole 60h is 5 μm or more. For example, the distance between the base surface 60s and the bottom 60hb of the hole 60h is about the same as the thickness of the functional unit 10F. Thereby, for example, in the function unit 10F, it is difficult to cause a large deformation. The hole 60 h may penetrate the base body 60. The hole 60 h may reach the base portion 65. The hole 65h may reach the functional unit 10F.

(Fourth embodiment)
The semiconductor device according to the present embodiment is formed using, for example, the wafer 160 according to the third embodiment.
FIG. 13 is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.
In the semiconductor device 111 according to the present embodiment, the substrate 50 is removed after the wafer 160 is formed. A first electrode 10e is formed on the surface of the first semiconductor layer 10 exposed by the removal. Then, the second electrode 20 e is formed on the surface of the second semiconductor layer 20.

  As shown in FIG. 13, the first electrode 10e overlaps the first low In composition ratio region 30a and the second low In composition ratio region 40a in the Z-axis direction. The first electrode 10e does not overlap the first high In composition ratio region 30b and the second high In composition ratio region 40b in the Z-axis direction. That is, the first electrode 10e is provided at a position that does not overlap the hole 60h of the base body 60 in the Z-axis direction.

  The first semiconductor layer 10 is disposed between the first electrode 10e and the second electrode 20e. The stacked body 40, the third semiconductor layer 30, and the second semiconductor layer 20 are disposed between the first semiconductor layer 10 and the second electrode 20e.

  A first low In composition ratio region 30a and a second low In composition ratio region 40a are disposed between the first electrode 10e and the second electrode 20e.

  As described for the wafer 160, in the third semiconductor layer 30, a difference in band gap energy is provided between the first high In composition ratio region 30b and the first low In composition ratio region 30a. As a result, a potential difference is generated in the third semiconductor layer 30, and a drive voltage for carriers is applied. At this time, the position of the first electrode 10e in the XY plane is shifted with respect to the position of the first high In composition ratio region 30b in the XY plane. Therefore, in the third semiconductor layer 30, carriers are driven from the central region of the first high In composition ratio region 30b toward the central region of the first low In composition ratio region 30a. Thereby, in the third semiconductor layer 30, the ratio of light emission in a region far from the first electrode 10e is higher than the ratio of light emission in a region near the first electrode 10e. Thereby, the in-plane uniformity of the luminous efficiency is increased.

  For example, in the film forming apparatus, the substrate 50 is disposed on the heater. For example, as the distance from the heater increases, the temperature of the surface of the substrate 50 decreases. For example, when the change in the distance from the heater is 1 mm, the change in the temperature of the surface of the substrate 50 is 80 ° C. When the hole 60 h is provided in the base body 60, the distance between the bottom surface of the base body 60 and the heater varies depending on the location, so that a temperature distribution is generated inside the base body 60. On the other hand, when the hole 60 h is provided in the base body 60 and the temperature distribution is generated, the heat is uniformed by heat conduction in the base body 60. Soaking occurs at an angle of about 45 degrees. Considering these, the difference in temperature between the region overlapping the central portion of the hole 60h and the region not overlapping the hole 60h is about 3 ° C.

  On the other hand, the GaInN layer (well layer 32) has a peak wavelength of 450 nm, for example. The peak wavelength in the GaInN layer depends on the temperature of crystal growth. For example, the dependence of the peak wavelength on the crystal growth temperature is about 1.5 nm / ° C. When the difference in temperature is about 3 ° C., the difference in emission wavelength (peak wavelength) is about 5 nm. The difference of about 5 nm in the emission wavelength corresponds to about 60 meV in terms of energy difference. That is, a potential difference of about 60 meV is generated in the third semiconductor layer 30. As a result, a drive voltage is generated along the direction from the first high In composition ratio region 30b toward the first low In composition ratio region 30a. The drive voltage in this case is about 60 meV.

  At this time, the position in the XY plane is shifted between the first electrode 10e and the first high In composition ratio region 30b. Carriers are driven along the direction from the first high In composition ratio region 30b toward the first low In composition ratio region 30a. Thereby, the luminous efficiency in the third semiconductor layer 30 is made uniform. That is, current concentration is suppressed and the droop effect can be reduced. Thereby, the light emission characteristics can be improved. For example, EQE (External Quantum Efficiency) can be improved. The EQE in the configuration in which the position in the XY plane is shifted between the first electrode 10e and the first high In composition ratio region 30b is higher than, for example, the EQE in the configuration in which the position is not shifted. The improvement in EQE is, for example, about 1%.

  For example, when the element size (the length of one side of a substantially square element) is 1 mm, the electrode width is 7 μm, and the distance between the electrodes is approximately 240 μm, the first electrode 10e and the first high In composition The EQE in the configuration in which the position in the XY plane is not shifted between the specific region 30b and the specific region 30b is 80%. At this time, the EQE in the configuration in which the position in the XY plane is shifted between the first electrode 10e and the first high In composition ratio region 30b is 81%. Loss is reduced from 20% to 19%. The loss amount can be reduced by 5% with respect to the conventional loss.

  In the substrate 60, the average grain size d60 of the crystal grains 60g is smaller than the width of the first electrode 10e (the length in the direction intersecting the Z-axis direction). Thereby, for example, in the hole 60h, high positional accuracy can be obtained in the relative position to the electrode.

  The range in which the current spreads between the first electrode 10e and the second electrode 20e is a range in which the angle with the Z-axis direction is 45 degrees or less. Therefore, the spread of current is approximately the same as the thickness of the first semiconductor layer 10. From the viewpoint of current spreading, the accuracy of the relative positional relationship between the first electrode 10e and the hole 60h is preferably about the same as the accuracy of the thickness of the first semiconductor layer 10. The average particle diameter d60 is, for example, equal to or less than the thickness of the first semiconductor layer 10.

(Fifth embodiment)
FIG. 14 is a schematic cross-sectional view illustrating a semiconductor device according to the fifth embodiment.
The semiconductor device 112 according to the present embodiment includes a wafer 153 and a functional unit 10F.

  Wafer 153 includes a substrate 50. The substrate 50 includes a base body 60, a base part 65, and an intermediate part 55. As will be described later, in this example, the second base layer 62 of the base portion 65 is n-type. Except for this, the configuration of the substrate 50 is the same as the configuration described for the wafer 152, for example.

  An intermediate portion 55 is disposed between the base portion 65 and the functional portion 10F.

  The functional unit 10 </ b> F includes the first semiconductor layer 10. The first semiconductor layer 10 includes a first nitride semiconductor of a first conductivity type.

  In this example, the semiconductor device 112 further includes a gate electrode 75ge, a source electrode 75se, a drain electrode 75de, and a gate insulating film 75gi. The functional unit 10F is disposed between the intermediate unit 55 and the gate electrode 75ge. The functional unit 10F is disposed between the intermediate unit 55 and the source electrode 75se. The functional unit 10F is disposed between the intermediate unit 55 and the drain electrode 75de.

  The functional unit 10 </ b> F includes a first semiconductor region 71, a second semiconductor region 72, and a third semiconductor region 73. The first semiconductor region 71 is provided between the gate electrode 75ge and the first semiconductor layer 10. The second semiconductor region 72 includes a portion provided between the gate electrode 75ge and the first semiconductor region 71. The third semiconductor region 73 is provided between the gate electrode 75ge and the second semiconductor region 72. The first semiconductor region 71, the second semiconductor region 72, and the third semiconductor region 73 include a nitride semiconductor.

  The source electrode 75se is electrically connected to the second semiconductor region 72. The drain electrode 75de is electrically connected to the second semiconductor region 72.

  The position of the gate electrode 75ge in the X-axis direction (second direction) intersecting the Z-axis direction (first direction from the base 60 to the base portion 65) is the position of the source electrode 75se in the X-axis direction (second direction). It is located between the position and the position of the drain electrode 75de in the X-axis direction (second direction).

  A gate insulating film 75gi is provided between the gate electrode 75ge and the third semiconductor region 73.

  The first semiconductor layer 10 includes, for example, GaN containing C (carbon). The first semiconductor layer 10 is n-type.

  The first semiconductor region 71 is provided on the first semiconductor layer 10. The first semiconductor region 71 is, for example, a GaN layer.

  The second semiconductor region 72 is provided on the first semiconductor region 71. The second semiconductor region 72 is, for example, a GaInN layer. The second semiconductor region 72 may be GaN, for example.

  The second semiconductor region 72 may have a two-layer structure. The second semiconductor region 72 includes a GaN layer and a GaInN layer. A GaInN layer is provided between the GaN layer and the first semiconductor region 71.

  The third semiconductor region 73 is provided on a part of the second semiconductor region 72. The third semiconductor region 73 is, for example, an AlGaN layer. The third semiconductor region 73 may be GaN, for example.

  A source region 75sr is provided in part of the first semiconductor region 71 and part of the second semiconductor region 72. A source electrode 75se is provided on the source region 75sr. The source electrode 75se is electrically connected to the second semiconductor region 72 and the first semiconductor region 71 through the source region 75sr.

  A drain region 75dr is provided in another part of the first semiconductor region 71 and another part of the second semiconductor region 72. A drain electrode 75de is provided on the drain region 75dr. The drain electrode 75de is electrically connected to the second semiconductor region 72 and the first semiconductor region 71 through the drain region 75dr.

  In the X-axis direction, the third semiconductor region 73 is provided between the source electrode 75se and the drain electrode 75de. A gate insulating film 75gi is provided on the third semiconductor region 73. The gate insulating film 75gi includes, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxide. The gate insulating film 75gi includes, for example, a mixture of a first element containing at least one of silicon and aluminum and a second element containing at least one of oxygen and nitrogen.

  The third semiconductor region 73 may extend over the source region 75sr and the drain region 75dr. The third semiconductor region 73 may contain an n-type impurity at a high concentration. As the n-type impurity, at least one of Si, Ge, and Sn is used.

  At least one of the source region 75sr and the drain region 75dr may include a high concentration n-type impurity. At least one of the portion of the third semiconductor region 73 above the source region 75sr and the portion of the third semiconductor region 73 above the drain region 75dr may contain high-concentration n-type impurities. .

  In the semiconductor device 112, the current flowing between the source electrode 75se and the drain electrode 75de is controlled in accordance with the voltage applied to the gate electrode 75ge. The semiconductor device 112 is a transistor, for example.

  In this example, the second underlayer 62 is conductive. For example, the second underlayer 62 includes n-type impurities (such as As, P, and Sb) in addition to silicon. The second underlayer 62 includes at least one of As and Sb.

  The semiconductor device 112 further includes a base-side electrode 76e. The base-side electrode 76e is electrically connected to the second base layer 62. The potential of the second underlayer 62 is controlled by the substrate side electrode 76e.

  For example, the hole 60 h is provided in the back surface 60 r of the base body 60. The hole 60 h reaches the second underlayer 62. A conductive film is formed on at least a part of the inner wall of the hole 60h. This conductive film becomes the base-side electrode 76e.

  As shown in FIG. 14, the base body 60 is provided around at least a part of the base body side electrode 76e in the XY plane (a plane intersecting the Z-axis direction (first direction)). In this example, the substrate 50 has a gap 76g. The gap 76g is provided between the base 60 and at least a part of the base-side electrode 76e. The base-side electrode 76e is provided on a part of the side wall of the hole 60h, and the base-side electrode 76e is not provided on another part of the side wall of the hole 60h.

  In this example, the center in the X-axis direction of the hole 60h and the X-axis direction of the base-side electrode 76e in the hole 60h are shifted. The position of the gap 76g in the second direction (for example, the X-axis direction) is the position of the drain electrode 75de in the second direction (for example, the X-axis direction) and the second direction of the interface between the base-side electrode 76e and the second base layer 62. (E.g., in the X-axis direction).

FIG. 15A and FIG. 15B are schematic views illustrating another semiconductor device according to the fifth embodiment.
FIG. 15A is a schematic cross-sectional view. FIG. 15B is a schematic plan view.

  The semiconductor device 113 according to the present embodiment also includes a wafer 153 and a functional unit 10F. The configuration of the wafer 153 has the same configuration as that described for the semiconductor device 112.

  In the semiconductor device 113, the functional unit 10 </ b> F further includes a fourth semiconductor region 74. The fourth semiconductor region 74 is provided between the first semiconductor region 71 and the second semiconductor region 72. The fourth semiconductor region 74 includes a nitride semiconductor. The fourth semiconductor region 74 includes a portion 74g provided between the gate electrode 75ge and the first semiconductor layer 10, and a portion 74r provided between the source electrode 75se and the first semiconductor layer 10. A boundary 74b is formed between the portion 74g and the portion 74r.

  The portion 74g is, for example, a GaN layer. The portion 74r is, for example, an AlGaN layer. The portion 74r may be GaN, for example. The conductivity type of the portion 74r is, for example, a p-type. The composition ratio of aluminum in the portion 74r provided between the source electrode 75se and the first semiconductor layer 10 is the composition of aluminum in the portion 74g provided between the gate electrode 75ge and the first semiconductor layer 10. It may be higher than the ratio.

An n ⁻ conductive first semiconductor layer 10 is provided on the substrate 50. A first semiconductor region 71 (for example, a GaN layer) is provided on the first semiconductor layer 10, and a fourth semiconductor region 74 is provided thereon. In the fourth semiconductor region 74, a portion 74r (AlGaN) and a portion 74g (GaN) are provided. A second semiconductor region 72 (for example, a GaN layer) is provided on the fourth semiconductor region 74. A third semiconductor region 73 (for example, an AlGaN layer) is provided on at least a part of the second semiconductor region 72.

  Also in this example, the substrate side electrode 76e is provided. The base-side electrode 76e is electrically connected to the second base layer 62 and further electrically connected to the first semiconductor layer 10.

  In the semiconductor device 113, a current flows from the source electrode 75se to the substrate side electrode 76e. This current is controlled by a bias voltage applied to the gate electrode 75ge. In the semiconductor device 113, the spread of current and the spread of heat during operation can be controlled by the size and arrangement of the holes 60h. Thereby, it is possible to control the characteristics of the apparatus. For example, it is possible to improve the spread of current and to suppress the temperature rise associated with the operation.

FIG. 16 is a schematic cross-sectional view illustrating another semiconductor device according to the fifth embodiment.
The semiconductor device 114 according to the present embodiment also includes a wafer 153 and a functional unit 10F. The configuration of the wafer 153 is as described for the semiconductor device 112.

  In the semiconductor device 114, the resistance of the first semiconductor layer 10 is relatively high. The first semiconductor layer 10 is a high-resistance GaN layer. The impurity concentration in the first semiconductor region 71 is lower than the impurity concentration in the first semiconductor layer 10. The first semiconductor region 71 is a high-purity GaN layer.

  In the semiconductor devices 112 and 114, the functional unit 10F is formed on the substrate 50 provided with the hole 60h. For this reason, in the area | region which overlaps with the hole 60h, and the area | region which does not overlap with the hole 60h, a temperature difference is formed during formation of the function part 10F. For example, the composition ratio of In in the layer (region) containing In changes between a region overlapping with the hole 60h and a region not overlapping with the hole 60h. As a result, a band gap energy difference is formed in the direction intersecting the Z-axis direction. For example, an electric field is formed along the direction from the source electrode 75se to the drain electrode 75de. Thereby, a bias voltage is applied to the carrier. Thereby, for example, the off time of the transistor is shortened, and the operation is speeded up. Switching energy can be reduced.

  In the semiconductor devices 112 to 114, it is desirable that the position accuracy of the hole 60h is high. In the embodiment, the width (for example, diameter) of the hole 60 h is equal to or larger than the average particle diameter d60 of the base body 60. The width (for example, the diameter) of the hole 60 h may be 1.5 times or more the average particle diameter d60 of the base body 60. That is, in the embodiment, the average particle diameter d60 is made smaller than the size of the hole 60h. This increases the accuracy of the position of the hole 60h. This increases the accuracy of the bias voltage that is formed.

  For example, in the embodiment, the base-side electrode 76e includes a portion 76ex that overlaps the base 60 in the second direction (X-axis direction). The width of the hole 60h corresponds to the sum of the length in the second direction of the portion 76ex overlapping the base body 60 in the second direction and the length of the gap 76g along the second direction. In the embodiment, this sum is an average particle diameter d60 or more.

  According to the embodiment, the manufacturing cost of the wafer can be suppressed. A nitride semiconductor layer with high crystal quality can be formed.

  According to the embodiment, a wafer and a semiconductor device that can suppress cracks can be provided.

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

  In the present specification, “vertical” and “parallel” include not only strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may be substantially vertical and substantially parallel. It ’s fine.

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, a person skilled in the art has a specific configuration of each element such as a substrate, a base, a base portion, a base layer, an intermediate portion, an intermediate layer, a functional portion, a semiconductor layer, a semiconductor region, and an electrode included in a wafer and a semiconductor device. The present invention is similarly implemented by appropriately selecting from known ranges, and is included in the scope of the present invention as long as similar effects can be obtained.

  Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all wafers and semiconductor devices that can be implemented by those skilled in the art based on the wafers and semiconductor devices described above as embodiments of the present invention are included in the present invention as long as they include the gist of the present invention. Belongs to the range.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... 1st semiconductor layer, 10F ... Functional part, 10e ... 1st electrode, 10p ... 1st semiconductor part, 10q ... 2nd semiconductor part, 20 ... 2nd semiconductor layer, 20e ... 2nd electrode, 21 ... 1st p layer 22 ... 2nd p layer, 23 ... 3rd p layer, 30 ... 3rd semiconductor layer, 30a ... 1st low In composition ratio area | region, 30b ... 1st high In composition ratio area | region, 31 ... barrier layer, 32 ... well layer, 40 ... Laminated body, 40a ... second low In composition ratio region, 40b ... second high In composition ratio region, 41 ... first layer, 42 ... second layer, 50 ... substrate, 51 ... first intermediate layer, 52 ... 2nd intermediate layer, 53 ... 3rd intermediate layer, 55 ... Intermediate part, 60 ... Base, 60b ... Grain boundary, 60dp ... Unevenness, 60g ... Crystal grain, 60h ... Hole, 60hb ... Bottom, 60p ... Base part, 60q ... Boundary part, 60r ... back side, 60s Base surface 61: First base layer 61a: First silicon oxide film 61b: Second silicon oxide film 62 ... Second base layer 62l: First surface 62s: Silicon substrate 62sa, 62sb ... surface 62u ... second surface, 63 ... third underlayer, 65 ... underlying portion, 71 ... first semiconductor region, 72 ... second semiconductor region, 73 ... third semiconductor region, 74 ... fourth semiconductor region, 74b ... boundary, 74g, 74s ... part, 75de ... drain electrode, 75dr ... drain region, 75ge ... gate electrode, 75gi ... gate insulating film, 75se ... source electrode, 75sr ... source region, 76e ... substrate side electrode, 76ex ... part, 76g ... gap 110 to 114 semiconductor device 150, 151, 152, 153, 160 wafer, C1 dislocation density, C2 difference, D60 ... depth, L1, L2 ... length, R1, R2 ... region, Re1-Re3 ... region, S1 ... first structure, S2 ... second structure, d60 ... average particle size, dTE ... thermal expansion coefficient Difference, t0, t1, t11, t2, t21, t22 ... thickness, tc ... critical film thickness

Claims (20)

A substrate including a plurality of crystal grains;
A base part,
With
The base portion is
An amorphous first underlayer;
A second underlayer containing silicon;
Including
The first underlayer is provided between the second underlayer and the base body,
The first underlayer has a thickness of 140 nanometers or less;
The second underlayer has a thickness of 70 nanometers or less;
The wafer having an average grain size of 3.1 micrometers or less.   The wafer according to claim 1, wherein the average particle size is 2.5 micrometers or more.   The wafer according to claim 1, wherein the plurality of polycrystals includes aluminum nitride.   The wafer according to claim 1, wherein the first foundation layer includes silicon oxide. The substrate has a substrate surface in contact with the first underlayer,
The base surface has irregularities,
The wafer according to any one of claims 1 to 4, wherein a depth of the unevenness is not less than 50 nanometers and not more than 65 nanometers. The thickness of the first underlayer is 15 nanometers or more;
The wafer according to claim 1, wherein the thickness of the second underlayer is 8 nanometers or more. A third underlayer,
The second underlayer is disposed between the first underlayer and the third underlayer,
The wafer according to claim 1, wherein a concentration of nitrogen contained in the third foundation layer is higher than a concentration of nitrogen contained in the second foundation layer. The second underlayer has a first surface on the first underlayer side, and a second surface opposite to the first surface,
The wafer according to claim 1, wherein the second surface is any one of a (111) surface of silicon and a (113) surface of silicon. The second underlayer has a first surface on the first underlayer side, and a second surface opposite to the first surface,
The wafer according to claim 1, wherein an angle between the second surface and the (111) surface of silicon is 1 degree or less. An intermediate part,
The base portion is disposed between the intermediate portion and the base body,
The intermediate part is
A first intermediate layer comprising aluminum nitride;
A second intermediate layer comprising aluminum, gallium and nitrogen;
A third intermediate layer comprising gallium and nitrogen;
Including
The first intermediate layer is disposed between the third intermediate layer and the base portion;
The wafer according to claim 1, wherein the second intermediate layer is disposed between the third intermediate layer and the first intermediate layer. 11. The wafer according to claim 10, wherein a threading dislocation density in the first intermediate layer is 1 × 10 ¹⁰ / cm ² or less. It further has a functional part,
The intermediate portion is disposed between the functional portion and the base portion,
The wafer according to claim 10, wherein the functional unit includes a first semiconductor layer including a first nitride semiconductor of a first conductivity type. The functional unit is
A second semiconductor layer including a second nitride semiconductor of a second conductivity type;
A third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer;
The wafer of claim 12, further comprising: A wafer according to claim 10 or 11,
A functional unit including a first semiconductor layer including a first nitride semiconductor of a first conductivity type;
With
A semiconductor device, wherein the intermediate portion is disposed between the base portion and the functional portion. A gate electrode;
A source electrode;
A drain electrode;
Further comprising
The functional part is disposed between the intermediate part and the gate electrode,
The functional unit is
A first semiconductor region provided between the gate electrode and the first semiconductor layer;
A second semiconductor region including a portion provided between the gate electrode and the first semiconductor region;
A third semiconductor region provided between the gate electrode and the second semiconductor region;
Including
The source electrode is electrically connected to the second semiconductor region;
The drain electrode is electrically connected to the second semiconductor region;
The position of the gate electrode in the second direction intersecting the first direction from the base toward the base portion is the position of the source electrode in the second direction and the position of the drain electrode in the second direction. The semiconductor device according to claim 14, which is located between the two. A substrate-side electrode;
The second underlayer is conductive,
The semiconductor device according to claim 15, wherein the base-side electrode is electrically connected to the second base layer. The base is provided around at least a part of the base-side electrode in a plane intersecting the first direction;
The substrate has a gap provided between the base and the at least part of the base-side electrode;
The position of the gap in the second direction is located between the position of the drain electrode in the second direction and the position in the second direction of the interface between the base-side electrode and the second underlayer. The semiconductor device according to claim 16.   The semiconductor device according to claim 17, wherein the base-side electrode is further electrically connected to the first semiconductor layer. The base-side electrode includes a portion overlapping the base in the second direction,
The sum of the length in the second direction of the portion overlapping the base in the second direction and the length of the gap along the second direction is equal to or greater than the average particle diameter. 18. The semiconductor device according to 18. The functional unit further includes a fourth semiconductor region provided between the first semiconductor region and the second semiconductor region,
The fourth semiconductor region is
A portion provided between the gate electrode and the first semiconductor layer;
A portion provided between the drain electrode and the first semiconductor layer;
Including
The aluminum composition ratio in the portion provided between the drain electrode and the first semiconductor layer is higher than the aluminum composition ratio in the portion provided between the gate electrode and the first semiconductor layer. The semiconductor device according to claim 17.