JP2017055019A - Semiconductor light-emitting device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting device which does not degrade its characteristics in a semiconductor transfer process, and a method for manufacturing the same.SOLUTION: A semiconductor light-emitting device comprises: a substrate; a semiconductor layer in contact with the substrate and including an amorphous or polycrystalline region therein; an emitter provided on the semiconductor layer and including a first semiconductor of a first conductivity type, a second semiconductor of a second conductivity type, and a light-emitting layer provided between the first semiconductor and the second semiconductor; and a first electrode provided between the semiconductor layer and the emitter and electrically connected to any of the first semiconductor and the second semiconductor.SELECTED DRAWING: Figure 1

Description

  Embodiments relate to a semiconductor light emitting device and a method for manufacturing the same.

  There is a semiconductor light emitting device in which a semiconductor including a light emitting layer is formed over a first substrate, and then the semiconductor is transferred onto a second substrate different from the first substrate. However, in this process, distortion may occur in the semiconductor, which may deteriorate the characteristics of the semiconductor light emitting device.

JP 2004-80042 A

  Embodiments provide a semiconductor light-emitting device that does not deteriorate its characteristics in the process of semiconductor transfer and a method for manufacturing the same.

  A semiconductor light emitting device according to an embodiment includes a substrate, a semiconductor layer in contact with the substrate and including an amorphous or polycrystalline region therein, and a first semiconductor of a first conductivity type provided on the semiconductor layer. A light emitting body including a second semiconductor of a second conductivity type, a light emitting layer provided between the first semiconductor and the second semiconductor, and provided between the semiconductor layer and the light emitting body. And a first electrode electrically connected to one of the first semiconductor and the second semiconductor.

1 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to a first embodiment. It is a schematic cross section showing the manufacturing process of the semiconductor light-emitting device concerning a 1st embodiment. FIG. 3 is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 2. FIG. 4 is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 3. FIG. 5 is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 4. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process following FIG. 5. FIG. 7 is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 6. It is a schematic cross section showing a semiconductor light emitting device according to a second embodiment. It is a schematic cross section showing a manufacturing process of a semiconductor light emitting device according to a second embodiment. FIG. 10 is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 9. It is a schematic cross section showing the manufacturing process following FIG. FIG. 12 is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 11.

  Hereinafter, embodiments will be described with reference to the drawings. The same parts in the drawings are denoted by the same reference numerals, detailed description thereof will be omitted as appropriate, and different parts will be described. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.

  Description of each embodiment is an illustration and does not limit this invention to it. In addition, elements constituting each embodiment are commonly applied if technically possible.

[First Embodiment]
FIG. 1 is a schematic cross-sectional view showing a semiconductor light emitting device 1 according to the first embodiment. Fig.1 (a) is sectional drawing along the AA shown in FIG.1 (b). FIG. 1B is a top view.

  As shown in FIG. 1A, the semiconductor light emitting device 1 includes a substrate 10, a semiconductor layer 20, and a light emitter 30. The substrate 10 is, for example, a conductive silicon substrate. The semiconductor layer 20 is provided on the substrate 10.

  The semiconductor layer 20 is in contact with the substrate 10 and includes an amorphous or polycrystalline region therein. The semiconductor layer 20 includes, for example, the same material as that of the substrate 10. The semiconductor layer 20 is, for example, a silicon layer.

  Here, “amorphous” means a state in which there is no regularity in the arrangement of atoms. For example, even if there is regularity between adjacent atoms, there is no regularity in the arrangement of atoms as a whole. Includes state. Further, “polycrystal” refers to a state including a plurality of randomly oriented crystal grains. For example, according to the X-ray intensity distribution with respect to the diffraction angle in X-ray diffraction, the half width of the intensity peak of the amorphous semiconductor is wider than that of the polycrystalline semiconductor, and the polycrystalline semiconductor is single crystal. It is wider than a semiconductor.

  The light emitter 30 is provided on the semiconductor layer 20. The light emitter 30 includes a first semiconductor (hereinafter, n-type semiconductor 31), a light emitting layer 33, and a second semiconductor (p-type semiconductor 35). The light emitting layer 33 is provided between the n-type semiconductor 31 and the p-type semiconductor 35. The upper surface 30a of the light emitter 30 is roughened to improve the light extraction efficiency.

  The semiconductor light emitting device 1 further includes a first electrode (hereinafter, p-side electrode 40), a second electrode (hereinafter, n-side electrode 50), and a back metal layer 60. The p-side electrode 40 is provided between the semiconductor layer 20 and the light emitter 30.

  The p-side electrode 40 includes a contact layer 41 and a cap layer 43. The contact layer 41 is in contact with the p-type semiconductor 35 and is electrically connected to the p-type semiconductor 35. The cap layer 43 covers and electrically connects the contact layer 41 on the p-type semiconductor. The semiconductor layer 20 is in contact with the cap layer 43. The cap layer 43 includes a portion (extending portion 43 e) that extends outside the light emitting body 30 along the surface of the semiconductor layer 20. The contact layer 41 includes a material that reflects light emitted from the light emitting layer 33, for example, silver or aluminum.

  The n-side electrode 50 is provided on the n-type semiconductor 31 and is electrically connected to the n-type semiconductor 31. The n-side electrode 50 also functions as a bonding pad, for example. The back metal layer 60 is electrically connected to the back surface of the substrate 10.

  The semiconductor light emitting device 1 further includes a passivation film 37 that covers the side surface of the light emitter 30 and a bonding pad 45. The passivation film 37 is a silicon oxide film, for example, and protects the end face of the light emitting layer 33. The bonding pad 45 is provided on the extended portion 43 e of the cap layer 43.

  The semiconductor layer 20 has conductivity, for example, and electrically connects the substrate 10 and the p-side electrode 40. The semiconductor light emitting device 1 is mounted on a mounting substrate, for example, and is electrically connected to the drive circuit via the n-side electrode 50 and the back surface metal layer 60 or the n-side electrode 50 and the bonding pad 45.

  As shown in FIG. 1B, the semiconductor light emitting device 1 has, for example, a rectangular outer shape. On the upper surface of the semiconductor layer 20, the outer edge 30 p of the light emitter 30 is located inside the outer edge 20 p of the semiconductor layer 20. Further, the outer edge 40 p of the p-side electrode 40 is located inside the outer edge 20 p of the semiconductor layer 20. The outer edge 41p of the contact layer 41 is located inside the outer edge 40p of the p-side electrode 40 (the outer edge of the cap layer 43). That is, the semiconductor layer 20 is exposed in the dicing region DL surrounding the light emitter 30.

  Next, with reference to FIGS. 2A to 7B, a method for manufacturing the semiconductor light emitting device 1 according to the first embodiment will be described. 2A to 7B are schematic cross-sectional views sequentially showing the manufacturing process of the semiconductor light emitting device 1.

  As shown in FIG. 2A, an n-type semiconductor layer 131, a light emitting layer 133, and a p-type semiconductor layer 135 are epitaxially grown on a substrate 100 in this order. The substrate 100 is, for example, a silicon substrate. The n-type semiconductor layer 131, the light emitting layer 133, and the p-type semiconductor layer 135 are formed by using, for example, MOCVD (Metal Organic Chemical Vapor Deposition) using an organic metal as a raw material.

  The n-type semiconductor layer 131 includes, for example, an n-type gallium nitride layer (GaN layer). The n-type semiconductor layer 131 may further include a buffer layer containing GaN, aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or the like. The buffer layer is provided between the substrate 100 and the n-type GaN layer.

  The light emitting layer 133 includes a quantum well composed of, for example, a well layer made of indium gallium nitride (InGaN) and a barrier layer made of GaN. The light emitting layer 133 may have a multiple quantum well structure including a plurality of quantum wells.

  The p-type semiconductor layer 135 has a structure in which, for example, a p-type AlGaN layer and a p-type GaN layer are stacked. The p-type AlGaN layer is formed on the light emitting layer 133, and the p-type GaN layer is formed on the p-type AlGaN layer.

  As shown in FIG. 2B, the contact layer 41 is selectively formed on the p-type semiconductor layer 135. The contact layer 41 is a metal layer containing silver, for example. Here, “selectively forming” means forming not to cover the entire surface of the p-type semiconductor layer 135 but to cover a predetermined region. For example, the metal layer formed on the entire surface of the p-type semiconductor layer 135 is patterned into a predetermined shape using photolithography.

  As shown in FIG. 2C, the cap layer 43 is selectively formed and the contact layer 41 is covered. The cap layer 43 has a stacked structure including, for example, platinum (Pt), titanium (Ti), and gold (Au) in this order from the contact layer 41 side.

  As shown in FIG. 3A, the semiconductor layer 20 is formed on the p-type semiconductor layer 135. The semiconductor layer 20 covers the contact layer 41 and the cap layer 43. For example, the semiconductor layer 20 preferably has a thickness that is three or more times the combined thickness of the contact layer 41 and the cap layer 43 in a direction perpendicular to the surface of the p-type semiconductor layer 135. The semiconductor layer 20 is formed to a thickness of 1 to 2 μm, for example. Thereby, for example, the surface of the semiconductor layer 20 can be planarized using CMP (Chemical Mechanical Polishing).

The semiconductor layer 20 is a silicon layer formed by using, for example, plasma CVD (Plasuma enhanced Chemical Vapor Deposition). The semiconductor layer 20 is formed using, for example, silane gas (SiH ₄ ) as a raw material. Alternatively, diborane (B ₂ H ₆ ) may be added to the silane gas and the semiconductor layer 20 may be doped with p-type impurities. Thereby, the semiconductor layer 20 having conductivity can be formed. The semiconductor layer 20 is heat-treated using, for example, a laser annealing method. Thereby, p-type impurity boron (B) can be activated without damaging each layer under the semiconductor layer 20.

  The semiconductor layer 20 is preferably deposited at a temperature that can avoid thermal transformation of the metal that is the material of the contact layer 41 and the cap layer 43. The semiconductor layer 20 is formed at a temperature of 400 ° C. or lower, for example. Thereby, the deformation of the contact layer 41 and the cap layer 43 can be suppressed, and the strain generated in the n-type semiconductor layer 131, the light emitting layer 133, and the p-type semiconductor layer 135 can be reduced. The semiconductor layer 20 formed through such a process includes, for example, an amorphous or polycrystalline region, or both.

  As shown in FIG. 3B, the surface 20s of the semiconductor layer 20 is planarized. For example, the surface 20 s of the semiconductor layer 20 is planarized by using CMP so as to be several nmRa (arithmetic average roughness) or less.

  As shown in FIG. 4A, the substrate 10 and the semiconductor layer 20 are arranged to face each other. Subsequently, as shown in FIG. 4B, the substrate 10 and the semiconductor layer 20 are bonded. This process is performed, for example, in a decompressed chamber. Further, before bonding the substrate 10 and the semiconductor layer 20, for example, the surface 10 s of the substrate 10 and the surface 20 s of the semiconductor layer 20 are irradiated with argon (Ar) ions. Thereby, the natural oxide film formed on the surfaces 10s and 20s and the adsorbed impurities can be removed.

  The substrate 10 can be bonded to the semiconductor layer 20 by, for example, applying pressure at room temperature. Therefore, the contact layer 41 and the cap layer 43 are not thermally denatured. That is, an increase in contact resistance and a decrease in reflectance can be avoided. Further, the substrate 10 can be bonded to the semiconductor layer 20 without generating thermal strain in the n-type semiconductor layer 131, the light emitting layer 133, and the p-type semiconductor layer 135.

  As shown in FIG. 5A, the substrate 100 is removed from the surface of the n-type semiconductor layer 131. For example, the substrate 100 is thinned by grinding and then removed by wet etching. 5A shows the upside down of FIG. 4B (see the XYZ axes in FIG. 5).

  As shown in FIG. 5B, the surface 131a of the n-type semiconductor layer 131 is roughened. For example, the n-type semiconductor layer 131 is wet-etched using an alkaline solution. In this etching process, an etching solution whose etching rate of the n-type semiconductor layer 131 depends on the crystal plane is used. As a result, a crystal plane whose etching rate is slower than the others can be exposed on the surface 131a. As a result, irregularities are formed on the surface 131a of the n-type semiconductor layer 131 to be roughened.

  As shown in FIG. 6A, the n-type semiconductor layer 131, the light emitting layer 133, and the p-type semiconductor layer 135 are selectively removed to form the light emitter 30. The light emitter 30 can be wet etched using, for example, hot phosphoric acid. The light emitter 30 includes an n-type semiconductor 31, a light-emitting layer 33, and a p-type semiconductor 35. The n-type semiconductor 31, the light emitting layer 33, and the p-type semiconductor 35 are part of the n-type semiconductor layer 131, the light-emitting layer 133, and the p-type semiconductor layer 135, respectively.

  As shown in FIG. 6B, a passivation film 37 is formed to cover the side surface 30 b of the light emitter 30. The passivation film 37 is, for example, a silicon oxide film or a silicon nitride film formed using plasma CVD, and protects the light emitting layer 33 exposed on the side surface 30b. Further, an opening 37 a is formed in the passivation film 37 on the extended portion 43 e of the cap layer 43. Further, a dicing region DL is formed between the light emitters 30 adjacent to each other on the upper surface of the semiconductor layer 20 (see FIG. 7B).

  As shown in FIG. 6C, a bonding pad 45 and an n-side electrode 50 are formed. The bonding pad 45 is formed on the extension part 43e inside the opening 37a and is electrically connected to the extension part 43e. The n-side electrode 50 is selectively formed on the light emitter 30 and is in contact with the upper surface 30a. For the bonding pad 45 and the n-side electrode 50, for example, an aluminum layer formed using a vacuum deposition method can be used. The bonding pad 45 and the n-side electrode 50 can be formed simultaneously.

  As shown in FIG. 7A, a back metal layer 60 is formed on the back surface of the substrate 10. For example, after the adhesive sheet 140 is attached to the upper surface 30a of the light emitter 30, the back surface of the substrate 10 is ground to a predetermined thickness (100 to 200 μm). Subsequently, for example, titanium (Ti), platinum (Pt), and gold (Au) are sequentially deposited to form the back metal layer 60.

  As shown in FIG. 7B, the semiconductor light emitting device 1 is formed into a chip. For example, the dicing sheet 150 is attached to the back surface of the substrate 10 and the semiconductor layer 20 and the substrate 10 are cut using a dicing blade.

  The semiconductor light emitting device 1 according to this embodiment includes a p-side electrode 40 that reflects light emitted from the light emitting layer 33 between the substrate 10 and the light emitter 30. Thereby, the light absorption of the board | substrate 10 can be suppressed. Further, the semiconductor layer 20 is exposed in the dicing region DL, and no metal other than the metal layer 60 on the back surface side of the substrate 10 is interposed. Therefore, it is easy to avoid chipping during dicing, and the manufacturing yield can be improved.

[Second Embodiment]
FIG. 8 is a schematic cross-sectional view showing the semiconductor light emitting device 2 according to the second embodiment. The semiconductor light emitting device 2 includes a substrate 10, a semiconductor layer 20, and a light emitter 30. The substrate 10 is, for example, a silicon substrate.

  The semiconductor layer 20 is provided on the substrate 10. The semiconductor layer 20 is in contact with the substrate 10 and includes an amorphous or polycrystalline region therein. The semiconductor layer 20 includes, for example, the same material as that of the substrate 10. The semiconductor layer 20 is, for example, a silicon layer.

  The light emitter 30 is provided on the semiconductor layer 20. The light emitter 30 includes an n-type semiconductor 31, a light-emitting layer 33, and a p-type semiconductor 35. The light emitter 30 has a via hole 39 that penetrates the p-type semiconductor 35 and the light-emitting layer 33 and reaches the n-type semiconductor 31.

  The semiconductor light emitting device 2 further includes a p-side electrode 40, an insulating layer 47, and an n-side electrode 55 between the semiconductor layer 20 and the light emitter 30. The n-side electrode 55 is provided on the bottom surface of the via hole 39 and is electrically connected to the n-type semiconductor 31.

  The p-side electrode 40 includes a contact layer 41 and a cap layer 43. The contact layer 41 is in contact with the p-type semiconductor 35 and is electrically connected to the p-type semiconductor 35. The cap layer 43 covers the contact layer 41 and is electrically connected to the contact layer 41.

  The insulating layer 47 is provided between the semiconductor layer 20 and the p-side electrode 40 and covers the p-side electrode 40. The p-side electrode 40 is electrically insulated from the semiconductor layer 20 by the insulating layer 47. The p-type semiconductor 35 is also electrically insulated from the semiconductor layer 20 by the insulating layer 47.

  Further, as shown in FIG. 8, the semiconductor layer 20 has a portion (extending portion 20 a) extending inside the via hole 39. The extending portion 20a is in contact with and electrically connected to the n-side electrode 55. The insulating layer 47 covers the inner wall of the via hole 39 and electrically insulates the light emitting layer 33 and the p-type semiconductor 35 from the semiconductor layer 20.

  In the present embodiment, the p-side electrode 40 and the n-side electrode 55 are provided between the semiconductor layer 20 and the light emitter 30. The p-side electrode 40 is electrically insulated from the semiconductor layer 20, and the n-side electrode 55 is electrically connected to the semiconductor layer 20. For example, the p-side electrode 40 is connected to the drive circuit via the bonding pad 45, and the n-side electrode 55 is electrically connected to the drive circuit via the semiconductor layer 20, the substrate 10, and the back metal layer 60.

  Next, with reference to FIGS. 9A to 12C, a method for manufacturing the semiconductor light emitting device 2 according to the second embodiment will be described. FIG. 9A to FIG. 12B are schematic cross-sectional views sequentially showing the manufacturing process of the semiconductor light emitting device 2.

  As shown in FIG. 9A, an n-type semiconductor layer 131, a light emitting layer 133, and a p-type semiconductor layer 135 are epitaxially grown on a substrate 100 in this order. The substrate 100 is, for example, a silicon substrate. Subsequently, the p-side electrode 40 is formed. For example, the contact layer 41 is formed on the p-type semiconductor layer 135 using a vacuum deposition method or a sputtering method. The contact layer 41 is patterned using, for example, photolithography. Further, a cap layer 43 covering the contact layer 41 is formed on the p-type semiconductor layer 135.

  As shown in FIG. 9B, a via hole 39 is formed. The via hole 39 is selectively formed by using, for example, RIE (Reactive Ion Etching). This etching is performed using, for example, a resist mask having an opening in a portion where the via hole 39 is to be formed. The via hole 39 is formed to a depth reaching the n-type semiconductor layer 131 through the p-type semiconductor layer 135 and the light emitting layer 133. The via hole 39 has a diameter of 30 μm to 100 μm, for example. Thereby, the density of the current flowing through the n-side electrode 55 can be reduced.

  As shown in FIG. 9C, the insulating layer 47 is formed. The insulating layer 47 covers the inner surfaces of the p-type semiconductor 35, the p-side electrode 40 and the via hole 39. The insulating layer 47 is, for example, a silicon oxide layer or a silicon nitride layer formed using plasma CVD. The insulating layer 47 is formed at a growth temperature of 300 ° C. or lower, for example. Thereby, for example, an increase in contact resistance between the p-type semiconductor 35 and the p-side electrode 40 and a decrease in the reflectance of the p-side electrode 40 can be avoided. The insulating layer 47 has a thickness of 500 nm to 1500 nm, for example. Thereby, the withstand voltage between the semiconductor layer 20 and the light emitter 30 and between the semiconductor layer 20 and the p-side electrode 40 can be made larger than a predetermined value.

  As shown in FIG. 10A, the n-side electrode 55 is formed on the bottom surface of the via hole 39. For example, the insulating layer 47 is selectively removed using a resist mask having an opening communicating with the bottom surface of the via hole 39. Subsequently, for example, an aluminum layer is formed using a vacuum deposition method. Thereafter, a portion to be the n-side electrode 55 is left on the bottom surface of the via hole 39, and the resist mask and the aluminum layer formed thereon are removed.

  As shown in FIG. 10B, the semiconductor layer 20 is formed on the insulating layer 47. The semiconductor layer 20 fills the inside of the via hole 39 and contacts the n-side electrode 55. The semiconductor layer 20 is formed to a thickness of 3 μm to 5 μm, for example. Thereby, the inside of the via hole 39 can be buried and planarized by using, for example, CMP (Chemical Mechanical Polishing).

The semiconductor layer 20 is a silicon layer formed by using, for example, plasma CVD (Plasuma enhanced Chemical Vapor Deposition). The semiconductor layer 20 is formed using, for example, silane gas (SiH ₄ ) added with phosphine (PH ₃ ) as a raw material. Thereby, a silicon layer doped with n-type impurities can be formed. The semiconductor layer 20 is heat-treated using, for example, a laser annealing method to activate phosphorus (P) that is an n-type impurity. The semiconductor layer 20 is formed, for example, at a temperature of 400 ° C. or lower, and includes an amorphous region or a polycrystalline region, or both.

  As shown in FIG. 11A, the surface 20s of the semiconductor layer 20 is planarized. For example, the surface 20 s of the semiconductor layer 20 is planarized by using CMP so as to be several nmRa (arithmetic average roughness) or less.

  As shown in FIG. 11B, the substrate 10 and the semiconductor layer 20 are bonded. The surface 10s of the substrate 10 and the surface 20s of the semiconductor layer 20 are opposed to each other, and then both are brought into contact with each other. Further, for example, the substrate 10 is bonded to the semiconductor layer 20 by applying pressure at room temperature.

  As shown in FIG. 12A, the substrate 100 is removed from the surface of the n-type semiconductor layer 131. The substrate 100 is removed using, for example, grinding and wet etching. In addition, Fig.12 (a) represents upside down of FIG.11 (b) (refer the XYZ axis | shaft in the same figure).

  As shown in FIG. 12B, the light emitter 30 is formed. For example, the surface 131a of the n-type semiconductor layer 131 is roughened by etching, and then the n-type semiconductor layer 131, the light emitting layer 133, and the p-type semiconductor layer 135 are selectively removed. The light emitter 30 includes an n-type semiconductor 31, a light-emitting layer 33, and a p-type semiconductor 35. The n-type semiconductor 31, the light emitting layer 33, and the p-type semiconductor 35 are part of the n-type semiconductor layer 131, the light-emitting layer 133, and the p-type semiconductor layer 135, respectively.

  As shown in FIG. 12C, a passivation film 37 is formed to cover the side surface 30 b of the light emitter 30. Further, a bonding pad 45 is formed. The bonding pad 45 is formed on the extension part 43e. Subsequently, the back surface metal layer 60 is formed according to the steps shown in FIGS. 7A and 7B, and the semiconductor light emitting device 2 is made into a chip.

  As described above, in this embodiment, each semiconductor layer to be the light emitter 30 is transferred to the substrate 10 by directly wafer bonding the substrate 10 and the semiconductor layer 20. This process can be performed at room temperature (room temperature), and for example, thermal strain generated in the light emitter 30 can be reduced as compared with the case where a metal bonding material such as a solder material is used. In addition, by using the semiconductor layer 20 as a bonding layer, it is possible to reduce the metal layer in the dicing region, and it is easy to make a chip by dicing.

In the present specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, 0 ≦ x + y + z ≦ 1) includes a group III-V compound semiconductor, and further includes a mixed crystal containing phosphorus (P), arsenic (As), etc. in addition to N (nitrogen) as a group V element. Further, in the above composition, those containing various elements added to control various physical properties such as conductivity type and those further containing various elements included unintentionally are also referred to as “nitride semiconductors”. To be included.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1, 2 ... Semiconductor light-emitting device 10, 100 ... Board | substrate, 10s, 20s, 131a ... Surface, 20 ... Semiconductor layer, 20a ... Extension part, 20p, 30p, 40p, 41p ... Outer edge, 30 ... Light-emitting body, 30a ... Upper surface, 30b ... side surface, 31 ... n-type semiconductor, 33, 133 ... light emitting layer, 35 ... p-type semiconductor, 37 ... passivation film, 37a ... opening, 39 ... via hole, 40 ... p-side electrode, 41 ... contact layer, 43 ... Cap layer, 43e ... Extension, 45 ... Bonding pad, 47 ... Insulating layer, 50, 55 ... n-side electrode, 60 ... Back metal layer, 131 ... n-type semiconductor layer, 135 ... p-type semiconductor layer, 140 ... Adhesive sheet, 150 ... Dicing sheet, DL ... Dicing area

Claims (5)

A substrate,
A semiconductor layer in contact with the substrate and including an amorphous or polycrystalline region therein;
A first conductivity type first semiconductor; a second conductivity type second semiconductor; and a light emitting layer provided between the first semiconductor and the second semiconductor. A light emitter;
A first electrode provided between the semiconductor layer and the light emitter and electrically connected to one of the first semiconductor and the second semiconductor;
A semiconductor light emitting device comprising:   2. The semiconductor device according to claim 1, further comprising a second electrode that is electrically connected to the other of the first semiconductor and the second semiconductor and electrically insulated from the semiconductor layer between the semiconductor layer and the light emitter. Semiconductor light emitting device.   The semiconductor light emitting device according to claim 1, wherein a surface of the semiconductor layer is exposed in a dicing region surrounding the light emitter.   The semiconductor light-emitting device according to claim 1, wherein the semiconductor layer includes the same material as the substrate. A laminated structure including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer is provided. Forming on one substrate;
Selectively forming an electrode electrically connected to the first semiconductor layer or the second semiconductor layer on the stacked structure;
Forming a third semiconductor layer covering the electrode on the stacked structure;
Bringing the surface of the second substrate into contact with the surface of the third semiconductor layer, and bonding the third semiconductor layer and the second substrate;
Removing the first substrate from the laminated structure;
A method for manufacturing a semiconductor light emitting device comprising:

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