JP2017055045A - Semiconductor light emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light emitting device which enables improvement of heat radiation performance.SOLUTION: A semiconductor light emitting device according to one embodiment includes: a substrate; a light emitting body provided on the substrate and including a first semiconductor having a first conductivity type, a second semiconductor having a second conductivity type, and a light emitting layer provided between the first semiconductor and the second semiconductor; a metal layer provided between the substrate and the light emitting body and electrically connected with one of the first semiconductor and the second semiconductor; and a metal body embedded in the substrate below the light emitting body and connected with the metal layer.SELECTED DRAWING: Figure 1

Description

  Embodiments relate to a semiconductor light emitting device.

  In order to increase the brightness of a semiconductor light emitting device, it is important to improve the light emission efficiency. For example, when the drive current of the semiconductor light emitting device is increased, the light output increases, but the temperature of the light emitting layer increases due to Joule heat, and the light emission efficiency decreases. Therefore, a technique for efficiently dissipating heat generated in the semiconductor light emitting device is required.

JP 2009-278139 A

  Embodiments provide a semiconductor light emitting device with improved heat dissipation.

  The semiconductor light emitting device according to the embodiment includes a substrate, a first semiconductor of the first conductivity type, a second semiconductor of the second conductivity type, the first semiconductor, and the second semiconductor. A light emitting layer including a light emitting layer, a metal layer provided between the substrate and the light emitting body, and electrically connected to one of the first semiconductor and the second semiconductor; A metal body embedded in the substrate below the light emitter and connected to the metal layer.

1 is a schematic diagram illustrating a semiconductor light emitting device according to an embodiment. It is a schematic cross section which shows the manufacturing process of the semiconductor light-emitting device concerning embodiment. FIG. 3 is a schematic cross-sectional view showing a manufacturing process following FIG. 2. FIG. 4 is a schematic cross-sectional view showing a manufacturing process following FIG. 3. FIG. 5 is a schematic cross-sectional view showing a manufacturing process following FIG. 4. It is a schematic cross section which shows the manufacturing process of the board | substrate which concerns on embodiment. FIG. 7 is a schematic cross-sectional view showing a manufacturing process following FIG. 6. FIG. 8 is a schematic cross-sectional view showing the manufacturing process following FIG. 7. It is a schematic plan view which shows the board | substrate which concerns on embodiment. It is a schematic diagram which shows the semiconductor light-emitting device which concerns on the modification of embodiment. It is a schematic diagram which shows the semiconductor light-emitting device which concerns on another modification of embodiment. It is a schematic diagram which shows the semiconductor light-emitting device which concerns on the other modification of embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. The same parts in the drawings are denoted by the same reference numerals, detailed description thereof will be omitted as appropriate, and different parts will be described. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.

  Furthermore, the arrangement and configuration of each part will be described using the X-axis, Y-axis, and Z-axis shown in each drawing. The X axis, the Y axis, and the Z axis are orthogonal to each other and represent the X direction, the Y direction, and the Z direction, respectively. Further, the Z direction may be described as the upper side and the opposite direction as the lower side.

  Description of embodiment is an illustration and does not limit this invention to it. In addition, elements constituting each embodiment are commonly applied if technically possible.

  FIG. 1 is a schematic cross-sectional view showing a semiconductor light emitting device 1 according to the first embodiment. Fig.1 (a) is sectional drawing along the AA shown in FIG.1 (b). FIG. 1B is a top view.

  As shown in FIG. 1A, the semiconductor light emitting device 1 includes a substrate 10, a light emitter 20, a metal layer 30, and a metal body 40. The substrate 10 is, for example, a conductive silicon substrate. The light emitter 20 is provided on the substrate 10 via the metal layer 30 and the metal body 40.

  The light emitter 20 includes a first semiconductor (hereinafter, n-type semiconductor 21), a light emitting layer 23, and a second semiconductor (p-type semiconductor 25). The light emitting layer 23 is provided between the n-type semiconductor 21 and the p-type semiconductor 25. The upper surface 20a of the light emitter 20 is roughened to improve light extraction efficiency.

  The metal layer 30 and the metal body 40 are provided below the light emitter 20. The metal layer 30 is located between the light emitter 20 and the metal body 40 and is bonded to the metal body 40. The metal body 40 is provided inside the substrate 10. The metal body 40 includes a first portion 41 and a second portion 43. The first portion 41 is embedded in a recess 10 a provided in the substrate 10. The second portion 43 extends downward from the first portion 41 in the substrate 10. The second portion 43 is provided at a depth that does not reach the back surface 10b of the substrate 10, for example.

  The semiconductor light emitting device 1 further includes a metal layer 45. The metal layer 45 is provided between the substrate 10 and the metal body 40 and functions as a barrier metal layer. The metal layer 45 suppresses diffusion of metal atoms from the metal body 40 to the substrate 10. The metal layer 45 includes, for example, at least one of tantalum (Ta) and tantalum nitride (TaN), titanium (Ti), and platinum (Pt).

  The semiconductor light emitting device 1 further includes a metal layer 31, a p-side electrode 51, an n-side electrode 53, and a bonding pad 55.

  The metal layer 31 is provided between the light emitter 20 and the metal layer 30. The metal layer 31 includes a barrier metal and suppresses diffusion of metal atoms from the metal layer 30 to the light emitter 20. The metal layer 31 includes a barrier metal such as tantalum (Ta) or tantalum nitride (TaN).

  The p-side electrode 51 is provided between the light emitter 20 and the metal layer 31 and is electrically connected to the p-type semiconductor 21. The p-side electrode 51 includes a metal that reflects light emitted from the light emitting layer 23. The p-side electrode 51 includes, for example, silver (Ag). The metal layer 31 suppresses the diffusion of metal atoms from the metal layer 30 to the p-side electrode 51, thereby reducing the reflectance of the p-side electrode 51 and between the p-type semiconductor 25 and the p-side electrode 51. Prevent increase in contact resistance.

  For example, the n-side electrode 53 is provided on the light emitter 20 and is electrically connected to the n-type semiconductor 21. The n-side electrode 53 also functions as a bonding pad, for example. The bonding pad 55 is provided on the metal layer 31 exposed to the outside of the light emitter 20.

  Metal layers 30 and 31 are electrically connected to p-type semiconductor 25 through p-side electrode 51. The bonding pad 55 is electrically connected to the p-side electrode 51 through the metal layers 30 and 31.

  The semiconductor light emitting device 1 further includes a back metal layer 13 and a passivation film 27 that covers the side surface of the light emitter 20. The back metal layer 13 is electrically connected to the back surface of the substrate 10. The passivation film 27 is a silicon oxide film, for example, and protects the end face of the light emitting layer 23.

  The semiconductor light emitting device 1 is mounted on a mounting substrate, for example. Then, it is electrically connected to the external drive circuit via the back metal layer 13 and the n-side electrode 53 or the n-side electrode 53 and the bonding pad 55. Furthermore, Joule heat generated in the light emitter 20 is dissipated to the mounting substrate side through the p-side electrode 51, the metal layer 30, the metal body 40, the substrate 10, and the back surface metal layer 13. In this example, the metal body 40 is embedded in the substrate 10 to improve the thermal conductivity in the heat dissipation path. Thereby, the luminous efficiency of the semiconductor light emitting device 1 can be improved and the output can be increased.

  As shown in FIG. 1B, the semiconductor light emitting device 1 has, for example, a rectangular outer shape. On the upper surface of the substrate 10, the outer edge 30 p of the metal layer 30 is located inside the outer edge 10 p of the substrate 10. Further, the outer edge 20p of the light emitter 20 is located on the inner side of the outer edge 30p of the metal layer 30. That is, the substrate 10 is exposed in the dicing region DL surrounding the light emitter 20.

  Next, with reference to FIGS. 2A to 5B, a method for manufacturing the semiconductor light emitting device 1 according to the embodiment will be described. FIG. 2A to FIG. 5B are schematic cross-sectional views sequentially showing the manufacturing process of the semiconductor light emitting device 1.

  As shown in FIG. 2A, an n-type semiconductor layer 121, a light emitting layer 123, and a p-type semiconductor layer 125 are epitaxially grown on a substrate 100 in this order. In addition, in FIG. 2 (a)-FIG.2 (c), it displayed upside down.

  The substrate 100 is, for example, a silicon substrate. The n-type semiconductor layer 121, the light emitting layer 123, and the p-type semiconductor layer 125 are formed using, for example, CVD (Metal Organic Chemical Vapor Deposition) using an organic metal as a raw material.

  The n-type semiconductor layer 121 includes, for example, an n-type gallium nitride layer (GaN layer). The n-type semiconductor layer 121 may further include a buffer layer containing GaN, aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or the like. The buffer layer is provided between the substrate 100 and the n-type GaN layer.

  The light emitting layer 123 includes a quantum well composed of, for example, a well layer made of indium gallium nitride (InGaN) and a barrier layer made of GaN. The light emitting layer 123 may have a multiple quantum well structure including a plurality of quantum wells.

  For example, the p-type semiconductor layer 125 has a structure in which a p-type AlGaN layer and a p-type GaN layer are stacked. The p-type AlGaN layer is formed on the light emitting layer 123, and the p-type GaN layer is formed on the p-type AlGaN layer.

  Further, as shown in FIG. 2A, the p-side electrode 51 and the insulating layer 35 are selectively formed on the p-type semiconductor layer 125. The p-side electrode 51 is a metal layer containing silver, for example. The insulating layer 35 is a silicon oxide layer formed using, for example, plasma enhanced chemical vapor deposition (CVD). The insulating layer 35 includes an opening 35a.

  Here, “selectively forming” means forming not to cover the entire surface of the p-type semiconductor layer 125 but to cover a predetermined region. For example, the opening 35 a is formed in the insulating layer 35 formed on the entire surface of the p-type semiconductor layer 125 using photolithography. The p-side electrode 51 is formed on the p-type semiconductor layer 125 exposed at the bottom surface of the opening 35a.

  As shown in FIG. 2B, metal layers 30 and 31 are formed. The metal layer 31 is formed so as to cover the upper surface of the insulating layer 35 and the inner surface of the opening 35a. The metal layer 31 covers the p-side electrode 51. The metal layer 30 is formed on the metal layer 31.

  The metal layer 31 is formed by using, for example, a sputtering method, and has a structure in which, for example, a tantalum nitride (TaN) layer, a tantalum (Ta) layer, and a copper (Cu) layer are stacked. For example, the tantalum nitride layer is in contact with the inner surface of the insulating layer 35 and the opening 35a. The copper layer is exposed on the entire surface of the metal layer 31 opposite to the light emitter 20. The tantalum layer is provided between the tantalum nitride layer and the copper layer. The tantalum nitride layer and the tantalum layer function as a barrier metal layer, for example, and suppress the diffusion of metal atoms from the metal layer 30 to each semiconductor layer.

  The metal layer 30 is a copper layer formed using, for example, a plating method. For example, the metal layer 30 has a thickness capable of filling the opening 35a and planarizing the surface by using CMP (Chemical Mechanical Polishing). For example, the thickness of the metal layer 30 is thicker than the total thickness of the metal layer 31 and the p-side electrode 51.

  As shown in FIG. 2C, the surface of the metal layer 30 is planarized. For example, a part of each of the metal layer 30 and the metal layer 31 is removed by using CMP to expose the insulating layer 35. Thereby, a planarized surface including the surface of the metal layer 30 and the surface of the insulating layer 35 is formed on the substrate 100.

  As shown in FIG. 3A, the substrate 10 is disposed so as to face the substrate 100. The metal body 40 is embedded in the substrate 10. The metal body 40 includes a first portion 41 and a second portion 43. The second portion 43 extends downward from the first portion inside the substrate 10. The metal body 40 is formed by the manufacturing process shown in FIGS. 7 (a) to 8 (c). The metal body 40 includes, for example, copper. A metal layer 45 is formed between the substrate 10 and the metal body 40. The metal layer 45 includes, for example, tantalum nitride (TaN) and tantalum (Ta), titanium (Ti), platinum (Pt), or the like.

  The surfaces of the metal layer 30 and the metal body 40 are treated with, for example, plasma activation or citric acid, and the surface oxide film is removed. Subsequently, for example, the metal layer 30 and the metal body 40 are opposed to each other using a double-sided alignment method.

  As shown in FIG. 3B, the metal layer 30 and the metal body 40 are brought into contact and joined. This process is performed using, for example, a Fusion bonding method. For example, pressure is applied from the back side of the substrate 10 and the substrate 100, and the temperature is raised as necessary. Simultaneously with the joining of the metal layer 30 and the metal body 40, the substrate 10 and the insulating layer 35 are also joined. The joining of the metal layer 30 and the metal body 40 can be performed at a low temperature, for example, room temperature (room temperature), and the generation of stress between the substrate 10 and the light emitter 20 after the joining can be suppressed.

  Subsequently, the substrate 100 is removed from the surface of the n-type semiconductor layer 121. For example, the substrate 100 is thinned by grinding and then removed by wet etching.

  As shown in FIG. 4A, the light emitter 20 is formed. For example, the surface of the n-type semiconductor layer 121 exposed after removing the substrate 100 is roughened. For example, the surface of the n-type semiconductor layer 121 is wet etched using an alkaline solution. Thereafter, the n-type semiconductor layer 121, the light-emitting layer 123, and the p-type semiconductor layer 125 are selectively removed to form the light-emitting body 20. The n-type semiconductor layer 121, the light emitting layer 123, and the p-type semiconductor layer 125 can be wet-etched using, for example, hot phosphoric acid. The light emitter 20 includes an n-type semiconductor 21, a light-emitting layer 23, and a p-type semiconductor 25. The n-type semiconductor 21, the light emitting layer 23, and the p-type semiconductor 25 are part of the n-type semiconductor layer 121, the light-emitting layer 123, and the p-type semiconductor layer 125, respectively.

  As shown in FIG. 4B, a passivation film 27 is formed to cover the side surface 20 b of the light emitter 20. The passivation film 27 is a silicon oxide film formed using, for example, plasma CVD. The passivation film 27 protects the light emitting layer 23 exposed on the side surface 20b. In addition, the passivation film 27 is selectively etched to form an opening 27 a that communicates with the metal layer 31 exposed outside the light emitter 20. Further, on the upper surface of the substrate 10, the passivation film 27 and the insulating layer 35 are removed, and a dicing region DL surrounding the light emitter 20 is formed.

  Subsequently, an n-side electrode 53 and a bonding pad 55 are formed. The n-side electrode 53 is selectively formed on the light emitter 20. The bonding pad 55 is in contact with the metal layer 31 inside the opening 27a. For the n-side electrode 53 and the bonding pad 55, for example, an aluminum layer formed using a vacuum deposition method can be used. Further, the n-side electrode 53 and the bonding pad 55 can be formed simultaneously.

  As shown in FIG. 5A, the back metal layer 13 is formed on the back surface of the substrate 10. For example, after the adhesive sheet 61 is attached to the upper surface 20a of the light emitter 20, the back surface of the substrate 10 is ground to a predetermined thickness (100 to 200 μm). Subsequently, for example, titanium (Ti), platinum (Pt), and gold (Au) are sequentially deposited to form the back surface metal layer 13. In this example, the substrate 10 is formed such that a part of the substrate 10 is interposed between the second portion 43 of the metal body 40 and the back surface metal layer 13. For example, the second portion 43 may be formed so as to penetrate the substrate 10 and contact the back surface metal layer 13.

  As shown in FIG. 5B, the semiconductor light emitting device 1 is formed into a chip. For example, the dicing sheet 63 is attached to the back surface of the substrate 10, and the substrate 10 and the back surface metal layer 13 are cut using a dicing blade. In the dicing region DL, the substrate 10 is exposed and no metal other than the back metal layer 13 is interposed. For example, the back metal layer 13 is a thin layer having a thickness of several tens of nanometers or less. For this reason, dicing becomes easy and defects such as chipping can be suppressed. As a result, the manufacturing yield of the semiconductor light emitting device 1 can be improved.

  Next, with reference to FIGS. 6A to 8C, a method for manufacturing the substrate 10 according to the embodiment will be described. FIG. 6A to FIG. 8C are schematic cross-sectional views sequentially showing the manufacturing process of the substrate 10.

  As shown in FIG. 6A, an insulating layer 101 is formed on the substrate 10, and a resist mask 103 is further formed on the insulating layer 101. The resist mask 103 is formed using, for example, photolithography. The resist mask 103 has an opening 103a from which the insulating layer 101 is exposed. The insulating layer 101 is, for example, a silicon oxide layer.

  As shown in FIG. 6B, the insulating layer 101 is selectively etched using the resist mask 103 to form an opening 101a. Subsequently, as shown in FIG. 6C, the substrate 10 is etched using the insulating layer 101 as a mask to form a recessed portion 10a.

  As shown in FIG. 7A, an insulating layer 105 is formed on the substrate 10 to cover the inner surface of the recess 10a and the upper surface 10c of the substrate 10. The insulating layer 105 is, for example, a silicon oxide layer.

  As shown in FIG. 7B, an opening 105 a is formed in the insulating layer 105. The opening 105a is formed using, for example, photolithography and communicates with the bottom surface of the recess 10a.

  As shown in FIG. 7C, a plurality of trenches 107 are formed in the substrate 10. The trench 107 is formed, for example, by selectively etching the substrate 10 using the insulating layer 105 as a mask. The trench 107 extends downward in the substrate 10 and has a depth of 50 μm to 150 μm, for example. For example, the trench 107 has a width of 10 to 50 μm in a direction parallel to the surface of the substrate 10. The trench 107 is formed so as not to penetrate the substrate 10.

  As shown in FIG. 8A, a metal layer 45 is formed on the substrate 10. The metal layer 45 is formed by using, for example, a sputtering method, and has a structure in which a tantalum nitride layer, a tantalum layer, and a copper layer are sequentially stacked. The metal layer 45 covers the upper surface of the substrate 10, the inner surface of the recess 10 a and the inner surface of the trench 107. The tantalum nitride layer is in contact with the surface of the substrate 10 and covers the entire surface thereof. The copper layer is exposed on the entire surface of the metal layer 45. The tantalum layer is formed between the tantalum nitride layer and the copper layer.

  As shown in FIG. 8B, the metal layer 110 is formed on the metal layer 45. The metal layer 110 is a copper layer formed by using, for example, a plating method. The metal layer 110 is formed so as to cover the entire surface of the metal layer 45 and bury the inside of the metal layer 107.

  As shown in FIG. 8C, the surface of the substrate 10 is planarized. The substrate 10 is planarized using, for example, CMP. The metal layer 110 is polished and removed until the upper surface 10c of the substrate 10 is exposed around the recess 10a. Thereby, the metal body 40 embedded in the substrate 10 is formed. The metal body 40 includes a first portion 41 in which the recess portion 10 a is embedded, and a second portion 43 in which the trench 107 is embedded. Further, the substrate 10 is formed with a flattened surface including the upper surface 10 c and the surface of the first portion 41.

  FIG. 9A and FIG. 9B are schematic plan views showing a metal body 40 provided in the substrate 10. FIGS. 9A and 9B are cross-sectional views taken along line BB shown in FIG. 8C.

  As shown in FIG. 9A, the second portion 43 of the metal body 40 may be formed in a stripe shape extending in the Y direction, for example. The width W1 in the X direction of the second portion 43 is, for example, 10 to 50 μm. Moreover, the space | interval W2 of the adjacent 2nd part 43 is provided narrower than W1, for example.

  As shown in FIG. 9B, the second portion 43 of the metal body 40 may be formed in a pillar shape having a circular cross section and extending in the Z direction, for example. The diameter R1 of the second portion 43 is, for example, 10 to 50 μm. Further, the interval W3 between the adjacent second portions 43 is provided narrower than R1, for example.

  Thus, in this embodiment, the thermal conductivity can be increased by embedding the metal body 40 in the substrate 10. Then, by providing the light emitter 20 on the substrate 10, heat dissipation from the light emitter 20 can be improved.

  Further, the metal layer 30 and the metal body 40 can be bonded at a low temperature, for example, at a normal temperature, and the bonding between the substrate 10 and the light emitting body 20 can be facilitated. In addition, the stress between the substrate 10 and the light emitter 20 can be suppressed, and the bonding strength is increased. Thereby, the reliability of the semiconductor light emitting device 1 can be improved.

  10 to 12 are schematic cross-sectional views showing semiconductor light emitting devices 2, 3 and 4 according to modifications of the embodiment.

  The semiconductor light emitting device 2 shown in FIG. 10 includes a plurality of metal bodies 60 inside the substrate 10. Further, a metal layer 65 provided between the substrate 10 and the metal body 60 is provided. For example, the metal body 60 extends through the insulating layer 47 provided on the surface of the substrate 10 into the substrate 10. The light emitting body 20 is provided on the substrate 10 by bonding the lower surface of the metal layer 30 and the upper surface of the metal body 60 exposed in the insulating layer 47. Further, when the metal layer 30 and the metal body 60 are joined, the insulating layer 35 and the insulating layer 47, and the metal layer 30 and the insulating layer 47 are connected. The metal layer 65 includes, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), or platinum (Pt), and functions as a barrier metal layer. In this example, it is not necessary to form a portion corresponding to the first portion 41 of the metal body 40 in the semiconductor light emitting device 1, and the manufacturing process is simplified compared to the steps shown in FIGS. 7A to 8C. it can.

  The semiconductor light emitting device 3 shown in FIG. 11 has a metal body 70 inside the substrate 10. Further, a metal layer 75 provided between the substrate 10 and the metal body 70 is provided. The metal body 70 is embedded in a recess 10 d provided on the substrate 10. The recess portion 10d is formed deeper than the recess portion 10a described above. The depth of the recess portion 10d is, for example, 100 μm to 150 μm. The light emitter 20 is provided on the substrate 10 by bonding the lower surface of the metal layer 30 and the upper surface of the metal body 70. The metal layer 75 includes, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), or platinum (Pt), and functions as a barrier metal layer. In this example, since the volume of the metal body 70 provided in the substrate 10 can be increased, the heat conduction of the substrate 10 can be further improved.

  In the semiconductor light emitting device 4 shown in FIG. 12, the second portion 43 of the metal body 40 penetrates the substrate 10 and contacts the back surface metal layer 13. The semiconductor light emitting device 4 is formed, for example, by thinning the substrate 10 until the end face 43a of the second portion 43 is exposed on the back surface in the step shown in FIG. In this example, since the metal body 40 is connected to the back surface metal layer 13, the heat conduction of the substrate 10 can be further improved.

In the present specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, 0 ≦ x + y + z ≦ 1) includes a group III-V compound semiconductor, and further includes a mixed crystal containing phosphorus (P), arsenic (As), etc. in addition to N (nitrogen) as a group V element. Furthermore, those having the above composition and further containing various elements added to control various physical properties such as conductivity type, and those further containing various elements included unintentionally, It is included in “nitride semiconductor”.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1, 2, 3, 4... Semiconductor light emitting device 10... Substrate 10 a 10 d recess portion 10 b back surface 10 c 20 a top surface 10 p 20 p 30 p. -Outer edge, 13 ... back metal layer, 20 ... illuminant, 20b ... side, 21 ... n-type semiconductor, 23, 123 ... light-emitting layer, 25 ... p-type semiconductor, 27 ... Passivation film, 27a, 35a, 101a, 103a ... Opening, 30, 31, 45, 65, 75 ... Metal layer, 35, 47, 101, 105, 105a ... Insulating layer, 40, 60, 70, 110 ... metal body, 41 ... first part, 43 ... second part, 43a ... end face, 51 ... p-side electrode, 53 ... n-side electrode, 55 ... bonding pads, 61 ... adhesive Sheet, 63 ... Dicing sheet, 100 ... Substrate, 103 ... Resist mask, 107 ... Trench, 121 ... n-type semiconductor layer, 125 ... p-type semiconductor layer, DL ... Dicing area

Claims (6)

A substrate,
A light emission provided on the substrate and including a first semiconductor of a first conductivity type, a second semiconductor of a second conductivity type, and a light emitting layer provided between the first semiconductor and the second semiconductor. Body,
A metal layer provided between the substrate and the light emitter and electrically connected to either the first semiconductor or the second semiconductor;
A metal body embedded in the substrate below the light emitter and connected to the metal layer;
A semiconductor light emitting device comprising:   2. The semiconductor light emitting device according to claim 1, wherein the metal body has a first portion embedded in a recess provided in the substrate, and a second portion extending from the first portion into the substrate.   The semiconductor light emitting device according to claim 1, wherein the metal body extends in the substrate in a direction from the light emitter toward the substrate.   The semiconductor light-emitting device according to claim 1, further comprising a plurality of the metal bodies extending in a direction from the light-emitting body toward the substrate in the substrate.   5. The semiconductor light emitting device according to claim 1, wherein an outer edge of the metal layer is positioned inside the outer edge of the substrate in a direction parallel to the substrate surface.   The semiconductor light-emitting device according to claim 1, wherein the metal body has an end surface that penetrates the substrate and is exposed on a surface of the substrate opposite to the metal layer.

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