JP2017049814A - Information processing apparatus and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing apparatus and an image forming apparatus that improve efficiency of use of a cache memory that is shared by a plurality of cores.SOLUTION: An image forming apparatus 1 comprises: a CPU 10 that includes a core 101, core 102, and core 103, which respectively execute different types of processing in parallel; a cache memory 121 that is shared by the core 101 and core 102; and a cache memory 122 that is used at least by the core 103. When determining a destination to allocate new processing while the core 101 executes preceding processing, the image forming apparatus determines a core to be the destination to allocate the new processing on the basis of the usage of the cache memory when the new processing is executed.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an information processing apparatus and an image forming apparatus.

  An information processing apparatus using a multi-core processor is known. In such an information processing apparatus, the problem of how to allocate processing (tasks and threads) to each core is one of the major technical issues. Patent Document 1 discloses a technique for assigning a task to a core that uses the same cache memory as the previously used core when assigning a core to a task similar to a task that has been once completed in order to improve the hit rate of the cache. Yes. Patent Document 2 discloses a technique for grouping processors that use the same cache memory and allocating threads to a plurality of processors in the group.

JP-A-6-96039 JP 11-259318 A

  When a process that uses a large amount of cache memory is assigned to two cores that use the same cache memory, these two cores overwrite each other, and the processor cannot exhibit its performance. It was.

  The present invention provides a technique for improving the use efficiency of a cache memory shared by a plurality of cores.

  The present invention includes a first core, a second core, and a third core, each of a plurality of cores that execute different processes in parallel, and a first cache memory that is shared by the first core and the second core, When determining the allocation destination of the second process when at least the second cache memory used in the third core and the first core are executing the first process, the second process is executed. An information processing apparatus is provided that includes a determination unit that determines a core to be assigned to the second process based on a cache memory usage amount.

  If the sum of the amount of cache memory used when executing the second process and the amount of cache memory used when executing the first process is greater than the free capacity of the first cache memory, the determining means The second process may be assigned to the core.

  When the sum of the amount of cache memory used when executing the second process and the amount of cache memory used when executing the first process is smaller than the free capacity of the first cache memory, the determining means You may assign the said 2nd process to a core with a low load among cores.

  If the sum of the amount of cache memory used when executing the second process and the amount of cache memory used when executing the first process is smaller than the free capacity of the first cache memory, the determining means The second process may be assigned to the core or the second core.

  The information processing apparatus includes a determination unit that determines whether or not the relevance between the first process and the second process is higher than a reference. When the relevance is determined to be higher than the reference, the determination unit includes: The second process may be assigned to the first core or the second core.

  When it is determined that the relevance is lower than the reference, the determining unit determines a core to which the second process is assigned based on a cache memory usage amount when the second process is executed. Also good.

  The determination unit may determine whether the relevance of the first process and the second process is higher than the reference based on at least one of an instruction type and a program that issued the instruction.

  The information processing apparatus includes a prediction unit that predicts a cache memory usage amount when the second process is executed, and the determination unit is configured to perform the first processing based on the cache memory usage amount predicted by the prediction unit. You may determine the core which becomes the allocation destination of 2 processes.

  The information processing apparatus includes a storage unit that stores a table in which attributes related to instructions and cache memory usage are associated with each other, and the prediction unit refers to the table stored in the storage unit and uses the cache memory The amount may be predicted.

  The first process and the second process are instructions relating to image formation, and the table may include at least one of a size of a medium on which the image is formed and a resolution of the image as attributes relating to the instruction. .

  The present invention also includes a first core, a second core, and a third core, each of a plurality of cores that execute different processes in parallel, a first cache memory shared by the first core and the second core, In addition, when the processing means including at least the second cache memory used in the third core and the first core are executing the first process relating to image formation, the assignment destination of the second process relating to image formation is determined. At this time, based on the cache memory usage amount when executing the second process, a determination unit that determines a core to which the second process is allocated, and an image is formed according to the instruction processed by the processing unit An image forming apparatus is provided.

According to the information processing apparatus of the first aspect, the usage efficiency of the first cache memory can be improved.
According to the information processing apparatus of the second aspect, the usage efficiency of the first cache memory can be improved as compared with the case where the second process is assigned to the first core or the second core.
According to the information processing apparatus of the third aspect, when the cache memory usage does not become a problem, the processing can be assigned to the core having a low load.
According to the information processing apparatus of the fourth aspect, the usage efficiency of the first cache memory can be further improved as compared with the case where processing is simply assigned to a core having a low load.
According to the information processing apparatus according to claim 5, the use efficiency of the first cache memory can be further improved as compared with the case where the core allocation is determined regardless of the relationship between the first process and the second process. Can do.
According to the information processing apparatus according to claim 6, the use efficiency of the first cache memory is further improved as compared with the case where only the cache memory use amount is considered regardless of the relationship between the first process and the second process. can do.
According to the information processing apparatus of the seventh aspect, the relevance can be determined according to the type of the instruction and the program that issued the instruction.
According to the information processing apparatus of the eighth aspect, the load can be further reduced as compared with the case where the cache memory usage is actually measured.
According to the information processing apparatus of the ninth aspect, it is possible to predict the cache memory usage more easily than when the cache memory usage is predicted without using a table.
According to the information processing apparatus of the tenth aspect, it is possible to predict the cache memory usage amount according to the parameter relating to image formation.
According to the image forming apparatus of the eleventh aspect, the usage efficiency of the first cache memory can be improved.

The figure which illustrates the composition of information processor 9 concerning related technology 1 is a diagram illustrating a hardware configuration of an image forming apparatus 1 according to an embodiment. The figure which illustrates the software configuration of the image forming apparatus 1 Flowchart showing operation of image forming apparatus 1 The figure which illustrates the processing management table concerning operation example 1 Diagram illustrating usage amount prediction table The figure which illustrates the processing management table concerning operation example 2

1. Overview FIG. 1 is a diagram illustrating a configuration of an information processing apparatus 9 according to related technology. The information processing apparatus 9 includes a CPU (Central Processing Unit) 90. The CPU 90 has a plurality of cores, in this example, four cores 901 to 904. Here, the “core” of the processor refers to a portion of the processor that executes instructions and performs operations. The CPU 90 further includes cache memories 911 to 914 and cache memories 921 to 922. The cache memories 911 to 914 are primary caches (so-called L1 caches) and are dedicated to the cores 901 to 904, respectively. The cache memories 921 and 922 are secondary caches (so-called L2 caches). The cache memory 921 is shared by the cores 901 and 902, and the cache memory 922 is shared by the cores 903 and 904. In general, the L1 cache may be included and referred to as “core”, but here the “core” does not include the L1 cache.

  The primary cache is a cache memory that is accessed with the highest priority from the core, and the secondary cache is a cache memory that is accessed with the next priority of the primary cache. The primary cache is faster and has a smaller capacity than the secondary cache. When an access request to the main memory (external memory) occurs, the core first checks whether the data at the access destination address is stored in the primary cache. When data at an access destination address (hereinafter simply referred to as “access destination data”) is stored in the primary cache, the core reads data from the primary cache. The fact that the access destination data is stored in the cache memory is called “hit”, and the rate at which hits occur is called “hit rate”. If the access destination data is not stored in the primary cache, the core checks whether the access destination data is stored in the secondary cache. When the access destination data is stored in the secondary cache, the core reads the data from the secondary cache. If the access destination data is not stored in the secondary cache, the core reads the data from the main memory.

  The CPU 90 is a so-called SMP (Symmetric Multi Processing) type processor, and the functions of the cores are the same. In addition to the multi-core type processors, there are also AMP (Asymmetric Multi Processing) type processors. For example, there are many tasks to be processed like a so-called multi-function machine, and printing, scanning, facsimile transmission / reception, UI In a device having many combinations of processes such as processes and network processes, an SMP type processor is generally used. For example, when performing data processing on the premise of continuous operation by pipeline, such as image processing, if the cache hit rate decreases, the core wait time due to access to the main memory occurs and the performance of the processor decreases. End up. Therefore, which process is assigned to which core is a problem that affects the performance of the processor.

  In particular, if the allocation of processing with a large amount of cache memory usage (hereinafter referred to as “cache usage”) to the core is not appropriate, the usage efficiency of the cache memory decreases, and as a result, the processor cannot fully perform. .

  This will be described using a more specific example. In this example, the capacities of the cache memories 921 and 922 (L2 cache) are each 512 kB. The core 901 is executing a copy process. The cache usage amount in the copy process is 384 kB. That is, 384 kB of the cache memory 921 is used for copy processing. Consider an example in which a new print process is assigned in this situation. The cache usage in the print process is 256 kB.

  In this example, newly generated processing is assigned to a core having a low load (usage rate). For example, if the print processing is assigned to the core 902 when the load on the core 902 is low, the total amount of cache used by the copy processing and print processing is 384 kB + 256 kB = 640 kB, which exceeds the capacity of the cache memory 921. In this case, the copy process and the print process overwrite each other in the cache memory 921, and the processor cannot exhibit sufficient performance. The present embodiment addresses such a problem.

2. Configuration FIG. 2 is a diagram illustrating a configuration of the image forming apparatus 1 according to an embodiment. The image forming apparatus 1 is an example of an information processing apparatus having a function of forming an image, and is a so-called multifunction machine, for example. The image forming apparatus 1 includes a CPU 10, a memory controller 20, a main storage device (main memory) 30, an IO controller 40, an auxiliary storage device 41, an image reading unit 42, an image forming unit 43, and a communication unit 44.

  The CPU 10 is a control device that controls each unit of the image forming apparatus 1 and is an example of a processing unit including a plurality of cores that execute different processes. The CPU 10 includes cores 101 to 104, cache memories 111 to 114, and cache memories 121 to 122. The cache memories 111 to 114 are primary caches (L1 caches) and are dedicated to the cores 101 to 104, respectively. The cache memories 121 to 122 are secondary caches (L2 caches). The cache memory 121 is shared by the cores 101 and 102, and the cache memory 122 is shared by the cores 103 and 104.

  The memory controller 20 controls reading and writing of data with respect to the main storage device 30. The main storage device 30 is a main storage device, and includes, for example, a DRAM (Dynamic Random Access Memory). The main storage device 30 functions as a work area when the CPU 10 executes a program and is an example of a storage unit that stores various data.

  The IO controller 40 is a device that controls peripheral devices connected to the CPU 10. In this example, an auxiliary storage device 41, an image reading unit 42, an image forming unit 43, and a communication unit 44 are connected to the IO controller 40. The auxiliary storage device 41 is a non-volatile storage device that stores data and programs, and includes, for example, an HDD (Hard Disk Drive). The image reading unit 42 is a device that optically reads a document, and includes, for example, a so-called scanner. The image forming unit 43 is an apparatus that forms an image on a medium (for example, paper), and performs image formation by, for example, an electrophotographic technique or an ink jet technique. The communication unit 44 is an interface that communicates with other devices.

  FIG. 3 is a diagram illustrating a software configuration of the image forming apparatus 1. The auxiliary storage device 41 implements a program (hereinafter referred to as “OS program”) for causing an OS (Operating System) of the image forming apparatus 1 to function and various applications (copy function, scanner function, facsimile transmission / reception function, etc.). A program (hereinafter referred to as “application program”) is stored. When the CPU 10 executes these programs, the OS 50 and the applications 61 to 63 are installed in the image forming apparatus 1.

  Each of the applications 61 to 63 instructs the OS 50 to execute processing. That is, processing is requested. The processing here refers to processing using hardware resources of the image forming apparatus 1, specifically, for example, processing to read an image from a document using the image reading unit 42, and processing to a medium using the image forming unit 43. Processing that forms an image and processing that performs facsimile transmission using the communication unit 44. The OS 50 assigns the process requested by the application to any one of the plurality of cores. The cores 101 to 104 are recognized as independent CPUs by the OS 50 (referred to as CPUs 1 to 4 in the following drawings).

  When a request for a new process occurs in the application, the OS 50 determines which core is to execute the process. Details are as follows. The OS 50 includes a detection unit 51, a determination unit 52, a prediction unit 53, and a determination unit 54.

  The detection unit 51 detects a process newly requested by the applications 61 to 63. Now, when a process in the core 101 (hereinafter referred to as “first process”) has already been assigned and the core 101 is executing the first process, the detection means 51 performs a new process (hereinafter “ Consider an example in which a request for “second processing” is detected. The OS 50 determines a core to which the second process is assigned, that is, a core that executes the second process.

  The determination unit 52 determines whether the relevance between the first process and the second process is higher than the reference. When it is determined that the relevance between the first process and the second process is higher than the reference, the determination unit 54 assigns the second process to the core sharing the core 101 and the L2 cache (that is, the core 101 or the core 102).

  When it is determined that the relevance between the first process and the second process is low, the prediction unit 53 predicts the cache memory usage amount when executing the second process. Based on the cache memory usage predicted by the prediction unit 53, the determination unit 54 determines the core to be assigned to the second process. Specifically, when the sum of the amount of cache memory used when executing the second process and the amount of cache memory used when executing the first process is larger than the free capacity of the cache memory 121 (an example of the first cache memory) The determination unit 54 assigns the second process to the core 103 (an example of a third core). When the sum of the cache memory usage amount when executing the second process and the cache memory usage amount when executing the first process is smaller than the free capacity of the cache memory 121, the determining means 54 The second process is assigned to a core with a low load.

3. Operation FIG. 4 is a flowchart showing the operation of the image forming apparatus 1. The flow in FIG. 3 starts when a request for a new process (hereinafter referred to as “new process”, an example of a second process) is detected. In the following description, software such as the OS 50 may be described as the subject of processing, which means that the CPU 10 executing the software executes processing in cooperation with other hardware resources. .

  In step S101, the OS 50 determines whether the new process uses a cache memory. Whether the cache memory is used is determined for each process, for example. More specifically, the main storage device 30 stores a table (not shown) in which processing is associated with whether or not the cache memory is used, and the OS 50 refers to this table and uses the cache memory for new processing. It is judged whether it is what to do. When it is determined that the new process uses the cache memory (S101: YES), the OS 50 shifts the process to step S102. When it is determined that the new process does not use the cache memory (S101: NO), the OS 50 shifts the process to step S111.

  In step S <b> 102, the OS 50 determines whether there is a process (hereinafter referred to as “preceding process”, which is an example of a first process) already executed by any one of the plurality of cores. The presence / absence of the preceding process is determined using the process management table.

  FIG. 5 is a diagram illustrating a process management table. The process management table includes a user ID, a process ID, a related process ID, a process, a cache usage, and a core record related to the process being executed. The “user ID” is an identifier that identifies a subject that uses the core, that is, an application in this example. “Process ID” is an identifier for uniquely specifying a process. The “related process ID” is a process ID of a process that is highly related to the process. “Processing type” indicates the type of the process. In this example, “copy” and “print” are described as processing types. “Cache usage” indicates the usage of the L2 cache by the processing. “Core” indicates a core to which the process is assigned (execution of the process).

  In the process management table, a record relating to the process currently being executed is recorded. If any record is recorded in the process management table, this means that there is a preceding process. If the process management table is empty and nothing is recorded, there is no preceding process. The process management table is stored in the main storage device 30. The OS 50 refers to the process management table stored in the main storage device 30 and determines whether there is a preceding process.

  Refer to FIG. 4 again. When it is determined that there is a preceding process (S102: YES), the OS 50 shifts the process to step S103. When it is determined that there is no preceding process (S102: NO), the OS 50 shifts the process to step S111.

  In step S103, the OS 50 determines whether there is a preceding process of the same type as the new process. The OS 50 refers to the process management table stored in the main storage device 30 and determines whether there is a preceding process of the same type as the new process. When it is determined that there is a preceding process of the same type as the new process (S103: YES), the OS 50 shifts the process to step S104. If it is determined that there is no preceding process of the same type as the new process (S103: NO), the OS 50 shifts the process to step S108.

  In step S104, the OS 50 determines whether there is a preceding process by the same user (that is, the same application) as the new process. The OS 50 refers to the process management table stored in the main storage device 30 to determine whether there is a preceding process by the same user as the new process. When it is determined that there is a preceding process by the same user as the new process (S104: YES), the OS 50 shifts the process to step S105. When it is determined that there is no preceding process by the same user as the new process (S104: NO), the OS 50 shifts the process to step S108.

  In step S105, the OS 50 registers a record of “related process ID” related to the new process in the process management table. In this example, the preceding process having the same process type and user ID as the new process is determined to be a preceding process having high relevance to the new process, and the process ID of the preceding process is registered as the associated process ID for the new process.

  At this point, since the new process record has not been registered in the process management table, the OS 50 registers the new process record in the process management table. Here, first, a user ID, a process ID, a process type, and a cache usage amount are registered. Since the cache usage is difficult to record the actual measurement value at the stage where the processing has not yet started, the predicted value is recorded.

  FIG. 6 is a diagram illustrating a usage amount prediction table for obtaining a cache usage amount prediction value. The usage amount prediction table is stored in the main storage device 30, and the OS 50 refers to the usage amount prediction table stored in the main storage device 30 to obtain a predicted value of the cache usage amount. In the usage amount prediction table, parameters used for processing are associated with predicted values of cache usage. FIG. 6 shows, as an example, a predicted value of cache usage related to print processing. In this example, “paper size”, “resolution”, and “mode” are used as parameters used in the printing process. “Paper size” indicates the size of the medium on which the image is formed. The larger the medium, the more the cache usage tends to increase. “Resolution” indicates the resolution of an image to be formed. The higher the resolution, the more the cache usage tends to increase. “Mode” indicates the type of image to be formed. Depending on the type of image to be formed, for example, different image processing is performed. In this example, the “mode” is “text” or “photo”. “Photos” use more cash than “Text”.

  With reference to FIG. 5, registration of a “related process ID” for a new process will be described. For example, consider a situation in which “print” processing is requested by the application with the user ID “002” when the processing with the processing IDs “100” and “101” is being executed. That is, in the table of FIG. 5, the process IDs “100” and “101” are the preceding processes, and the process ID “102” is the new process. At this time, the process with the process ID “101” in the preceding process has the same user ID and process type as the new process. Therefore, it is determined that the new process is highly related to the process with the process ID “101”, and “101” is recorded in the record of the related process ID corresponding to the process ID “102”.

  Refer to FIG. 4 again. In step S106, the OS 50 assigns a process to the core that shares the L2 cache with the preceding process. For example, in the table of FIG. 5, the process with process IDs “100” and “101” is the preceding process, and the process with process ID “102” is the new process, the preceding process is executed. A new process is assigned to the CPU 3 or the CPU 4 (core 103 or core 104) that is the core sharing the L2 cache with the CPU 3 (core 103) that is the core. Which of the CPU 3 and the CPU 4 is assigned a process is determined according to, for example, the core load. That is, the OS 50 assigns a new process to the core with the lowest load. When the core assignment is determined, the OS 50 registers the core record in the process management table.

  In step S107, the core to which the process is assigned starts executing a new process. When the process is started, the flow of FIG. 4 ends.

  In step S108, the OS 50 registers a new process record in the process management table. In this case, the “related process ID” for the new process is not registered and remains a null value.

  In step S109, the OS 50 determines whether there is a core with sufficient free space in the L2 cache. Specifically, the OS 50 determines, for each L2 cache, whether the sum of the cache usage of the preceding process and the cache usage of the new process is less than the capacity of the L2 cache. The cache usage amounts of the preceding process and the new process are predicted using the usage amount prediction table. If this sum is less than the capacity of the L2 cache, the OPS 50 determines that the free capacity of the L2 cache is sufficient. When it is determined that there is a core with sufficient free space in the L2 cache (S109: YES), the OS 50 shifts the processing to step S110. When it is determined that there is no core having sufficient free space in the L2 cache (S109: NO), the OS 50 shifts the processing to step S112.

  In step S110, the OS 50 assigns the process to a core that does not share the L2 cache with the preceding process. In this case, the sum of the cache usage of the preceding process and the cache usage of the new process is less than or equal to the capacity of the L2 cache. Never meet. When the core assignment is determined, the OS 50 registers the core record in the process management table. When registration in the table is completed, the OS 50 shifts the processing to step S107.

When there are a plurality of cores with sufficient free capacity in the L2 cache, the OS 50 assigns a new process to one core selected based on any of the following criteria, for example.
(1) Core with the least free space in the L2 cache (2) Core with the lowest load (3) Core executing a predecessor with higher relevance (4) Core criteria determined in advance for each processing type ( According to 1), an L2 cache having a larger free space is secured for processing that will be requested in the future. According to criterion (2), the load is distributed. According to the criterion (3), the possibility of improving the cache hit rate is increased. According to criterion (4), the processing load for selecting a core is reduced. The preceding process having higher relevance means a preceding process having the same process type or user ID as the new process.

  In step S111, the OS 50 registers a new process record in the process management table. In this case, the “related process ID” for the new process is not registered and remains a null value.

  In step S112, the OS 50 determines a core to which a new process is allocated according to the core load. That is, the OS 50 assigns a new process to the core with the lowest load. When the core assignment is determined, the OS 50 registers the core record in the process management table. When registration in the table is completed, the OS 50 shifts the processing to step S107.

  A more detailed operation example (operation example 1) will be described with reference to FIG. The operation example 1 is an example in which a plurality of processes with different types are executed. Specifically, an example in which an application with a user ID “001” requests a copy process and an application with a user ID “002” requests a print process. In this example, the younger process ID is the process requested earlier.

(1) Operation example 1-1
New processing: 101
Pre-processing: 100
Since the process types of the preceding process and the new process are different, the new process is assigned to the core with the lowest load among the cores with sufficient free space. In this example, the load on the CPU 3 (core 103) is the lowest. New processing is assigned to the CPU 3.

(2) Operation example 1-2
New processing: 102
Pre-processing: 100, 101
Among the preceding processes, the process ID “101” has the same user ID and process type as the new process. Therefore, “101” is registered as the related process ID, and the CPU 3 or the CPU 4 (core 103 or core 104) sharing the L2 cache with the CPU 3 is the allocation candidate. Of these, new processing is assigned to the core with the lowest load. In this example, the load on the CPU 4 (core 104) is the lowest. New processing is assigned to the CPU 4.

(3) Operation example 1-3
New processing: 103
Pre-processing: 100, 101, 102
Among the preceding processes, the process ID “100” has the same user ID and process type as the new process. Therefore, “100” is registered as the related process ID, and CPU1 or CPU2 (core 101 or core 102) sharing the L2 cache with CPU1 is the candidate for assignment destination. Of these, new processing is assigned to the core with the lowest load. In this example, the load on the CPU 2 (core 102) is the lowest. New processing is assigned to the CPU 2.

  For example, in the case of the same processing by the same user, there is a high possibility that the data used is common. Therefore, the L2 cache assigns these processes to a common core, thereby increasing the possibility of improving the cache hit rate.

  FIG. 6 is a diagram illustrating a process management table according to the second operation example. The operation example 2 is an example in which a plurality of processes having the same type are executed. Specifically, an example is shown in which an application with a user ID “001” requests print processing of a page, and an application with a user ID “002” requests print processing of another page. In this example, the younger process ID is the process requested earlier.

(1) Operation example 2-1
New processing: 101
Pre-processing: 100
Since the process types of the preceding process and the new process are different, the new process is assigned to the core with the lowest load among the cores with sufficient free space. In this example, the load on the CPU 3 (core 103) is the lowest. New processing is assigned to the CPU 3.

(2) Operation example 2-2
New processing: 102
Pre-processing: 100, 101
Among the preceding processes, the process ID “101” has the same user ID and process type as the new process. Therefore, “101” is registered as the related process ID, and the CPU 3 or the CPU 4 (core 103 or core 104) sharing the L2 cache with the CPU 3 is the allocation candidate. Of these, new processing is assigned to the core with the lowest load. In this example, the load on the CPU 4 (core 104) is the lowest. New processing is assigned to the CPU 4.

(3) Operation example 2-3
New processing: 103
Pre-processing: 100, 101, 102
Among the preceding processes, the process ID “100” has the same user ID and process type as the new process. Therefore, “100” is registered as the related process ID, and CPU1 or CPU2 (core 101 or core 102) sharing the L2 cache with CPU1 is the candidate for assignment destination. Of these, new processing is assigned to the core with the lowest load. In this example, the load on the CPU 2 (core 102) is the lowest. New processing is assigned to the CPU 2.

  For example, when printing images of the same page, there is a high possibility that the data used is common. Therefore, the L2 cache assigns these processes to a common core, thereby increasing the possibility of improving the cache hit rate.

4). Modifications The present invention is not limited to the above-described embodiments, and various modifications can be made. Hereinafter, some modifications will be described. Two or more of the following modifications may be used in combination.

  The configuration of the CPU 10 is not limited to that illustrated in FIG. The number of cores and the hierarchical structure of the cache memory are merely examples. The CPU 10 may have at least two cores sharing the first cache memory and at least one core using a second cache memory different from the first cache memory. The first cache memory may be shared by three or more cores. Further, the CPU 10 may have an L3 cache below the L2 cache.

  Further, the CPU 10 is not limited to one in which a plurality of cores and a cache memory are physically mounted on one chip. The present invention may be applied to an information processing apparatus in which a plurality of CPU chips share one cache memory.

  Furthermore, the “plurality of cores” in the embodiments is not limited to a plurality of physically different cores. One physical core may be used as a plurality of cores in a logical (pseudo) manner in a time division manner.

  The information processing apparatus according to the present invention is not limited to the image forming apparatus 1 illustrated in FIG. As long as a plurality of processes are executed in parallel using the CPU 10, the information processing apparatus may be any apparatus. For example, the information processing apparatus may be a personal computer, a smartphone, or a tablet terminal.

  The software configuration of the information processing apparatus is not limited to that illustrated in FIG. The sharing of functions by the OS and application is merely an example. The information processing apparatus only needs to have a software component that generates a process and a software component that determines a core that executes the generated process.

  The operation of the information processing apparatus is not limited to that illustrated in FIG. For example, the core assignment in step S112 is not limited to the assignment according to the core load. A new process may be assigned to a core having the smallest free space in the L2 cache, a core that is executing a prior process with higher relevance, or a core that is predetermined for each process type.

  The method for evaluating the relationship between the preceding process and the new process is not limited to the one exemplified in the embodiment. In the embodiment, the relevance is evaluated based on whether the processing type and the user ID are the same, but other criteria may be used.

  The method for obtaining the cache usage is not limited to the one exemplified in the embodiment. For example, each application may notify the cache usage when requesting processing from the OS 50. The OS 50 determines whether there is sufficient free space in the L2 cache using the cache usage amount notified from the application.

  The cache memory that is the target of determining whether there is sufficient free space is not limited to the L2 cache. Any level of cache memory can be used as long as it is shared by a plurality of cores.

  Further, the CPU 10 is not limited to one in which a plurality of cores and a cache memory are physically mounted on one chip. The present invention may be applied to an information processing apparatus in which a plurality of CPU chips share one cache memory.

DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 9 ... Information processing apparatus, 10 ... CPU, 20 ... Memory controller, 30 ... Main storage device, 40 ... IO controller, 41 ... Auxiliary storage device, 42 ... Image reading unit, 43 ... Image forming unit, 44 ... Communication unit, 50 ... OS, 51 ... Detection means, 52 ... Judgment means, 53 ... Prediction means, 54 ... Determination means, 61-63 ... Application, 90 ... CPU, 101-104 ... Core, 111-114 ... Cache Memory (L1), 121-122 ... Cache memory (L2), 901-904 ... Core, 911-914 ... Cache memory (L1), 921-922 ... Cache memory (L2)

Claims (11)

A plurality of cores including a first core, a second core, and a third core, each executing different processes in parallel;
A first cache memory shared by the first core and the second core;
A second cache memory used in at least the third core;
In the case where the first core is executing the first process, when determining the allocation destination of the second process, the allocation of the second process is based on the cache memory usage amount when executing the second process. An information processing apparatus comprising: a determining unit that determines a core that is a destination. If the sum of the amount of cache memory used when executing the second process and the amount of cache memory used when executing the first process is greater than the free capacity of the first cache memory, the determining means The information processing apparatus according to claim 1, wherein the second process is assigned to a core. When the sum of the amount of cache memory used when executing the second process and the amount of cache memory used when executing the first process is smaller than the free capacity of the first cache memory, the determining means The information processing apparatus according to claim 2, wherein the second process is assigned to a core having a low load among the cores. If the sum of the amount of cache memory used when executing the second process and the amount of cache memory used when executing the first process is smaller than the free capacity of the first cache memory, the determining means The information processing apparatus according to claim 3, wherein the second process is assigned to a core or the second core. Determining means for determining whether the relevance of the first process and the second process is higher than a reference;
The determination means allocates the second process to the first core or the second core when the relevance is determined to be higher than the reference. 5. The information processing apparatus described in 1. When it is determined that the relevance is lower than the reference, the determining unit determines a core to which the second process is allocated based on a cache memory usage amount when the second process is executed. The information processing apparatus according to claim 5. The determination means determines whether the relevance of the first process and the second process is higher than the reference based on at least one of an instruction type and a program that issued the instruction. 6. The information processing apparatus according to 6. Predicting means for predicting the amount of cache memory used when executing the second process;
The information processing apparatus according to claim 7, wherein the determination unit determines a core to be assigned to the second process based on the cache memory usage predicted by the prediction unit. Storage means for storing a table in which attributes relating to instructions and cache memory usage are associated with each other;
The information processing apparatus according to claim 8, wherein the prediction unit predicts the cache memory usage with reference to a table stored in the storage unit. The first process and the second process are instructions related to image formation,
The information processing apparatus according to claim 9, wherein the table includes at least one of a size of a medium on which the image is formed and a resolution of the image as an attribute related to the command. A plurality of cores including a first core, a second core, and a third core, each executing different processes in parallel, a first cache memory shared by the first core and the second core, and at least the third core Processing means including a second cache memory used in
When the first core is executing the first process related to image formation, when determining the allocation destination of the second process related to image formation, based on the cache memory usage amount when executing the second process, Determining means for determining a core to be assigned to the second process;
An image forming apparatus comprising: an image forming unit that forms an image according to a command processed by the processing unit.

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