JP2014153931A - Processor system, electronic apparatus, and system control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor system capable of effectively utilizing resources by distributing the operation load in accordance with a use state of the system, an electronic apparatus, and a system control program.SOLUTION: A processor system 500 includes a plurality of processor cores. The processor system 500 includes: storage means 501 in which information which is set to each of a plurality of programs and shows whether a processor core for execution should be fixed or not is stored; first determination means 502 which determines, on the basis of the information, whether a processor core should be fixed to each of one or more programs to be executed or not; measurement means 503 which measures an execution frequency of each program; and second determination means 504 which determines whether a processor core set for a program to which fixing of the processor core is determined by the first determination means 502 should be fixed to this program or not on the basis of the measured execution frequency of the program.

Description

  The present invention relates to a processor system having a plurality of processor cores, an electronic apparatus equipped with the processor system, and a system control program executed in the processor system.

  In order to distribute a plurality of processes and increase the speed of the entire process, a processor system having a plurality of processor cores is employed. There are two types of operation of this processor system, SMP (Symmetrical Multi Processing) and AMP (Asymmetrical Multi Processing).

  SMP is a method of performing parallel processing by dynamically distributing a plurality of programs so that loads of a plurality of processor cores are uniform. On the other hand, AMP is a method in which a specific program is executed by a predetermined processor core regardless of the load. In this AMP, since a specific program is allocated to a specific processor core, real-time performance of the program can be guaranteed. Here, having real-time property means that processing by a program can be completed within a certain time.

  An embedded device or the like that is incorporated to realize a specific function has a problem that when a processor core is changed during operation by SMP, a cache cannot be effectively used when a program that requires precise operation timing is used. It was. There is also a problem that real-time performance cannot be guaranteed by this change. On the other hand, in AMP, such a problem does not occur, but since the processing is concentrated on a specific processor core, there is a problem that the load is biased.

  Therefore, a technique has been proposed in which SMP and AMP are mixed to guarantee a real-time property, and the processor cores operating as AMPs are sequentially changed to prevent the load from being concentrated on a specific processor core (see Patent Document 1). ). In this technique, a processor core used as an AMP and a processor core used as an SMP are fixedly allocated at startup.

  In the above technique, depending on the system usage status, processor cores distributed as AMP may be vacant, or conversely, loads may be concentrated. In this case, it is not possible to prevent the load from being concentrated on a specific processor core, to effectively use resources, and to improve the execution efficiency of the program.

  In view of the above problems, the present invention is a processor system including a plurality of processor cores, and stores information indicating whether to fix a processor core to be executed, which is set for each of a plurality of programs. Means, first determination means for determining whether to fix the processor core to each of the one or more programs started, measurement means for measuring the execution frequency of each program, A second determination unit that determines, based on the measured execution frequency, whether or not the program determined to fix the processor core by the determination unit should be fixed to the processor core set for the program. A system is provided.

  According to the present invention, it is possible to dynamically distribute the load according to the usage status of the system, to effectively use resources, and to improve the execution efficiency of the program.

1 is a diagram illustrating a hardware configuration of an image forming apparatus according to an embodiment. FIG. 2 is a diagram illustrating an example of an internal configuration of a CPU provided in the image forming apparatus illustrated in FIG. 1. FIG. 2 is a diagram illustrating a software configuration of the image forming apparatus illustrated in FIG. 1. The figure which illustrated the execution image at the time of CPU shown in FIG. 2 executing a some program. The functional block diagram of the processor system of this embodiment. The figure which illustrated the table as information memorized by the storage means with which the processor system shown in Drawing 5 is provided. 6 is a flowchart illustrating the flow of processing executed by the processor system shown in FIG. 5. The figure which showed another example of the table memorize | stored in a memory | storage means. The figure which showed another example of the table memorize | stored in a memory | storage means.

  FIG. 1 is a diagram illustrating a hardware configuration of the image forming apparatus according to the present exemplary embodiment. The image forming apparatus shown in FIG. 1 includes a processor system having a plurality of processor cores, and is configured to execute a plurality of programs in parallel. Here, an image forming apparatus is exemplified as an apparatus on which the processor system is mounted. However, the image forming apparatus is not limited to the image forming apparatus, and any electronic device may be used.

  Examples of the electronic device include a PC, a scanner device, a copier, a fax device, a digital video camera, a digital camera, a game machine, a PDA (Personal Digital Assistant), a smartphone, and a tablet terminal. Examples of the image forming apparatus include a printer and an MFP (Multi Function Peripheral). The printer may be a laser printer or an ink jet printer. Hereinafter, the image forming apparatus will be described in detail as an MFP.

  The MFP 100 includes a controller board 101 as a control unit and an image forming unit 110 that performs image formation. The controller board 101 includes a CPU 102, a ROM 103, a RAM 104, an image processing unit 105, an operation unit 106, an HDD 107, an FCU (Facsimile Control Unit) 108, and a network control unit 109. The image forming unit 110 includes a plotter 111 that executes printing and a scanner 112 that reads an image such as a document.

  The CPU 102 controls the operation of the image forming apparatus 100 by executing an OS, various programs, and the like. The ROM 103 is a non-volatile memory in which a program executed by the CPU 102 is stored. The RAM 104 is a volatile memory used as a work area for the CPU 102. The CPU 102 expands the program read from the ROM 103 or the like on the RAM 104, and executes the expanded program.

  The image processing unit 105 generates image data that has been subjected to drawing processing to be transferred to the image forming unit 110, and performs processing such as correction and compression on the read image data. The operation unit 106 includes an operation panel, receives input of operation information from the user, and displays information to the user. The HDD 107 stores various data sent from the image forming unit 110. The FCU 108 controls facsimile transmission and reception. The network control unit 109 is connected to a network 120 such as a LAN or the Internet, and communicates with an external device 121 connected to the network 120. In addition, the controller board 101 may include a USB interface, an SD card slot, and the like.

  The plotter 111 receives the image data output from the image processing unit 105 of the controller board 101, and prints out an image based on the image data. If the plotter 111 is an electrophotographic system, the plotter 111 includes a photosensitive drum, a charging unit, an exposure device, a developing unit, a transfer unit, a fixing unit, a cleaning unit, a static elimination unit, and the like. Each of these units is well known and will not be described in detail.

  The scanner 112 reads an image recorded on a medium such as paper, generates image data of the read image, and outputs the image data to the controller board 101. The scanner 112 includes a light source such as a fluorescent lamp or an LED, a photoelectric conversion element such as a CCD image sensor or a CMOS image sensor, and the like.

  The external device 121 is a PC or the like, sends a print instruction to the MFP 100, and controls the MFP 100. For example, the external device 121 can convert a document or the like created by the user into a print command that can be interpreted by the MFP 100, and transmit the print command to the MFP 100. Further, the external device 121 can acquire image data of an image read by the MFP 100 and store it in a storage device provided in the external device 121. Note that the external device 121 can be equipped with a printer driver for conversion to the print command.

  As shown in FIG. 2, the CPU 102 includes a plurality of processor cores 200, 210, 220, and 230 of the same type. The CPU 102 includes an L1 cache 201 and an L2 cache 202 for the processor core 200, and includes an L1 cache 211 and an L2 cache 212 for the processor core 210. Further, the CPU 102 includes an L1 cache 221 and an L2 cache 222 for the processor core 220, and includes an L1 cache 231 and an L2 cache 232 for the processor core 230. Further, the CPU 102 includes an L3 cache 240 common to the processor cores 200, 210, 220, and 230.

  The L1 caches 201, 211, 221, and 231 are high-speed and small-capacity cache memories, and the L2 caches 202, 212, 222, and 232 are low-speed and large-capacity cache memories than the L1 cache. The L3 cache 240 is a cache memory that is slower than the L2 cache and larger in capacity, but faster than the RAM 104 that is the main memory. Data, instructions, etc. that are frequently used are stored in the L1 cache, which is the fastest.

  The processor cores 200, 210, 220, and 230 execute processing for reading or writing data and instructions from the L 1, L 2, L 3, or the RAM 104. For example, the processor core 200 is configured to first search the L1 cache 201 for necessary data and instructions, and if not, search the L2 cache 202, the L3 cache 240, and the RAM 104 in order.

  Each of the processor cores 200, 210, 220, and 230 can operate independently, and for example, four programs can be simultaneously executed in parallel. For this reason, processing can be performed efficiently. 2 illustrates the configuration having four processor cores, the number of processor cores is not limited to four, but may be two, three, or five or more. Further, the cache may be only the L1 cache or only the L1 cache and the L2 cache.

  FIG. 3 is a diagram illustrating a configuration example of software executed on the controller board 101. The MFP 100 is installed with various software in order to realize various functions. One of the installed software includes a BIOS / monitor program 300 stored in the ROM 103. The BIOS is a program for controlling devices such as the plotter 111 and the scanner 112 provided in the MFP 100. The monitor program is a program for monitoring the operation of MFP 100.

  Examples of other software include an OS 301, a copy application 302, a printer application 303, a scanner application 304, and a FAX application 305. The OS 301 provides basic functions commonly used by applications such as input / output functions and memory management. The OS 301 is activated by the BIOS.

  The copy application 302 is an application program that realizes a copy function for reading a document or the like and printing it. A printer application 303 is an application program that realizes a printing function, and a scanner application 304 is an application program that realizes a scanner function for reading a document or the like. The FAX application 305 is an application program that realizes a facsimile function for reading a document or the like and transmitting it by fax.

  In FIG. 3, four applications are illustrated, but two, three, or five or more applications may be implemented. Examples of other applications include a mail application that implements a mail function, an application that executes communication processing with other devices, and an application that executes data output to a user interface.

  A plurality of applications shown in FIG. 3 can be executed in parallel by a plurality of processor cores as shown in FIG. The CPU 102 has two operation modes, SMP and AMP as described above. In order to improve the processing capability, the SMP automatically distributes each application to an idle processor core so that the load on each processor core is uniform. On the other hand, the AMP executes each application in a fixed manner on a specific processor core in order to suppress the occurrence of useless scheduling and guarantee real-time performance.

  Here, with reference to FIG. 4, the execution image of the method (conventional method) in Patent Document 1 and the method (present method) in the present invention will be described. FIG. 4A illustrates an execution image of the conventional method, and FIG. 4B illustrates an execution image of the present method. The hardware configuration of the image forming apparatus is the same as that shown in FIG. 1, the configuration of the CPU 102 is the same as that shown in FIG. 2, and the software configuration is the same as that shown in FIG. To do.

  For example, the copy application 302 is set to be executed on the core 3 as a processor core to be executed, and the scanner application 304 is set to be executed on the core 4 as a processor core to be executed. Other applications are set so that the remaining core 1 and core 2 are executed in parallel.

  With this setting, the core 3 is fixed for the copy application 302 and the core 4 is fixed for the scanner application 304. In MFP 100 set in this way, applications 1-a, 1-b, 1-c, 2-a, 2-b are executed as other applications, and application 3-a is executed as copy application 302. To do.

  In the conventional method, as shown in FIG. 4A, the applications 1-a, 1-b, 1-c, 2-a, 2-b are executed in parallel on the core 1 and the core 2, and the application 3 -A is executed on the fixed core 3. The core 4 is in an idle state because the scanner application 304 is not executed. In this conventional method, the copy application 302 is set to the core 4 and the scanner application 304 is fixed to the core 3 for execution at the next startup, thereby distributing the load on the processor core.

  However, if the user does not use the scanner function much, either one of the core 3 and the core 4 is in an idle state and is not used, resulting in a waste of the entire system.

  In this method, as shown in FIG. 4B, the core 4 fixed to the scanner application 304 that is not often used is used for other applications similar to the core 1 and the core 2. The cores 4 are also allocated and executed with the applications 1-b, 2-b, which are part of the applications 1-a, 1-b, 1-c, 2-a, 2-b. By doing so, it is possible to distribute the load of the processor cores and eliminate the waste of resources, thereby achieving effective use.

  In order to realize this, the processor system 500 having a plurality of processor cores includes a storage unit 501, a first determination unit 502, a measurement unit 503, and a second determination unit 504 as shown in FIG. Consists of including. Although not shown, the processor system 500 naturally includes a plurality of processor cores.

  As the storage unit 501, the L1 cache, the L2 cache, the L3 cache shown in FIG. 2, the RAM 104, the HDD 107, etc. shown in FIG. 1 can be used. The storage unit 501 stores information regarding whether or not to fix a processor core to be executed, which is set for each of applications as a plurality of programs. Here, fixing the processor core means that only one processor core that determines execution of the program is performed, and the other processor cores are not allowed to be fixed. The information stored in the storage unit 501 may be in any format, but may be in a table format as shown in FIG.

  In the table 505 shown in FIG. 6, a program name is used as information for identifying a program, and the program name is associated with the above information. This information is information indicating whether or not the program is a target for fixing the processor core (core fixation target), and is “target” or “non-target”. Examples of programs to be fixed include a scanner application, a printer application, a copy application, and the like that execute a process that requires real-time processing such as control of a scanner and a printer. Examples of the non-fixed program include an application that executes processing without time restrictions such as communication processing when the image forming apparatus functions as a server and data output to a user interface.

  The table 505 also includes information (execution core) indicating which processor core is fixed. For example, the number “1” assigned to the core. When not fixed to any processor core, a specific value such as “−1” which is not assigned to any core is set. In the table shown in FIG. 6, the program A is fixed to be executed by the core 1, and the programs B and C are set to be executed by an empty core without fixing the core. Here, the program name and the core number are used, but any other information may be used as long as the information can identify the program and the core.

  The information in the table 505 may be only the information described above, but in addition thereto, the number of executions indicating the execution frequency of the program can be included. If a processor core is fixed for a program that is executed less frequently and is not frequently used, resources are wasted so that other programs can be allocated to the processor core. .

  Referring to FIG. 5 again, the first determination unit 502 determines whether to fix the processor core for each of the one or more programs to be executed with reference to the table 505. That is, the first determination unit 502 refers to the core fixation target in the table 505, determines that the object is fixed if it is “target”, and determines that it is not fixed if it is “non-target”.

  The measuring unit 503 measures the execution frequency of each program. The measuring unit 503 can measure the number of executions of each program since the MFP 100 is turned on as the execution frequency. In order to measure the number of executions, the measuring means 503 can be configured to include a counter. The counter can count the number of executions at the start or end of each program. Each time the execution count increases by 1, the measuring unit 503 can overwrite the execution count associated with the program in the table 505.

  The measuring unit 503 can also measure the CPU usage rate at the previous execution time of each program as the execution frequency. The CPU usage rate is a rate at which the program occupies the processing time of the processor core. This CPU usage rate can be acquired using, for example, a general command provided by the OS. As a general command, when the OS is Linux (registered trademark), a top command can be used. The acquired CPU usage rate can also be stored in the table 505 in association with each program.

  The measuring means 503 can detect either the number of executions or the CPU usage rate, or both. The CPU usage rate is not limited to that at the previous execution, but may be the usage rate at the previous execution. Further, it may be an average of a plurality of CPU usage rates, such as the last time and the last time.

  The second determination unit 504 determines, based on the measured execution frequency, whether or not the program determined by the first determination unit 502 to fix the processor core should be fixed to the processor core set for the program. . A threshold is set in advance for the execution frequency, and it is determined whether or not it should be actually fixed by determining whether or not it is equal to or greater than the threshold. When the execution frequency is the number of executions, it is determined whether or not it is a certain number or more, and when it is the CPU usage rate, it is determined whether or not it is a certain value or more.

  As for the threshold value, an optimum value can be obtained by simulation, a test, or the like in consideration of the load deviation of the processor core, the execution efficiency of the program, and the like.

  Only the program determined to be fixed by the above processing is fixed to the processor core associated with the execution of the program. For the other programs, each processor core to be executed is determined for each program so that the load of unfixed processor cores is distributed by the scheduler of the OS.

  Processing for fixing the program to the specific core executed by the processor system will be described in detail with reference to the flowchart shown in FIG. The system control program is started to execute this process, and the process starts from step 700. This system control program can be automatically started after the MFP 100 is turned on and the OS is started, for example.

  In step 710, it is determined whether there is a program that is fixed to a specific core and has a low execution frequency. The processor system further includes third determination means, and this third determination means can make this determination. In this determination, with reference to the table 505, it is determined whether there is a program whose execution core has a value other than “−1” and whose execution frequency is less than a predetermined number. The execution frequency may be the CPU usage rate, not the number of executions.

  This will be specifically described with reference to the table shown in FIG. For example, it is assumed that the predetermined number of times is 10. In the determination in step 710, first, the program A is specified as a program whose execution core has a value other than “−1”. Then, it is determined whether or not the value of the number of executions of the program A is less than 10, and it is determined that it is not more than 10.

  Referring to FIG. 7 again, if it is determined in step 710 that there is, the process proceeds to step 720, and the corresponding core is removed from the fixation target. This is to effectively use the core in other programs. The specific processing here is processing for adding the core to the scheduling target of the scheduler of the OS.

  A general OS scheduler defines a queue for each core and sequentially executes programs connected to the queue. At this time, it is possible to connect the program only to the queue of the core that is the scheduling target, and in the processing of step 720, the core fixed to the program with low execution frequency is added to the core that is the scheduling target. To do. Thereby, the core fixed to the program with low execution frequency is also subject to scheduling, and it is possible to prevent the core from becoming free. After the process of step 720 is completed, the process proceeds to step 730. Also, if it is determined in step 710 that there is not, the process proceeds to step 730.

  In step 730, the first determination unit 502 determines whether or not the executed program is a core fixation target. Specifically, the first determination unit 502 refers to the table 505 and determines whether or not the core fixation target column in the table 505 is “target”. If it is “target”, the process proceeds to step 740, and if it is “non-target”, the process proceeds to step 770.

  In step 740, the measuring means 503 measures the execution frequency of the program. In this example, the measuring unit 503 measures the number of executions of the program, and overwrites and records the number of executions in the table 505.

  In step 750, the second determining means 504 determines whether or not the program should actually be fixed to the specific core. In this example, the second determination unit 504 determines whether the number of executions of the program in the table 505 is a predetermined number or more. If it is more than a certain number of times, it is determined that it should be fixed, and if it is less than a certain number of times, it is determined not to be fixed.

  If it is determined in step 750 that the program should be fixed, the process proceeds to step 760, and the program is fixed to the specific core. In this process, first, core identification information (for example, a core number) for identifying a specific core to be fixed is recorded in the execution core column in the table 505. Then, the program is excluded from the cores to be scheduled by the OS scheduler, and the program connected to the core queue is moved to the core queue not to be fixed. If the program is already fixed to the specific core, control is performed so that the program is executed on the same core. With this fixing, the process proceeds to step 780 and the process is terminated.

  If it is determined in step 750 that the program is not to be fixed, or if it is determined in step 730 that the program is not to be fixed, an execution core for executing the program is determined by the OS scheduler in step 770, and this process is performed in step 780. finish.

  In this way, by fixing the program to be executed on a specific core, the cache hit rate increases especially in a program that uses a large amount of memory such as image processing, so the program is executed efficiently. it can.

  If it is set in the table 505 so that a program with high execution frequency is fixed to a specific core, the program is fixed to the specific core by the above processing. When the specific core is executing the program and the core is fixed to another program, if the specific core is fixed, the load is concentrated on the specific core.

  Therefore, the table 505 shown in FIG. 5 is a table 505 shown in FIG. 8, and a flag indicating whether each program is being executed is added. If each program is being executed, a flag is set and 1 is set. If not running, the flag is set to zero. For this reason, the flag is set to 1 when the program is started, and the flag is set to 0 when the program ends. In order to detect the information of the flag, the processor system 500 can include detection means for detecting whether or not each program is being executed.

  This flag is excluded if the flag is 1 when it is fixed to a certain core in step 760 of the flowchart shown in FIG. In FIG. 8, since the flag 1 is set for the program A, the core 1 fixed to the program A is excluded. Since not all cores can be fixed, the core 0 is always excluded from the fixed target. When there are four cores from core 0 to core 3, core 0 and core 1 are excluded, and any one of remaining core 2 and core 3 is selected as the core to be immobilized.

  In order to perform such processing, the processor system 500 can include core fixing means. The core fixing means applies a processor core other than the processor core fixed to one or more programs detected as being executed by the detecting means to the program determined to be fixed to the processor core by the second determining means 504. Fix it.

  Note that when selecting from a plurality of processor cores, for example, the one with the smaller number of executions can be selected as the core to be fixed. This is an example and is not limited to this method. Note that adding a flag can prevent a load from being concentrated on a specific core.

  In a processor system having four cores from core 0 to core 3, as shown in the table 505 in FIG. 9, the cores 1 to 3 are fixed to the execution of each program, and are newly fixed. May be executed. Since the core 0 is always excluded from the fixation target as described above, if one core is fixed to each program, the core cannot be fixed to the new program.

  Therefore, from the result of measuring the CPU usage rate of each core, the core to be fixed is changed between the fixed cores within a range where the CPU usage rate of each core does not exceed 100%. For example, if the CPU usage rate of the core 1 is about 40% and the CPU usage rate of the core 2 is about 50%, even if both are combined, it is about 90% and does not exceed 100%. For this reason, the program A fixed to the core 1 and the program D fixed to the core 2 are fixed to be executed by the same core 1, and the above new program is fixed to be executed by the core 2. can do.

  In order to perform such processing, the processor system 500 can include a changing unit. The changing unit operates when each of the two or more processor cores is fixed to each of the two or more programs and a new program to be fixed is started. The changing means changes the processor core to be fixed based on the CPU usage rate measured by the measuring means 503, and fixes each of the two or more programs and the new program to each of the two or more processor cores. To do.

  By providing this changing means, even if the number of programs to be fixed becomes larger than the total number of cores, the execution core of the program can be fixed while distributing the load of each core.

  The present invention has been described with the above-described embodiment as a processor system, an image forming apparatus as an example of an electronic device, and a system control program. However, the present invention is not limited to the above-described embodiment. Therefore, other embodiments, additions, changes, deletions, and the like can be changed within a range that can be conceived by those skilled in the art, and as long as the effects and advantages of the present invention are exhibited in any aspect, the present invention It is included in the range.

DESCRIPTION OF SYMBOLS 100 ... MFP, 101 ... Controller board, 102 ... CPU, 103 ... ROM, 104 ... RAM, 105 ... Image processing part, 106 ... Operation part, 107 ... HDD, 108 ... FCU, 109 ... Network control part, 110 ... Image formation Means 111 ... Plotter 112 ... Scanner 120 ... Network 121 ... External device 200, 210, 220, 230 ... Processor core 201, 211, 221, 231 ... L1 cache 202, 212, 222, 232 ... L2 Cache, 240 ... L3 cache, 300 ... BIOS / monitor program, 301 ... OS, 302 ... Copy application, 303 ... Printer application, 304 ... Scanner application, 305 ... FAX application, 500 ... Processor system, 5 1 ... storage unit, 502 ... first determining means, 503 ... measuring device, 504 ... second determining means, 505 ... table

JP 2011-1003007 A

Claims (8)

A processor system having a plurality of processor cores,
Storage means for storing information on whether or not to fix a processor core to be executed, set for each of a plurality of programs;
First determination means for determining whether to fix a processor core for each of the one or more activated programs based on the information;
A measuring means for measuring the execution frequency of each program;
A processor system including: a second determination unit that determines, based on the measured execution frequency, whether or not the program should be fixed to the processor core for the program determined to fix the processor core by the first determination unit; .   2. The measurement unit according to claim 1, wherein the measurement unit measures the number of executions of each program, and the second determination unit determines that the program should be fixed to the processor core when the measured number of executions is a predetermined number or more. Processor system.   2. The measurement unit measures a CPU usage rate of each program, and the second determination unit determines that the CPU usage rate should be fixed to the processor core when the measured CPU usage rate is a predetermined value or more. The processor system described in 1.   The measuring means measures the number of executions of each program and the CPU usage rate of each program, and the second determining means is that the measured number of executions is a predetermined number or more and the measured CPU usage rate is constant. The processor system according to claim 1, wherein if it is equal to or greater than the value, it is determined that the processor core should be fixed.   Detection means for detecting whether or not each program is being executed, and one or more detected as being executed by the detection means for the program determined to be fixed to the processor core by the second determination means 5. The processor system according to claim 1, further comprising: a core fixing unit that fixes a processor core other than the processor core fixed to the program.   When each of two or more processor cores is fixed to each of two or more programs and a new program that should fix the processor cores is activated, the fixed number is determined based on the CPU usage rate measured by the measurement means. 6. The apparatus according to claim 1, further comprising a changing unit that changes a processor core to fix each of the two or more programs and the new program to each of the two or more processors. Processor system.   An electronic device comprising the processor system according to claim 1. A system control program executed by a processor system having a plurality of processor cores, wherein the processor system sets information on whether to fix a processor core to be executed set for each of the plurality of programs. Storage means for storing, the system control program,
Measuring the execution frequency of each program;
Determining whether to fix a processor core for each of the one or more activated programs based on the information;
A system control program for causing the processor system to execute, based on the measured execution frequency, whether or not the program should be fixed to the processor core for a program determined to fix the processor core.