JP2017041693A - Communication device and communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication device and a communication system that reduce noise on a communication line as much as possible.SOLUTION: A communication device (master 3 or slave 4) connected with a bus 2 in a communication system 1 comprises a logic circuit (master logic circuit 7 or slave logic circuit 17) that includes: a voltage switching unit 8 for switching the amplitude voltage of communication among a plurality of stages; a communication error detection unit for detecting a communication error in communication performed via a bus; and a voltage switching control unit for switching the amplitude voltage of communication to higher voltage when a communication error is detected, and for switching the amplitude voltage of communication to lower voltage when communication is performed normally.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a communication device and a communication system that perform communication by connecting a plurality of communication devices to a communication line.

  For example, LIN (Local Interconnect Network) communication is known as an in-vehicle communication system mounted on a vehicle. In this LIN communication, a plurality of communication devices (for example, ECU (Electronic Control Unit)) are connected to a communication line (serial bus), and communication is performed between the plurality of communication devices via the communication line. For example, a configuration described in Patent Document 1 is known. The configuration of Patent Document 1 includes a voltage switching unit that switches the voltage level of a data pulse for performing communication on a communication line to at least two different voltage levels. When communicating high priority data, the voltage level is increased. You are in control.

JP 2006-33391 A

  In recent years, in vehicle communication, it has been required to reduce noise on a communication line. On the other hand, in the case of the above configuration, the voltage level is increased when communicating high-priority data, and during this communication, the voltage level is increased, which causes a problem that noise on the communication line increases. To do.

  Therefore, an object of the present invention is to provide a communication device and a communication system that can reduce noise on a communication line as much as possible.

  The invention according to claim 1 is a communication device connected to a bus of a communication system, and detects a communication error in communication executed via the voltage switching unit that switches the amplitude voltage of communication in a plurality of stages. A communication error detection unit, and a voltage switching control unit that switches to increase the communication amplitude voltage when a communication error is detected, and switches to decrease the communication amplitude voltage when communication is normally executed. It is provided.

  The invention according to claim 8 is a communication system including a bus and a plurality of communication devices connected to the bus, wherein at least one communication device includes a voltage switching unit that switches the amplitude voltage of communication in a plurality of stages. The communication error detection unit for detecting a communication error of communication executed via the bus, and when the communication error is detected, the communication is switched to increase the amplitude voltage of the communication, and when the communication error is not detected, It is characterized in that it includes a voltage switching control unit that switches so as to lower the amplitude voltage of communication.

The block diagram of the whole schematic structure of the communication system which shows 1st Embodiment of this invention. Block diagram of master logic circuit Electrical circuit diagram of switching circuit Block diagram of slave logic circuit Time chart (part 1) Time chart (part 2) Time chart (part 3) Flow chart of voltage switching control Voltage switching control time chart Flowchart of voltage switching control showing the second embodiment of the present invention. Voltage switching control time chart Flowchart of voltage switching control showing the third embodiment of the present invention. Voltage switching control time chart Flowchart of voltage switching control showing the fourth embodiment of the present invention. Voltage switching control time chart Electrical circuit diagram of switching circuit showing a fifth embodiment of the present invention Electrical circuit diagram of switching circuit showing a sixth embodiment of the present invention The electric circuit diagram of the principal part of the receiver circuit which shows 7th Embodiment of this invention The electric circuit diagram of the principal part of the receiver circuit which shows 8th Embodiment of this invention The figure which shows 9th Embodiment of this invention and is a figure explaining communication data

  Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. First, FIG. 1 is a block diagram showing an overall schematic configuration of a communication system according to the present embodiment. As shown in FIG. 1, the communication system 1 includes a bus 2 that is a communication line, and a plurality of communication devices 3 and 4 connected to the bus 2. The communication device 3 is a master communication device. The communication device 4 is a slave communication device, and one or more slave communication devices 4 are connected to the bus 2.

  The master communication device 3 includes a driver circuit 5, a receiver circuit 6, a master logic circuit 7, and a switching circuit (voltage switching unit) 8. The driver circuit 5 receives the transmission data signal A1 from the master logic circuit 7, generates a transmission signal (pulse signal), and outputs the generated transmission signal to the bus 2. The receiver circuit 6 receives a voltage signal (pulse signal) from the bus 2, generates a reception signal A 2, and outputs the generated reception signal A 2 to the master logic circuit 7.

  As illustrated in FIG. 2, the master logic circuit 7 includes a transmission control unit 9, a reception control unit 10, a communication error detection unit 11, and a switching control unit (voltage switching control unit) 12. The transmission control unit 9 outputs the transmission data signal A1 output from the microcomputer or the like to the driver circuit 5. The reception control unit 10 receives the reception signal A2 from the receiver circuit 6, and executes necessary processing based on the input reception signal A2.

  The communication error detection unit 11 detects whether or not a communication error has occurred based on the reception signal A2 from the receiver circuit 6. When the communication error is detected, the communication error detection signal is displayed. When the communication error is not detected, the communication is normal. A detection signal is output to the switching control unit 12. When receiving the communication error detection signal, the switching control unit 12 outputs a high switching control signal for increasing the bus voltage (that is, the communication amplitude voltage) to the switching circuit 8, and when receiving the communication normality detection signal, A low switching control signal for lowering the voltage is output to the switching circuit 8.

  The switching circuit 8 has a function of switching the bus voltage to a plurality of levels, for example, two levels. The switching circuit 8 switches the bus voltage high when a high switching control signal is received from the master logic circuit 7 (switching control unit 12), and the bus circuit when the low switching control signal is received from the master logic circuit 7 Switch the voltage low.

  A specific configuration of an example of the switching circuit 8 includes three diodes 13, 13, 13 and a changeover switch 14 as shown in FIG. 3. The series circuit of the two diodes 13 and 13 is connected between the constant voltage power supply terminal Va and the contact a of the changeover switch 14. One diode 13 is connected between the constant voltage power supply terminal Va and the contact b of the changeover switch 14. The common contact c of the changeover switch 14 is connected to a terminal that supplies a voltage to the bus 2. When the contact (ca) of the changeover switch 14 is turned on, a low voltage is supplied to the bus 2 due to a forward voltage drop of the two diodes 13 and 13, and the bus voltage is switched to a low voltage. ing. When the contact point (c-b) of the changeover switch 14 is turned on, a high voltage is supplied to the bus 2 due to a forward voltage drop of one diode 13, and the bus voltage is switched to a high voltage. . In the case of this configuration, the diode 13 has a function as a pull-up resistor that sets the bus voltage to a high level.

  The changeover switch 14 is controlled by the master logic circuit 7. That is, when the changeover switch 14 receives the low switching control signal from the master logic circuit 7, the contact (ca) is turned on, and when the changeover switch 14 receives the high switching control signal from the master logic circuit 7, the contact (c− b) is turned on.

  The slave communication device 4 includes a driver circuit 5, a receiver circuit 6, a slave logic circuit 17, and a switching circuit 8. The driver circuit 5 other than the slave logic circuit 17, the receiver circuit 6, and the switching circuit 8 have the same configuration as the driver circuit 5, the receiver circuit 6, and the switching circuit 8 of the master communication device 3. The driver circuit 5 receives the transmission data signal B 1 from the slave logic circuit 17, generates a transmission signal, and outputs the generated transmission signal to the bus 2. The receiver circuit 6 receives a voltage signal from the bus 2, generates a reception signal B 2, and outputs the generated reception signal B 2 to the slave logic circuit 17.

  As shown in FIG. 4, the slave logic circuit 17 includes a transmission control unit 19, a reception control unit 20, a communication error detection unit 11, and a switching control unit 12. The communication error detection unit 11 and the switching control unit 12 have the same configuration as the communication error detection unit 11 and the switching control unit 12 of the master logic circuit 7. The transmission control unit 19 outputs the transmission data signal B1 output from the microcomputer or the like to the driver circuit 5. The reception control unit 20 receives the reception signal B2 from the receiver circuit 6, and executes necessary processing based on the input reception signal B2.

  The communication system 1 according to the present embodiment is configured to transmit and receive data by, for example, CXPI (Clock Extension Peripheral Interface) communication. This CXPI communication will be described with reference to FIG.

  First, in CXPI communication, the master communication device 3 always supplies the clock signal Sc (see FIG. 5A) to the bus 2 and transmits the clock signal Sc to the slave communication device 4. The master communication device 3 and the slave communication device 4 are configured to transmit the data signal superimposed on the clock signal Sc. In this case, the transmission signal corresponding to 1-bit data “0” (the signal superimposed on the clock signal Sc) is a waveform signal as shown in FIG. A transmission signal corresponding to 1-bit data “1” is a waveform signal as shown in FIG.

  Next, signals output from the master communication device 3 to the bus 2 will be described with reference to FIG. In the master communication device 3, the transmission control unit 9 of the master logic circuit 7 outputs, for example, a data signal Sa1 as shown in FIG. 6A to the driver circuit 5 as a transmission control signal. . As the data signal Sa1, for example, a UART signal (NRZ method) output from a microcomputer is used. The driver circuit 5 receives the data signal Sa1 from the master logic circuit 7, converts the data signal Sa1 into PWM, and outputs a transmission signal Sa2 as shown in FIG. The transmission signal Sa2 becomes a waveform of a signal that actually flows through the bus 2.

  A signal output from the slave communication device 4 to the bus 2 will be described with reference to FIG. In this case, a clock signal Sc as shown in FIG. 7A is always output from the master communication device 3 to the bus 2. In this state, for example, a transmission signal Sa3 as shown in FIG. Then, the waveform of the signal that actually flows through the bus 2 is the signal Sa4 (see FIG. 7C) obtained by ANDing the clock signal Sc shown in FIG. 7A and the transmission signal Sa3 shown in FIG. It becomes.

  Next, the operation of the master logic circuit 7 of the master communication device 3 having the above-described configuration, particularly the control for detecting the communication error and switching the bus voltage will be described with reference to the flowchart of FIG. The control for detecting a communication error by the slave logic circuit 17 of the slave communication device 4 and switching the bus voltage is the same as the control by the master logic circuit 7 of the master communication device 3.

  When communication is started by the master communication device 3, first, an edge (rising edge or falling edge) of the reception signal A2 is detected in step S10 of FIG. Subsequently, the process proceeds to step S20, where 0/1 determination (determination of data “0” or data “1”) is performed. Then, the process proceeds to step S30, and it is determined whether or not data for one frame has been received. If one frame of data has not been received (“NO” in step S30), the process returns to step S10.

  In step S30, when data for one frame is received (“YES”), the process proceeds to step S40 to determine whether or not a communication error has occurred. If no communication error has occurred ("NO" in step S40), the process proceeds to step S50, and it is determined whether or not the bus voltage is the minimum voltage (MIN voltage). If the bus voltage is the minimum voltage (“YES” in step S50), the process returns to step S10. In step S50, when the bus voltage is not the minimum voltage ("NO"), the process proceeds to step S60, and the bus voltage is decreased. In this case, in a configuration in which the bus voltage is switched to, for example, two levels of high and low, the bus voltage is switched to a low voltage (MIN voltage). After this, the process returns to step S10.

  In step S40, when a communication error occurs ("YES"), the process proceeds to step S70 to determine whether or not the bus voltage is the maximum voltage (MAX voltage). If the bus voltage is the maximum voltage (“YES” in step S70), the process returns to step S10. In step S70, when the bus voltage is not the maximum voltage ("NO"), the process proceeds to step S80, where the bus voltage is increased. In this case, the bus voltage is switched to a high voltage (MAX voltage) in a configuration in which the bus voltage is switched to, for example, two levels of high and low. After this, the process returns to step S10.

  Next, a specific example of bus voltage switching control by the master communication device 3 will be described with reference to the time chart of FIG. As shown in FIG. 9A, the clock signal Sc is output from the communication device 3 to the bus 2. Then, as illustrated in FIG. 9B, the communication device 3 receives the reception signal A <b> 2 from the bus 2. Further, as shown in FIG. 9C, the communication device 3 sets the bus voltage E to the low voltage V1 at the start of communication.

  Thereafter, when the communication device 3 detects a communication error at the rising edge of the reception signal A2 at time t1, the communication device 3 switches the bus voltage to the high voltage V2 at the time of detection. Thereafter, communication is performed with the bus voltage switched to the high voltage V2. At time t2, when the communication device 3 detects normal communication at the rising edge of the reception signal A2, the communication device 3 switches the bus voltage to the low voltage V1 at the time of detection. Thereafter, communication is performed with the bus voltage switched to the low voltage V1.

  Thereafter, when the communication device 3 detects a communication error at the rising edge of the reception signal A2 at time t3, the communication device 3 switches the bus voltage to the high voltage V2 at the time of detection. Thereafter, the switching control described above is repeatedly executed.

  In each of the slave communication devices 4, the same control as the bus voltage switching control by the master communication device 3 described above (that is, when a communication error is detected by setting the bus voltage to the low voltage V1 at the start of communication). The bus voltage is switched to the high voltage V2, and after that, when communication normality is detected, the bus voltage is switched to the low voltage V1, and the same control for repeating the switching of the bus voltage is executed.

  According to this embodiment having such a configuration, the bus voltage is set to the low voltage V1 at the start of communication, the bus voltage is switched to the high voltage V2 when a communication error is detected, and then the bus voltage is changed to the normal communication. Since the switching to the low voltage V1 and the subsequent switching of the same bus voltage are repeated, the communication can be executed with the bus voltage basically set to the low voltage V1. Therefore, communication noise can be reduced.

  In particular, in this embodiment, since communication is performed using CXPI communication, the clock signal Sc (synchronization signal) is output from the master logic circuit 7 of the master communication device 3 via the driver circuit 5 ( In FIG. 7A, the slave logic circuit 17 receives the clock signal Sc from the master via the receiver circuit 6 of the slave communication device 4, and synchronizes. Then, the slave communication device 4 transmits the transmission signal Sa3 to the bus 2 so as to overlap the clock signal Sc from the master (see FIG. 7B). In this case, in FIGS. 7A and 7B, the outputs of the driver circuits 5 of the master communication device 3 and the slave communication device 4 are turned on (low level) in the portion indicated by the section T, and then the master Since the output of the driver circuit 5 of the communication device 3 is turned off (high level), the current that has been drawn to the master communication device 3 side until then flows to the slave communication device 4 side at once. Occur. The noise tends to increase as the transmission voltage (bus voltage) of the bus 2 increases.

  On the other hand, in the present embodiment, the bus voltage is basically set to the low voltage V1, that is, the communication is executed with the lowest possible transmission voltage, so that the noise peculiar to the CXPI communication is reduced. can do.

  10 and 11 show a second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same structure as 1st Embodiment. In the first embodiment, after detecting a communication error and switching the bus voltage to the high voltage V2, the bus voltage is switched to the low voltage V1 when the normal communication is detected once. In the embodiment, the configuration is such that the bus voltage is switched to the low voltage V1 when normal communication is detected a plurality of times, for example, twice in succession. Specifically, step S45 is inserted between step S40 and step S50 of the flowchart of FIG. 8 to create the flowchart of FIG.

  First, steps S10 to S40 in FIG. 10 are executed in the same manner as steps S10 to S40 in FIG. 8 of the first embodiment. In step S40, when a communication error has not occurred (communication was normal) (“NO”), the process proceeds to step S45, and it is determined whether or not normal communication has continued twice. If the normal communication has not continued twice ("NO" in step S45), the process returns to step S10.

  In step S45, when the normal communication continues twice ("YES"), the process proceeds to step S50. And the process after this step S50 is performed similarly to the process after step S50 of FIG. 8 of 1st Embodiment.

  Next, a specific example of bus voltage switching control by the master communication device 3 of the second embodiment will be described with reference to the time chart of FIG. As shown in FIG. 11A, the clock signal Sc is output from the communication device 3 to the bus 2. Then, as shown in FIG. 11B, the communication device 3 receives the reception signal A2 from the bus 2. Further, as shown in FIG. 11C, the communication device 3 sets the bus voltage E to the low voltage V1 at the start of communication.

  Thereafter, when the communication device 3 detects a communication error at the rising edge of the reception signal A2 at time t1, the communication device 3 switches the bus voltage to the high voltage V2 at the time of detection. Thereafter, communication is performed with the bus voltage switched to the high voltage V2. At time t2, even when the communication device 3 detects normal communication (first time) at the rising edge of the reception signal A2, the bus voltage is not switched. After that, at time t21, when the communication device 3 detects the communication normality twice continuously at the rising edge of the reception signal A2 (that is, when the communication is normally executed continuously for a plurality of frames), the communication device 3 The device 3 switches the bus voltage to the low voltage V1. Thereafter, communication is performed with the bus voltage switched to the low voltage V1.

  The configurations of the second embodiment other than those described above are the same as the configurations of the first embodiment. Therefore, in the second embodiment, substantially the same operational effects as in the first embodiment can be obtained. In particular, in the second embodiment, when the normal communication is detected a plurality of times, for example, twice continuously, the bus voltage is switched to the low voltage V1, so that a communication error occurs with respect to the noise that is continuously generated. It can be set as the structure which is hard to generate | occur | produce.

  In the second embodiment, when the normal communication is detected twice, the bus voltage is switched to the low voltage V1. However, the present invention is not limited to this, and the normal communication is continued three times or more. The bus voltage may be switched to the low voltage V1 when detected.

  12 and 13 show a third embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same structure as 1st Embodiment. In the first embodiment, it is configured to detect a communication error after completing reception of data for one frame. However, in the second embodiment, a communication error is detected at an arbitrary timing during communication. When a communication error is detected, the bus voltage is switched to the high voltage V2. Specifically, step S25 is inserted between step S20 and step S30 of the flowchart of FIG. 8 to create the flowchart of FIG.

  First, step S10 and step S20 in FIG. 12 are executed in the same manner as step S10 and step S20 in FIG. 8 of the first embodiment. Then, it progresses to step S25 and it is determined whether the communication error 2 which can be detected at the arbitrary timings during communication has occurred. Examples of the communication error 2 include a data error whose fixed value is not correct. In step S25, when communication error 2 has not occurred (communication was normal) ("NO"), the process proceeds to step S30, and it is determined whether or not data for one frame has been received. And the process after this step S30 is performed similarly to the process after step S30 of FIG. 8 of 1st Embodiment.

  If communication error 2 occurs in step S25 ("YES"), the process proceeds to step S70 to determine whether or not the bus voltage is the maximum voltage (MAX voltage). And the process after this step S70 is performed similarly to the process after step S70 of FIG. 8 of 1st Embodiment.

  Next, a specific example of bus voltage switching control by the master communication device 3 of the third embodiment will be described with reference to the time chart of FIG. As shown in FIG. 13A, the clock signal Sc is output from the communication device 3 to the bus 2. Then, as illustrated in FIG. 13B, the communication device 3 receives the reception signal A <b> 2 from the bus 2. As shown in FIG. 13C, the communication device 3 sets the bus voltage E to the low voltage V1 at the start of communication.

  Thereafter, at time t1, when the communication device 3 detects a communication error (communication error after completing reception of one frame of data) at the rising edge of the reception signal A2, the communication device 3 detects the bus voltage at the time of detection. Switch to high voltage V2. Thereafter, communication is performed with the bus voltage switched to the high voltage V2. At time t2, when the communication device 3 detects normal communication at the rising edge of the reception signal A2, the communication device 3 switches the bus voltage to the low voltage V1 at the time of detection. Thereafter, communication is performed with the bus voltage switched to the low voltage V1.

  Thereafter, when the communication device 3 detects a communication error 2 (a communication error that can be detected at an arbitrary timing during communication) at time t31, the communication device 3 switches the bus voltage to the high voltage V2 at the time of detection. Thereafter, communication is performed with the bus voltage switched to the high voltage V2. In the third embodiment, data transmission (communication) is continued even if the communication error 2 is detected.

  The configuration of the third embodiment other than that described above is the same as the configuration of the first embodiment. Therefore, in the third embodiment, substantially the same operational effects as in the first embodiment can be obtained.

  14 and 15 show a fourth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same structure as 3rd Embodiment. In the third embodiment, the data transmission (communication) is continued even if the communication error 2 is detected. However, in the fourth embodiment, when the communication error 2 is detected, the data transmission (at that time) The communication is terminated, and the bus voltage is switched to the high voltage V2, and then the data is retransmitted. Specifically, step S90 is inserted after step S80 in the flowchart in FIG. 12 to create the flowchart in FIG.

  First, Steps S10 to S80 in FIG. 14 are executed in the same manner as Steps S10 to S80 in FIG. 12 of the third embodiment. In the fourth embodiment, step S80 is executed to switch the bus voltage to a high voltage, and then the process proceeds to step S90 to stop data transmission, that is, frame transmission, and then data (frame) in which communication error 2 has occurred. ) Is retransmitted.

  Next, a specific example of bus voltage switching control by the master communication device 3 according to the fourth embodiment will be described with reference to the time chart of FIG. As shown in FIG. 15A, the clock signal Sc is output from the communication device 3 to the bus 2. Then, as illustrated in FIG. 15B, the communication device 3 receives the reception signal A <b> 2 from the bus 2. Further, as shown in FIG. 15C, the communication device 3 sets the bus voltage E to the low voltage V1 at the start of communication.

  Thereafter, at time t1, when the communication device 3 detects a communication error (communication error after completing reception of one frame of data) at the rising edge of the reception signal A2, the communication device 3 detects the bus voltage at the time of detection. Switch to high voltage V2. Thereafter, communication is performed with the bus voltage switched to the high voltage V2. At time t2, when the communication device 3 detects normal communication at the rising edge of the reception signal A2, the communication device 3 switches the bus voltage to the low voltage V1 at the time of detection. Thereafter, communication is performed with the bus voltage switched to the low voltage V1.

  Thereafter, when the communication device 3 detects a communication error 2 (a communication error that can be detected at an arbitrary timing during communication) at time t31, the communication device 3 switches the bus voltage to the high voltage V2 at the time of detection. Furthermore, in the fourth embodiment, when the communication error 2 is detected, the communication device 3 stops data transmission (communication), switches the bus voltage to the high voltage V2, and then retransmits data at time t32. (Re-communication). In this case, the communication device 3 has a function as a communication unit.

  The configuration of the fourth embodiment other than the above is the same as the configuration of the third embodiment. Therefore, in the fourth embodiment, substantially the same operational effects as in the third embodiment can be obtained.

  FIG. 16 shows a fifth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same structure as 1st Embodiment. In the first embodiment, the switching circuit 8 is configured by the diode 13, but in the fifth embodiment, the switching circuit 8 is configured by a constant voltage circuit.

  A specific configuration of the switching circuit 8 according to the fifth embodiment includes two constant voltage circuits 21 and 22 and a changeover switch 14 as shown in FIG. The first constant voltage circuit (REG1) 21 outputs a high voltage of the bus voltage, the input terminal is connected to the constant voltage power supply terminal Va, and the output terminal is connected to the contact b of the changeover switch 14. . The second constant voltage circuit (REG2) 22 outputs a low voltage of the bus voltage, the input terminal is connected to the constant voltage power supply terminal Va, and the output terminal is connected to the contact a of the changeover switch 14. .

  In the case of this configuration, when the contact (ca) of the changeover switch 14 is turned on, the low voltage output from the second constant voltage circuit 22 is supplied to the bus 2 and the bus voltage is switched to the low voltage. It has a configuration. When the contact point (c-b) of the changeover switch 14 is turned on, the high voltage output from the first constant voltage circuit 21 is supplied to the bus 2 and the bus voltage is switched to the high voltage.

  The configurations of the fifth embodiment other than those described above are the same as the configurations of the first embodiment. Therefore, in the fifth embodiment, substantially the same operational effects as in the first embodiment can be obtained.

  FIG. 17 shows a sixth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same structure as 1st Embodiment. In the first embodiment, the switching circuit 8 that supplies the voltage of two stages (high voltage and low voltage) to the bus 2 is provided. However, in the sixth embodiment, the switching circuit that supplies the voltage of three stages to the bus 2. 23.

  A specific configuration of the switching circuit 23 according to the sixth embodiment includes six diodes 13 and a changeover switch 24 as shown in FIG. A series circuit of the three diodes 13, 13, 13 is connected between the constant voltage power supply terminal Va and the contact a of the changeover switch 24. The series circuit of the two diodes 13 and 13 is connected between the constant voltage power supply terminal Va and the contact b of the changeover switch 14. One diode 13 is connected between the constant voltage power supply terminal Va and the contact c of the changeover switch 14. A common contact d of the changeover switch 24 is connected to a terminal that supplies a voltage to the bus 2.

  In this configuration, when the contact (da) of the changeover switch 24 is turned on, the first voltage (MIN voltage) is supplied to the bus 2 due to the forward voltage drop of the three diodes 13, 13, 13. The bus voltage is switched to the first voltage. When the contact point (db) of the changeover switch 24 is turned on, the second voltage (voltage between the MIN voltage and the MAX voltage) is supplied to the bus 2 due to the forward voltage drop of the two diodes 13 and 13. Thus, the bus voltage is switched to the second voltage. When the contact (dc) of the changeover switch 14 is turned on, the third voltage (MAX voltage) is supplied to the bus 2 due to the forward voltage drop of one diode 13, and the bus voltage is switched to the third voltage. It has a configuration that can be. The changeover switch 24 is switch-controlled by the master logic circuit 7 (or the slave logic circuit 17).

  The configuration of the sixth embodiment other than that described above is the same as the configuration of the first embodiment. Therefore, in the sixth embodiment, substantially the same operational effects as in the first embodiment can be obtained. In particular, in the sixth embodiment, the bus voltage is configured to be switched between the first voltage, the second voltage, and the third voltage, so that when the communication error occurs once and returns to normal communication, the bus voltage Switches from first voltage-> second voltage-> first voltage. On the other hand, in the configuration in which the bus voltage is switched between the first voltage or the third voltage and the two stages, when the communication error occurs once and the normal communication is returned, the bus voltage is changed from the first voltage to the third voltage. > Switches to the first voltage. Therefore, the configuration in which the bus voltage is switched to three stages (sixth embodiment) can return to normal at a lower voltage than the configuration in which the bus voltage is switched to two stages, so that noise can be further reduced.

  In the sixth embodiment, the bus voltage is switched to three stages. However, the present invention is not limited to this, and the bus voltage may be switched to four or more stages.

  FIG. 18 shows a seventh embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same structure as 1st Embodiment. In the seventh embodiment, the threshold voltage of the comparator 25 provided in the receiver circuit 6 of the communication devices 3 and 4 is reduced.

  The comparator 25 has a + input terminal connected to the bus 2 and a − input terminal connected to an intermediate connection point between the resistors 26 and 27. The resistance value of the resistor 26 is three times the resistance value of the resistor 27. The other end of the resistor 26 is connected to the battery voltage terminal VB, and the other end of the resistor 27 is connected to the ground. As a result, a voltage that is 1/4 of the voltage at the battery voltage terminal VB is input to the negative input terminal of the comparator 25 as a threshold voltage.

  The configurations of the seventh embodiment other than those described above are the same as the configurations of the first embodiment. Therefore, also in the seventh embodiment, substantially the same operational effects as in the first embodiment can be obtained. In particular, in the seventh embodiment, since the threshold voltage of the comparator 25 of the receiver circuit 6 is reduced, communication can be executed even when the bus voltage is set to a lower voltage.

  FIG. 19 shows an eighth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same structure as 7th Embodiment. In the eighth embodiment, the threshold voltage of the comparator 25 of the receiver circuit 6 is configured to be switchable in two stages.

  Specifically, as shown in FIG. 19, three resistors 26, 27, and 27 are connected in series between the battery voltage terminal VB and the ground. The resistance value of the resistor 26 is three times the resistance value of the resistor 27. The intermediate connection point of the resistors 26 and 27 is connected to the contact a of the changeover switch 28, the intermediate connection point of the resistors 27 and 27 is connected to the contact b of the changeover switch 28, and the common contact c of the changeover switch 28 is connected to the − Connected to the input terminal. The changeover switch 28 is controlled by the master logic circuit 7 (or the slave logic circuit 17).

  In the case of the above configuration, when the contact (ca) of the changeover switch 28 is turned on, 2/5 of the voltage of the battery voltage terminal VB is input to the −input terminal of the comparator 25 as the threshold voltage. When the contact (c-b) of the changeover switch 28 is turned on, a voltage that is 1/5 of the voltage of the battery voltage terminal VB is input to the negative input terminal of the comparator 25 as a threshold voltage. For example, when the bus voltage is switched to a low voltage, a voltage that is 1/5 of the voltage at the battery voltage terminal VB is input to the negative input terminal of the comparator 25 as a threshold voltage. Further, when the bus voltage is switched to a high voltage, a voltage that is 2/5 of the voltage of the battery voltage terminal VB is input to the negative input terminal of the comparator 25 as a threshold voltage.

  The configuration of the eighth embodiment other than that described above is the same as the configuration of the seventh embodiment. Accordingly, in the eighth embodiment, substantially the same operational effects as in the seventh embodiment can be obtained. In particular, in the eighth embodiment, the threshold voltage of the comparator 25 of the receiver circuit 6 is configured to be switchable in two stages. Therefore, when the control for switching the bus voltage in two stages is executed, the communication is executed satisfactorily. be able to.

  In the eighth embodiment, the threshold voltage of the comparator 25 of the receiver circuit 6 is configured to be switchable in two stages. However, the present invention is not limited to this, and the threshold voltage of the comparator 25 is switched to three or more stages. It may be configured as possible.

  FIG. 20 shows a ninth embodiment of the present invention. When data communication is performed on the bus 2, as shown in FIG. 20, frame data is transmitted to the bus 2, and after an IFS (Inter Frame Space) time elapses, an idle state (a state in which there is no data on the bus 2) is entered. However, in the CXPI communication, the clock signal Sc is output even in the idle state. In the ninth embodiment, when the clock signal Sc is output to the bus 2 in the idle state, the bus voltage is set to a low voltage (MIN voltage).

  The configurations of the ninth embodiment other than those described above are the same as the configurations of the first embodiment. Therefore, in the ninth embodiment, substantially the same operational effects as in the first embodiment can be obtained. The voltage control of the ninth embodiment is also preferably applied to the above-described second to eighth embodiments.

  In each of the above embodiments, the bus voltage is switched to the high voltage V2 when a communication error is detected once. Instead, when a communication error is detected twice in succession. Alternatively, the bus voltage may be switched to the high voltage V2 (that is, when a communication error is detected continuously for a plurality of frames). Furthermore, the bus voltage may be switched to the high voltage V2 when a communication error is detected three times or more.

  In each embodiment described above, the present invention is applied to CXPI communication. However, the present invention is not limited to this, and may be applied to other communication such as LIN and CAN (Controller Area Network). In each of the above embodiments, the communication error detection unit 11 is provided in the logic circuits 7 and 17, but may be provided in the receiver circuit 6 instead.

  In the above embodiments, the communication devices 3 and 4 are each provided with a configuration for switching the bus voltage (communication error detection unit 11, switching control unit 12, and switching circuit 8). A configuration (communication error detection unit 11, switching control unit 12, switching circuit 8) for switching the bus voltage to at least one communication device among a plurality of communication devices 3 and 4 connected to the bus 2 is not provided. You may comprise so that it may provide.

  In the drawings, 1 is a communication system, 2 is a bus, 3 is a master communication device, 4 is a slave communication device, 5 is a driver circuit, 6 is a receiver circuit, 7 is a logic circuit for master, 8 is a switching circuit (voltage switching) Part), 9 is a transmission control part, 10 is a reception control part, 11 is a communication error detection part, 12 is a switching control part (voltage switching control part), 17 is a logic circuit for slaves, and 23 is a switching circuit (voltage switching part). It is.

Claims (8)

A communication device (3, 4) connected to the bus (2) of the communication system (1),
A voltage switching unit (8) for switching the amplitude voltage of communication in a plurality of stages;
A communication error detector (11) for detecting a communication error of communication executed via the bus (2);
A voltage switching control unit (12) that switches to increase the amplitude voltage of communication when a communication error is detected, and switches to decrease the amplitude voltage of communication when communication is normally executed;
A communication device comprising:   The communication apparatus according to claim 1, wherein the voltage switching control unit (12) performs switching so as to increase a communication amplitude voltage when a communication error is continuously detected for a plurality of frames.   The communication apparatus according to claim 1 or 2, wherein the voltage switching control unit (12) performs switching so as to lower an amplitude voltage of communication when communication is normally executed for a plurality of frames continuously.   The voltage switching control unit (12) switches so as to increase the amplitude voltage of communication when a communication error is detected during communication for one frame when a communication error is detected. The communication device described.   A communication unit (3, 4) is provided that executes re-communication at the time of switching the amplitude voltage of communication when a communication error is detected and the amplitude voltage of communication is switched high during the communication for one frame. The communication apparatus according to claim 4. A receiver circuit (6) for comparing the voltage of the bus (2) with a determination voltage;
The communication device according to any one of claims 1 to 5, wherein the receiver circuit (6) is configured to change the determination voltage in accordance with an amplitude voltage of communication.   The communication device according to any one of claims 1 to 6, further comprising a pull-up resistor (13) for setting a communication amplitude voltage to a high level. A communication system comprising a bus (2) and a plurality of communication devices (3, 4) connected to the bus (2),
At least one communication device (3, 4)
A voltage switching unit (8) for switching the amplitude voltage of communication in a plurality of stages;
A communication error detector (11) for detecting a communication error of communication executed via the bus;
A voltage switching control unit (12) that switches to increase the communication amplitude voltage when a communication error is detected, and switches to decrease the communication amplitude voltage when no communication error is detected. A communication system characterized by the above.

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