JP2017038133A - Transmission device - Google Patents

Transmission device Download PDF

Info

Publication number
JP2017038133A
JP2017038133A JP2015157067A JP2015157067A JP2017038133A JP 2017038133 A JP2017038133 A JP 2017038133A JP 2015157067 A JP2015157067 A JP 2015157067A JP 2015157067 A JP2015157067 A JP 2015157067A JP 2017038133 A JP2017038133 A JP 2017038133A
Authority
JP
Japan
Prior art keywords
transmission
impedance
transmission line
characteristic impedance
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2015157067A
Other languages
Japanese (ja)
Other versions
JP6385316B2 (en
Inventor
幸司 澁谷
Koji Shibuya
幸司 澁谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2015157067A priority Critical patent/JP6385316B2/en
Publication of JP2017038133A publication Critical patent/JP2017038133A/en
Application granted granted Critical
Publication of JP6385316B2 publication Critical patent/JP6385316B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Dc Digital Transmission (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a transmission device capable of suppressing influence of reflection over a wide frequency range.SOLUTION: To a pre-stage side and a post-stage side of an impedance mismatch part 2, two transmission lines 4a1, 4b1, having the same delay time as that of the impedance mismatch part 2 are connected. Further, to the transmission line 4a1 and the transmission line 4b1, transmission lines 4a2, 4a3 and transmission lines 4b2, 4b3 are connected, respectively. These transmission lines 4a2, 4a3 and transmission lines 4b2, 4b3 have delay time of 2times (n: integer) of the delay time of the transmission lines 4a1, 4b1. Characteristic impedance of each of transmission lines 4a1, 4a2, 4a3, 4b1, 4b2, 4b3 is so set that a reflection coefficient of each connection part of the transmission lines becomes equal.SELECTED DRAWING: Figure 1

Description

本発明は、例えばプリント基板に形成された伝送線路の一部区間にインピーダンス不整合部がある場合に、広い周波数範囲で反射の影響を抑えることのできる伝送装置に関するものである。   The present invention relates to a transmission apparatus that can suppress the influence of reflection in a wide frequency range when, for example, an impedance mismatching portion is present in a part of a transmission line formed on a printed circuit board.

プリント基板の配線を用いて高速な信号を伝送する場合、配線の特性インピーダンスが整合していないと、この不整合部において一部の信号が反射し、伝送波形が劣化する要因となる。配線のインピーダンスは、配線電極の断面構造や基板材料により決まる電気パラメータであり、一般的には配線の幅を適切に設計してインピーダンスを管理することにより不整合反射に伴う波形劣化を防止する。   When high-speed signals are transmitted using the wiring of the printed circuit board, if the characteristic impedance of the wiring is not matched, a part of the signal is reflected at the mismatched portion, and the transmission waveform is deteriorated. The impedance of the wiring is an electrical parameter determined by the cross-sectional structure of the wiring electrode and the substrate material. In general, the impedance is managed by appropriately designing the width of the wiring to prevent waveform deterioration due to mismatch reflection.

図９に、プリント基板の一般的な配線構成を示す。プリント基板１上の送信回路５と受信回路６の接続を行うにあたり、送信回路５から受信回路６への信号の伝送路である信号線３ａ，３ｂの途中に基板コネクタ２が実装されている。一般に、基板コネクタ２は、プリント基板１の特性インピーダンスとは異なるため、反射に伴う波形劣化が避けられない。   FIG. 9 shows a general wiring configuration of the printed circuit board. When connecting the transmission circuit 5 and the reception circuit 6 on the printed circuit board 1, the board connector 2 is mounted in the middle of the signal lines 3 a and 3 b that are signal transmission paths from the transmission circuit 5 to the reception circuit 6. In general, since the board connector 2 is different from the characteristic impedance of the printed board 1, waveform deterioration due to reflection is unavoidable.

こうした状況を、配線インピーダンスを配線幅で模擬する形で伝送路をモデル化した例を図１０に示す。図１０では、基板コネクタ２のインピーダンスが低い状況を太い配線幅でモデル化し、インピーダンス不整合部２として表している。配線の特性インピーダンスは配線幅の設計で調整することができる一方、使用するコネクタが決まっている場合は、不整合反射の影響が避けられない状況である。こうした状況においても、広い範囲で反射波形による影響を抑制するための伝送路を構成する手法が課題となる。   FIG. 10 shows an example in which the transmission path is modeled in such a manner that the wiring impedance is simulated by the wiring width. In FIG. 10, a situation where the impedance of the board connector 2 is low is modeled with a thick wiring width, and is represented as the impedance mismatching portion 2. The characteristic impedance of the wiring can be adjusted by designing the wiring width. On the other hand, when the connector to be used is determined, the influence of mismatched reflection is unavoidable. Even in such a situation, a method of configuring a transmission path for suppressing the influence of the reflected waveform over a wide range becomes a problem.

このような課題に対処するため、プリント基板配線等の一部区間にインピーダンス不整合部がある場合、λ／４変成器をインピーダンス不整合部に付加するといった手法が広く知られており、またλ／４ごとにインピーダンスを変化させる手法が用いられていた（例えば、特許文献１参照）。   In order to deal with such a problem, when there is an impedance mismatching part in a part of the printed circuit board wiring or the like, a method of adding a λ / 4 transformer to the impedance mismatching part is widely known. A method of changing the impedance every / 4 has been used (see, for example, Patent Document 1).

特表２０１３−５１３２７４号公報Special table 2013-513274 gazette

しかしながら、λ／４線路を用いた技術では、その長さが四分の一波長となる周波数でしか機能せず、別の周波数では反射が大きくなる場合があり、従って、例えばデジタル伝送といった広帯域に低反射であることが求められる伝送線路では適用が困難であった。   However, the technology using the λ / 4 line only functions at a frequency whose length is a quarter wavelength, and reflection may increase at another frequency. It has been difficult to apply to transmission lines that are required to have low reflection.

この発明は上記のような課題を解決するためになされたもので、広い周波数範囲で反射の影響を抑えることのできる伝送装置を得ることを目的とする。   The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a transmission apparatus that can suppress the influence of reflection in a wide frequency range.

この発明に係る伝送装置は、伝送線路内のインピーダンス不整合区間の前段側と後段側にそれぞれ接続され、インピーダンス不整合区間と同じ遅延時間を持つ二つの伝送線路と、インピーダンス不整合区間と同じ遅延時間を持つ二つの伝送線路にそれぞれ接続され、インピーダンス不整合区間と同じ遅延時間を持つ伝送線路の遅延時間に対して、２ｎ倍（ｎは正の整数）の遅延時間を持ち、かつ、ｎの値が小さいほどインピーダンス不整合区間に近い側に接続された複数の伝送線路とを備え、各伝送線路の特性インピーダンスは、各伝送線路間接続部の反射係数が等しくなるよう設定されたものである。 The transmission apparatus according to the present invention includes two transmission lines connected to the front and rear stages of the impedance mismatch section in the transmission line, having the same delay time as the impedance mismatch section, and the same delay as the impedance mismatch section. It has a delay time of 2 n times (n is a positive integer) with respect to the delay time of the transmission line that is connected to each of the two transmission lines having time and has the same delay time as the impedance mismatch section, and n The smaller the value is, the more the transmission impedance is connected to the side closer to the impedance mismatch section, and the characteristic impedance of each transmission line is set so that the reflection coefficient of each transmission line connection is equal. is there.

この発明の伝送装置は、伝送線路内のインピーダンス不整合区間の前段側と後段側に、インピーダンス不整合区間と同じ遅延時間を持つ伝送線路と、この伝送線路の遅延時間に対して、２ｎ倍（ｎは正の整数）の遅延時間を持ち、かつ、ｎの値が小さいほどインピーダンス不整合区間に近い側に接続された複数の伝送線路とを接続し、各伝送線路の特性インピーダンスを、各伝送線路間接続部の反射係数が等しくなるようにしたので、広い周波数範囲で反射の影響を抑えることができる。 The transmission apparatus according to the present invention has a transmission line having the same delay time as the impedance mismatch section on the front and rear sides of the impedance mismatch section in the transmission line, and 2 n times the delay time of the transmission line. (N is a positive integer), and the smaller the value of n, the more the transmission lines connected to the side closer to the impedance mismatching section are connected, and the characteristic impedance of each transmission line is Since the reflection coefficient of the connection part between transmission lines is made equal, the influence of reflection can be suppressed in a wide frequency range.

この発明の実施の形態１による伝送装置の構成を示す説明図である。It is explanatory drawing which shows the structure of the transmission apparatus by Embodiment 1 of this invention. この発明の実施の形態１による伝送装置の計算例を示す説明図である。It is explanatory drawing which shows the example of a calculation of the transmission apparatus by Embodiment 1 of this invention. この発明の実施の形態１による伝送装置と従来の構成とのシミュレーション例を示す説明図である。It is explanatory drawing which shows the example of a simulation with the transmission apparatus by Embodiment 1 of this invention, and the conventional structure. この発明の実施の形態２による伝送装置の構成を示す説明図である。It is explanatory drawing which shows the structure of the transmission apparatus by Embodiment 2 of this invention. この発明の実施の形態３による伝送装置の構成を示す説明図である。It is explanatory drawing which shows the structure of the transmission apparatus by Embodiment 3 of this invention. この発明の実施の形態４による伝送装置の構成を示す説明図である。It is explanatory drawing which shows the structure of the transmission apparatus by Embodiment 4 of this invention. この発明の実施の形態５による伝送装置の構成を示す説明図である。It is explanatory drawing which shows the structure of the transmission apparatus by Embodiment 5 of this invention. この発明の実施の形態６による伝送装置の構成を示す説明図である。It is explanatory drawing which shows the structure of the transmission apparatus by Embodiment 6 of this invention. プリント基板の一般的な配線構成を示す説明図である。It is explanatory drawing which shows the general wiring structure of a printed circuit board. 図９の構成をモデル化した例を示す説明図である。It is explanatory drawing which shows the example which modeled the structure of FIG.

実施の形態１．
図１は、この発明の実施の形態１による伝送装置の構成を示す説明図である。
図１は図１０に対応して伝送路をモデル化して示しており、プリント基板１上に送信回路５と受信回路６が設けられ、これらの信号を伝送する信号線３ａ，３ｂの途中にインピーダンス不整合区間であるインピーダンス不整合部２が存在している。実施の形態１では、さらに伝送線路内のインピーダンス不整合部２と、送信回路５の出力端に接続される信号線３ａとの間に、特性インピーダンスの異なる伝送線路４ａ１，４ａ２，４ａ３を接続し、また、インピーダンス不整合部２と、受信回路６の入力端に接続される信号線３ｂとの間に、特性インピーダンスの異なる伝送線路４ｂ１，４ｂ２，４ｂ３を接続している。また、各伝送線路の遅延時間は、各伝送線路の長さを変えることで、インピーダンス不整合区間に近い側から順に、インピーダンス不整合区間の遅延時間の１倍、２倍、４倍、…、２ｎ−１倍としている。ここで、ｎは各伝送線路に割り振られた連番であり、インピーダンス不整合区間を０とし、インピーダンス不整合区間に近い側から１，２，３，…となる。 Embodiment 1 FIG.
FIG. 1 is an explanatory diagram showing a configuration of a transmission apparatus according to Embodiment 1 of the present invention.
FIG. 1 shows a transmission line modeled corresponding to FIG. 10. A transmission circuit 5 and a reception circuit 6 are provided on a printed circuit board 1, and impedance is placed in the middle of signal lines 3 a and 3 b for transmitting these signals. There is an impedance mismatching section 2 that is a mismatching section. In the first embodiment, transmission lines 4a1, 4a2, and 4a3 having different characteristic impedances are further connected between the impedance mismatching unit 2 in the transmission line and the signal line 3a connected to the output terminal of the transmission circuit 5. In addition, transmission lines 4b1, 4b2, and 4b3 having different characteristic impedances are connected between the impedance mismatching unit 2 and the signal line 3b connected to the input terminal of the receiving circuit 6. In addition, the delay time of each transmission line is changed by changing the length of each transmission line, so that the delay time of the impedance mismatch section is 1 time, 2 times, 4 times,... 2 n-1 times. Here, n is a serial number assigned to each transmission line, and the impedance mismatch interval is set to 0, and is 1, 2, 3,... From the side close to the impedance mismatch interval.

また、各伝送線路の特性インピーダンスは、各伝送線路間の接続部の反射係数が等しくなるように設定されている。具体的には以下の式（１）を満たすように設定されている。

Figure 2017038133
Moreover, the characteristic impedance of each transmission line is set so that the reflection coefficient of the connection part between each transmission line becomes equal. Specifically, it is set to satisfy the following expression (1).
Figure 2017038133

上式（１）において、Ｎはｎの最大数であり、送信回路５の出力インピーダンスまたは受信回路６の入力インピーダンスとインピーダンス不整合部２の状態とに応じて適宜決定する。例えば、プリント基板に実装する際には、改善度と実装性のトレードオフでシミュレーションなどを実施し決定する。このような構成は、配線長が長くなるシステム、例えば、バックプレーンシステムに適用が可能である。図１の場合はＮ＝４であり、ｎ＝４は信号線３ａ，３ｂを示す。Ｚｎはｎ番目の線路の特性インピーダンスである。ＺＮはＮ番目の線路の特性インピーダンス、すなわち信号線３ａ，３ｂの特性インピーダンスである。Ｚ０はインピーダンス不整合区間の特性インピーダンスである。なお、両端に相当するＺＮは、送信回路５の出力インピーダンスまたは受信回路６の入力インピーダンスと整合する値とし、一般的には５０Ωであることが多い。上式（１）からｎ番目の伝送線路の特性インピーダンスＺｎを計算することができる。計算例を図２に示す。図１及び図２に示す例では、伝送線路４ａ１，４ａ２，４ａ３及び伝送線路４ｂ１，４ｂ２，４ｂ３の特性インピーダンスを、その配線幅を変えることで所望の値としているが、それぞれの伝送線路の誘電体厚で設定してもよく、また、配線幅と誘電体厚の両方の値を変化させて設定してもよい。 In the above formula (1), N is the maximum number of n, and is appropriately determined according to the output impedance of the transmission circuit 5 or the input impedance of the reception circuit 6 and the state of the impedance mismatching unit 2. For example, when mounting on a printed circuit board, a decision is made by performing a simulation or the like with a trade-off between the degree of improvement and mountability. Such a configuration can be applied to a system having a long wiring length, for example, a backplane system. In the case of FIG. 1, N = 4, and n = 4 indicates the signal lines 3a and 3b. Z n is the characteristic impedance of the nth line. Z N is the characteristic impedance of the N-th line, that is, the signal line 3a, the characteristic impedance of 3b. Z 0 is the characteristic impedance in the impedance mismatch section. Note that Z N corresponding to both ends is a value that matches the output impedance of the transmission circuit 5 or the input impedance of the reception circuit 6, and is generally 50Ω in many cases. The characteristic impedance Zn of the nth transmission line can be calculated from the above equation (1). A calculation example is shown in FIG. In the example shown in FIGS. 1 and 2, the characteristic impedances of the transmission lines 4a1, 4a2, 4a3 and the transmission lines 4b1, 4b2, 4b3 are set to desired values by changing their wiring widths. It may be set by the body thickness, or may be set by changing both values of the wiring width and the dielectric thickness.

実施の形態１の伝送装置では、インピーダンス不整合部２の前段側と後段側の伝送線路の各段でそれぞれ式（１）を満たすことにより、各段の不連続部で生じる反射波の大きさをほぼ同じとすることができる。また、伝送線路４ａ１，４ａ２，４ａ３及び伝送線路４ｂ１，４ｂ２，４ｂ３の遅延時間を、インピーダンス不整合部２の遅延時間の１倍、２倍、４倍、…、２ｎ−１倍としているので、各不連続部で生じる反射波の位相が特定の周波数で全てそろうことが無い。また、特定の周波数である二つの反射波が同位相の場合、別の反射波が逆位相で打ち消すような関係となる。具体的に説明すると、Ｚ２が半波長共振（Ｚ３−Ｚ２間不整合による反射と、Ｚ２−Ｚ１間不整合による反射が同位相）する周波数で、Ｚ１がλ／４変成器（Ｚ２−Ｚ１間不整合による反射と、Ｚ１−Ｚ０間不整合による反射が逆位相）として動作するというように、広い周波数に渡って強い反射が生じない構造になる。 In the transmission apparatus according to the first embodiment, the magnitude of the reflected wave generated at the discontinuous portion of each stage is satisfied by satisfying the expression (1) at each stage of the transmission line on the front and rear sides of the impedance mismatching section 2. Can be substantially the same. In addition, the delay times of the transmission lines 4a1, 4a2, 4a3 and the transmission lines 4b1, 4b2, 4b3 are set to 1 time, 2 times, 4 times, ... 2 n-1 times the delay time of the impedance mismatching unit 2. The phases of the reflected waves generated at each discontinuous part are not all aligned at a specific frequency. Further, when two reflected waves having a specific frequency are in phase, another reflected wave cancels out in opposite phase. More specifically, (a reflection by Z 3 -Z 2 between mismatching, reflection by Z 2 -Z 1 between mismatch in phase) Z 2 is a half-wavelength resonance at a frequency, Z 1 is lambda / 4 transformer vessels (and reflection by Z 2 -Z 1 between mismatch, reflection due to mismatch between Z 1 -Z 0 is antiphase) so that it operates as a, becomes strong reflection does not occur structure over a wide frequency.

図３に、シミュレーション例を示す．
図中の破線で示す特性が図１０の反射特性、実線が図１の反射特性である。従来の図１０では特定の周波数（２．５ＧＨｚ及び７．５ＧＨｚ）で強い反射が生じているのに対し、実施の形態１の反射特性では広い周波数範囲でそのような強い反射が生じていないことが確認できる。 Figure 3 shows a simulation example.
The characteristic indicated by the broken line in the figure is the reflection characteristic in FIG. 10, and the solid line is the reflection characteristic in FIG. In FIG. 10 of the related art, strong reflection occurs at specific frequencies (2.5 GHz and 7.5 GHz), whereas in the reflection characteristic of the first embodiment, such strong reflection does not occur in a wide frequency range. Can be confirmed.

以上説明したように、実施の形態１の伝送装置によれば、伝送線路内のインピーダンス不整合区間の前段側と後段側にそれぞれ接続され、インピーダンス不整合区間と同じ遅延時間を持つ二つの伝送線路と、インピーダンス不整合区間と同じ遅延時間を持つ二つの伝送線路にそれぞれ接続され、インピーダンス不整合区間と同じ遅延時間を持つ伝送線路の遅延時間に対して、２ｎ倍（ｎは正の整数）の遅延時間を持ち、かつ、ｎの値が小さいほどインピーダンス不整合区間に近い側に接続された複数の伝送線路とを備え、各伝送線路の特性インピーダンスは、各伝送線路間接続部の反射係数が等しくなるよう設定されたので、広い周波数に渡って強い反射（多くの反射波が同位相）が生じない構造を得ることができ、広帯域で反射を低減することが要求されるデジタル伝送にも適用することができる。 As described above, according to the transmission apparatus of the first embodiment, two transmission lines connected to the front side and the rear side of the impedance mismatch section in the transmission line, respectively, have the same delay time as the impedance mismatch section. And 2 n times (n is a positive integer) with respect to the delay time of the transmission line that is connected to each of the two transmission lines having the same delay time as that of the impedance mismatch section and has the same delay time as that of the impedance mismatch section. And a plurality of transmission lines connected closer to the impedance mismatch section as the value of n is smaller, the characteristic impedance of each transmission line is the reflection coefficient of the connection part between the transmission lines Are set to be equal, it is possible to obtain a structure that does not produce strong reflection over many frequencies (many reflected waves have the same phase) and reduce reflection in a wide band. It can also be applied to digital transmissions that are required.

また、実施の形態１の伝送装置によれば、各伝送線路の特性インピーダンスＺｎは式（１）を満たすようにしたので、各伝送線路間の接続部の反射係数を等しくすることができる。 Further, according to the transmission apparatus of the first embodiment, the characteristic impedance Z n of the transmission line since to satisfy the equation (1), it is possible to equalize the reflection coefficient of the connecting portion between the transmission lines.

また、実施の形態１の伝送装置によれば、各伝送線路の特性インピーダンスの設定を、各伝送線路の配線幅で行うようにしたので、容易に各伝送線路の特性インピーダンスの設定を行うことができる。   Further, according to the transmission apparatus of the first embodiment, the characteristic impedance of each transmission line is set by the wiring width of each transmission line, so that the characteristic impedance of each transmission line can be easily set. it can.

また、実施の形態１の伝送装置によれば、各伝送線路の特性インピーダンスの設定を、各伝送線路の誘電体厚で行うようにしたので、容易に各伝送線路の特性インピーダンスの設定を行うことができる。   In addition, according to the transmission apparatus of the first embodiment, the characteristic impedance of each transmission line is set by the dielectric thickness of each transmission line, so that the characteristic impedance of each transmission line can be easily set. Can do.

実施の形態２．
図４は、実施の形態２の伝送装置の構成を示す説明図である。実施の形態２の伝送装置は、各伝送線路の接続部分を近似曲線の形状とし、これら近似曲線部分の特性インピーダンスを連続的に変化するインピーダンス分布としたものである。
図４において、プリント基板１上に形成された信号線３ａ，３ｂは、実施の形態１と同様である。また、各段の伝送線路４ａ１，４ａ２，４ａ３及び伝送線路４ｂ１，４ｂ２，４ｂ３の遅延時間と特性インピーダンスは実施の形態１と同様である。すなわち、実施の形態２においても、各段の伝送線路の遅延時間がインピーダンス不整合部２の遅延時間の２ｎ−１倍となるよう設定され、かつ、各段の伝送線路の特性インピーダンスが式（１）に従うよう構成されている。 Embodiment 2. FIG.
FIG. 4 is an explanatory diagram illustrating a configuration of the transmission apparatus according to the second embodiment. In the transmission apparatus according to the second embodiment, the connection portion of each transmission line has an approximate curve shape, and the characteristic impedance of these approximate curve portions is an impedance distribution that continuously changes.
In FIG. 4, signal lines 3a and 3b formed on the printed circuit board 1 are the same as those in the first embodiment. The delay times and characteristic impedances of the transmission lines 4a1, 4a2, 4a3 and the transmission lines 4b1, 4b2, 4b3 in each stage are the same as those in the first embodiment. That is, also in the second embodiment, the delay time of each stage transmission line is set to be 2 n-1 times the delay time of the impedance mismatching unit 2, and the characteristic impedance of each stage transmission line is expressed by the equation It is configured to comply with (1).

一方、実施の形態２のインピーダンス不整合部２から伝送線路４ａ１，４ａ２，４ａ３及び伝送線路４ｂ１，４ｂ２，４ｂ３に至る各段の特性インピーダンスが変化する接続部分において、インピーダンス変化を曲線で近似した形状とし、近似曲線部分の伝送インピーダンス分布を連続的に変化させるよう構成している。   On the other hand, in the connection portion where the characteristic impedance of each stage from the impedance mismatching part 2 of the second embodiment to the transmission lines 4a1, 4a2, 4a3 and the transmission lines 4b1, 4b2, 4b3 changes, the shape approximating the impedance change with a curve The transmission impedance distribution in the approximate curve portion is continuously changed.

以上説明したように、実施の形態２の伝送装置によれば、各伝送線路の接続部分を近似曲線の形状とし、近似曲線部分の特性インピーダンスは連続的に変化するインピーダンス分布であるようにしたので、実施の形態１と同様の効果が得られるのに加え、急峻なインピーダンス変化が無くなるため、製造上の不具合が発生しにくいという効果が得られる。   As described above, according to the transmission device of the second embodiment, the connection portion of each transmission line is formed in the shape of an approximate curve, and the characteristic impedance of the approximate curve portion is an impedance distribution that changes continuously. In addition to the same effects as those of the first embodiment, since there is no steep impedance change, there is an effect that manufacturing defects are hardly generated.

実施の形態３．
図５は、実施の形態３の伝送装置の構成を示す説明図である。実施の形態３の伝送装置は、各伝送線路の接続部分をテーパ状とし、これらテーパ状部分の特性インピーダンスを連続的に変化するインピーダンス分布としたものである。
図５において、プリント基板１上に形成された信号線３ａ，３ｂは、実施の形態１と同様である。また、各段の伝送線路４ａ１，４ａ２，４ａ３及び伝送線路４ｂ１，４ｂ２，４ｂ３の遅延時間と特性インピーダンスは実施の形態１と同様である。すなわち、実施の形態３においても、各段の伝送線路の遅延時間がインピーダンス不整合部２の遅延時間の２ｎ−１倍となるよう設定され、かつ、各段の伝送線路の特性インピーダンスが式（１）に従うよう構成されている。 Embodiment 3 FIG.
FIG. 5 is an explanatory diagram illustrating a configuration of the transmission apparatus according to the third embodiment. In the transmission apparatus according to the third embodiment, the connection portions of the transmission lines are tapered, and the characteristic impedance of these tapered portions is an impedance distribution that continuously changes.
In FIG. 5, signal lines 3a and 3b formed on the printed circuit board 1 are the same as those in the first embodiment. The delay times and characteristic impedances of the transmission lines 4a1, 4a2, 4a3 and the transmission lines 4b1, 4b2, 4b3 in each stage are the same as those in the first embodiment. That is, also in the third embodiment, the delay time of each stage transmission line is set to be 2 n-1 times the delay time of the impedance mismatching unit 2, and the characteristic impedance of each stage transmission line is expressed by the equation It is configured to comply with (1).

一方、実施の形態３のインピーダンス不整合部２から伝送線路４ａ１，４ａ２，４ａ３及び伝送線路４ｂ１，４ｂ２，４ｂ３に至る各段の特性インピーダンスが変化する接続部分において、配線幅をテーパ状とし、テーパ状部分の伝送インピーダンスを連続的に変化させるよう構成している。   On the other hand, in the connection portion where the characteristic impedance of each stage from the impedance mismatching part 2 of the third embodiment to the transmission lines 4a1, 4a2, 4a3 and the transmission lines 4b1, 4b2, 4b3 changes, the wiring width is tapered and tapered. The transmission impedance of the shaped portion is continuously changed.

以上説明したように、実施の形態３の伝送装置によれば、各伝送線路の接続部分をテーパ状とし、テーパ状部分の特性インピーダンスは連続的に変化するインピーダンス分布であるようにしたので、実施の形態１と同様の効果が得られるのに加え、急峻なインピーダンス変化が無くなるため、製造上の不具合が発生しにくいという効果が得られる。さらに、テーパ状の構成で接続したため、従来の基板パターン設計ツールによって容易に設計できるという利点が得られる。   As described above, according to the transmission apparatus of the third embodiment, the connection portion of each transmission line is tapered, and the characteristic impedance of the tapered portion is an impedance distribution that changes continuously. In addition to obtaining the same effect as in the first embodiment, since there is no steep impedance change, there is obtained an effect that a manufacturing defect is hardly generated. Further, since the connection is made in a tapered configuration, there is an advantage that it can be easily designed by a conventional substrate pattern design tool.

実施の形態４．
実施の形態１〜３では、シングルエンドの配線で伝送路を構成した例を示したが、伝送路を１対の差動配線により構成してもよく、これを実施の形態４として以下説明する。 Embodiment 4 FIG.
In the first to third embodiments, an example in which the transmission path is configured by single-ended wiring has been described. However, the transmission path may be configured by a pair of differential wirings, which will be described below as a fourth embodiment. .

図６は、実施の形態４に係る伝送装置の構成を示す説明図である。ここで、インピーダンス不整合部２と、伝送線路４ａ１，４ａ２，４ａ３及び伝送線路４ｂ１，４ｂ２，４ｂ３と、信号線３ａ，３ｂとの多段構成における遅延時間及び特性インピーダンスの関係は実施の形態１と同様である。また、実施の形態４における差動線路の特性インピーダンスは、１対のペア配線の配線間隙を変更することにより管理されている。   FIG. 6 is an explanatory diagram showing the configuration of the transmission apparatus according to the fourth embodiment. Here, the relationship between the delay time and the characteristic impedance in the multistage configuration of the impedance mismatching section 2, the transmission lines 4a1, 4a2, 4a3, the transmission lines 4b1, 4b2, 4b3, and the signal lines 3a, 3b is the same as that of the first embodiment. It is the same. Further, the characteristic impedance of the differential line in the fourth embodiment is managed by changing the wiring gap between a pair of pair wirings.

実施の形態４では、信号線３ａと伝送線路４ａ１，４ａ２，４ａ３、信号線３ｂと伝送線路４ｂ１，４ｂ２，４ｂ３の各段の配線は、特性インピーダンスが式（１）に従うよう構成している。これにより、差動線路においても、各段の接合部にて生じる反射波の大きさが同一となり、広い周波数にわたって反射波を低いレベルに抑制することができる。   In the fourth embodiment, the wiring of each stage of the signal line 3a and the transmission lines 4a1, 4a2, and 4a3 and the signal line 3b and the transmission lines 4b1, 4b2, and 4b3 is configured such that the characteristic impedance conforms to the equation (1). Thereby, also in a differential line, the magnitude | size of the reflected wave which arises in the junction part of each step becomes the same, and a reflected wave can be suppressed to a low level over a wide frequency.

なお、本実施の形態では、差動配線の特性インピーダンスの調整手法として、差動配線の配線間隙で管理する手法を示したが、配線幅や誘電体厚を変更する方法を利用できることはいうまでもない。   In the present embodiment, as a method of adjusting the characteristic impedance of the differential wiring, a method of managing the wiring gap of the differential wiring is shown. However, it goes without saying that a method of changing the wiring width and the dielectric thickness can be used. Nor.

以上説明したように、実施の形態４の伝送装置によれば、各伝送線路は差動線路であり、各伝送線路の特性インピーダンスは差動インピーダンスであるようにしたので、伝送線路が差動線路である場合に、広い周波数に渡って強い反射（多くの反射波が同位相）が生じない構造を得ることができる。   As described above, according to the transmission apparatus of the fourth embodiment, each transmission line is a differential line, and the characteristic impedance of each transmission line is a differential impedance. In this case, it is possible to obtain a structure in which strong reflection (a large number of reflected waves have the same phase) does not occur over a wide frequency range.

また、実施の形態４の伝送装置によれば、各伝送線路の特性インピーダンスを差動線路間の間隔で設定するようにしたので、差動線路においても広い周波数に渡って強い反射を防止できる効果を得られる。   Further, according to the transmission device of the fourth embodiment, since the characteristic impedance of each transmission line is set by the interval between the differential lines, the differential line can also prevent strong reflection over a wide frequency range. Can be obtained.

実施の形態５．
図７は、実施の形態５に係る伝送装置の構成を示す説明図である。実施の形態５の伝送装置は、インピーダンス不整合区間に最も遠い側に接続された伝送線路の特性インピーダンスを、各伝送線路を介して信号を送出する送信回路の出力インピーダンスと等しくしたものである。
図７において、プリント基板１上に形成された信号線３ａ，３ｂは、インピーダンス不整合区間に最も遠い側に接続された伝送線路であり、実施の形態１と同様に送信回路５の出力インピーダンスまたは受信回路６の入力インピーダンスと整合する値に設定されている。また、各段の伝送線路４ａ１，４ａ２，４ａ３及び伝送線路４ｂ１，４ｂ２，４ｂ３の遅延時間と特性インピーダンスは実施の形態１と同様である。すなわち、実施の形態５においても、各段の伝送線路は遅延時間がインピーダンス不整合部２の遅延時間の２ｎ−１倍となるよう設定され、かつ、各段の伝送線路の特性インピーダンスが式（１）に従うよう構成されている。さらに、実施の形態５では、伝送路の一端に接続された、伝送路を駆動する送信回路５の出力インピーダンスは出力抵抗５１により調整されるよう構成されている。 Embodiment 5 FIG.
FIG. 7 is an explanatory diagram showing the configuration of the transmission apparatus according to the fifth embodiment. In the transmission apparatus according to the fifth embodiment, the characteristic impedance of the transmission line connected to the farthest side in the impedance mismatching section is made equal to the output impedance of the transmission circuit that sends a signal through each transmission line.
In FIG. 7, signal lines 3 a and 3 b formed on the printed circuit board 1 are transmission lines connected to the farthest side in the impedance mismatching section, and the output impedance or the transmission circuit 5 or the like as in the first embodiment. The value is set to match the input impedance of the receiving circuit 6. The delay times and characteristic impedances of the transmission lines 4a1, 4a2, 4a3 and the transmission lines 4b1, 4b2, 4b3 in each stage are the same as those in the first embodiment. That is, also in the fifth embodiment, the transmission line of each stage is set so that the delay time is 2 n-1 times the delay time of the impedance mismatching unit 2, and the characteristic impedance of the transmission line of each stage is expressed by the equation It is configured to comply with (1). Furthermore, in the fifth embodiment, the output impedance of the transmission circuit 5 that is connected to one end of the transmission line and drives the transmission line is adjusted by the output resistor 51.

上記の構成において、送信回路５に接続される信号線３ａの特性インピーダンスは、出力抵抗５１の抵抗値と同一となる様に構成されている。これにより、送信回路５の出力インピーダンスと信号線３ａの特性インピーダンスが等しくなり、送信回路５と信号線３ａの接続部において、不整合反射に伴う波形劣化がなくなり、良好な信号伝送が可能となる。   In the above configuration, the characteristic impedance of the signal line 3 a connected to the transmission circuit 5 is configured to be the same as the resistance value of the output resistor 51. As a result, the output impedance of the transmission circuit 5 is equal to the characteristic impedance of the signal line 3a, and waveform deterioration due to mismatched reflection is eliminated at the connection portion between the transmission circuit 5 and the signal line 3a, thereby enabling good signal transmission. .

以上説明したように、実施の形態５の伝送装置によれば、インピーダンス不整合区間に最も遠い側に接続された伝送線路の特性インピーダンスを、各伝送線路を介して信号を送出する送信回路の出力インピーダンスと等しくしたので、信号の出力回路と伝送路の接続部において、不整合反射に伴う波形劣化を無くすことができ、良好な信号伝送が可能となる。   As described above, according to the transmission apparatus of the fifth embodiment, the characteristic impedance of the transmission line connected to the farthest side in the impedance mismatch section is output from the transmission circuit that sends a signal through each transmission line. Since it is equal to the impedance, waveform deterioration due to mismatched reflection can be eliminated at the connection portion between the signal output circuit and the transmission path, and good signal transmission is possible.

実施の形態６．
図８は、実施の形態６に係る伝送装置の構成を示す説明図である。実施の形態６の伝送装置は、インピーダンス不整合区間に最も遠い側に接続された伝送線路の特性インピーダンスを、各伝送線路を介して信号を受信する受信回路の入力インピーダンスと等しくしたものである。
図８において、プリント基板１上に形成された信号線３ａ，３ｂは、インピーダンス不整合区間に最も遠い側に接続された伝送線路であり、実施の形態１と同様に送信回路５の出力インピーダンスまたは受信回路６の入力インピーダンスと整合する値に設定されている。また、各段の伝送線路４ａ１，４ａ２，４ａ３及び伝送線路４ｂ１，４ｂ２，４ｂ３の遅延時間と特性インピーダンスは実施の形態１と同様である。すなわち、実施の形態６においても、各段の伝送線路は遅延時間がインピーダンス不整合部２の遅延時間の２ｎ−１倍となるよう設定され、かつ、各段の伝送線路の特性インピーダンスが式（１）に従うよう構成されている。さらに、実施の形態６では、伝送路の一端に接続された、伝送路を伝搬した信号を受信する受信回路６の入力インピーダンスは終端抵抗６１により調整されるよう構成されている。 Embodiment 6 FIG.
FIG. 8 is an explanatory diagram showing the configuration of the transmission apparatus according to the sixth embodiment. In the transmission device of the sixth embodiment, the characteristic impedance of the transmission line connected to the farthest side in the impedance mismatch section is made equal to the input impedance of the receiving circuit that receives a signal via each transmission line.
In FIG. 8, signal lines 3a and 3b formed on the printed circuit board 1 are transmission lines connected to the side farthest from the impedance mismatching section, and the output impedance of the transmission circuit 5 or the same as in the first embodiment. The value is set to match the input impedance of the receiving circuit 6. The delay times and characteristic impedances of the transmission lines 4a1, 4a2, 4a3 and the transmission lines 4b1, 4b2, 4b3 in each stage are the same as those in the first embodiment. That is, also in the sixth embodiment, the transmission line of each stage is set so that the delay time is 2 n-1 times the delay time of the impedance mismatching unit 2, and the characteristic impedance of the transmission line of each stage is expressed by the equation It is configured to comply with (1). Furthermore, in the sixth embodiment, the input impedance of the receiving circuit 6 connected to one end of the transmission line and receiving the signal propagated through the transmission line is adjusted by the termination resistor 61.

上記の構成において、受信回路６に接続される信号線３ｂの特性インピーダンスは、終端抵抗６１の抵抗値と同一となる様に構成されている。これにより、受信回路６の入力インピーダンスと信号線３ｂの特性インピーダンスが等しくなり、受信回路６と信号線３ｂの接続部において、不整合反射に伴う波形劣化がなくなり、良好な信号伝送が可能となる。   In the above configuration, the characteristic impedance of the signal line 3 b connected to the receiving circuit 6 is configured to be the same as the resistance value of the termination resistor 61. As a result, the input impedance of the receiving circuit 6 and the characteristic impedance of the signal line 3b become equal, and there is no waveform deterioration due to mismatched reflection at the connection portion between the receiving circuit 6 and the signal line 3b, and good signal transmission is possible. .

以上説明したように、実施の形態６の伝送装置によれば、インピーダンス不整合区間に最も遠い側に接続された伝送線路の特性インピーダンスを、各伝送線路を介して信号を受信する受信回路の入力インピーダンスと等しくしたので、受信回路と伝送路の接続部において、不整合反射に伴う波形劣化を無くすことができ、良好な信号伝送が可能となる。   As described above, according to the transmission apparatus of the sixth embodiment, the characteristic impedance of the transmission line connected to the farthest side in the impedance mismatch section is input to the receiving circuit that receives a signal via each transmission line. Since it is equal to the impedance, waveform deterioration due to mismatched reflection can be eliminated at the connection portion between the receiving circuit and the transmission path, and good signal transmission is possible.

なお、本願発明はその発明の範囲内において、各実施の形態の自由な組み合わせ、あるいは各実施の形態の任意の構成要素の変形、もしくは各実施の形態において任意の構成要素の省略が可能である。   In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

１ プリント基板、２ インピーダンス不整合部、３ａ，３ｂ 信号線、４ａ１，４ａ２，４ａ３，４ｂ１，４ｂ２，４ｂ３ 伝送線路、５ 送信回路、６ 受信回路、５１ 出力抵抗、６１ 終端抵抗。   DESCRIPTION OF SYMBOLS 1 Printed circuit board, 2 Impedance mismatch part, 3a, 3b Signal line, 4a1, 4a2, 4a3, 4b1, 4b2, 4b3 Transmission line, 5 Transmission circuit, 6 Reception circuit, 51 Output resistance, 61 Termination resistance

Claims (10)

伝送線路内のインピーダンス不整合区間の前段側と後段側にそれぞれ接続され、前記インピーダンス不整合区間と同じ遅延時間を持つ二つの伝送線路と、
前記インピーダンス不整合区間と同じ遅延時間を持つ二つの伝送線路にそれぞれ接続され、当該インピーダンス不整合区間と同じ遅延時間を持つ伝送線路の遅延時間に対して、２ｎ倍（ｎは正の整数）の遅延時間を持ち、かつ、ｎの値が小さいほど前記インピーダンス不整合区間に近い側に接続された複数の伝送線路とを備え、
前記各伝送線路の特性インピーダンスは、当該各伝送線路間接続部の反射係数が等しくなるよう設定されたことを特徴とする伝送装置。 Two transmission lines connected respectively to the front side and the rear side of the impedance mismatch section in the transmission line, and having the same delay time as the impedance mismatch section,
2 n times (n is a positive integer) with respect to the delay time of the transmission line that is connected to each of the two transmission lines having the same delay time as the impedance mismatch section and has the same delay time as the impedance mismatch section And a plurality of transmission lines connected to the side closer to the impedance mismatch section as the value of n is smaller,
The characteristic impedance of each transmission line is set so that the reflection coefficient of each connection part between the transmission lines is equal. 前記各伝送線路の特性インピーダンスＺｎは、
Figure 2017038133

ただし、Ｎはｎの最大値
を満たすことを特徴とする請求項１記載の伝送装置。 The characteristic impedance Z n of each transmission line is
Figure 2017038133

2. The transmission apparatus according to claim 1, wherein N satisfies a maximum value of n. 前記各伝送線路の接続部分を近似曲線の形状とし、当該近似曲線部分の特性インピーダンスは連続的に変化するインピーダンス分布であることを特徴とする請求項１または請求項２記載の伝送装置。   The transmission apparatus according to claim 1 or 2, wherein a connection portion of each transmission line has a shape of an approximate curve, and a characteristic impedance of the approximate curve portion is an impedance distribution that changes continuously. 前記各伝送線路の特性インピーダンスの設定を、当該各伝送線路の配線幅で行うことを特徴とする請求項１から請求項３のうちのいずれか１項記載の伝送装置。   The transmission device according to any one of claims 1 to 3, wherein the setting of the characteristic impedance of each transmission line is performed by the wiring width of each transmission line. 前記各伝送線路の特性インピーダンスの設定を、当該各伝送線路の誘電体厚で行うことを特徴とする請求項１から請求項４のうちのいずれか１項記載の伝送装置。   The transmission apparatus according to any one of claims 1 to 4, wherein the characteristic impedance of each transmission line is set by a dielectric thickness of each transmission line. 前記各伝送線路の接続部分をテーパ状とし、当該テーパ状部分の特性インピーダンスは連続的に変化するインピーダンス分布であることを特徴とする請求項１、請求項２、請求項４及び請求項５のうちのいずれか１項記載の伝送装置。   The connection part of each said transmission line is made into a taper shape, The characteristic impedance of the said taper part is the impedance distribution which changes continuously, The claim 1, 2, 4, and 5 of Claim 5 characterized by the above-mentioned. The transmission apparatus of any one of them. 前記各伝送線路は差動線路であり、当該各伝送線路の特性インピーダンスは差動インピーダンスであることを特徴とする請求項１から請求項６のうちのいずれか１項記載の伝送装置。   Each transmission line is a differential line, The characteristic impedance of each said transmission line is a differential impedance, The transmission apparatus of any one of Claims 1-6 characterized by the above-mentioned. 前記各伝送線路の特性インピーダンスを前記差動線路間の間隔で設定することを特徴とする請求項７記載の伝送装置。   8. The transmission apparatus according to claim 7, wherein a characteristic impedance of each transmission line is set by an interval between the differential lines. 前記インピーダンス不整合区間に最も遠い側に接続された伝送線路の特性インピーダンスを、前記各伝送線路を介して信号を送出する送信回路の出力インピーダンスと等しくしたことを特徴とする請求項１から請求項８のうちのいずれか１項記載の伝送装置。   The characteristic impedance of the transmission line connected to the side farthest from the impedance mismatching section is made equal to the output impedance of a transmission circuit that sends a signal through each transmission line. The transmission device according to claim 1. 前記インピーダンス不整合区間に最も遠い側に接続された伝送線路の特性インピーダンスを、前記各伝送線路を介して信号を受信する受信回路の出力インピーダンスと等しくしたことを特徴とする請求項１から請求項８のうちのいずれか１項記載の伝送装置。   The characteristic impedance of the transmission line connected to the side farthest from the impedance mismatching section is made equal to the output impedance of a receiving circuit that receives a signal through each transmission line. The transmission device according to claim 1.
JP2015157067A 2015-08-07 2015-08-07 Transmission equipment Active JP6385316B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2015157067A JP6385316B2 (en) 2015-08-07 2015-08-07 Transmission equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015157067A JP6385316B2 (en) 2015-08-07 2015-08-07 Transmission equipment

Publications (2)

Publication Number Publication Date
JP2017038133A true JP2017038133A (en) 2017-02-16
JP6385316B2 JP6385316B2 (en) 2018-09-05

Family

ID=58047975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015157067A Active JP6385316B2 (en) 2015-08-07 2015-08-07 Transmission equipment

Country Status (1)

Country Link
JP (1) JP6385316B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020115978A1 (en) * 2018-12-06 2020-06-11 ソニーセミコンダクタソリューションズ株式会社 Transmission device, printed wiring board, and information apparatus
CN111696959A (en) * 2020-06-19 2020-09-22 安徽大学 Millimeter wave broadband matching structure of ball grid array in wafer level packaging and design method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020144740A1 (en) 2019-01-08 2020-07-16 三菱電機株式会社 Transmission path design assistance device, transmission path design assistance method, and program

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001134355A (en) * 1999-11-02 2001-05-18 Nec Corp Signal transmission system
JP2014106699A (en) * 2012-11-27 2014-06-09 Mitsubishi Electric Corp Bus system
US8884644B1 (en) * 2007-06-18 2014-11-11 Marvell Israel (M.I.S.L) Ltd. Impedance discontinuity compensator for electronic packages

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001134355A (en) * 1999-11-02 2001-05-18 Nec Corp Signal transmission system
US8884644B1 (en) * 2007-06-18 2014-11-11 Marvell Israel (M.I.S.L) Ltd. Impedance discontinuity compensator for electronic packages
JP2014106699A (en) * 2012-11-27 2014-06-09 Mitsubishi Electric Corp Bus system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
D.POZER, "MICROWAVE ENGINEERING", vol. Second Edition, JPN6018026210, 22 July 1999 (1999-07-22), pages 277 - 278, ISSN: 0003835280 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020115978A1 (en) * 2018-12-06 2020-06-11 ソニーセミコンダクタソリューションズ株式会社 Transmission device, printed wiring board, and information apparatus
US12027743B2 (en) 2018-12-06 2024-07-02 Sony Semiconductor Solutions Corporation Transmission apparatus, printed circuit board, and information appliance
CN111696959A (en) * 2020-06-19 2020-09-22 安徽大学 Millimeter wave broadband matching structure of ball grid array in wafer level packaging and design method
CN111696959B (en) * 2020-06-19 2022-07-01 安徽大学 Millimeter wave broadband matching structure of ball grid array in wafer level packaging and design method

Also Published As

Publication number Publication date
JP6385316B2 (en) 2018-09-05

Similar Documents

Publication Publication Date Title
US8428155B2 (en) Printed circuit board
JP2008294837A (en) Signal transmission circuit and system
JP6385316B2 (en) Transmission equipment
WO2012133755A1 (en) Transmission system and method for constructing backplane system
JP2016029785A (en) Communication system
CN103682545B (en) Directional coupler and method for designing thereof
US9768993B2 (en) Multiband equalizer, error rate measurement system using the same, error rate measurement device, and path selection method
CN104039075A (en) Pcb circuit
JP4739178B2 (en) Signal equalizer
US20140285283A1 (en) Galvanically Isolated, Directional Coupler
JP2016052111A (en) Impedance converter
Gazda et al. Time domain analysis of a wideband common-mode suppression filter for bent interconnects
TW201311064A (en) Printed circuit board
JP2007150803A (en) Impedance transformer
JP2009055284A (en) Waveform equalizing circuit
JP2010268154A (en) Signal equalizer
JP6379754B2 (en) Printed wiring board
JP6656494B2 (en) Signal transmission system
KR20150057673A (en) Directional coupler device with high isolation characteristics
JP2016207834A (en) Printed-circuit board
TWI566654B (en) Circuit topology for multiple loads
JP7227662B1 (en) Electromagnetic interference reduction device and electric circuit design method
JP5487779B2 (en) Printed wiring board and printed wiring method
US9236645B2 (en) Serpentine delay line structure
JP6389655B2 (en) Printed circuit boards and electronic equipment

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20171005

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20180710

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20180807

R150 Certificate of patent or registration of utility model

Ref document number: 6385316

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250