JP2017034193A - Wiring board and manufacturing method therefor, and electronic apparatus - Google Patents

Wiring board and manufacturing method therefor, and electronic apparatus Download PDF

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JP2017034193A
JP2017034193A JP2015155433A JP2015155433A JP2017034193A JP 2017034193 A JP2017034193 A JP 2017034193A JP 2015155433 A JP2015155433 A JP 2015155433A JP 2015155433 A JP2015155433 A JP 2015155433A JP 2017034193 A JP2017034193 A JP 2017034193A
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hole
insulating
wiring board
conductive
conductive portion
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JP6586814B2 (en
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秀明 長岡
Hideaki Nagaoka
秀明 長岡
赤星 知幸
Tomoyuki Akaboshi
知幸 赤星
水谷 大輔
Daisuke Mizutani
大輔 水谷
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Fujitsu Ltd
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Fujitsu Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable wiring board by, by taking account of thermal expansion of an insulation material filling a first through-hole in a first insulation part and the thermal expansion of a second insulation part, reducing stress load on a third conductive part resulting mainly from the thermal expansion of the latter together with stress load on a second conductive part resulting mainly from the thermal expansion of the former, thereby preventing fracture in both as much as possible, and to provide a manufacturing method for the wiring board, and to provide an electronic apparatus.SOLUTION: A wiring board comprises: a core substrate 11 having a through-hole 11a; a conductive film 21 formed on the internal wall of the through-hole 11a; resin 22 filling the through-hole 11a via the conductive film 21; an insulation film 23 formed on the core substrate 11; a land 24 formed in the insulation film 23, electrically connected with the conductive film 21, and having a through-hole 24a on the resin 22; and a veer 26 electrically connected with the land 24 within the insulation film 23.SELECTED DRAWING: Figure 1

Description

本発明は、配線基板及びその製造方法、並びに電子装置に関するものである。   The present invention relates to a wiring board, a manufacturing method thereof, and an electronic device.

配線基板としては、例えば図10に示すように、絶縁層又は基板等の絶縁部、例えばコア基板101を貫通する貫通電極102を有するものがある。貫通電極102は、コア基板101に形成された貫通孔101aの内壁を導電膜111で覆い、貫通孔101a内を導電膜111を介して樹脂112で埋め込んで形成される。配線基板では、コア基板101の上面及び下面にそれぞれビルドアップ層103が積層され、各ビルドアップ層103の絶縁膜113内には、導電膜111と接続された導電体であるランド114、その上方のランド115、ランド114とランド115とを接続するビア116が形成されている。   As a wiring substrate, for example, as shown in FIG. 10, there is an insulating layer or an insulating part such as a substrate, for example, one having a through electrode 102 that penetrates a core substrate 101. The through electrode 102 is formed by covering the inner wall of the through hole 101 a formed in the core substrate 101 with the conductive film 111 and filling the through hole 101 a with the resin 112 through the conductive film 111. In the wiring board, build-up layers 103 are respectively laminated on the upper surface and the lower surface of the core substrate 101, and in the insulating film 113 of each build-up layer 103, there are lands 114 that are conductors connected to the conductive film 111, and thereabove. Land 115, and via 116 connecting land 114 and land 115 are formed.

特開2000−49458号公報JP 2000-49458 A 特開2003−218529号公報JP 2003-218529 A 特開2015−126053号公報JP2015-126053A

図10のような貫通電極102を有する配線基板では、用いられる材料、即ち絶縁材料、導電材料及び樹脂材料に熱膨張率差が存在する。樹脂112は比較的大きく熱膨張し、その後の冷却で収縮する。そのため、コア基板101の導電膜111及び樹脂112の上にランド114を形成すると、図11のように、貫通孔101a内の樹脂112の膨張及び収縮に起因してランド114に応力が印加され(円C内に示す)、ランド114に破断が生じる懸念がある。   In the wiring board having the through electrode 102 as shown in FIG. 10, there is a difference in thermal expansion coefficient between the materials used, that is, the insulating material, the conductive material, and the resin material. The resin 112 is relatively large in thermal expansion and contracts by subsequent cooling. Therefore, when the land 114 is formed on the conductive film 111 and the resin 112 of the core substrate 101, stress is applied to the land 114 due to the expansion and contraction of the resin 112 in the through hole 101a as shown in FIG. There is a concern that the land 114 may break.

本発明は、第1絶縁部の第1貫通孔内を埋め込む絶縁材の熱膨張及び第2絶縁部の熱膨張を考慮して、主に前者の熱膨張に起因する第2導電部の応力負荷と共に、主に後者の熱膨張に起因する第3導電部の応力負荷を軽減して双方の破断を可及的に防止し、信頼性の高い配線基板及びその製造方法、並びに電子装置を提供することを目的とする。   The present invention considers the thermal expansion of the insulating material embedded in the first through hole of the first insulating portion and the thermal expansion of the second insulating portion, and mainly stress load of the second conductive portion due to the former thermal expansion. In addition, a highly reliable wiring board, a method of manufacturing the same, and an electronic device are provided by reducing the stress load on the third conductive portion mainly caused by the latter thermal expansion and preventing the breakage of both as much as possible. For the purpose.

1つの態様として、配線基板は、第1貫通孔を有する第1絶縁部と、前記第1貫通孔の内壁に形成された第1導電部と、前記第1貫通孔を前記第1導電部を介して埋め込む絶縁材と、前記第1絶縁部上に形成された第2絶縁部と、前記第2絶縁部内に形成されて前記第1導電部と接続されており、前記絶縁材上に第2貫通孔を有する第2導電部と、前記第2絶縁部内で前記第2導電部と接続されている第3導電部とを含む。   As one aspect, the wiring board includes a first insulating part having a first through hole, a first conductive part formed on an inner wall of the first through hole, and the first through part as the first conductive part. An insulating material embedded therein, a second insulating portion formed on the first insulating portion, a second insulating portion formed in the second insulating portion and connected to the first conductive portion, and a second on the insulating material A second conductive part having a through hole; and a third conductive part connected to the second conductive part in the second insulating part.

1つの態様として、配線基板の製造方法は、第1絶縁部に第1貫通孔を形成する工程と、前記第1貫通孔の内壁に第1導電部を形成する工程と、前記第1貫通孔を前記第1導電部を介して絶縁材で埋め込む工程と、前記第1絶縁部上に、前記第1導電部と接続される第2導電部を形成する工程と、前記第2導電部に、前記絶縁材の表面の一部を露出させる第2貫通孔を形成する工程と、前記第1絶縁部上に、前記第2導電部を覆って前記第2貫通孔を埋め込む第2絶縁部を形成する工程と、前記第2絶縁部に、前記第2導電部と接続される第3導電部を形成する工程とを含む。   As one aspect, a method for manufacturing a wiring board includes a step of forming a first through hole in a first insulating portion, a step of forming a first conductive portion on an inner wall of the first through hole, and the first through hole. Embedded with an insulating material through the first conductive portion, forming a second conductive portion connected to the first conductive portion on the first insulating portion, and in the second conductive portion, Forming a second through hole exposing a part of the surface of the insulating material; and forming a second insulating portion on the first insulating portion so as to cover the second conductive portion and bury the second through hole. And a step of forming a third conductive portion connected to the second conductive portion in the second insulating portion.

1つの態様として、電子装置は、配線基板と、前記配線基板に搭載された電子部品とを備え、前記配線基板は、第1貫通孔を有する第1絶縁部と、前記第1貫通孔の内壁に形成された第1導電部と、前記第1貫通孔を前記第1導電部を介して埋め込む絶縁材と、前記第1絶縁部上に形成された第2絶縁部と、前記第2絶縁部内に形成されて前記第1導電部と接続されており、前記絶縁材上に第2貫通孔を有する第2導電部と、前記第2絶縁部内で前記第2導電部と接続されている第3導電部とを含む。   As one aspect, an electronic device includes a wiring board and an electronic component mounted on the wiring board, and the wiring board includes a first insulating portion having a first through hole, and an inner wall of the first through hole. A first conductive part formed on the first conductive part, an insulating material filling the first through-hole through the first conductive part, a second insulating part formed on the first insulating part, and in the second insulating part And a second conductive part having a second through hole on the insulating material, and a third conductive part connected to the second conductive part in the second insulating part. A conductive portion.

上記の諸態様によれば、第1絶縁部の第1貫通孔内を埋め込む絶縁材の熱膨張及び第2絶縁部の熱膨張を考慮して、主に前者の熱膨張に起因する第2導電部の応力負荷と共に、主に後者の熱膨張に起因する第3導電部の応力負荷を軽減して双方の破断を可及的に防止し、信頼性の高い配線基板及び電子装置が実現する。   According to the above aspects, in consideration of the thermal expansion of the insulating material filling the first through hole of the first insulating portion and the thermal expansion of the second insulating portion, the second conductivity mainly resulting from the thermal expansion of the former. In addition to the stress load on the part, the stress load on the third conductive part mainly due to the latter thermal expansion is reduced to prevent the breakage of both as much as possible, thereby realizing a highly reliable wiring board and electronic device.

第1の実施形態による配線基板の主要構成を示す一部断面図である。It is a partial cross section figure which shows the main structures of the wiring board by 1st Embodiment. 第1の実施形態による配線基板の奏する作用効果を説明するための一部断面図である。It is a partial cross section for demonstrating the effect which the wiring board by 1st Embodiment show | plays. 第1の実施形態による配線基板の製造方法を工程順に示すフロー図である。It is a flowchart which shows the manufacturing method of the wiring board by 1st Embodiment to process order. 第1の実施形態による配線基板の製造方法を工程順に示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing method of the wiring board by 1st Embodiment to process order. 図4に引き続き、第1の実施形態による配線基板の製造方法を工程順に示す概略断面図である。FIG. 5 is a schematic cross-sectional view subsequent to FIG. 4, showing the method of manufacturing the wiring board according to the first embodiment in the order of steps. 第1の本実施形態の比較例による配線基板の主要構成及びシミュレーション解析結果を示す模式図である。It is a schematic diagram which shows the main structure and simulation analysis result of the wiring board by the comparative example of 1st this embodiment. 第1の本実施形態による配線基板の主要構成及びシミュレーション解析結果を示す模式図である。It is a schematic diagram which shows the main structure and simulation analysis result of the wiring board by 1st this embodiment. 第2の実施形態による電子装置の主要構成を示す一部断面図である。It is a partial cross section figure which shows the main structures of the electronic device by 2nd Embodiment. 第2の実施形態の変形例による電子装置の主要構成を示す一部断面図である。It is a partial cross section figure which shows the main structures of the electronic device by the modification of 2nd Embodiment. 従来の配線基板の主要構成を示す一部断面図である。It is a partial cross section figure which shows the main structures of the conventional wiring board. 従来の配線基板の課題を説明するための一部断面図である。It is a partial cross section for demonstrating the subject of the conventional wiring board.

以下、配線基板及び電子装置の諸実施形態について、図面を参照しながら詳細に説明する。   Hereinafter, embodiments of a wiring board and an electronic device will be described in detail with reference to the drawings.

(第1の実施形態)
本実施形態では、配線基板及びその製造方法を開示する。
(First embodiment)
In the present embodiment, a wiring board and a manufacturing method thereof are disclosed.

−配線基板の概略構成−
図1は、第1の実施形態による配線基板の主要構成を示す一部断面図である。
この配線基板は、第1絶縁部であるコア基板11、コア基板11を貫通する貫通電極12、コア基板11の上面及び下面にそれぞれ積層されたビルドアップ層13を備えて構成されている。
−Schematic configuration of wiring board−
FIG. 1 is a partial cross-sectional view showing the main configuration of the wiring board according to the first embodiment.
This wiring board includes a core substrate 11 that is a first insulating portion, a through electrode 12 that penetrates the core substrate 11, and a buildup layer 13 that is laminated on each of the upper and lower surfaces of the core substrate 11.

コア基板11には、例えば、ガラスエポキシ基板、ポリイミド基板、ビスマレイミドトリアジン基板等の有機系絶縁基板、又はセラミック基板等の無機系絶縁基板を用いることができる。   For the core substrate 11, for example, an organic insulating substrate such as a glass epoxy substrate, a polyimide substrate, or a bismaleimide triazine substrate, or an inorganic insulating substrate such as a ceramic substrate can be used.

貫通電極12は、コア基板11に形成された第1貫通孔である貫通孔11aの内壁を第2導電部である導電膜21で覆い、貫通孔11a内を導電膜21を介して絶縁材である樹脂22で埋め込んで形成されている。導電膜21には、例えば、銅(Cu)、銀(Ag)、金(Au)、アルミニウム(Al)等を用いることができる。本実施形態では例えばCuを用いる。樹脂22には、例えばエポキシ樹脂を用いることができる。   The through electrode 12 covers the inner wall of the through hole 11a that is the first through hole formed in the core substrate 11 with the conductive film 21 that is the second conductive portion, and the inside of the through hole 11a is made of an insulating material via the conductive film 21. It is formed by being embedded with a certain resin 22. For the conductive film 21, for example, copper (Cu), silver (Ag), gold (Au), aluminum (Al), or the like can be used. In this embodiment, for example, Cu is used. For example, an epoxy resin can be used as the resin 22.

ビルドアップ層13は、絶縁膜23内に、導電膜21と電気的に接続された第2導電部であるランド24、その上方の第4導電部であるランド25、ランド24とランド25とを電気的に接続する第3導電部であるビア26が形成されてなる。絶縁膜23には、例えば、ガラスフィラー、ガラス繊維、炭素繊維等を含有する、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂等の樹脂材料(プリプレグ)を用いることができる。ランド24,25及びビア26には、各種導電材料を用いることができる。本実施形態では例えばCuを用いる。コア基板11の上面及び下面のビルドアップ層13は、本実施形態では単層の場合を例示するが、所望の複数層に積層形成される。   In the insulating film 23, the build-up layer 13 includes a land 24 that is a second conductive portion electrically connected to the conductive film 21, a land 25 that is a fourth conductive portion above the land 24, and a land 24 and a land 25. A via 26, which is a third conductive portion to be electrically connected, is formed. For the insulating film 23, for example, a resin material (prepreg) such as an epoxy resin, a phenol resin, or a polyimide resin containing glass filler, glass fiber, carbon fiber, or the like can be used. Various conductive materials can be used for the lands 24 and 25 and the via 26. In this embodiment, for example, Cu is used. The build-up layers 13 on the upper surface and the lower surface of the core substrate 11 are exemplified as a single layer in the present embodiment, but are laminated in a desired plurality of layers.

ビア26は、ランド24上において、導電膜21の上方に位置整合する部位を包含する領域に、詳細には導電膜21及び樹脂22に跨る領域(導電膜21と樹脂22との境界を含む領域)に形成されており、本実施形態では図示のように2箇所に設けられている。ビア26を当該領域に形成することにより、ランド24に押圧が付与され、樹脂22のランド24側への熱膨張を抑えることができる。   The via 26 is a region on the land 24 that includes a portion that is aligned above the conductive film 21, specifically a region that extends over the conductive film 21 and the resin 22 (a region that includes the boundary between the conductive film 21 and the resin 22. In this embodiment, it is provided at two locations as shown in the figure. By forming the via 26 in the region, the land 24 is pressed and thermal expansion of the resin 22 toward the land 24 can be suppressed.

本実施形態では、ランド24には、樹脂22上、ここでは2つのビア26間の部位に、第2貫通孔である貫通孔24aが形成されている。貫通孔24aにおいて、樹脂22とビルドアップ層13の絶縁材料とが接触している。更に、ランド25には、貫通孔24aの上方に位置整合する部位、ここでは2つのビア26間の部位に、第3貫通孔である貫通孔25aが形成されている。   In the present embodiment, the land 24 is formed with a through hole 24 a that is a second through hole on the resin 22, here in a region between the two vias 26. In the through hole 24a, the resin 22 and the insulating material of the buildup layer 13 are in contact with each other. Further, the land 25 is formed with a through hole 25a, which is a third through hole, at a position aligned above the through hole 24a, in this case, between the two vias 26.

樹脂22に熱膨張が生じた場合、後述するようにランド24に貫通孔を有しない構成では、当該熱膨張による応力がビア26に集中し、ビア26に破壊が生じる虞がある。本実施形態では、ランド24に貫通孔24aが、ランド25に貫通孔25aがそれぞれ形成されている。そのため、樹脂22に熱膨張の圧力が高まると、図2に示すように、貫通孔24aで樹脂22がビルドアップ層13の絶縁膜23を押しのけて例えば矢印Aの方向に膨張する。これに伴い、貫通孔25aで絶縁膜23が外方へ例えば矢印Bの方向に膨張する。この作用により、ランド24に対する当該熱膨張による応力が緩和されてランド24の破壊が防止されると共に、ビア26に対する当該熱膨張による応力が緩和されてビア26の破壊が防止される。   When thermal expansion occurs in the resin 22, as will be described later, in a configuration in which the land 24 does not have a through hole, stress due to the thermal expansion concentrates on the via 26, and the via 26 may be broken. In the present embodiment, a through hole 24 a is formed in the land 24, and a through hole 25 a is formed in the land 25. Therefore, when the pressure of thermal expansion increases in the resin 22, as shown in FIG. 2, the resin 22 pushes the insulating film 23 of the buildup layer 13 through the through hole 24a and expands in the direction of the arrow A, for example. Along with this, the insulating film 23 expands outward, for example, in the direction of arrow B in the through hole 25a. By this action, the stress due to the thermal expansion on the land 24 is relieved to prevent the land 24 from being destroyed, and the stress due to the thermal expansion on the via 26 is relieved to prevent the via 26 from being destroyed.

−配線基板の製造方法−
図3は、本実施形態による配線基板の製造方法を工程順に示すフロー図である。図4及び図5は、本実施形態による配線基板の製造方法を工程順に示す概略断面図である。図4及び図5において、図1に対応する構成部材については、同符号を付す。
-Wiring board manufacturing method-
FIG. 3 is a flowchart showing the method of manufacturing the wiring board according to the present embodiment in the order of steps. 4 and 5 are schematic cross-sectional views showing the method of manufacturing the wiring board according to the present embodiment in the order of steps. 4 and 5, the same reference numerals are given to the structural members corresponding to FIG. 1.

先ず、図4(a)に示すように、上面及び下面の双方に導電膜31が形成されたコア基板11を用意する(ステップS1)。
導電膜31は、例えばCuからなり、厚み0.015mm程度に形成されている。コア基板11は、例えば厚み0.85mm程度のものである。
First, as shown in FIG. 4A, the core substrate 11 having the conductive film 31 formed on both the upper surface and the lower surface is prepared (step S1).
The conductive film 31 is made of Cu, for example, and has a thickness of about 0.015 mm. The core substrate 11 has a thickness of about 0.85 mm, for example.

続いて、図4(b)に示すように、コア基板11に貫通電極12を形成する(ステップS2)。
詳細には先ず、所定のドリルを用いてコア基板11を加工し、例えば0.15mm程度の径の貫通孔11aを形成する。
次に、例えば無電解メッキ法、又は無電解メッキ法と電解メッキ法を用いて、貫通孔11aの内壁に導電膜21を形成する。導電膜21は例えばCuを材料とし、厚み0.025mm程度に形成する。
次に、貫通孔11a内を、導電膜21を介して絶縁材である樹脂22で充填する。以上により、コア基板11を貫通する貫通電極12が形成される。
Subsequently, as shown in FIG. 4B, the through electrode 12 is formed on the core substrate 11 (step S2).
Specifically, first, the core substrate 11 is processed using a predetermined drill to form a through hole 11a having a diameter of about 0.15 mm, for example.
Next, the conductive film 21 is formed on the inner wall of the through hole 11a using, for example, an electroless plating method, or an electroless plating method and an electrolytic plating method. The conductive film 21 is made of, for example, Cu and has a thickness of about 0.025 mm.
Next, the inside of the through hole 11 a is filled with a resin 22 that is an insulating material via a conductive film 21. Thus, the through electrode 12 that penetrates the core substrate 11 is formed.

続いて、図4(c)に示すように、導電膜32を形成する(ステップS3)。
詳細には、例えば無電解メッキ法、又は無電解メッキ法と電解メッキ法を用いて、コア基板11の上面及び下面の双方に、導電膜31上及び貫通電極12上を覆うように導電膜32を形成する。導電膜32は例えばCuを材料とし、厚み0.015mm程度に形成される。
Subsequently, as shown in FIG. 4C, a conductive film 32 is formed (step S3).
Specifically, the conductive film 32 is formed on both the upper surface and the lower surface of the core substrate 11 so as to cover the conductive film 31 and the through electrode 12 by using, for example, an electroless plating method or an electroless plating method and an electrolytic plating method. Form. The conductive film 32 is made of, for example, Cu and has a thickness of about 0.015 mm.

続いて、図4(d)に示すように、導電膜31,32をパターニングする(ステップS4)。
詳細には、フォトリソグラフィ技術とエッチング技術を用いて導電膜31,32をパターニングする。これにより、導電膜31に貫通電極12の樹脂22の表面の一部を露出させる貫通孔24aが形成され、コア基板11上で導電膜31,32がその一部を残して除去されてランド24が形成される。貫通孔24aは、例えば0.06mm程度の径に形成される。ランド24は、例えば0.25mm程度の径に形成される。なお、貫通孔24aの形成工程とランド24の形成工程とでは、エッチングする導電膜の厚みが異なるため、両者を別工程として、順次行うようにしても良い。ランド24は、後述する工程でビアを形成するために必要な導体面積を十分に確保すべく、導電膜32の形成時に導電膜32の厚みを適宜調整する必要がある。
Subsequently, as shown in FIG. 4D, the conductive films 31 and 32 are patterned (step S4).
Specifically, the conductive films 31 and 32 are patterned using a photolithography technique and an etching technique. As a result, a through hole 24 a that exposes a part of the surface of the resin 22 of the through electrode 12 is formed in the conductive film 31, and the conductive films 31 and 32 are removed on the core substrate 11 leaving a part of the land 24. Is formed. The through hole 24a is formed with a diameter of about 0.06 mm, for example. The land 24 is formed with a diameter of, for example, about 0.25 mm. Note that, since the thickness of the conductive film to be etched is different between the formation process of the through hole 24a and the formation process of the land 24, both may be sequentially performed as separate processes. The land 24 needs to appropriately adjust the thickness of the conductive film 32 when the conductive film 32 is formed in order to secure a sufficient conductor area necessary for forming a via in a process described later.

続いて、図5(a)に示すように、絶縁膜23を形成する(ステップS5)。
詳細には、コア基板11の上面及び下面の双方に、貫通孔24a内を埋め込みランド24上を覆うように絶縁膜23を形成する。絶縁膜23は、例えば厚み0.075mm程度に形成される。
Subsequently, as shown in FIG. 5A, an insulating film 23 is formed (step S5).
Specifically, the insulating film 23 is formed on both the upper surface and the lower surface of the core substrate 11 so as to fill the through holes 24 a and cover the lands 24. The insulating film 23 is formed with a thickness of about 0.075 mm, for example.

続いて、図5(b)に示すように、ビア26を形成する(ステップS6)。
詳細には先ず、絶縁膜23にランド24の表面の一部を露出させる開口を形成する。開口は、導電膜21及び樹脂22に跨る領域(導電膜21と樹脂22との境界を含む領域)に、例えば0.06mm程度の径で0.03mm程度の深さに形成される。開口の形成には、例えば炭酸ガスレーザ、エキシマレーザ、UV(Ultra Violet)レーザ、YAG(Yttrium Aluminum Garnet)レーザ等のレーザを用いる。
次に、例えば無電解メッキ法、又は無電解メッキ法と電解メッキ法を用いて、開口を導電材料、例えばCuで埋め込む。以上により、ランド24と電気的に接続されるビア26が形成される。
Subsequently, as shown in FIG. 5B, a via 26 is formed (step S6).
Specifically, first, an opening for exposing a part of the surface of the land 24 is formed in the insulating film 23. The opening is formed in a region straddling the conductive film 21 and the resin 22 (a region including the boundary between the conductive film 21 and the resin 22), for example, with a diameter of about 0.06 mm and a depth of about 0.03 mm. For forming the opening, for example, a laser such as a carbon dioxide laser, an excimer laser, a UV (Ultra Violet) laser, a YAG (Yttrium Aluminum Garnet) laser is used.
Next, the opening is filled with a conductive material, for example, Cu, using, for example, an electroless plating method, or an electroless plating method and an electrolytic plating method. As a result, the via 26 electrically connected to the land 24 is formed.

続いて、図5(c)に示すように、ランド25を形成する(ステップS7)。
詳細には先ず、例えば無電解メッキ法、又は無電解メッキ法と電解メッキ法を用いて、コア基板11の上面及び下面の双方に、導電膜31上及び貫通電極12上を覆うように導電膜を形成する。導電膜は例えばCuを材料とし、厚み0.015mm程度に形成される。
次に、フォトリソグラフィ技術とエッチング技術を用いて導電膜をパターニングする。これにより、ビア26間の領域で導電膜に絶縁膜23の表面の一部を露出させる貫通孔25aが形成され、絶縁膜23上で導電膜がその一部を残して除去されてランド25が形成される。貫通孔25aは、ランド24の貫通孔24aの上方に整合する位置に、例えば0.06mm程度の径に形成される。ランド25は、例えば0.25mm程度の径に形成される。以上により、絶縁膜23内に、ランド24、その上方のランド25、ランド24とランド25とを電気的に接続するビア26を備えたビルドアップ層13が形成される。
Subsequently, as shown in FIG. 5C, lands 25 are formed (step S7).
Specifically, first, for example, by using an electroless plating method or an electroless plating method and an electrolytic plating method, a conductive film is formed on both the upper surface and the lower surface of the core substrate 11 so as to cover the conductive film 31 and the through electrode 12. Form. The conductive film is made of, for example, Cu and has a thickness of about 0.015 mm.
Next, the conductive film is patterned using a photolithography technique and an etching technique. As a result, a through hole 25a exposing a part of the surface of the insulating film 23 is formed in the conductive film in the region between the vias 26, and the conductive film is removed on the insulating film 23 leaving a part of the land 25. It is formed. The through hole 25a is formed at a position aligned above the through hole 24a of the land 24, for example, with a diameter of about 0.06 mm. The land 25 is formed with a diameter of about 0.25 mm, for example. As a result, the buildup layer 13 including the land 24, the land 25 above the land 24, and the via 26 that electrically connects the land 24 and the land 25 is formed in the insulating film 23.

しかる後、絶縁膜23の形成工程(ステップS5)、ビア25の形成工程(ステップS6)、及びランド25の形成工程(ステップS7)を、ビルドアップ層13として所望する層数だけ繰り返す。以上により、本実施形態による配線基板が形成される。   Thereafter, the process of forming the insulating film 23 (step S5), the process of forming the via 25 (step S6), and the process of forming the land 25 (step S7) are repeated as many times as desired for the buildup layer 13. As described above, the wiring board according to the present embodiment is formed.

本実施形態による配線基板の奏する技術的効果を確認するため、本実施形態の比較例(特許文献3)との比較に基づくシミュレーション解析を行った。
図6は、本実施形態の比較例による配線基板の主要構成及びシミュレーション解析結果を示す模式図である。図7は、本実施形態による配線基板の主要構成(図1に対応する)及びシミュレーション解析結果を示す模式図である。
In order to confirm the technical effect of the wiring board according to the present embodiment, a simulation analysis based on a comparison with the comparative example (Patent Document 3) of the present embodiment was performed.
FIG. 6 is a schematic diagram illustrating a main configuration of a wiring board and a simulation analysis result according to a comparative example of the present embodiment. FIG. 7 is a schematic diagram showing a main configuration (corresponding to FIG. 1) of the wiring board according to the present embodiment and a simulation analysis result.

比較例による配線基板は、本実施形態による配線基板と、ビルドアップ層103のランド114,115に貫通孔を有しない点で相違する。その他の点については本実施形態による配線基板と同様とされている。即ち、比較例による配線基板は、コア基板101、コア基板101を貫通する貫通電極102、コア基板101の上面及び下面にそれぞれ積層されたビルドアップ層103を備えて構成されている。貫通電極102は、コア基板101に形成された貫通孔101aの内壁を導電膜111で覆い、貫通孔101a内を導電膜111を介して樹脂112で埋め込んで形成されている。ビルドアップ層103は、絶縁膜113内に、導電膜111と電気的に接続されたランド114、その上方のランド115、ランド114とランド115とを電気的に接続するビア116が形成されてなる。   The wiring board according to the comparative example is different from the wiring board according to the present embodiment in that the lands 114 and 115 of the buildup layer 103 do not have through holes. The other points are the same as those of the wiring board according to the present embodiment. That is, the wiring board according to the comparative example includes a core substrate 101, a through electrode 102 that penetrates the core substrate 101, and a buildup layer 103 that is laminated on each of the upper and lower surfaces of the core substrate 101. The through electrode 102 is formed by covering the inner wall of the through hole 101 a formed in the core substrate 101 with the conductive film 111 and filling the through hole 101 a with the resin 112 through the conductive film 111. The buildup layer 103 is formed by forming a land 114 electrically connected to the conductive film 111, a land 115 above the conductive film 111, and a via 116 electrically connecting the land 114 and the land 115 in the insulating film 113. .

ビア116は、ランド114上において、導電膜111の上方に位置整合する部位を包含する領域に、詳細には導電膜111及び樹脂112に跨る領域(導電膜111と樹脂112との境界を含む領域)に形成されており、本実施形態では図示のように2箇所に設けられている。ビア116を当該領域に形成することにより、ランド114に押圧が付与され、樹脂112のランド114側への熱膨張を抑えることができる。   The via 116 is a region on the land 114 that includes a position aligned above the conductive film 111, specifically a region that extends over the conductive film 111 and the resin 112 (a region that includes a boundary between the conductive film 111 and the resin 112. In this embodiment, it is provided at two locations as shown in the figure. By forming the via 116 in the region, the land 114 is pressed, and thermal expansion of the resin 112 toward the land 114 can be suppressed.

比較例では、樹脂112の熱膨張によるランド114の破断を防止する一方で、樹脂112の熱膨張を押さえ付けて抑制しているビア116に応力が集中し易くなる。更に、ビア116の下方及び上方がランド114,115で覆われているため、絶縁膜113が熱膨張した際に、当該熱膨張が主に絶縁膜113の水平方向へ広がり、絶縁膜113内のビア116に集中し易くなる。図6に示すように、ビア116の上部及び下部で大きな応力が印加されており、中央部でも応力は比較的大きいことが判る。当該応力に起因して、ビア116に破断が生じる虞がある。   In the comparative example, the land 114 is prevented from being broken due to the thermal expansion of the resin 112, while the stress is easily concentrated on the via 116 that suppresses and suppresses the thermal expansion of the resin 112. Furthermore, since the lower and upper sides of the via 116 are covered with the lands 114 and 115, when the insulating film 113 is thermally expanded, the thermal expansion mainly spreads in the horizontal direction of the insulating film 113, and the inside of the insulating film 113 It becomes easy to concentrate on the via 116. As shown in FIG. 6, a large stress is applied to the upper and lower portions of the via 116, and it can be seen that the stress is relatively large even in the central portion. Due to the stress, the via 116 may break.

これに対して本実施形態では、図7に示すように、樹脂22が熱膨張すると、これに起因して発生する応力は、ビア26で抑制されることに加え、ランド24の貫通孔24aからビルドアップ層13の絶縁膜23に分散される。更に、樹脂22の熱膨張を押さえ付けて抑制することによりビア26に発生する応力、及び絶縁膜23の熱膨張に起因して発生する応力は、ランド25の貫通孔25aから外方へ分散される。その結果、図7に示すように、ビア26に印加される応力は、比較例のビア116に比べて(特に下部及び中央部で)低減する。その結果、当該応力によるビア26の破断が抑止される。   In contrast, in this embodiment, as shown in FIG. 7, when the resin 22 is thermally expanded, the stress generated due to this is suppressed by the via 26, and from the through hole 24 a of the land 24. Dispersed in the insulating film 23 of the buildup layer 13. Further, the stress generated in the via 26 by suppressing the thermal expansion of the resin 22 by pressing and the stress generated due to the thermal expansion of the insulating film 23 are dispersed outward from the through hole 25a of the land 25. The As a result, as shown in FIG. 7, the stress applied to the via 26 is reduced (particularly at the lower and center portions) compared to the via 116 of the comparative example. As a result, the breakage of the via 26 due to the stress is suppressed.

以上説明したように、本実施形態によれば、貫通電極12の貫通孔11a内を埋め込む樹脂22の熱膨張及びビルドアップ層13の絶縁膜23の熱膨張を考慮して、主に前者の熱膨張に起因するランド24の応力負荷と共に、主に後者の熱膨張に起因するビア26の応力負荷を軽減して双方の破断を可及的に防止し、信頼性の高い配線基板が実現する。   As described above, according to the present embodiment, in consideration of the thermal expansion of the resin 22 that fills the through hole 11a of the through electrode 12 and the thermal expansion of the insulating film 23 of the buildup layer 13, the former heat is mainly used. Together with the stress load on the land 24 caused by the expansion, the stress load on the via 26 mainly caused by the latter thermal expansion is reduced to prevent breakage of both as much as possible, thereby realizing a highly reliable wiring board.

(第2の実施形態)
本実施形態では、第1の実施形態による配線基板を備えた電子装置を開示する。
図8は、第2の実施形態による電子装置の主要構成を示す一部断面図である。
(Second Embodiment)
In the present embodiment, an electronic device including the wiring board according to the first embodiment is disclosed.
FIG. 8 is a partial cross-sectional view showing the main configuration of the electronic device according to the second embodiment.

この電子装置は、第1の実施形態による配線基板10に電子部品20が搭載されて構成されている。
配線基板10は、図1の配線基板と同様のものであるが、コア基板11の上面及び下面にそれぞれ積層されたビルドアップ層13が、上下それぞれで複数層、図示の例では2層に積層されている。
This electronic device is configured by mounting an electronic component 20 on the wiring board 10 according to the first embodiment.
The wiring board 10 is the same as the wiring board of FIG. 1, but the build-up layers 13 respectively laminated on the upper surface and the lower surface of the core substrate 11 are laminated in a plurality of layers in the upper and lower sides, and in the illustrated example, in two layers. Has been.

電子部品20としては、半導体素子(半導体チップ)、半導体素子を含む半導体パッケージ等が挙げられる。
最上層及び最下層のビルドアップ層13の表面には、電極(ランド25)の表面を露出させる開口を有する保護膜41が形成されている。保護膜41には、例えばソルダーレジスト等が用いられる。配線基板10の最上層の電極(ランド25)上には、ハンダバンプ等の接合材42が設けられている。接合材42により、電極(ランド25)と電子部品20とが電気的に接続されている。
Examples of the electronic component 20 include a semiconductor element (semiconductor chip), a semiconductor package including the semiconductor element, and the like.
A protective film 41 having an opening exposing the surface of the electrode (land 25) is formed on the surfaces of the uppermost layer and the lowermost buildup layer 13. For the protective film 41, for example, a solder resist or the like is used. A bonding material 42 such as a solder bump is provided on the uppermost electrode (land 25) of the wiring board 10. The electrode (land 25) and the electronic component 20 are electrically connected by the bonding material 42.

本実施形態によれば、貫通電極12の貫通孔11a内を埋め込む樹脂22の熱膨張及びビルドアップ層13の絶縁膜23の熱膨張を考慮して、主に前者の熱膨張に起因するランド24の応力負荷と共に、主に後者の熱膨張に起因するビア26の応力負荷を軽減して双方の破断を可及的に防止し、信頼性の高い配線基板10を備えた、信頼性の高い電子装置が実現する。   According to the present embodiment, considering the thermal expansion of the resin 22 filling the through-hole 11a of the through-electrode 12 and the thermal expansion of the insulating film 23 of the buildup layer 13, the land 24 mainly caused by the former thermal expansion is considered. In addition to the stress load of the latter, the stress load of the via 26 caused mainly by the latter thermal expansion is reduced to prevent both of the breaks as much as possible, and the highly reliable electronic circuit having the highly reliable wiring board 10 is provided. The device is realized.

(変形例)
以下、第2の実施形態の変形例について説明する。本例では、第2の実施形態による電子装置が、更に他の配線基板に搭載された電子装置を開示する。
図9は、第2の実施形態の変形例による電子装置の主要構成を示す一部断面図である。
(Modification)
Hereinafter, modifications of the second embodiment will be described. In this example, the electronic device according to the second embodiment is disclosed as an electronic device mounted on another wiring board.
FIG. 9 is a partial cross-sectional view showing the main configuration of an electronic device according to a modification of the second embodiment.

この電子装置は、第2の実施形態による、配線基板10に電子部品20が搭載された電子装置が、他の配線基板30に搭載されて構成されている。配線基板10の最上層及び最下層の電極(ランド25)上には、ハンダバンプ等の接合材42が設けられている。配線基板10の最上層では、接合材42により電極(ランド25)と電子部品20とが電気的に接続されている。配線基板10の最下層では、接合材42により電極(ランド25)と配線基板30とが電気的に接続されている。   The electronic device according to the second embodiment is configured by mounting an electronic device in which an electronic component 20 is mounted on a wiring board 10 on another wiring board 30. A bonding material 42 such as a solder bump is provided on the uppermost layer and the lowermost electrode (land 25) of the wiring substrate 10. In the uppermost layer of the wiring substrate 10, the electrode (land 25) and the electronic component 20 are electrically connected by the bonding material 42. In the lowermost layer of the wiring board 10, the electrode (land 25) and the wiring board 30 are electrically connected by the bonding material 42.

本例によれば、貫通電極12の貫通孔11a内を埋め込む樹脂22の熱膨張及びビルドアップ層13の絶縁膜23の熱膨張を考慮して、主に前者の熱膨張に起因するランド24の応力負荷と共に、主に後者の熱膨張に起因するビア26の応力負荷を軽減して双方の破断を可及的に防止し、信頼性の高い配線基板10を備えた、信頼性の高い電子装置が実現する。   According to this example, the thermal expansion of the resin 22 filling the through hole 11a of the through electrode 12 and the thermal expansion of the insulating film 23 of the buildup layer 13 are considered, and the land 24 mainly caused by the thermal expansion of the former is considered. A highly reliable electronic device including the highly reliable wiring board 10 that reduces the stress load of the via 26 caused mainly by the latter thermal expansion together with the stress load and prevents the breakage of both vias as much as possible. Is realized.

以下、配線基板及びその製造方法、並びに電子装置の諸態様を付記としてまとめて記載する。   Hereinafter, various aspects of the wiring board, the manufacturing method thereof, and the electronic device are collectively described as supplementary notes.

(付記1)第1貫通孔を有する第1絶縁部と、
前記第1貫通孔の内壁に形成された第1導電部と、
前記第1貫通孔を前記第1導電部を介して埋め込む絶縁材と、
前記第1絶縁部上に形成された第2絶縁部と、
前記第2絶縁部内に形成されて前記第1導電部と接続されており、前記絶縁材上に第2貫通孔を有する第2導電部と、
前記第2絶縁部内で前記第2導電部と接続されている第3導電部と
を含むことを特徴とする配線基板。
(Appendix 1) a first insulating part having a first through hole;
A first conductive portion formed on the inner wall of the first through hole;
An insulating material that embeds the first through hole through the first conductive portion;
A second insulating part formed on the first insulating part;
A second conductive portion formed in the second insulating portion and connected to the first conductive portion, and having a second through hole on the insulating material;
A wiring board comprising: a third conductive part connected to the second conductive part in the second insulating part.

(付記2)前記第3導電部は、前記第1導電部の上方に整合する位置に形成されていることを特徴とする付記1に記載の配線基板。   (Supplementary note 2) The wiring board according to supplementary note 1, wherein the third conductive portion is formed at a position aligned above the first conductive portion.

(付記3)前記第2絶縁部上で前記第3導電部と接続されており、前記第2貫通孔の上方に位置整合する部位に第3貫通孔を有する第4導電部を更に含むことを特徴とする付記1又は2に記載の配線基板。   (Additional remark 3) It is connected with the said 3rd electroconductive part on the said 2nd insulating part, and further contains the 4th electroconductive part which has a 3rd through-hole in the site | part aligned above the said 2nd through-hole. The wiring board according to appendix 1 or 2, which is characterized.

(付記4)前記第2絶縁部は、前記第1絶縁部の上面及び下面にそれぞれ形成されていることを特徴とする付記1〜3のいずれか1項に記載の配線基板。   (Appendix 4) The wiring board according to any one of appendices 1 to 3, wherein the second insulating portion is formed on an upper surface and a lower surface of the first insulating portion, respectively.

(付記5)前記第2貫通孔において、前記第1絶縁部と前記第2絶縁部とが接触していることを特徴とする付記1〜4のいずれか1項に記載の配線基板。   (Appendix 5) The wiring board according to any one of appendices 1 to 4, wherein the first insulating portion and the second insulating portion are in contact with each other in the second through hole.

(付記6)第1絶縁部に第1貫通孔を形成する工程と、
前記第1貫通孔の内壁に第1導電部を形成する工程と、
前記第1貫通孔を前記第1導電部を介して絶縁材で埋め込む工程と、
前記第1絶縁部上に、前記第1導電部と接続される第2導電部を形成する工程と、
前記第2導電部に、前記絶縁材の表面の一部を露出させる第2貫通孔を形成する工程と、
前記第1絶縁部上に、前記第2導電部を覆って前記第2貫通孔を埋め込む第2絶縁部を形成する工程と、
前記第2絶縁部に、前記第2導電部と接続される第3導電部を形成する工程と、
を含むことを特徴とする配線基板の製造方法。
(Appendix 6) forming a first through hole in the first insulating portion;
Forming a first conductive portion on the inner wall of the first through hole;
Filling the first through hole with an insulating material through the first conductive portion;
Forming a second conductive portion connected to the first conductive portion on the first insulating portion;
Forming a second through hole in the second conductive portion to expose a part of the surface of the insulating material;
Forming a second insulating portion on the first insulating portion so as to cover the second conductive portion and bury the second through hole;
Forming a third conductive portion connected to the second conductive portion in the second insulating portion;
A method for manufacturing a wiring board, comprising:

(付記7)前記第3導電部は、前記第1導電部の上方に整合する位置に形成されることを特徴とする付記6に記載の配線基板の製造方法。   (Additional remark 7) The said 3rd electroconductive part is formed in the position aligned above the said 1st electroconductive part, The manufacturing method of the wiring board of Additional remark 6 characterized by the above-mentioned.

(付記8)前記第2絶縁部上で前記第3導電部と接続される第4導電部を形成する工程と、
前記第4導電部の前記第2貫通孔の上方に位置整合する部位に第3貫通孔を形成する工程と
を更に含むことを特徴とする付記6又は7に記載の配線基板の製造方法。
(Appendix 8) Forming a fourth conductive portion connected to the third conductive portion on the second insulating portion;
The method of manufacturing a wiring board according to appendix 6 or 7, further comprising: forming a third through hole at a position aligned with the second through hole of the fourth conductive portion.

(付記9)前記第2絶縁部は、前記第1絶縁部の上面及び下面にそれぞれ形成されることを特徴とする付記6〜8のいずれか1項に記載の配線基板の製造方法。   (Additional remark 9) The said 2nd insulation part is formed in the upper surface and lower surface of a said 1st insulation part, respectively, The manufacturing method of the wiring board of any one of Additional remarks 6-8 characterized by the above-mentioned.

(付記10)前記第2貫通孔において、前記第1絶縁部と前記第2絶縁部とが接触することを特徴とする付記6〜9のいずれか1項に記載の配線基板の製造方法。   (Additional remark 10) The said 1st insulating part and the said 2nd insulating part contact in the said 2nd through-hole, The manufacturing method of the wiring board of any one of Additional remark 6-9 characterized by the above-mentioned.

(付記11)配線基板と、
前記配線基板に搭載された電子部品と
を備え、
前記配線基板は、
第1貫通孔を有する第1絶縁部と、
前記第1貫通孔の内壁に形成された第1導電部と、
前記第1貫通孔を前記第1導電部を介して埋め込む絶縁材と、
前記第1絶縁部上に形成された第2絶縁部と、
前記第2絶縁部内に形成されて前記第1導電部と接続されており、前記絶縁材上に第2貫通孔を有する第2導電部と、
前記第2絶縁部内で前記第2導電部と接続されている第3導電部と
を含むことを特徴とする電子装置。
(Appendix 11) a wiring board;
An electronic component mounted on the wiring board,
The wiring board is
A first insulating part having a first through hole;
A first conductive portion formed on the inner wall of the first through hole;
An insulating material that embeds the first through hole through the first conductive portion;
A second insulating part formed on the first insulating part;
A second conductive portion formed in the second insulating portion and connected to the first conductive portion, and having a second through hole on the insulating material;
An electronic device comprising: a third conductive portion connected to the second conductive portion in the second insulating portion.

(付記12)前記第3導電部は、前記第1導電部の上方に整合する位置に形成されていることを特徴とする付記11に記載の電子装置。   (Additional remark 12) The said 3rd electroconductive part is formed in the position aligned above the said 1st electroconductive part, The electronic device of Additional remark 11 characterized by the above-mentioned.

(付記13)前記配線基板は、前記第2絶縁部上で前記第3導電部と接続されており、前記第2貫通孔の上方に位置整合する部位に第3貫通孔を有する第4導電部を更に含むことを特徴とする付記11又は12に記載の電子装置。   (Additional remark 13) The said wiring board is connected with the said 3rd electroconductive part on the said 2nd insulating part, and the 4th electroconductive part which has a 3rd through-hole in the site | part aligned above the said 2nd through-hole. The electronic device according to appendix 11 or 12, further comprising:

(付記14)前記第2絶縁部は、前記第1絶縁部の上面及び下面にそれぞれ形成されていることを特徴とする付記11〜13のいずれか1項に記載の電子装置。   (Supplementary note 14) The electronic device according to any one of supplementary notes 11 to 13, wherein the second insulating portion is formed on an upper surface and a lower surface of the first insulating portion, respectively.

(付記15)前記第2貫通孔において、前記第1絶縁部と前記第2絶縁部とが接触していることを特徴とする付記11〜14のいずれか1項に記載の電子装置。   (Supplementary note 15) The electronic device according to any one of Supplementary notes 11 to 14, wherein the first insulating portion and the second insulating portion are in contact with each other in the second through hole.

10,30 配線基板
11,101 コア基板
11a,24a,25a,101a 貫通孔
12,102 貫通電極
13,103 ビルドアップ層
20 電子部品
21,31,32,111 導電膜
22,112 樹脂
23,113 絶縁膜
24,25,114,115 ランド
26,116 ビア
41 保護膜
42 接合材
10, 30 Wiring substrate 11, 101 Core substrate 11a, 24a, 25a, 101a Through hole 12, 102 Through electrode 13, 103 Build-up layer 20 Electronic component 21, 31, 32, 111 Conductive film 22, 112 Resin 23, 113 Insulation Films 24, 25, 114, 115 Lands 26, 116 Via 41 Protective film 42 Bonding material

Claims (11)

第1貫通孔を有する第1絶縁部と、
前記第1貫通孔の内壁に形成された第1導電部と、
前記第1貫通孔を前記第1導電部を介して埋め込む絶縁材と、
前記第1絶縁部上に形成された第2絶縁部と、
前記第2絶縁部内に形成されて前記第1導電部と接続されており、前記絶縁材上に第2貫通孔を有する第2導電部と、
前記第2絶縁部内で前記第2導電部と接続されている第3導電部と
を含むことを特徴とする配線基板。
A first insulating part having a first through hole;
A first conductive portion formed on the inner wall of the first through hole;
An insulating material that embeds the first through hole through the first conductive portion;
A second insulating part formed on the first insulating part;
A second conductive portion formed in the second insulating portion and connected to the first conductive portion, and having a second through hole on the insulating material;
A wiring board comprising: a third conductive part connected to the second conductive part in the second insulating part.
前記第3導電部は、前記第1導電部の上方に整合する位置に形成されていることを特徴とする請求項1に記載の配線基板。   The wiring board according to claim 1, wherein the third conductive portion is formed at a position aligned above the first conductive portion. 前記第2絶縁部上で前記第3導電部と接続されており、前記第2貫通孔の上方に整合する位置に第3貫通孔を有する第4導電部を更に含むことを特徴とする請求項1又は2に記載の配線基板。   The semiconductor device further comprises a fourth conductive portion connected to the third conductive portion on the second insulating portion and having a third through hole at a position aligned above the second through hole. The wiring board according to 1 or 2. 前記第2絶縁部は、前記第1絶縁部の上面及び下面にそれぞれ形成されていることを特徴とする請求項1〜3のいずれか1項に記載の配線基板。   The wiring board according to claim 1, wherein the second insulating portion is formed on an upper surface and a lower surface of the first insulating portion, respectively. 前記第2貫通孔において、前記第1絶縁部と前記第2絶縁部とが接触していることを特徴とする請求項1〜4のいずれか1項に記載の配線基板。   5. The wiring board according to claim 1, wherein the first insulating portion and the second insulating portion are in contact with each other in the second through hole. 第1絶縁部に第1貫通孔を形成する工程と、
前記第1貫通孔の内壁に第1導電部を形成する工程と、
前記第1貫通孔を前記第1導電部を介して絶縁材で埋め込む工程と、
前記第1絶縁部上に、前記第1導電部と接続される第2導電部を形成する工程と、
前記第2導電部に、前記絶縁材の表面の一部を露出させる第2貫通孔を形成する工程と、
前記第1絶縁部上に、前記第2導電部を覆って前記第2貫通孔を埋め込む第2絶縁部を形成する工程と、
前記第2絶縁部に、前記第2導電部と接続される第3導電部を形成する工程と
を含むことを特徴とする配線基板の製造方法。
Forming a first through hole in the first insulating portion;
Forming a first conductive portion on the inner wall of the first through hole;
Filling the first through hole with an insulating material through the first conductive portion;
Forming a second conductive portion connected to the first conductive portion on the first insulating portion;
Forming a second through hole in the second conductive portion to expose a part of the surface of the insulating material;
Forming a second insulating portion on the first insulating portion so as to cover the second conductive portion and bury the second through hole;
Forming a third conductive portion connected to the second conductive portion in the second insulating portion. A method of manufacturing a wiring board, comprising:
前記第3導電部は、前記第1導電部の上方に整合する位置に形成されることを特徴とする請求項6に記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 6, wherein the third conductive portion is formed at a position aligned above the first conductive portion. 前記第2絶縁部上で前記第3導電部と接続される第4導電部を形成する工程と、
前記第4導電部の前記第2貫通孔の上方に整合する位置に第3貫通孔を形成する工程と
を更に含むことを特徴とする請求項6又は7に記載の配線基板の製造方法。
Forming a fourth conductive portion connected to the third conductive portion on the second insulating portion;
The method for manufacturing a wiring board according to claim 6, further comprising: forming a third through hole at a position aligned with the second through hole of the fourth conductive portion.
前記第2絶縁部は、前記第1絶縁部の上面及び下面にそれぞれ形成されることを特徴とする請求項6〜8のいずれか1項に記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 6, wherein the second insulating portion is formed on an upper surface and a lower surface of the first insulating portion, respectively. 前記第2貫通孔において、前記第1絶縁部と前記第2絶縁部とが接触することを特徴とする請求項6〜9のいずれか1項に記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 6, wherein the first insulating portion and the second insulating portion are in contact with each other in the second through hole. 配線基板と、
前記配線基板に搭載された電子部品と
を備え、
前記配線基板は、
第1貫通孔を有する第1絶縁部と、
前記第1貫通孔の内壁に形成された第1導電部と、
前記第1貫通孔を前記第1導電部を介して埋め込む絶縁材と、
前記第1絶縁部上に形成された第2絶縁部と、
前記第2絶縁部内に形成されて前記第1導電部と接続されており、前記絶縁材上に第2貫通孔を有する第2導電部と、
前記第2絶縁部内で前記第2導電部と接続されている第3導電部と
を含むことを特徴とする電子装置。
A wiring board;
An electronic component mounted on the wiring board,
The wiring board is
A first insulating part having a first through hole;
A first conductive portion formed on the inner wall of the first through hole;
An insulating material that embeds the first through hole through the first conductive portion;
A second insulating part formed on the first insulating part;
A second conductive portion formed in the second insulating portion and connected to the first conductive portion, and having a second through hole on the insulating material;
An electronic device comprising: a third conductive portion connected to the second conductive portion in the second insulating portion.
JP2015155433A 2015-08-05 2015-08-05 WIRING BOARD, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE Expired - Fee Related JP6586814B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7458824B2 (en) 2020-02-28 2024-04-01 京セラ株式会社 Printed wiring board and method for manufacturing printed wiring board

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002280750A (en) * 2001-03-16 2002-09-27 Victor Co Of Japan Ltd Multilayer printed wiring board and method for manufacturing the same
JP2015126053A (en) * 2013-12-26 2015-07-06 富士通株式会社 Wiring board, wiring board manufacturing method and electronic apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002280750A (en) * 2001-03-16 2002-09-27 Victor Co Of Japan Ltd Multilayer printed wiring board and method for manufacturing the same
JP2015126053A (en) * 2013-12-26 2015-07-06 富士通株式会社 Wiring board, wiring board manufacturing method and electronic apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7458824B2 (en) 2020-02-28 2024-04-01 京セラ株式会社 Printed wiring board and method for manufacturing printed wiring board

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