JP2017022585A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory system that comprises a host device and a memory device connected with it, and can simply achieve high-speed encryption communication between the devices at low cost.SOLUTION: A host device 2 comprises: a transmission control circuit 22 for controlling command transmission to a memory device 3 in synchronization with a clock C1; an encryption/decryption circuit 24 as an encryption circuit for generating an encryption command S5A by encrypting a command S5 to be transmitted to the memory device 3 in synchronization with the clock C1; a reception control circuit 23 for controlling data reception from the memory device 3 in synchronization with a clock C2; and the encryption/decryption circuit 24 as a decryption circuit for decrypting encryption data S7A received from the memory device 3 in synchronization with the clock C2.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a memory system including a host device and a memory device.

  In a memory system that operates in synchronization with a clock in a memory system that includes a host device and a memory device connected to the host device, the propagation delay of the clock and data transmitted and received between the two devices increases as the operation speed increases. Therefore, data transfer within one cycle of the clock is becoming difficult.

  Therefore, in a conventional memory system, data transmission / reception has been performed between both devices in synchronization with a data strobe signal generated inside the system in order to prevent data loss due to an increase in the amount of data delay ( For example, see Patent Documents 1 to 3 below).

  Further, when performing encrypted communication between both devices, in the conventional memory system, both encryption processing and decryption processing are executed in synchronization with a common single clock.

JP 2004-145999 A JP 2011-216079 A Special table 2011-508311 gazette

  However, in encrypted communication that executes both encryption processing and decryption processing in synchronization with a single clock, the encryption processing and decryption processing must be appropriately synchronized as the communication speed increases. Is becoming difficult.

  The present invention has been made in view of such circumstances, and in a memory system including a host device and a memory device connected thereto, high-speed encrypted communication between both devices can be realized at low cost and easily. The purpose is to obtain a simple memory system.

  A memory system according to a first aspect of the present invention includes a host device and a memory device connected to the host device, and the host device sends a command to the memory device in synchronization with a first clock. A transmission control circuit for controlling transmission; a cipher circuit for generating an encrypted command by encrypting a command to be transmitted to the memory device in synchronization with a first clock; and the synchronization circuit in synchronization with a second clock. A reception control circuit that controls reception of data from the memory device, and a decryption circuit that decrypts encrypted data received from the memory device in synchronization with a second clock.

  According to the memory system of the first aspect, the transmission control circuit and the encryption circuit operate in synchronization with the first clock, and the reception control circuit and the decryption circuit operate in synchronization with the second clock. Therefore, even when the communication speed is increased, the encryption process and the decryption process can be appropriately synchronized. As a result, the high-speed encryption communication between the host device and the memory device can be performed at low cost and at a low cost. This can be realized easily.

  The memory system according to a second aspect of the present invention is the memory system according to the first aspect, in particular, the memory device includes a memory array in which data is stored, and a control circuit that controls access to the memory array. The transmission control circuit transmits a first clock to the control circuit, and the control circuit uses the first clock received from the transmission control circuit as a second clock to the reception control circuit. It is characterized by transmitting.

  According to the memory system of the second aspect, the control circuit of the memory device feeds back the first clock received from the transmission control circuit of the host device, so that the second clock is sent to the reception control circuit of the host device. Send. The reception control circuit controls data reception from the memory device in synchronization with the fed back second clock. Accordingly, since it is not necessary to newly generate a data strobe signal different from the first and second clocks, the mounting of the data strobe signal generation circuit and the timing adjustment circuit can be omitted. As a result, the host device and the memory device can be omitted. It is possible to easily realize high-speed encrypted communication with the network at low cost. Further, since the first clock is fed back as the second clock, when data read from the memory array is transmitted from the memory device to the host device in synchronization with the second clock, wiring delay and buffer delay are caused. The accompanying propagation delay amount can be substantially offset between the second clock and the data, and as a result, data loss can be prevented.

  The memory system according to a third aspect of the present invention is the memory system according to the second aspect, in particular, the host device further includes a main control circuit that controls the transmission control circuit and the reception control circuit, The main control circuit determines a predetermined correction value based on a propagation delay amount between the host device and the memory device, and the transmission control circuit is based on the correction value input from the main control circuit. Then, the cycle number of the first clock from the start of data reception from the memory device to the completion of the data reception is corrected.

  According to the memory system of the third aspect, the main control circuit of the host device determines a predetermined correction value based on the propagation delay amount between the host device and the memory device, and the transmission control circuit Based on the value, the number of cycles of the first clock from the start of data reception from the memory device to the completion of data reception is corrected. In this way, by correcting the fixed cycle number specified by the communication protocol based on the correction value determined from the indefinite propagation delay amount, the fixed cycle number can be secured without excess or deficiency. Since the internal states of the encryption circuit and the decryption circuit and the encryption circuit and the decryption circuit of the memory device can be matched, the system can be operated normally.

  The memory system according to a fourth aspect of the present invention is the memory system according to the third aspect, in which the transmission control circuit includes a first counter that counts the number of cycles of the first clock, and the reception control The circuit includes a second counter that counts the number of cycles of the second clock, and the main control circuit is configured to receive a Ready signal from the memory device after command transmission to the memory device is completed. The correction is based on the count value of the first counter and the count value of the second counter from when the first Busy signal is received from the memory device to when the Ready signal is received from the memory device. It is characterized by determining a value.

  According to the memory system of the fourth aspect, the main control circuit includes the count value of the first counter until the Ready signal is received from the memory device after the command transmission to the memory device is completed, and the memory device The correction value is determined based on the count value of the second counter from the reception of the first Busy signal to the reception of the Ready signal from the memory device. Therefore, the correction value can be accurately determined based on the indefinite propagation delay amount associated with the wiring delay and the buffer delay and the indefinite busy cycle number associated with the data reading from the memory array. It becomes possible to correct to.

  The memory system according to a fifth aspect of the present invention is the memory system according to the third aspect, in which the transmission control circuit includes a first counter that counts the number of cycles of the first clock, and the main control The circuit calculates the correction value based on a count value of the first counter from completion of command transmission to the memory device to reception of a first Busy signal from the memory device. It is what.

  According to the memory system of the fifth aspect, the main control circuit is based on the count value of the first counter until the first Busy signal is received from the memory device after the command transmission to the memory device is completed. To determine the correction value. Therefore, the correction value can be easily determined based on the indefinite propagation delay amount accompanying the wiring delay and the buffer delay. In addition, since the correction value can be determined early without waiting for the completion of the Busy cycle, error processing can be started early when the correction value is an abnormal value. Furthermore, since the second counter is not necessary and the count value of the first counter can be reduced, the circuit scale of the host device as a whole can be reduced.

  In the memory system according to the sixth aspect of the present invention, in the memory system according to any one of the first to fifth aspects, a common encryption / decryption circuit is mounted as the encryption circuit and the decryption circuit. It is characterized by.

  According to the memory system of the sixth aspect, since the common encryption / decryption circuit is mounted as the encryption circuit and the decryption circuit, the circuit scale of the host device is compared with the case where the encryption circuit and the decryption circuit are individually mounted. Can be reduced.

  A memory system according to a seventh aspect of the present invention is characterized in that, in the memory system according to any one of the first to fifth aspects, the encryption circuit and the decryption circuit are individually mounted. To do.

  According to the memory system according to the seventh aspect, since the encryption circuit and the decryption circuit are individually mounted, it is possible to easily perform optimum circuit designs for the encryption circuit and the decryption circuit, respectively.

  The memory system according to an eighth aspect of the present invention is the memory system according to the seventh aspect, in particular, the transmission control circuit inputs the first synchronization signal to the encryption circuit and the decryption circuit, thereby The decryption circuit operates by operating the decryption circuit within a period in which the encryption circuit executes command encryption, and the reception control circuit inputs a second synchronization signal to the encryption circuit and the decryption circuit, thereby Is characterized in that the encryption circuit is operated during a period in which the encrypted data is decrypted.

  According to the memory system of the eighth aspect, the transmission control circuit inputs the first synchronization signal to the encryption circuit and the decryption circuit, so that the encryption circuit decrypts the command within the period during which the command is encrypted. Operate the circuit. In addition, the reception control circuit inputs the second synchronization signal to the encryption circuit and the decryption circuit, thereby operating the encryption circuit during the period in which the decryption circuit is decrypting the encrypted data. In this way, by operating one of the encryption circuit and the decryption circuit while the other is running, the internal state of the key stream of the encryption circuit and the decryption circuit can be matched, As a result, it is possible to realize appropriate encrypted communication.

  ADVANTAGE OF THE INVENTION According to this invention, the memory system which can implement | achieve the high-speed encryption communication between a host apparatus and a memory device easily at low cost can be obtained.

It is a figure which shows the structure of the memory system which concerns on Embodiment 1 of this invention. 3 is a timing chart showing a read operation of the memory system. It is a figure which shows the structure of the memory system which concerns on Embodiment 2 of this invention. It is a figure which shows the structure of the memory system which concerns on a modification. 3 is a timing chart showing a read operation of the memory system.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the element which attached | subjected the same code | symbol in different drawing shall show the same or corresponding element.

<Embodiment 1>
FIG. 1 is a diagram showing a configuration of a memory system 1 according to Embodiment 1 of the present invention. As shown in FIG. 1, the memory system 1 includes a host device 2 and a memory device 3 such as a semiconductor memory that is detachably connected to the host device 2.

  The host device 2 includes a CPU 11, an internal memory 12, and a memory controller 13. The memory controller 13 includes a main control circuit 21, a transmission control circuit 22, a reception control circuit 23, and an encryption / decryption circuit 24. The transmission control circuit 22 controls the encryption process of the command S5 by the encryption / decryption circuit 24 and the transmission process of the encryption command S5 to the memory device 3 in synchronization with the clock C1. The reception control circuit 23 controls the reception process of the encrypted data S7A from the memory device 3 and the decryption process of the encrypted data S7A by the encryption / decryption circuit 24 in synchronization with the clock C2. The main control circuit 21 controls the transmission control circuit 22 and the reception control circuit 23. As shown in FIG. 1, the transmission control circuit 22 includes an access generation circuit 31 and a transmission counter 32, and the reception control circuit 23 includes a synchronization circuit 41 and a reception counter 42.

  A common reference clock C0 is input to the main control circuit 21, the access generation circuit 31, the transmission counter 32, the encryption / decryption circuit 24, the synchronization circuit 41, and the reception counter. The access generation circuit 31 generates the clock C1 based on the reference clock C0. For example, by dividing the reference clock C0, a clock C1 having four cycles of the reference clock C0 as one cycle is generated.

  The memory device 3 includes a memory array 52 in which arbitrary data S6 such as content data is stored, and a control circuit 51 that controls access to the memory array 52. The control circuit 51 has an encryption / decryption circuit 61 similar to the encryption / decryption circuit 24.

  Hereinafter, the operation of the memory system 1 will be described by taking as an example a process of reading the data S7 stored in the memory array 52 from the memory device 3 to the host device 2. The following example is based on a memory system in which the command length is fixed to 8 bytes and the read data length is fixed to 512 bytes according to the communication protocol, and the Ready / Busy method is adopted as the latency method. Further, the command and read data are objects of encryption, and the Busy signal and Ready signal are not examples of encryption.

  FIG. 2 is a timing chart showing the read operation of the memory system 1. The CPU 11 inputs a read command including address information and a read size to the main control circuit 21. The main control circuit 21 decodes the input read command and inputs the command data S1 and the control signal S2 including the access information and the access start flag to the transmission control circuit 22.

  The access generation circuit 31 generates an access control signal S4 for accessing the memory device 3 based on the inputted access information, and transmits the access control signal S4 to the memory device 3. Further, the access generation circuit 31 generates the clock C1 based on the reference clock C0 as described above, and transmits the clock C1 to the memory device 3. In addition, the transmission control circuit 22 generates a synchronization signal T1 that is synchronized with the clock C1 and inputs the synchronization signal T1 to the encryption / decryption circuit 24. The transmission control circuit 22 generates a non-encrypted command S5 based on the input command data S1, and inputs the command S5 to the encryption / decryption circuit 24.

  The encryption / decryption circuit 24 executes encryption processing of the command S5 in synchronization with the synchronization signal T1, thereby generating an encryption command S5A, and transmits the encryption command S5A to the memory device 3 in synchronization with the clock C1. To do. In the example of the present embodiment, the command length is 8 bytes, and 1-byte data transfer is performed in one cycle of the clock C1, and therefore a fixed-length period P1 (FIG. 2) corresponding to 8 cycles of the clock C1 This is the command transmission period. When the transmission of the last byte (eighth byte) of the encrypted command S5A is completed, the transmission control circuit 22 causes the transmission counter 32 to start a count operation, and the transmission counter 32 counts the number of cycles of the clock C1 thereafter. Further, when the transmission of the last byte (eighth byte) of the encryption command S5A is completed, the transmission control circuit 22 stops inputting the synchronization signal T1 to the encryption / decryption circuit 24. Thereby, the operation of the encryption / decryption circuit 24 stops with the end of the command transmission period P1.

  The control circuit 51 of the memory device 3 sends the clock C1 received from the host device 2 back to the host device 2, thereby transmitting the clock C2 having the same frequency as the clock C1 to the host device 2. Note that a clock C2 different from the clock C1 may be transmitted from the memory device 3 to the host device 2.

  The encryption / decryption circuit 61 restores the non-encrypted command S5 by decrypting the received encrypted command S5A. Further, the control circuit 51 reads desired data S7 from the memory array 52 by decoding the command S5. The control circuit 51 transmits the Busy signal S6 to the host device 2 until the process of reading the data S7 from the memory array 52 and the process of encrypting the data S7 by the encryption / decryption circuit 61 are completed. When the reading process and the encryption process are completed, the Ready signal S6 is transmitted, and the encrypted data S7A is transmitted following the Ready signal S6. The Busy signal S6, the Ready signal S6, and the encrypted data S7A are transmitted in synchronization with the clock C2.

  Referring to FIG. 2, a period P2 from when the host apparatus 2 completes transmission of the last byte of the encrypted command S5A to when reception of the Ready signal S6 is completed is a Ready / Busy period. Further, a period P3 following the Ready / Busy period P2 is a data reception period in which the host device 2 receives the encrypted data S7A from the memory device 3. In the example of the present embodiment, the read data length is 512 bytes, and data transfer of 1 byte is performed in one cycle of the clock C2, so that a fixed length period P3 corresponding to 512 cycles of the clock C2 is a data reception period. It becomes. However, as will be described later, the number of cycles of the data reception period P3 related to the clock C1 is corrected.

  When an encrypted command and encrypted data are transmitted / received between the host device 2 and the memory device 3, the host device 2 and the memory device 3 are indefinite due to the wiring delay between both devices and the buffer delay of the input / output buffer of the memory device 3 A long propagation delay occurs. When high-speed communication is performed using the high-frequency clocks C1 and C2, the propagation delay amount becomes larger than one cycle of the clocks C1 and C2. As shown in FIG. 2, the propagation delay PD exceeding one cycle of the clocks C1 and C2 is between the end of transmission of the last byte of the encrypted command S5A and the start of reception of the leading Busy signal S6. It has occurred. Since the delay amount of the propagation delay PD is indefinite and the number of cycles in which the Busy signal continues is also indefinite, the Ready / Busy period P2 has an indefinite length.

  Referring to FIG. 1, the reception control circuit 23 of the host device 2 receives the Busy signal S6, the Ready signal S6, and the encrypted data S7A, which are sequentially transmitted from the memory device 3, in synchronization with the clock C2. The reception control circuit 23 inputs the Busy signal S6 and the Ready signal S6 to the main control circuit 21, and inputs the encrypted data S7A to the encryption / decryption circuit 24. Further, every time the Busy signal S6 is received, the synchronization circuit 41 generates the synchronization signal T2 by synchronizing the Busy signal S6 with the reference clock C0, and inputs the synchronization signal T2 to the main control circuit 21. Further, when the synchronization circuit 41 receives the leading Busy signal S6, the synchronization counter 41 causes the reception counter 42 to start counting, and the reception counter 42 counts the number of cycles of the subsequent synchronization signal T2. When the Ready / Busy period P2 is also the encryption target period, the synchronization signal T2 is input to the encryption / decryption circuit 24.

  When the Ready signal S6 is input from the reception control circuit 23, the main control circuit 21 acquires the count values S3 and S8 at that time from the transmission counter 32 and the reception counter 42, respectively. Then, the delay cycle correction value is calculated by subtracting the count value S8 from the count value S3, and the delay cycle correction value is input to the access generation circuit 31 as access information. Further, when the Ready signal S6 is input from the reception control circuit 23, the main control circuit 21 ends the Ready / Busy period P2, and then proceeds to the data reception period P3.

  The access generation circuit 31 corrects the number of cycles in the data reception period based on the input delay cycle correction value. In the example of the present embodiment, the read data length is 512 bytes, and data transfer of 1 byte is performed in one cycle of the clock C1, so that the clock C1 is originally 512 after the Ready / Busy period P2 ends. The end point of the data reception period P3 is the time when the cycle has progressed. The access generation circuit 31 subtracts the number of cycles corresponding to the input delay cycle correction value from the number of cycles of the data reception period specified in the communication protocol (512 cycles in this example), thereby obtaining the data reception period P3. Correct the number of cycles. For example, when the delay cycle correction value is “2 cycles”, the end point of the data reception period P3 is the time when the clock C1 has progressed 510 (= 512-2) cycles after the Ready / Busy period P2 ends. Become.

  In the corrected data reception period P3, the reception control circuit 23 inputs the encrypted data S7A received from the memory device 3 to the encryption / decryption circuit 24. Further, every time the encrypted circuit S7A is received, the synchronization circuit 41 generates the synchronization signal T3 by synchronizing the encrypted data S7A with the reference clock C0, and inputs the synchronization signal T3 to the encryption / decryption circuit 24. .

  The encryption / decryption circuit 24 restores the non-encrypted data S7 by executing the decryption process of the encrypted data S7A in synchronization with the synchronization signal T3, and inputs the data S7 to the main control circuit 21. The main control circuit 21 transfers the data S7 sequentially input from the reception control circuit 23 to the CPU 11.

  Thus, according to the memory system 1 according to the present embodiment, the transmission control circuit 22 and the encryption / decryption circuit 24 as the encryption circuit operate in synchronization with the clock C1 (first clock), and the reception control circuit 23 and The encryption / decryption circuit 24 as a decryption circuit operates in synchronization with the clock C2 (second clock). Therefore, even when the communication speed is increased, the encryption process and the decryption process can be appropriately synchronized. As a result, the high-speed encryption communication between the host device 2 and the memory device 3 can be reduced. It can be realized easily and cost-effectively.

  Further, the control circuit 51 of the memory device 3 feeds back the clock C1 received from the transmission control circuit 22 of the host device 2 to transmit it to the reception control circuit 23 of the host device 2 as the clock C2. The reception control circuit 23 controls data reception from the memory device 3 in synchronization with the fed back clock C2. Accordingly, since it is not necessary to newly generate a data strobe signal different from the clocks C1 and C2, mounting of a data strobe signal generation circuit and a timing adjustment circuit can be omitted. As a result, the host device 2 and the memory device 3 It is possible to easily realize high-speed encrypted communication between the two at low cost. Since the clock C1 is fed back as the clock C2, when the encrypted data S7A is transmitted from the memory device 3 to the host device 2 in synchronization with the clock C2, the propagation delay amount associated with the wiring delay and the buffer delay is clocked. C2 and encrypted data S7A can be substantially offset, and as a result, data loss can be prevented.

  Further, the main control circuit 21 of the host device 2 determines a delay cycle correction value based on the propagation delay amount between the host device 2 and the memory device 3, and the transmission control circuit 22 is based on the delay cycle correction value. Thus, the cycle number of the clock C1 from the start of data reception from the memory device 3 to the completion of data reception is corrected. In this way, by correcting the fixed cycle number specified by the communication protocol based on the delay cycle correction value determined from the indefinite propagation delay amount, the fixed cycle number can be secured without excess or deficiency. Since the internal state of the encryption circuit and the decryption circuit (the encryption / decryption circuit 24 in the above example) of the device 2 and the encryption circuit and the decryption circuit (the encryption / decryption circuit 61 in the above example) of the memory device 3 can be matched, The system can be operated normally.

  In addition, the main control circuit 21 counts the count value S3 of the transmission counter 32 from the completion of command transmission to the memory device 3 to the reception of the Ready signal S6 from the memory device 3, and the first Busy signal from the memory device 3. The delay cycle correction value is determined based on the count value S8 of the reception counter 42 from when S6 is received until the Ready signal S6 is received from the memory device 3. Accordingly, the delay cycle correction value can be accurately determined based on the indefinite propagation delay amount accompanying the wiring delay and the buffer delay and the indefinite Busy cycle number accompanying reading of data from the memory array 52, so that the fixed cycle number Can be corrected with high accuracy.

  Further, since the common encryption / decryption circuit 24 is mounted as the encryption circuit and the decryption circuit, the circuit scale of the host device 2 can be reduced as compared with the case where the encryption circuit and the decryption circuit are individually mounted. .

<Embodiment 2>
FIG. 3 is a diagram showing a configuration of the memory system 1 according to the second embodiment of the present invention. Instead of the encryption / decryption circuit 24 shown in FIG. 1, an encryption circuit 24A and a decryption circuit 24B are individually mounted.

  In the command transmission period P1, the command S5 is input from the transmission control circuit 22 to the encryption circuit 24A in order to generate the encrypted command S5A from the non-encrypted command S5. At this time, the synchronization signal T1 for operating the encryption circuit 24A is input from the transmission control circuit 22 to the encryption circuit 24A and also input to the decryption circuit 24B.

  In the data reception period P3, the encrypted data S7A is input from the reception control circuit 23 to the decryption circuit 24B in order to restore the encrypted data S7A to the non-encrypted data S7. At this time, the synchronization signal T3 for operating the decryption circuit 24B is input from the reception control circuit 23 to the decryption circuit 24B and also to the encryption circuit 24A.

  As described above, according to the memory system 1 according to the present embodiment, since the encryption circuit 24A and the decryption circuit 24B are individually mounted, it is easy to optimally design each of the encryption circuit 24A and the decryption circuit 24B. Can be done.

  Also, the transmission control circuit 22 inputs the synchronization signal T1 (first synchronization signal) to the encryption circuit 24A and the decryption circuit 24B, so that the encryption circuit 24A decrypts the command S5 within the period. The circuit 24B is operated. In addition, the reception control circuit 23 inputs the synchronization signal T3 (second synchronization signal) to the encryption circuit 24A and the decryption circuit 24B, so that the decryption circuit 24B performs the decryption of the encrypted data S7A. The cryptographic circuit 24A is operated at In this way, by operating one of the encryption circuit 24A and the decryption circuit 24B while the other is executing a process, the internal state of the key stream or the like of the encryption circuit 24A and the decryption circuit 24B is matched. As a result, appropriate encryption communication can be realized.

<Modification>
FIG. 4 is a diagram showing a configuration of the memory system 1 according to a modification of the first embodiment. The reception counter 42 is omitted from the configuration shown in FIG. FIG. 5 is a timing chart showing the read operation of the memory system 1.

  When the transmission of the last byte (eighth byte) of the encrypted command S5A is completed, the access generation circuit 31 causes the transmission counter 32 to start a count operation, and the transmission counter 32 counts the number of cycles of the clock C1 thereafter.

  When the leading Busy signal S6 is input from the reception control circuit 23, the main control circuit 21 acquires the count value S3 at that time from the transmission counter 32. Then, the number of cycles indicated by the count value S3 is determined as a delay cycle correction value, and the delay cycle correction value is input to the access generation circuit 31 as access information.

  The access generation circuit 31 subtracts the number of cycles corresponding to the input delay cycle correction value from the number of cycles of the data reception period specified in the communication protocol (512 cycles in this example), thereby obtaining the data reception period P3. Correct the number of cycles. For example, when the delay cycle correction value is “2 cycles”, the end point of the data reception period P3 is the time when the clock C1 has progressed 510 (= 512-2) cycles after the Ready / Busy period P2 ends. Become.

  Thus, according to the memory system 1 according to this modification, the main control circuit 21 receives the first Busy signal S6 from the memory device 3 after the transmission of the encryption command S5A to the memory device 3 is completed. The delay cycle correction value is determined based on the count value S3 of the transmission counter 32 until the above. Therefore, it becomes possible to easily determine the delay cycle correction value based on the indefinite propagation delay amount accompanying the wiring delay and the buffer delay. Further, since the delay cycle correction value can be determined early without waiting for the completion of the Ready / Busy period P2, error processing can be started early when the delay cycle correction value is an abnormal value. Furthermore, since the reception counter 42 is not required and the count value of the transmission counter 32 can be reduced, the circuit scale of the host device 2 can be reduced as a whole.

  In addition, although the example which applies this modification to the said Embodiment 1 was described in the above description, this modification can also be applied to the said Embodiment 2, and can acquire the effect similar to the above. Can do.

DESCRIPTION OF SYMBOLS 1 Memory system 2 Host apparatus 3 Memory apparatus 21 Main control circuit 22 Transmission control circuit 23 Reception control circuit 24 Encryption / decryption circuit 24A Encryption circuit 24B Decryption circuit 51 Control circuit 52 Memory array

Claims (8)

A host device;
A memory device connected to the host device;
With
The host device is
A transmission control circuit for controlling command transmission to the memory device in synchronization with a first clock;
An encryption circuit for generating an encrypted command by encrypting a command to be transmitted to the memory device in synchronization with a first clock;
A reception control circuit for controlling data reception from the memory device in synchronization with a second clock;
A decryption circuit for decrypting encrypted data received from the memory device in synchronization with a second clock;
A memory system. The memory device includes:
A memory array in which data is stored;
A control circuit for controlling access to the memory array;
Have
The transmission control circuit transmits a first clock to the control circuit;
The memory system according to claim 1, wherein the control circuit transmits the first clock received from the transmission control circuit to the reception control circuit as a second clock. The host device further includes a main control circuit that controls the transmission control circuit and the reception control circuit,
The main control circuit determines a predetermined correction value based on a propagation delay amount between the host device and the memory device,
The transmission control circuit corrects the number of cycles of the first clock from the start of data reception from the memory device to the completion of the data reception based on the correction value input from the main control circuit. The memory system according to claim 2. The transmission control circuit includes a first counter that counts the number of cycles of the first clock,
The reception control circuit includes a second counter that counts the number of cycles of the second clock,
The main control circuit receives the count value of the first counter from the completion of command transmission to the memory device to reception of a Ready signal from the memory device, and the first Busy signal from the memory device. The memory system according to claim 3, wherein the correction value is determined based on a count value of the second counter until a Ready signal is received from the memory device. The transmission control circuit includes a first counter that counts the number of cycles of the first clock,
The main control circuit calculates the correction value based on a count value of the first counter from completion of command transmission to the memory device to reception of a first Busy signal from the memory device. The memory system according to claim 3.   The memory system according to claim 1, wherein a common encryption / decryption circuit is mounted as the encryption circuit and the decryption circuit.   The memory system according to claim 1, wherein the encryption circuit and the decryption circuit are individually mounted. The transmission control circuit inputs a first synchronization signal to the encryption circuit and the decryption circuit, thereby operating the decryption circuit within a period in which the encryption circuit is executing command encryption,
The reception control circuit operates the encryption circuit during a period in which the decryption circuit performs decryption of encrypted data by inputting a second synchronization signal to the encryption circuit and the decryption circuit. The memory system according to claim 7.

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