JP2017016570A - Compiler device, compiler method and compiler program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compiler device that can generate objects capable of efficiently using an arithmetic unit owned by a processor.SOLUTION: The present compiler device comprises an extraction unit, a first generation unit, a second generation unit and a third generation unit. The extraction unit is configured to extract a command string in an input source file when detecting a repeat command instructing to repeat the command string in the input source file, and the first generation unit is configured to convert a command to be included in the extracted command string into an integer command of implementing an integer computation to generate an integer command string. The second generation unit is configured to convert the command to be included in the extracted command string into a floating point command implementing a floating point computation, and generates a floating point command string. The third generation unit is configured to generate an output command string including the integer command string and the floating point command string on the basis of the number of integer arithmetic units and number of floating point arithmetic units which serve as an execution environment of objects having a source file compiled and are owned by processors.SELECTED DRAWING: Figure 12

Description

  The present invention relates to a compiler apparatus, a compiling method, and a compiler program.

  Recent processors have a plurality of computing units that execute input instructions, thereby realizing a superscalar that executes a plurality of instructions in parallel. Further, recent processors realize an out-of-order that can be executed by changing the order of instructions when there is no dependency relationship or branch instruction between instructions. The arithmetic unit includes an integer arithmetic unit that performs integer arithmetic and a floating point arithmetic unit that performs floating point arithmetic. That is, an integer instruction that performs an integer operation is executed by an integer arithmetic unit, and a floating point instruction that performs a floating point operation is executed by a floating point arithmetic unit.

JP-A-4-307624 Japanese Patent Laid-Open No. 11-110215

  Therefore, if there is a bias in the ratio of integer instructions and floating point instructions included in the object executed by the processor, there is a risk that the processing will be concentrated on one of the integer arithmetic unit and the floating point arithmetic unit. As a result, the other arithmetic unit may not be used efficiently. Accordingly, an object of one aspect of the disclosed technique is to provide a compiler apparatus that can generate an object that can efficiently use an arithmetic unit included in a processor.

  One aspect of the disclosed technique is exemplified by the following compiler apparatus. The compiler apparatus includes an extraction unit, a first generation unit, a second generation unit, and a third generation unit. When the extraction unit detects a repetitive instruction instructing repetition of the instruction sequence in the input source file, the extraction unit extracts an instruction sequence repeated by the repetitive instruction. The first generation unit generates an integer instruction sequence by converting an instruction included in the extracted instruction sequence into an integer instruction for performing an integer operation. The second generation unit converts an instruction included in the extracted instruction sequence into a floating point instruction for performing a floating point operation, and generates a floating point instruction sequence. The third generation unit outputs an output instruction including an integer instruction sequence and a floating-point instruction sequence based on the number of integer arithmetic units and the number of floating-point arithmetic units included in a processor that is an execution environment of an object compiled from a source file. Generate a column.

  This compiler apparatus can generate an object that can efficiently use an arithmetic unit included in a processor.

FIG. 1 is a diagram illustrating a hardware configuration of the information processing apparatus. FIG. 2 is a diagram illustrating an example of a configuration of a processor included in the information processing apparatus. FIG. 3 is a diagram illustrating an example of the intermediate code. FIG. 4 is a diagram illustrating an example of the relationship between blocks and instructions. FIG. 5 is a diagram illustrating an example of a loop instruction sequence. FIG. 6 is a diagram illustrating an example of an instruction sequence after loop expansion. FIG. 7 is a diagram illustrating an example of processing in which each instruction included in the instruction sequence input to the processor is executed by a plurality of arithmetic units. FIG. 8 is a diagram illustrating an example of a state in which each instruction included in the instruction sequence is distributed and executed by a plurality of arithmetic units. FIG. 9 is a diagram illustrating an example of a state in which execution of each instruction included in the instruction sequence is concentrated on one arithmetic unit. FIG. 10 is a diagram illustrating an example of a flow of processing for compiling a program. FIG. 11 is a diagram illustrating an example of compilation and execution of a program after compilation. FIG. 12 is a diagram illustrating an example of processing blocks of the compiler apparatus according to the first embodiment. FIG. 13 is a diagram showing an example of a loop instruction sequence input to the compiler apparatus. FIG. 14 is a diagram illustrating an example of a source file that is not suitable for loop expansion. FIG. 15 is a diagram illustrating an example of the flow of loop expansion processing by the compiler apparatus according to the first embodiment. FIG. 16 is a diagram illustrating an example of a loop structure. FIG. 17 is a diagram illustrating an example of a loop instruction sequence input in the first embodiment. FIG. 18 is a diagram illustrating an example of a detailed flow of the processes of F4 and F5 of FIG. FIG. 19 is a diagram illustrating an example of the FU conversion table. FIG. 20 is a diagram illustrating an example of the IU conversion table. FIG. 21 is a diagram illustrating an example of correspondence between before and after conversion of each instruction included in the input loop operation instruction sequence into an integer instruction. FIG. 22 is a diagram illustrating an example of correspondence between before and after conversion of each instruction included in the input loop operation instruction sequence into a floating-point operation instruction. FIG. 23 is a diagram illustrating an example of a loop operation instruction sequence expansion process. FIG. 24 is a diagram illustrating an example of a virtual register map. FIG. 25 is a diagram illustrating an example of a virtual register conversion process in the reference list operand. FIG. 26 is a diagram illustrating an example of correspondence before and after the loop expansion of the memory operand. FIG. 27 is a diagram illustrating conversion of memory operands at each expansion number. FIG. 28 is a diagram illustrating an example of a virtual register operand conversion process in the definition list operand. FIG. 29 is a diagram illustrating an example of an instruction sequence stored in the output loop instruction sequence storage unit. FIG. 30 is a diagram illustrating an example of a loop instruction sequence in which the rotation speed is corrected. FIG. 31 is a diagram illustrating an example of an instruction sequence of a loop after loop expansion. FIG. 32 is a diagram illustrating an example of a usage state of an arithmetic unit when an instruction sequence is executed. FIG. 33 is a diagram illustrating an example of a usage state of an arithmetic unit when an instruction sequence is executed. FIG. 34 is an example of a processing block for performing loop expansion of the compiler apparatus according to the first comparative example. FIG. 35 is a diagram exemplifying a loop instruction sequence. FIG. 36 is a diagram illustrating an example of an instruction sequence in which the loop illustrated in FIG. 35 is loop expanded by the compiler apparatus according to the first comparative example. FIG. 37 is a diagram schematically illustrating loop expansion according to the second comparative example. FIG. 38 is a diagram illustrating FIG. 37 by pseudo code. FIG. 39 is an example of a diagram comparing the loop expansion according to the first comparative example and the loop expansion according to the first embodiment. FIG. 40 is a diagram illustrating an example of a loop included in a source file input to the compiler. FIG. 41 is a diagram illustrating an example of an instruction sequence obtained by performing loop expansion on the loop illustrated in FIG. 40 according to the first comparative example. FIG. 42 is a diagram illustrating an example of an instruction sequence obtained by performing loop expansion according to the first embodiment on the loop illustrated in FIG. FIG. 43 is a diagram illustrating an example of the regression calculation. FIG. 44 is a diagram illustrating an example of an instruction including a reference operand and a definition operand. FIG. 45 is a diagram showing an example of a loop instruction string input to the compiler apparatus. FIG. 46 is a diagram illustrating an example of an instruction sequence in which the instruction sequence after loop expansion illustrated in FIG. 45 is expressed by intermediate code. FIG. 47 is a diagram illustrating an example of the flow of loop expansion processing performed by the compiler apparatus according to the first modification. FIG. 48 is a diagram showing an example of a detailed flow of the processing of R1 and R2 of FIG. FIG. 49 is an example of a diagram illustrating initialization processing for regression calculation. FIG. 50 is a diagram illustrating an example of a loop operation instruction sequence expansion process. FIG. 51 is a diagram illustrating an example of a regression calculation instruction. FIG. 52 is a diagram illustrating an example of rewrite processing of a regression calculation instruction. FIG. 53 is a diagram illustrating an example of rewrite processing of a regression calculation instruction. FIG. 54 is a diagram illustrating an example of rewrite processing of a regression calculation instruction. FIG. 55 is a diagram illustrating an example of rewrite processing of a regression calculation instruction. FIG. 56 is a diagram illustrating an example of rewrite processing of a regression calculation instruction. FIG. 57 is a diagram showing an example of a loop operation instruction sequence after loop expansion. FIG. 58 is a diagram showing an example of an initialization instruction sequence after loop expansion. FIG. 59 is a diagram illustrating an example of a converged instruction sequence after loop expansion. FIG. 60 is a diagram showing an example of a loop instruction sequence after loop expansion. FIG. 61 is a diagram showing an example of a loop instruction sequence after loop expansion.

  Hereinafter, a compiler apparatus according to an embodiment will be described with reference to the drawings. The configuration of the embodiment described below is an exemplification, and the disclosed technology is not limited to the configuration of the embodiment.

<First Embodiment>
FIG. 1 is a diagram illustrating a hardware configuration of the information processing apparatus 100. The information processing apparatus 100 includes a processor 101, a main storage unit 102, an auxiliary storage unit 103, a communication unit 104, and a connection bus B1. The processor 101, the main storage unit 102, the auxiliary storage unit 103, and the communication unit 104 are connected to each other by a connection bus B1. The information processing apparatus 100 can be used as the compiler apparatus 10 according to the first embodiment, for example. The compiler apparatus 10 generates an object executable by the processor by compiling a source file of the input program.

In the information processing apparatus 100, the processor 101 expands the program stored in the auxiliary storage unit 103 in the work area of the main storage unit 102, and controls peripheral devices through execution of the program. Thereby, the information processing apparatus 100 can execute a process that matches a predetermined purpose. The main storage unit 102 and the auxiliary storage unit 103 are recording media that can be read by the information processing apparatus 100.

  The main storage unit 102 is exemplified as a storage unit that is directly accessed from the processor 101. The main storage unit 102 includes a random access memory (RAM) and a read only memory (ROM).

  The auxiliary storage unit 103 stores various programs and various data in a recording medium in a readable and writable manner. The auxiliary storage unit 103 is also called an external storage device. The auxiliary storage unit 103 stores an operating system (OS), various programs, various tables, and the like. The OS includes a communication interface program that exchanges data with an external device or the like connected via the communication unit 104. Examples of the external device include other information processing devices and external storage devices connected via a computer network or the like. The auxiliary storage unit 103 may be a part of a cloud system that is a group of computers on a network, for example.

The auxiliary storage unit 103 includes, for example, an Erasable Programmable ROM (EPROM), a solid state drive (SSD), and a hard disk drive (Hard Disk).
Drive, HDD). The auxiliary storage unit 103 is, for example, a Compact Disc (CD) drive device, a Digital Versatile Disc (DVD) drive device, or a Blu-ray (registered trademark) Disc (BD) drive device. Further, the auxiliary storage unit 103 may be provided by Network Attached Storage (NAS) or Storage Area Network (SAN).

  A recording medium that can be read by the information processing apparatus 100 is a recording medium that stores information such as data and programs by electrical, magnetic, optical, mechanical, or chemical action and can be read from the information processing apparatus 100. Say medium. Examples of such a recording medium that can be removed from the information processing apparatus 100 include a flexible disk, a magneto-optical disk, a CD-ROM, a CD-R / W, a DVD, a Blu-ray disk, a DAT, an 8 mm tape, a flash memory, and the like. There are memory cards. In addition, as a recording medium fixed to the information processing apparatus 100, there are a hard disk, an SSD, a ROM, and the like.

  The communication unit 104 is, for example, an interface with a computer network. The communication unit 104 communicates with an external device via a computer network.

  The information processing apparatus 100 may further include, for example, an input unit that receives an operation instruction from a user or the like. Examples of such an input unit include an input device such as a keyboard, a pointing device, a touch panel, an acceleration sensor, or a voice input device.

The information processing apparatus 100 may include an output unit that outputs data processed by the processor 101 and data stored in the main storage unit 102, for example. Examples of such an output unit include output devices such as a Cathode Ray Tube (CRT) display, a Liquid Crystal Display (LCD), a Plasma Display Panel (PDP), an Electroluminescence (EL) panel, an organic EL panel, or a printer.

FIG. 2 is a diagram illustrating an example of the configuration of the processor 101 included in the information processing apparatus 100. The processor 101 has one integer arithmetic unit 101a and two floating point arithmetic units 101b and 101b. The integer arithmetic unit 101a is an arithmetic unit that performs integer arithmetic. The floating point arithmetic units 101b and 101b are arithmetic units that execute floating point arithmetic. The processor 101 includes a plurality of arithmetic units, so that a plurality of instructions can be executed in parallel. In the drawing, the integer arithmetic unit 101a is described as “IU”, and the floating point arithmetic unit 101b is described as “FU”.

  Here, an intermediate code that is an expression of an instruction in the compiler apparatus 10 will be described. FIG. 3 is a diagram illustrating an example of the intermediate code. The intermediate code will be described with reference to FIG.

“Ld”, “mult”, and “st” illustrated in FIG. 3 are examples of instruction codes represented by intermediate codes. There are two types of instruction codes: integer type integer instructions and floating point type floating point instructions. An integer instruction performs an integer operation. Floating point instructions perform floating point operations. That is, the integer instruction is executed by the integer arithmetic unit 101a, and the floating point instruction is executed by the floating point arithmetic unit 101b. “Ld”, “mult”, and “st” illustrated in FIG. 3 are all examples of integer instructions. "[A + $ g1], $ g2", "$ g2, 5, $ g3" and "$ g3, [b + $ g1]" described after the instruction are arguments passed to the instruction and operands. Called. For example, a plurality of operands can be specified by separating them with a comma (,). As the operand, a virtual register, a memory operand, a constant, or the like is designated. An integer type operand is specified for the integer instruction. A floating-point type operand is specified for the floating-point instruction.

The virtual register is a virtual register used in the intermediate code. In Figure 3, “$ g1
”,“ $ G2 ”, and“ $ g3 ”are examples of virtual registers. The virtual register is a virtual register inside the compiler that is allocated when the source file is compiled by the compiler apparatus 10. The virtual registers include an integer type virtual register that handles integers and a floating point type virtual register that handles floating point numbers. In this specification, the integer type is also referred to as int type, and the floating point type is also referred to as float type. An int type virtual register is specified by a combination of a virtual register name “$ g” and a number that is a virtual register number. A float type virtual register is specified by a combination of a virtual register name “$ f” and a number that is a virtual register number. In both the int type and float type virtual registers, the virtual register number starts from 1, and the virtual register number is incremented by 1 each time a new virtual register is created.

A memory operand is specified by an address constant, a virtual register, and an offset. In FIG. 3, “[a + $ g1]” and “[b + $ g1]” are examples of memory operands. The address constant is specified by a character string as a label indicating the address. In FIG. 3, “a” in “[a + $ g1]” and “b” in “[b + $ g1]” are address constants. The offset is a numerical value indicating the distance from the address specified by the address constant and the virtual register. In FIG. 3, the offsets of “[a + $ g1]” and “[b + $ g1]” are both “0”. That is, “[a + $ g1]” illustrated in FIG. 3 specifies the memory at the address obtained by adding the address indicated by the address constant “a” and the value of the virtual register “$ g1”. Further, “[b + $ g1]” illustrated in FIG. 3 specifies the memory at the address obtained by adding the address indicated by the address constant “b” and the value of the virtual register “$ g1”.

“Label” in FIG. 3 is a label indicating the head position of the block. The block includes a plurality of instructions. In the branch instruction or the jump instruction, the process is advanced to the head of the block by specifying the label. A basic block is a block that does not include a branch in the block. Since the basic block does not include a branch, when the first instruction in the basic block is executed, the instruction is executed up to the last instruction without branching on the way.

FIG. 4 is a diagram illustrating an example of the relationship between blocks and instructions. FIG. 4 shows an example of the relationship between a block and an instruction based on the instruction sequence illustrated in FIG. In the first “ld” instruction, the value of the memory specified by the address indicated by the sum of the value indicated by the address constant “a” and the value stored in the virtual register “$ g1” is the virtual register “$ g2”. Is read. In the next “mult” instruction, the result of multiplication of the value read into the virtual register “$ g2” and the number “5” is stored in the virtual register “$ g3”. In the last “st” instruction, the value stored in the virtual register “$ g3” is stored in the memory specified by the address indicated by the sum of the address constant “b” and the virtual register “$ g1”. .

FIG. 5 is a diagram illustrating an example of a loop instruction sequence. The instruction sequence of the loop includes an initialization instruction sequence, a loop operation instruction sequence, and a loop instruction sequence. The initialization instruction sequence initializes the loop. The initialization of the loop includes initialization of a loop counter used for the loop. In FIG. 5, the loop counter is initialized by assigning 0 to the virtual register “$ g1” designated as the loop counter. The label “Label” specifies the head position of the loop operation instruction sequence. The loop operation instruction sequence includes instructions that are repeatedly executed by the loop. The loop instruction sequence includes an addition instruction or subtraction instruction and a comparison branch instruction. The addition instruction or subtraction instruction in the loop instruction sequence changes the value of the loop counter by addition or subtraction. In FIG. 5, “4” is added to the loop counter “$ g1” by the addition instruction “add”. The comparison branch instruction branches the process according to a specified condition. In FIG. 7, when the value of the loop counter “$ g1” is less than “90 × 4”, the process proceeds to the head position of the loop operation instruction sequence specified by the label “Label”. That is, the loop repeatedly executes the instructions in the loop operation instruction sequence according to the conditions specified by the initialization instruction sequence and the loop instruction sequence. When the loop operation instruction sequence is a basic block, the loop is referred to as an innermost loop.

FIG. 6 is a diagram illustrating an example of an instruction sequence after loop expansion. FIG. 6 is an example of an instruction sequence obtained by loop expansion of the instruction sequence of the loop illustrated in FIG. Loop unrolling is also called loop unrolling. In the loop expansion, the number of rotations of the loop is reduced by expanding the instructions in the loop operation instruction sequence. In FIG. 6, the loop is expanded so that three rotations of the loop operation instruction sequence illustrated in FIG. 5 are executed in one loop. The number of loop operation instruction sequences before expansion that are executed in one loop after expansion is referred to as the number of loop expansions. In the case of FIG. 6, the number of expansions is “3”. That is, the loop expansion reduces the number of loop rotations and increases the number of instruction sequences executed in one loop. Each of A, B, and C illustrated in FIG. 6 corresponds to an instruction sequence for one loop rotation of the loop instruction sequence illustrated in FIG. Expansion numbers are assigned to the instruction sequences exemplified by A, B, and C in this order. That is, the expansion number of the instruction sequence illustrated by A is 1, the expansion number of the instruction sequence illustrated by B is 2, and the expansion number of the instruction sequence illustrated by C is 3. For example, the offset value of the memory operand after conversion can be calculated by multiplying the offset value before conversion by the value of (development number −1). For example, in the instruction sequence before conversion illustrated in FIG. 5, the value of the virtual register “$ g1” is incremented by “4” every rotation by the addition instruction. Therefore, in the instruction sequence after loop expansion illustrated in FIG. 6, for example, an offset value of “(2-1) × 4 = 4” is added to the memory operand of the B instruction sequence (expansion number 2). Yes. Further, with the loop expansion, the increment per one rotation of the loop counter in the loop instruction sequence is corrected. Since the expansion number is “3” in the loop illustrated in FIG. 6, “4 × 3” is added to the loop counter “$ g1” in the addition instruction in the loop instruction string. By performing loop expansion, branch instructions between the instruction sequences exemplified by A, B, and C can be eliminated. As a result of the elimination of the branch instruction, each instruction sequence exemplified by A, B, and C can be executed in parallel by a plurality of arithmetic units. Therefore, the efficiency of parallel execution of instructions can be increased by loop expansion.

FIG. 7 is a diagram illustrating an example of processing in which each instruction included in the instruction sequence input to the processor 101 is executed by a plurality of arithmetic units. In FIG. 7, FU0 corresponds to one of the floating point arithmetic units 101b, and FU1 corresponds to the other of the floating point arithmetic units 101b. IU0 corresponds to the integer arithmetic unit 101a. FIG. 7 illustrates processing from the first cycle to the third cycle. The instruction “fadd” included in the instruction sequence of FIG. 7 is an example of a floating-point instruction. The “fadd” which is a floating point instruction is executed by the FU0 or FU1 which is the floating point arithmetic unit 101b. As a result, in the first cycle, “fadd $ f0, $ f1, $ f2” described in the first line of the instruction sequence is executed by FU0, and “fadd $ f3, $ f4” described in the second line of the instruction sequence is executed. , $ f5 "is executed by FU1. In the second cycle, “fadd $ f6, $ f7, $ f8” described in the third row of the instruction sequence is executed by FU0, and “fadd $ f9, $ f10, $ f11” described in the fourth row of the instruction sequence is executed. "Is executed in FU1. In the third cycle, “fadd $ f12, $ f13, $ f14” described in the fifth line of the instruction sequence is executed by FU0. This instruction sequence does not include integer instructions. Therefore, IU0, which is an integer arithmetic unit 101b that executes integer instructions, does not perform processing while the processor 101 executes the instruction sequence of FIG.

FIG. 8 is a diagram illustrating an example of a state in which each instruction included in the instruction sequence is distributed and executed by a plurality of arithmetic units. In FIG. 8, processing from the first cycle to the third cycle is illustrated. The instruction “add” included in the instruction sequence of FIG. 8 is an example of an integer instruction. The integer instruction “add” is executed by the IU0 which is the integer arithmetic unit 101b. As a result, in the first cycle, “fadd $ f0, $ f1, $ f2” described in the first line of the instruction sequence is executed by FU0, and “fadd $ f3, $ f4” described in the second line of the instruction sequence is executed. , $ f5 ”is executed by FU1, and“ add $ g0, $ g1, $ g2 ”described in the third line of the instruction sequence is executed by IU0. In the second cycle, “fadd $ f6, $ f7, $ f8” described in the fourth row of the instruction sequence is executed by FU0, and “fadd $ f9, $ f10, $ f11” described in the fifth row of the instruction sequence is executed. Is FU
1 is executed.

  FIG. 9 is a diagram illustrating an example of a state in which execution of each instruction included in the instruction sequence is concentrated on one arithmetic unit. In FIG. 9, processing from the first cycle to the third cycle is illustrated. All the instructions included in the instruction sequence of FIG. 9 are integer instructions. Therefore, all the instructions included in the instruction sequence of FIG. 9 are executed by IU0 which is the integer arithmetic unit 101b. As a result, FU0 and FU1, which are floating point arithmetic units, do not perform processing while the processor 101 executes the instruction sequence illustrated in FIG.

  As can be seen by comparing FIG. 8 and FIG. 9, if the instruction included in the instruction sequence input to the processor 101 is biased to one of the integer instruction and the floating-point instruction, the arithmetic unit included in the processor 101 cannot be used effectively. There is a fear.

  FIG. 10 is a diagram illustrating an example of a flow of processing for compiling a program. Compilation of the program is executed by the compiler apparatus 10. At T1, the compiler apparatus 10 performs syntax analysis of the source file of the input program. In the syntax analysis, it is analyzed whether or not the source file matches the specification of the programming language. At T2, the compiler apparatus 10 performs optimization. Optimization includes loop expansion that expands the instructions contained in the loop. At T3, the compiler apparatus 10 performs register allocation. Here, the compiler apparatus 10 assigns a virtual register to a register included in the processor 101. At T4, the compiler apparatus 10 performs instruction scheduling. In instruction scheduling, the execution order of each instruction is rearranged so that the integer arithmetic unit 101a and floating point arithmetic units 101b and 101b of the processor 101 can be used efficiently. At T <b> 5, the compiler apparatus 10 generates code that can be executed by the processor 101. Executable code is also referred to as an object.

FIG. 11 is a diagram illustrating an example of compilation and execution of a program after compilation. T11 corresponds to T2 in FIG. At T11, the optimization process described in this embodiment is performed. T12 and T13 are processes corresponding to T4 and T5 in FIG. 10, respectively. In T14, the processor 101 executes the compiled program. The processor 101 detects instructions that can be executed simultaneously from the execution format objects generated in T13, and executes the instructions detected by out-of-order and superscalar in parallel.

<Processing Block of Compiler Device 10>
FIG. 12 is a diagram illustrating an example of processing blocks of the compiler apparatus 10 according to the first embodiment. FIG. 12 illustrates processing blocks of the optimization unit 200, the intermediate code unit 260, the machine model 201, the NFU number storage unit 202, and the NIU number storage unit 203. For example, the processor 101 in FIG. 1 executes a computer program loaded in the main storage unit 102 as each processing block in FIG. However, at least a part of any of the processing blocks in FIG. 12 may include a hardware circuit, a dedicated processor, or a digital signal processor (DSP).

  The machine model 201 stores information for each processor type in advance. The machine model 201 stores, for example, the numbers of integer arithmetic units and floating point arithmetic units for each processor type. The machine model 201 is an example of a “processor information storage unit”.

  For example, the optimization unit 200 performs an optimization process exemplified by T2 in FIG. The optimization unit 200 includes an arithmetic unit number acquisition unit 210, an instruction conversion unit 220, and an instruction expansion unit 230. The arithmetic unit number acquisition unit 210 acquires the number of arithmetic units included in the processor 101. The arithmetic unit number acquisition unit 210 includes an NIU acquisition unit 211 that acquires the number of integer arithmetic units and an NFU acquisition unit 212 that acquires the number of floating point arithmetic units. The processor 101 refers to the machine model 201 as the NIU acquisition unit 211 and acquires the number of integer arithmetic units 101 a included in the processor 101. The NIU acquisition unit 211 stores the acquired number of integer arithmetic units 101 a in the NIU number storage unit 203. The processor 101 refers to the machine model 201 as the NFU acquisition unit 202 and acquires the number of floating point arithmetic units 101b included in the processor 101. The NFU acquisition unit 212 stores the acquired number of floating-point arithmetic units 101 b in the NFU number storage unit 202. The arithmetic unit number acquisition unit 210 is an example of a “calculator unit acquisition unit”.

  The instruction conversion unit 220 calculates the number of integer instructions and floating point instructions included in the loop operation instruction sequence. Further, the instruction conversion unit 220 converts integer instructions into floating point instructions and floating point instructions into integer instructions. The instruction conversion unit 220 includes an IU instruction conversion unit 221 and an FU instruction conversion unit 222. As the IU instruction conversion unit 221, the processor 101 converts an instruction included in the loop operation instruction sequence stored in the loop operation instruction sequence storage unit 261 into an integer instruction. The IU instruction conversion unit 221 stores the instruction converted into the integer instruction in the IU conversion instruction string storage unit 263. As the FU instruction conversion unit 222, the processor 101 converts an instruction included in the loop operation instruction sequence stored in the loop operation instruction sequence storage unit 261 into a floating-point instruction. The FU instruction conversion unit 222 stores the instruction converted into the floating point instruction in the FU conversion instruction string storage unit 262. The instruction conversion unit 220 is an example of an “extraction unit”.

  The instruction expansion unit 230 expands a loop operation instruction sequence included in the loop instruction sequence. The instruction expansion unit 230 includes an IU instruction expansion unit 231 and a FU instruction expansion unit 232. The processor 101 expands the loop operation instruction sequence converted into the integer instruction by the IU instruction conversion unit 221 as the IU instruction expansion unit 231. The processor 101 expands the loop operation instruction sequence converted into the floating point instruction by the FU instruction conversion unit 222 as the FU instruction expansion unit 232. The IU instruction expansion unit 231 is an example of a “first generation unit”. The FU instruction expansion unit 232 is an example of a “second generation unit”. The instruction expansion unit 230 is an example of a “third generation unit”.

The loop instruction correction unit 240 corrects the loop instruction accompanying the loop expansion by the instruction expansion unit 230. For example, the loop command correction unit 240 corrects a numerical value added to the loop counter in the loop command. The loop command correction unit 240 is an example of a “determination unit”.

  The intermediate code unit 260 stores the intermediate code input to the compiler apparatus 10. The intermediate code unit 260 includes a loop operation instruction sequence storage unit 261, an FU conversion instruction sequence storage unit 262, an IU conversion instruction sequence storage unit 263, an FU output instruction sequence storage unit 264, an IU output instruction sequence storage unit 265, and an output instruction sequence storage. Part 266.

  The loop operation instruction sequence storage unit 261 stores a loop operation instruction sequence included in the source file input to the compiler apparatus 10. The FU conversion instruction string storage unit 262 stores an instruction converted into a floating point instruction by the FU instruction conversion unit 222. The IU conversion instruction string storage unit 263 stores an instruction converted into an integer instruction by the IU instruction conversion unit 221. The number of instructions stored in the FU conversion instruction string storage unit 262 is added to the FU output instruction string storage unit 264 by the number of floating-point arithmetic units 101b acquired by the NFU acquisition unit 212. In the IU output instruction sequence storage unit 265, the instructions stored in the IU conversion instruction sequence storage unit 263 are added by the number of integer arithmetic units 101a acquired by the NIU acquisition unit 211. Each instruction sequence stored in the FU output instruction sequence storage unit 264 and the IU output instruction sequence storage unit 265 is added to the output loop instruction sequence storage unit 266.

  An optimization process in compilation by the compiler apparatus 10 having the above configuration will be described with reference to the drawings.

FIG. 13 is a diagram illustrating an example of a loop instruction sequence input to the compiler apparatus 10. The left side of FIG. 13 is an example of a source file before loop expansion, and the right side of FIG. 13 is an example of a source file after loop expansion. The compiler apparatus 10 determines whether or not the loop instruction sequence included in the input source file can be loop-expanded. The compiler apparatus 10 expands the instruction sequence of the loop that is determined to be loop expandable. FIG. 14 is a diagram illustrating an example of a source file that is not suitable for loop expansion. The left side of FIG. 14 is an example of a source file before loop expansion, and the source file on the left side of FIG. 14 has a dependency between “a [i + 1]” and “a [i]”. Here, “i” is a loop counter. That is, FIG.
In the source file illustrated in (1), there is a dependency between the rotations of the loop. Therefore, the instructions “a [i + 1] = b [i] * c [i] + a [i];” illustrated on the left side of FIG. 14 and “a [i + 2] = [b [i + 1] ] * c [i + 1] + a [i + 1]; "cannot be executed in parallel. Therefore, when there is a dependency relationship between the rotations of the loop, the compiler apparatus 10 of the first embodiment can be excluded from the loop expansion target.

  FIG. 15 is a diagram illustrating an example of the flow of loop expansion processing by the compiler apparatus 10 according to the first embodiment. The loop expansion process will be described with reference to FIG.

  In F1, the compiler apparatus 10 detects the innermost loop from the input source file. The compiler apparatus 10 extracts a loop operation instruction sequence from the detected innermost loop instruction sequence. Various known methods can be applied to the detection of the innermost loop.

  FIG. 16 is a diagram illustrating an example of a loop structure. As described above, in the loop, the loop counter is initialized by the initialization instruction sequence, and each instruction of the loop operation instruction sequence is repeatedly executed by the label and the loop instruction sequence. That is, the compiler apparatus 10 can detect a loop from a source file by detecting a block sandwiched between a label and a loop instruction sequence, for example.

FIG. 17 is a diagram illustrating an example of a loop instruction sequence input in the first embodiment. The instruction sequence illustrated in FIG. 17 is expressed by an intermediate code. In the instruction sequence illustrated in FIG. 17, the loop operation instruction sequence sandwiched between the label “Label0” and the loop instruction sequence is repeatedly executed. In the following description, processing is performed for the instruction sequence illustrated in FIG.

  Returning to FIG. 15, in F2, the instruction conversion unit 220 calculates the number of integer instructions and the number of floating-point instructions included in the extracted loop operation instruction sequence. In F3, the instruction conversion unit 220 determines whether the number of integer instructions or floating-point instructions included in the loop operation instruction sequence is biased. Whether there is a bias is, for example, “the value obtained by dividing the number of floating point instructions included in the loop operation instruction sequence by the loop operation instruction sequence” or “the number of integer instructions included in the loop operation instruction sequence It is possible to determine whether any of “value divided by column” is equal to or greater than a predetermined value. The predetermined value is a value determined based on the number of integer arithmetic units 101a and floating point arithmetic units 101b of the processor 101, for example. The determined predetermined value is stored in the machine model 201. The predetermined value is “0.9”, for example. If it is determined that there is a bias in the number of integer instructions or floating-point instructions (YES in F3), the process proceeds to F4 and F5. If it is determined that there is no bias in the number of integer instructions or floating point instructions (NO in F3), the process ends.

  In F4, the FU instruction conversion unit 222 converts the instruction included in the loop operation instruction sequence extracted in F1 into a floating-point instruction and stores it in the FU conversion instruction sequence storage unit 262. In F5, the IU instruction conversion unit 221 converts the instruction included in the loop operation instruction sequence extracted in F1 into an integer instruction and stores it in the IU conversion instruction sequence storage unit 263.

  FIG. 18 is a diagram illustrating an example of a detailed flow of the processes of F4 and F5 of FIG. Hereinafter, the processes of F4 and F5 of FIG. 15 will be described with reference to FIG.

  In G1, the instruction conversion unit 220 creates a result list. The result list is a list for temporarily storing instruction sequences being converted, and is prepared in the main storage unit 102, for example. In G2, the instruction conversion unit 220 extracts instructions in order from the beginning of the loop operation instruction sequence. In G3, the instruction conversion unit 220 duplicates the fetched instruction. The fetched instruction is copied to the main storage unit 102, for example. The duplicated instruction is referred to herein as instruction A. The processing of G3 is performed in order to prevent the input instruction sequence from being destroyed due to malfunction of the compiler apparatus 10 or the like. In G4, the instruction conversion unit 220 adds the instruction A to the result list. In G5, the instruction conversion unit 220 extracts the instruction code of the instruction A. In G6, the instruction conversion unit 220 determines whether to convert to an integer instruction or to a floating point instruction. In the case of the processing of F4 in FIG. 15, the processing proceeds to G7 for the conversion processing to the floating point instruction. In the process of F5 in FIG. 15, the process proceeds to G8 for conversion to an integer instruction.

In G7, the FU instruction conversion unit 222 refers to the FU conversion table and extracts the converted instruction code and instruction type. FIG. 19 is a diagram illustrating an example of the FU conversion table 301. The FU conversion table 301 is a table showing correspondence between instructions before and after conversion when a floating-point instruction is converted into an integer instruction. The FU conversion table 301 is stored in, for example, the main storage unit 102 or the auxiliary storage unit 103 in FIG. FIG. 19 illustrates an instruction code and instruction type before conversion, and an instruction code and instruction type after conversion. Referring to FIG. 19, it can be seen that an instruction of int type is converted to a float type instruction before conversion. In addition, it can be seen that an instruction that is a float type before the conversion remains a float type after the conversion. In G7 of FIG. 18, the FU instruction conversion unit 222 refers to the FU conversion table 301 illustrated in FIG. 19 and extracts the instruction code and the instruction type after the instruction A is converted into a floating-point instruction. For example, when the instruction code of the instruction A before conversion is “mult”, “fumult” is extracted as the instruction code after conversion, and “float” is extracted as the type of the instruction after conversion. Note that “fuadd” and “fumult” are integer instructions operated by the floating-point arithmetic unit 101b, and, for example, a float type virtual register is designated as the operand. That is, "fuadd" and "fumult" are floats
The bit string stored in the type virtual register is treated as an integer.

In G8, the IU instruction conversion unit 221 refers to the IU conversion table and extracts the converted instruction code and instruction type. FIG. 20 is a diagram illustrating an example of the IU conversion table 302. The IU conversion table 302 is a table showing correspondence between instructions before and after conversion when an integer instruction is converted into a floating-point instruction. The IU conversion table 302 is stored in, for example, the main storage unit 102 or the auxiliary storage unit 103 in FIG. FIG. 20 illustrates an instruction code and instruction type before conversion, and an instruction code and instruction type after conversion. Referring to FIG. 20, it can be seen that an instruction that is a float type is converted to an int type instruction before the conversion. It can also be seen that an instruction that is int type before conversion remains int type after conversion. In G8 of FIG. 18, the IU instruction conversion unit 221 refers to the IU conversion table illustrated in FIG. 20 and extracts the instruction code and the instruction type after converting the instruction A into an integer instruction. For example, when the instruction code of the instruction A before conversion is “fmult”, “iufmult” is extracted as the instruction code after conversion, and “int” is extracted as the type of the instruction after conversion. Note that “iufadd” and “iufmult” are floating-point instructions that are calculated by the integer arithmetic unit 101a, and for example, an int-type virtual register is specified as the operand. That is, “iufadd” and “iufmult” operate by treating the bit string stored in the int-type virtual register as a floating-point number.

  FIG. 21 is a diagram illustrating an example of correspondence between before and after conversion of each instruction included in the input loop operation instruction sequence into an integer instruction. In the input loop operation instruction sequence, all instructions are integer instructions. Therefore, even if conversion to an integer instruction is executed, the instruction code and the instruction type are not changed. FIG. 22 is a diagram illustrating an example of correspondence between before and after conversion of each instruction included in the input loop operation instruction sequence into a floating-point operation instruction. Although all instructions were integer instructions before conversion, it can be seen that all instructions are floating point instructions after conversion.

  Returning to FIG. 18, in G9, the instruction code and instruction type converted in G7 or G8 are set to the instruction A. That is, in the result list, the instruction A added to the result list in G4 is rewritten with the instruction code and instruction type converted by G7 or G8. In G10, the instruction conversion unit 220 determines whether or not an instruction that has not yet been converted remains in the loop operation instruction sequence. When conversion of all instructions included in the loop operation instruction sequence is completed (NO in G10), the process ends. If an instruction that has not yet been converted remains in the loop operation instruction sequence (YES in G10), the process proceeds to G2.

  Returning to FIG. 15, in F <b> 6, the NIU acquisition unit 211 acquires the number of NIUs that is the number of integer arithmetic units 101 a included in the processor 101 with reference to the machine model 201. Further, the NFU acquisition unit 212 refers to the machine model 201 and acquires the number of NFUs that is the number of floating-point arithmetic units 101 b included in the processor 101. Here, “1” is acquired as the number of NIUs, and “2” is acquired as the number of NFUs.

  In F7, the FU instruction expansion unit 232 expands the instruction sequence stored in the FU conversion instruction sequence storage unit 262, and stores the expanded instruction sequence in the FU output instruction sequence storage unit 264. In F8, the IU instruction expansion unit 231 expands the instruction sequence stored in the IU conversion instruction sequence storage unit 263, and stores the expanded instruction sequence in the IU output instruction sequence storage unit 265. In F9, it is determined whether the process of F7 has been repeated NFU times. If it has been repeated NFU times (YES in F9), the process proceeds to F11. If not repeated NFU times (NO in F9), the process returns to F7. In F10, it is determined whether the process of F8 has been repeated NIU times. If it is repeated NIU times (YES in F10), the process proceeds to F11. If not repeated NIU times (NO in F10), the process returns to F8.

FIG. 23 is a diagram illustrating an example of a loop operation instruction sequence expansion process. The process in FIG. 23 is an example of a diagram illustrating details of the processes in F7 to F10 in FIG. With reference to FIG. 23, the expansion processing of the loop operation instruction sequence will be described.

  In H1, the instruction expansion unit 230 receives an input of a loop operation instruction sequence that is a target of loop expansion. The instruction expansion unit 230 extracts a virtual register included in the reference list operand of the input loop operation instruction sequence, and creates a virtual register map.

  FIG. 24 is a diagram illustrating an example of a virtual register map. The virtual register map is a map that associates a virtual register before loop expansion and a virtual register after loop expansion. In the virtual register map, the virtual register after the loop expansion is associated with the virtual register before the loop expansion on a one-to-one basis. The virtual register after the loop expansion is newly created by the instruction expansion unit 230. The correspondence between the virtual register before the loop expansion and the virtual register after the loop expansion is associated with, for example, a hash function. That is, the virtual register map can be a hash table.

  Returning to FIG. 23, in H2, the instruction expansion unit 230 extracts instructions in order from the head of the input loop operation instruction sequence. In H3, the instruction expansion unit 230 sequentially extracts the reference list operand of the instruction extracted in H2. In H4, the instruction expansion unit 230 determines whether the operand extracted in H3 is a virtual register. If the operand is a virtual register (YES in H4), the process proceeds to H5. If the operand is not a virtual register (NO in H4), the process proceeds to H6. In H5, the instruction expansion unit 230 performs virtual register conversion based on the virtual address map created in H1.

FIG. 25 is a diagram illustrating an example of a virtual register conversion process in the reference list operand. In J1, the instruction expansion unit 230 refers to the virtual register map created in H1 of FIG. 23, and extracts the virtual register after conversion corresponding to the virtual register before conversion. In J2, the virtual register before conversion is rewritten with the virtual register after conversion taken out in J1. For example, referring to FIG. 24, the virtual register “$ g1” before loop expansion is converted to “$ f2” after loop expansion. At this time, the value stored in the virtual register “$ g1” is stored in the virtual register “$ f2” without changing the bit string. That is, in the process of J2, the sign, mantissa, radix, exponent, etc. of the value stored in the virtual register before rewriting is not distinguished. In the process of J2, the bit string stored in the virtual register before rewriting is stored in the virtual register after rewriting as it is.

  Returning to FIG. 23, in H6, the instruction expansion unit 230 determines whether or not the operand fetched in H3 is a memory address. If the operand is a memory operand (YES in H6), the process proceeds to H7. If the operand is not a memory operand (NO in H6), the process proceeds to H8. In H7, the instruction expansion unit 230 converts the memory operand specified as the operand.

FIG. 26 is a diagram illustrating an example of correspondence before and after the loop expansion of the memory operand. In FIG. 26, the memory operand “a + $ g1” is calculated by “a + $ g1 + (development number−1) × (increment value of $ g1)”. Here, “increment value of $ g1” is an increment value per rotation in the loop before unfolding. That is, it can be said that the value is added to the loop counter “$ g1” by the addition instruction of the loop instruction sequence. FIG. 27 is a diagram illustrating conversion of memory operands at each expansion number. In the expansion number 1, when the memory operand “a + $ g1” is converted, “a + $ g1” is obtained from “a + $ g1 + (1-1) × 4”. In the expansion number 2, when the memory operand “a + $ g1” is converted, “a + $ g1 + 4” is obtained from “a + $ g1 + (2-1) × 4”. In the expansion number 3, when the memory operand “a + $ g1” is converted, “a + $ g1 + 8” is obtained from “a + $ g1 + (3-1) × 4”. At this time, the value stored in the area specified by the memory operand “a + $ g1” is stored in the memory operand “a + $ g” without changing the bit string.
Stored in the area specified by “1 + 8”. That is, in the processes of FIGS. 26 and 27, the sign, mantissa, radix, exponent, and the like of the value stored in the area specified by the memory operand before rewriting are not distinguished. In the processing of FIG. 26 and FIG. 27, the bit string stored in the area specified by the memory operand before rewriting is stored as it is in the area specified by the memory operand after rewriting.

  Returning to FIG. 23, in H8, the instruction expansion unit 230 determines whether there is an unprocessed reference list operand. If there is an unprocessed reference list operand (YES in H8), the process proceeds to H3. If there is no unprocessed reference list operand (NO in H8), the process proceeds to H9.

  In H9, the instruction expansion unit 230 extracts definition list operands in order. In H10, the instruction expansion unit 230 determines whether the operand extracted in H9 is a virtual register. If the operand is a virtual register (YES in H10), the process proceeds to H11. If the operand is not a virtual register (NO in H10), the process proceeds to H12.

FIG. 28 is a diagram illustrating an example of a virtual register operand conversion process in the definition list operand. FIG. 28 is a diagram illustrating details of the processing in H11 of FIG. In K1, the instruction expansion unit 230 determines whether the type of the instruction to be converted into the operand is an int type. If it is an int type (YES in K1), the process proceeds to K2. If not int type (NO in K1), the process proceeds to K3. In K2, the instruction expansion unit 230 newly creates an int type virtual register. In K3, the instruction expansion unit 230 newly creates a float type virtual register. In K4, the instruction conversion unit 230 adds the correspondence between the operand before conversion and the virtual register created in K3 or K4 to the virtual register map. In K5, the instruction expansion unit 230 converts the operand into a virtual register created by K3 or K4. At this time, the value stored in the virtual register before conversion is stored in the virtual register after conversion without changing the bit string. That is, in the process of K5, the sign, mantissa, radix, exponent, etc. of the value stored in the virtual register before rewriting is not distinguished. In the process of K5, the bit string stored in the virtual register before rewriting is stored in the virtual register after rewriting as it is.

  Returning to FIG. 23, in H12, the instruction expansion unit 230 determines whether or not the operand extracted in H9 is a memory operand. If it is a memory operand (YES in H12), the process proceeds to H13. If it is not a memory operand (NO in H12), the process proceeds to H14. The content of the process of H13 is the same as that of H7. That is, in H13, the processes illustrated in FIGS. 26 and 27 are executed. In H14, the instruction expansion unit 230 determines whether there is an unprocessed definition list operand. If there is an unprocessed definition list operand (YES in H14), the process proceeds to H9. If there is no unprocessed definition list operand (NO in H14), the process ends.

  Returning to FIG. 15, in F <b> 11, the instruction expansion unit 230 stores the instructions stored in the FU output instruction sequence storage unit 264 and the IU output instruction sequence storage unit 265 in the output loop instruction sequence storage unit 266.

FIG. 29 is a diagram illustrating an example of an instruction sequence stored in the output loop instruction sequence storage unit 266. FIG. 29 shows an example of an instruction sequence in which a loop operation instruction sequence included in the instruction sequence of the loop illustrated in FIG. 17 is loop expanded. In the instruction sequence illustrated in FIG. 29, the instruction sequences with expansion numbers 1 and 2 are instruction sequences based on floating-point instructions. Further, the instruction sequence with the expansion number 3 is an instruction sequence based on integer instructions. As a result, the output loop instruction string storage unit 266 includes
Two instruction sequences based on floating-point instructions and one instruction sequence based on integer instructions are stored. That is, the number of instruction sequences based on floating point instructions and the number of instruction sequences based on integer instructions stored in the output loop instruction sequence storage unit 266 are respectively the number of floating point arithmetic units 101b and integer arithmetic units 101a included in the processor 101. Match.

Returning to FIG. 15, in F12, the instruction expansion unit 230 corrects the rotation speed of the loop. Correction of the rotation speed of the loop is performed by correcting the increment of the loop counter per one rotation of the loop. Correction of the increment of the loop counter is calculated by, for example, “(number of unfolded loops) × (increment value of loop counter before loop unfolding)”. Here, the number of loop expansions is “(number of integer arithmetic units 101a) + (number of floating point arithmetic units 101b)”. Therefore, by correcting the increment of the loop counter, the number of rotations of the loop after loop expansion is “(number of rotations of the loop before loop expansion) / (number of integer arithmetic units 101a + number of floating point arithmetic units 101b)”. " The number of expansions of the loop operation instruction sequence illustrated in FIG. 29 is “3”. That is, the process executed by the loop of one rotation after the loop expansion corresponds to the process for three rotations of the loop before the loop expansion. Referring to FIG. 17, the loop counter “$ g1” before the loop expansion is incremented by “4” per one loop rotation. Therefore, after loop expansion, the value of the loop counter “$ g1” is calculated as “12” by “(number of expansions) 3 × (increment value of the loop counter before loop expansion) 4”. FIG. 30 is a diagram illustrating an example of a loop instruction sequence in which the rotation speed is corrected. Referring to FIG. 30, in the addition instruction of the loop instruction sequence, it can be seen that the increment of the loop counter “$ g1” is “12”.

  FIG. 31 is a diagram illustrating an example of an instruction sequence of a loop after loop expansion. In FIG. 31, the initialized instruction sequence is followed by the expanded loop operation instruction sequence and the corrected loop instruction sequence. The instruction sequence developed in this way is changed by the arithmetic unit of the processor 101 while the execution order is changed so that it can be easily executed in parallel by a plurality of arithmetic units by the instruction scheduling exemplified in T4 of FIG. Executed.

  FIG. 32 and FIG. 33 are diagrams showing an example of the usage state of the arithmetic unit when the instruction sequence is executed. FIG. 32 is a diagram illustrating an example of a usage state of an arithmetic unit when an instruction sequence in which all instructions are converted into floating-point instructions is executed. FIG. 33 shows an example of the usage status of an arithmetic unit when an instruction sequence in which integer instructions and floating-point instructions are mixed is executed according to the numbers of the integer arithmetic unit 101a and the floating-point arithmetic unit 101b of the processor 101. FIG. That is, FIG. 33 is an illustration of a state in which the instruction sequence that has undergone loop expansion according to the first embodiment is executed by the computing unit. Comparing FIG. 32 and FIG. 33, it can be seen that the operation unit included in the processor 101 is used more efficiently in the case illustrated in FIG.

(First comparative example)
In the first comparative example, a compiler apparatus will be described in which an instruction sequence of an input loop is loop-expanded by a predetermined number of expansions and no instruction type conversion is performed. FIG. 34 is an example of a processing block that performs loop expansion of the compiler apparatus 500 according to the first comparative example. The information processing apparatus 100 can also be used as the compiler apparatus 500. In FIG. 34, each processing block of the expansion number determination unit 501, the instruction expansion unit 502, the loop instruction correction unit 503, the input loop instruction string storage unit 504, the expansion instruction string storage unit 505, and the output loop instruction string storage unit 506 is illustrated. ing. For example, the processor 101 in FIG. 1 executes a computer program loaded in the main storage unit 102 as each processing block in FIG. However, at least a part of any of the processing blocks in FIG. 34 may include a hardware circuit, a dedicated processor, or a digital signal processor (DSP).

The input loop instruction string storage unit 504 stores an instruction string of a loop to be loop expanded. The processor 101 of the compiler apparatus 500 determines the number of loop expansions as the expansion number determination unit 501. The number of expansions is determined based on the number of registers included in the processor 101, the number of instructions included in the loop operation instruction sequence stored in the input loop instruction sequence storage unit 504, and the like. The processor 101 of the compiler apparatus 500 expands the instruction sequence included in the loop operation instruction sequence as the instruction expansion unit 502. The expanded instruction sequence is stored in the expanded instruction sequence storage unit 505. The processor 101 of the compiler apparatus 500, as the loop instruction correction unit 503, corrects the increment of the loop counter and the loop end condition in the expanded loop instruction. The instruction sequence of the loop developed by the above processing is stored in the output loop instruction sequence storage unit 506.

  FIG. 35 is a diagram exemplifying a loop instruction sequence. In the loop illustrated in FIG. 35, all the instructions included in the loop operation instruction sequence are integer instructions. FIG. 36 is a diagram illustrating an example of an instruction sequence in which the loop illustrated in FIG. 35 is expanded by the compiler device 500 according to the first comparative example. The expanded instruction sequence illustrated in FIG. 36 is also an integer instruction. As illustrated in FIG. 2, the processor 101 does not include a plurality of integer arithmetic units 101a. Therefore, when the processor 101 executes the instruction sequence illustrated in FIG. 36, the processing is concentrated on one integer arithmetic unit 101a, and the floating point arithmetic units 101b and 101b are not used. Therefore, it cannot be said that a plurality of arithmetic units included in the processor 101 are efficiently used.

(Second comparative example)
In the second comparative example, processing for converting an integer instruction into a floating-point instruction and a floating-point instruction into an integer instruction is added in loop expansion. FIG. 37 is a diagram schematically illustrating loop expansion according to the second comparative example. FIG. 38 is a diagram illustrating FIG. 37 by pseudo code. In the second comparative example, an IU instruction sequence using integer instructions and a FU instruction sequence using floating-point instructions are generated by loop expansion. That is, in the second comparative example, an IU instruction string converted from an original instruction string before loop expansion into an integer instruction and an FU instruction string converted into a floating-point instruction are generated. The generated instruction sequence is included in an object generated by the compiler apparatus according to the second comparative example. When the object is executed, the IU instruction sequence or the FU instruction sequence is executed according to the usage status of the arithmetic unit of the processor 101. That is, the IU instruction sequence or the FU instruction sequence is executed according to the usage status of the arithmetic unit included in the processor 101. The instruction sequences executed by the respective arithmetic units are different threads. That is, in the second comparative example, the IU instruction sequence and the FU instruction sequence are executed by multithreading. The usage status of the arithmetic unit included in the processor 101 can be acquired by an OS system call. This system call returns whether an integer operation or a floating-point operation is frequently executed when the object is executed, and which of the integer arithmetic unit 101a and the floating-point arithmetic units 101b and 101b is free.

  In the second comparative example, the computing unit is efficiently used by acquiring information on a computing unit that is free by a system call. However, in the second comparative example, in order to acquire the usage status of the computing unit by another thread, the usage status of the computing unit is dynamically acquired during execution of the object. For this reason, in the second comparative example, an overhead associated with a function call such as a system call occurs.

(Comparison between the comparative example and the first embodiment)
FIG. 39 is an example of a diagram comparing the loop expansion according to the first comparative example and the loop expansion according to the first embodiment. In FIG. 39, the instruction sequence before expansion is described as “original instruction sequence”. In the loop expansion according to the first comparative example, the “original instruction sequence” is expanded twice. In the loop expansion according to the first embodiment, the instruction sequence based on the floating-point instruction (indicated as the instruction sequence converted to the FU instruction in the figure) is rotated twice by the integer instruction in accordance with the number of arithmetic units included in the processor 101a. An instruction sequence (indicated as an IU instruction sequence in the figure) is expanded by one rotation. For example, "
When the “original instruction sequence” is an instruction sequence based on a floating-point instruction, the instructions can be executed in parallel by the two floating-point arithmetic units 101b and 101b even in the loop expansion according to the first comparative example. However, the integer calculator 101a does not perform any processing during this time. In the loop expansion according to the first embodiment, as described above, the loop expansion is performed in accordance with the number of arithmetic units included in the processor 101a. For this reason, in the instruction sequence after loop expansion according to the first embodiment, the floating-point instruction sequence is executed by the two floating-point arithmetic units 101b and 101b, and the integer instruction sequence is executed by the integer arithmetic unit 101a. That is, it can be seen that the arithmetic unit included in the processor 101 can be used more efficiently when the loop expansion according to the first embodiment is performed than in the first comparative example.

  FIG. 40 is a diagram illustrating an example of a loop included in a source file input to the compiler. The loop illustrated in FIG. 40 includes three integer instructions. FIG. 41 is a diagram illustrating an example of an instruction sequence obtained by performing loop expansion on the loop illustrated in FIG. 40 according to the first comparative example. In FIG. 41, an instruction sequence by integer instructions is illustrated for two rotations. The instructions included in the instruction sequence after loop expansion do not include floating point instructions. Therefore, the instruction sequence expanded by the loop in the first comparative example is executed by the integer arithmetic unit 101a. During this time, the floating point arithmetic units 101b and 101b are not performing processing.

  FIG. 42 is a diagram illustrating an example of an instruction sequence obtained by performing loop expansion according to the first embodiment on the loop illustrated in FIG. In the first embodiment, the numbers of integer instruction sequences and floating-point instruction sequences included in the expanded instruction sequence are determined according to the numbers of integer arithmetic units 101a and floating-point arithmetic units 101b of the processor 101. That is, as illustrated in FIG. 42, two floating-point instruction sequences (indicated as FU integer instructions in the figure) obtained by converting integer instructions into floating-point instructions are generated, and one integer instruction sequence based on the integer instructions is generated. Is done. As a result, one integer instruction sequence is executed by the integer arithmetic unit 101a, and two floating point instruction sequences are executed by the floating point arithmetic units 101b and 101b, respectively. As a result, according to the first embodiment, the arithmetic unit included in the processor 101 can be used more efficiently.

  In the first embodiment, the integer instruction sequence and the floating-point instruction sequence included in the loop operation instruction sequence after the loop expansion are changed according to the numbers of the integer arithmetic units 101a and the floating-point arithmetic units 101b of the processor 101 at the time of compilation. The number was determined. The integer instruction sequence and the floating-point instruction sequence expanded in a loop are assigned to the integer arithmetic unit 101a and the floating-point arithmetic unit 101b by the instruction scheduler of the processor 101. Therefore, according to the first embodiment, it is not necessary to acquire the usage status of the arithmetic unit by the system call during the execution of the object. As a result, compared to the second comparative example, overhead due to a system call invocation during object execution is suppressed.

(Effect of 1st Embodiment)
In the first embodiment, the compiler apparatus 10 selects the innermost loop in which a loop operation instruction sequence does not include a branch instruction as a target of loop expansion. As a result, the compiler apparatus 10 does not have to expand including the branch destination instruction in the loop expansion.

  In the first embodiment, the compiler apparatus 10 omits the processes after F4 and F5 in FIG. 15 when there is no bias in the number of integer instructions or floating-point instructions included in the loop operation instruction sequence. Therefore, the compiler apparatus 10 can suppress a long compile time.

In the first embodiment, the compiler apparatus 10 converts the type of each instruction included in the loop operation instruction sequence based on the FU conversion table 301 and the IU conversion table 302. As a result, the compiler apparatus 10 has only an integer instruction and only a floating-point instruction in the converted instruction string even if both the integer instruction and the floating-point instruction are included in the loop operation instruction string before the conversion. An instruction sequence can be generated.

  In the first embodiment, the compiler apparatus 10 converts the instruction type, and then, according to the number of integer arithmetic units 101a and floating point arithmetic units 101b of the processor 101, the instruction sequence using integer instructions and the instructions using floating point instructions Column and output. As a result, the compiler apparatus 10 can generate an object that can use the arithmetic unit of the processor 101 more efficiently.

  In the first embodiment, the compiler apparatus 10 acquires the numbers of integer arithmetic units 101 a and floating point arithmetic units 101 b of the processor 101 from the machine model 201. As a result, the compiling apparatus 10 can generate objects for various processors by registering the number of integer arithmetic units and floating point arithmetic units for each processor type in the machine model 201.

  In the first embodiment, the compiler apparatus 10 performs, for example, the conversion to the floating point instruction by F4 in FIG. 15 and the conversion to the integer instruction by F5 in FIG. 15 in parallel. However, the compiler apparatus 10 is not limited to the configuration in which the conversion to the floating point instruction and the conversion to the integer instruction are performed in parallel. The compiler apparatus 10 may execute either the conversion to the floating-point instruction or the conversion to the integer instruction first, and the other after that.

  In the first embodiment, the compiler apparatus 10 is compiled for the processor 101 included in the compiler apparatus 10. However, the compiler apparatus 10 may be a cross compiler apparatus that accepts designation of a processor type and executes compilation for a designated processor. In this case, the compiling apparatus 10 may acquire the numbers of integer arithmetic units and floating point arithmetic units included in the designated processor from the machine model 201.

<First Modification>
In the first embodiment, a loop having no dependency relationship between each rotation of the loop is set as a target of loop expansion. In the first modification, a loop having a regression calculation dependency between each rotation of the loop is also subject to loop expansion. Constituent elements common to the first embodiment are denoted by the same reference numerals, and description thereof is omitted. Hereinafter, a first modification will be described with reference to the drawings.

  FIG. 43 is a diagram illustrating an example of the regression calculation. In one equation, a definition and a reference that contain the same variable are called regression operations. In FIG. 43, the variable “A” is included in both the definition and the reference of the formula. That is, the equation illustrated in FIG. 43 is a regression calculation of the variable “A”.

FIG. 44 is a diagram illustrating an example of an instruction including a reference operand and a definition operand. FIG. 44 illustrates an “add” instruction. This “add” instruction uses “op1 as a reference operand.
”And“ op2 ”and“ op3 ”as a definition operand. The compiler apparatus 10 according to the first modified example sets an instruction in which “op1” or “op2” as a reference operand is equal to “op3” as a definition operand and “op1” and “op2” are different as loop expansion targets. It is determined that

FIG. 45 is a diagram showing an example of a loop instruction string input to the compiler apparatus 10. The left side of FIG. 45 is an example of an instruction sequence of a loop before loop expansion, and the right side of FIG. 45 is an example of an instruction sequence of a loop after loop expansion. In the loop operation instruction sequence of the loop illustrated on the left side of FIG. 45, the variable “a” is included in both the definition and the reference in the expression “a = a + b [i] * c [i]”. Therefore, this equation is a regression calculation. In regression calculation, there is a dependency between loop rotations, so it is difficult to unroll the loop as it is.

Therefore, when a regression operation is included in the loop operation instruction sequence, the loop operation instruction is modified so that no dependency occurs between the rotations of the loop. That is, by creating definition operands that are independent from each other in the instruction sequences of the expansion numbers 1, 2, and 3 illustrated in FIG. 45, the instruction sequences of the expansion numbers are operated independently from the instruction sequences of the other expansion numbers. Make it possible. After the loop is completed, the same value as the instruction sequence before the loop expansion can be output by adding the values calculated by the instruction sequences of the respective expansion numbers. An instruction for adding the values calculated by the instruction sequence of each expansion number after the loop ends is called a convergence instruction. FIG. 46 is a diagram illustrating an example of an instruction sequence in which the instruction sequence after loop expansion illustrated in FIG. 45 is expressed by intermediate code. In FIG. 46, the part “add $ g5, $ g2, $ g2” is the regression calculation. In the following, processing for loop expansion of the intermediate code illustrated in FIG. 46 will be described.

  FIG. 47 is a diagram showing an example of the flow of loop expansion processing by the compiler apparatus 10 according to the first modification. Hereinafter, with reference to FIG. 47, the loop expansion processing of the first modification will be described.

  The processing from F1 to F3 in FIG. 47 is the same as the processing from F1 to F3 in FIG. Therefore, the description is omitted. In R1, the FU instruction conversion unit 222 of the compiler apparatus 10 converts the instruction included in the loop operation instruction sequence extracted in F1 into a floating-point instruction, and stores it in the FU conversion instruction sequence storage unit 262. In R2, the IU instruction conversion unit 221 of the compiler apparatus 10 converts the instruction included in the loop operation instruction sequence extracted in F1 into an integer instruction and stores it in the IU conversion instruction sequence storage unit 263.

  FIG. 48 is a diagram showing an example of a detailed flow of the processing of R1 and R2 of FIG. The processing flow of R1 and R2 in FIG. 47 will be described with reference to FIG. In U1, the instruction conversion unit 220 creates an initialization instruction sequence result list that stores the initialization instruction sequence after loop expansion. In U2, the instruction conversion unit 220 creates an operation instruction sequence result list for storing the loop operation instruction sequence after loop expansion. In U3, the instruction conversion unit 220 creates a converged instruction string result list for storing the converged instructions after loop expansion. Each list created in U1 to U3 is provided on the main storage unit 102 or the auxiliary storage unit 103 of the compiler apparatus 10, for example. The processing from G2 to G10 in FIG. 48 is the same as the processing from G2 to G10 in FIG. Therefore, the description is omitted.

  Returning to FIG. 47, the processing of F6 is the same as the processing of F6 of FIG. Therefore, the description is omitted. In R3, the instruction conversion unit 220 executes initialization processing for regression calculation.

  FIG. 49 is an example of a diagram illustrating initialization processing for regression calculation. FIG. 49 is a diagram showing an example of a detailed flow of the process of R3 of FIG. With reference to FIG. 49, the flow of initialization processing for regression calculation will be described.

  In C1, the instruction conversion unit 220 creates a virtual register map. As described with reference to FIG. 24, the virtual register map is a map showing the correspondence between the virtual register before the loop conversion and the virtual register after the loop conversion. The created virtual map is stored on the main storage unit 102 or the auxiliary storage unit 103, for example.

  In C2, the instruction conversion unit 220 adds the correspondence of the regression calculation definition before and after the loop expansion to the virtual register map created in C1. For example, taking the intermediate code illustrated in FIG. 46 as an example, the instruction conversion unit 220 executes the process of C2 for the definition “$ g2” of the regression operation “add $ g1, $ g2, $ g2”.

  In C3, the instruction conversion unit 220 determines whether there is a next regression operation instruction in the loop operation instruction sequence. If there is a next regression operation instruction (YES in C3), the process proceeds to C2. If there is no next regression calculation command (NO in C3), the process is terminated. That is, the initialization process for regression calculation illustrated in FIG. 49 is executed for all regression calculation instructions included in the loop calculation instruction sequence.

  Returning to FIG. 47, in R4, the FU instruction expansion unit 232 expands the instruction sequence stored in the FU conversion instruction sequence storage unit 262, and stores the expanded instruction sequence in the FU output instruction sequence storage unit 264. In R5, the IU instruction expansion unit 231 expands the instruction sequence stored in the IU conversion instruction sequence storage unit 263, and stores the expanded instruction sequence in the IU output instruction sequence storage unit 265.

  FIG. 50 is a diagram illustrating an example of a loop operation instruction sequence expansion process. FIG. 50 is a diagram showing an example of a detailed flow of the processing of R4 and R5 of FIG. With reference to FIG. 50, the expansion processing of the loop operation instruction sequence will be described.

  The process of H2 is the same as the process of H2 in FIG. Therefore, the description is omitted. In D1, the instruction expansion unit 230 determines whether or not the instruction extracted in H2 is a regression operation. If it is a regression calculation (YES in D1), the process proceeds to D2. If it is not a regression calculation (NO in D1), the process proceeds to H3.

FIG. 51 is a diagram illustrating an example of a regression calculation instruction. FIG. 51 shows the range of the reference list and the definition list for the convenience of explanation with respect to the instruction shown as an example in FIG. That is, in the addition instruction “add” shown as an example in FIG. 44, “op1”, “op2” are used as reference operands.
”And“ op3 ”as a definition operand. In the addition instruction “add” illustrated in FIG. 51, the reference operand “op1” and the definition operand “op3” are the same variable, and “op1” and “op2” are different variables.

FIG. 52 is a diagram illustrating an example of rewrite processing of a regression calculation instruction. FIG. 52 is a diagram showing an example of a detailed flow of the process D2 of FIG. Hereinafter, with reference to FIG. 52, the rewrite processing of the regression calculation instruction will be described. In E1, the instruction expansion unit 230 determines that the reference operand “op1
"Is an integer type (int type) or not. If “op1” is an integer type, the process proceeds to E2. If “op1” is not an integer type, the process proceeds to E5.

  In E2, the instruction expansion unit 230 determines whether or not the instruction to be rewritten is an integer instruction. If the instruction to be rewritten is an integer instruction, the process proceeds to E3. If the instruction to be rewritten is not an integer instruction, the process proceeds to E4.

  In E3, the instruction conversion unit 230 rewrites the regression calculation instruction. FIG. 53 is a diagram illustrating an example of rewrite processing of a regression calculation instruction. FIG. 53 is a diagram showing an example of a detailed flow of the process of E3 in FIG. Hereinafter, the process of E3 in FIG. 52 will be described with reference to FIG.

In E31, the instruction expansion unit 230 newly creates an integer type (int type) virtual register. In FIG. 53, the created virtual register is described as “new”. In E32, the instruction expansion unit 230 adds an instruction for initializing the virtual register created in E31 to the initialization instruction sequence result list created in U1 of FIG. Here, the instruction “mov 0, new” is added. That is, the instruction added to the initialization instruction sequence result list in E32 initializes the virtual register “new” created in E31 with “0”.

In E33, the instruction expansion unit 230 rewrites the regression calculation instruction using the virtual register created in E31. The rewritten instruction is “add new, op2, new”. In E34, the instruction expansion unit 230 adds an addition instruction to be executed after the loop ends to the convergence instruction string result list. Here, “add new, op3, op3” is added to the convergence instruction string result list.

  In E35, the instruction expansion unit 230 refers to the virtual register map created in C1 of FIG. 49, and extracts the virtual register after loop expansion corresponding to the virtual register “op2” (described as newOP2 in FIG. 53). In E36, the instruction expansion unit 230 rewrites the regression calculation as “add new, newOP2, new”.

  Returning to FIG. 52, in E4, the instruction conversion unit 230 rewrites the regression operation instruction. FIG. 54 is a diagram illustrating an example of rewrite processing of a regression calculation instruction. FIG. 54 is a diagram showing an example of a detailed flow of the process E4 of FIG. Hereinafter, the process of E4 of FIG. 52 will be described with reference to FIG.

In E51, the instruction expansion unit 230 newly creates a floating-point type (float type) virtual register. In E51 of FIG. 54, the created virtual register is described as “new1”. In E52, the instruction expansion unit 230 adds an instruction for initializing the virtual register created in E51 to the initialization instruction sequence result list created in U1 of FIG. Here, the instruction “mov 0, new1” is added. That is, the instruction added to the initialization instruction sequence result list in E52 initializes the virtual register “new1” created in E51 with “0”.

In E53, the instruction expansion unit 230 rewrites the regression calculation instruction using the virtual register created in E51. The rewritten instruction is “fadd new1, op2, new1”. In E54, the instruction expansion unit 230 newly creates an integer type (int type) virtual register. E5 in FIG.
4, the created virtual register is described as “new2”. In E55, the instruction expansion unit 230 adds an instruction for performing variable type conversion to the converged instruction string result list. Here, “movftoi new1, new2” is added. This instruction does not convert the value of the floating-point type virtual register “new1” into the integer type, and substitutes it into “new2”, which is the integer type virtual register, without changing the bit string.

In E56, the instruction expansion unit 230 adds an addition instruction to be executed after the end of the loop to the convergence instruction string result list. Here, “add new2, op3, op3” is added. In E57, the instruction expansion unit 230 refers to the virtual register map created in C1 of FIG. 49 and extracts the virtual register after loop expansion corresponding to the virtual register “op2” (described as newOP2 in FIG. 53). In E58, the instruction expansion unit 230 rewrites the regression calculation as “fadd new2, newOP2, new2”.

  Returning to FIG. 52, in E5, the instruction expansion unit 230 determines whether or not the instruction to be rewritten is an integer instruction. If the instruction to be rewritten is an integer instruction, the process proceeds to E6. If the instruction to be rewritten is not an integer instruction, the process proceeds to E7.

  FIG. 55 is a diagram illustrating an example of rewrite processing of a regression calculation instruction. FIG. 55 is a diagram showing an example of a detailed flow of the process of E6 of FIG. Hereinafter, the process of E6 of FIG. 52 will be described with reference to FIG.

The processing from E31 to E33 is the same as the processing from E31 to E33 in FIG. Therefore, the description is omitted. In E61, the instruction expansion unit 230 newly creates a floating-point type (float type) virtual register. In E61 of FIG. 55, the created virtual register is described as “new2”. In E62, the instruction expansion unit 230 adds an instruction for performing variable type conversion to the converged instruction string result list. Here, “movftoi new2, new” is added. This instruction does not convert the value of the floating-point type virtual register “new2” into the integer type, and substitutes it into “new”, which is the integer type virtual register, without changing the bit string.

  In E63, the instruction expansion unit 230 adds the addition instruction executed after the loop ends to the converged instruction string result list. Here, “fadd new, op3, op3” is added. The processing from E35 to E36 is the same as the processing from E35 to E36 in FIG. Therefore, the description is omitted.

  FIG. 56 is a diagram illustrating an example of rewrite processing of a regression calculation instruction. FIG. 56 is a diagram showing an example of a detailed flow of the process of E7 of FIG. Hereinafter, the processing of E7 in FIG. 52 will be described with reference to FIG.

The processing from E51 to E53 is the same as the processing from E51 to E53 in FIG. Therefore, the description is omitted. In E71, the instruction expansion unit 230 adds the addition instruction executed after the loop ends to the converged instruction string result list. Here, “fadd new1, op3, op3” is added. The processing from E35 to E36 is the same as the processing from E35 to E36 in FIG. Therefore, the description is omitted.

  Returning to FIG. 50, the processing from H3 to H15 is the same as the processing from H3 to H15 in FIG. Therefore, the description is omitted.

  Returning to FIG. 47, the processing from F9 to F12 is the same as the processing from F9 to F12 in FIG. Therefore, the description is omitted.

  FIG. 57 is a diagram showing an example of a loop operation instruction sequence after loop expansion. The instruction sequences of the expansion numbers 1 and 3 are expanded by the loop expansion method illustrated in FIG. The instruction sequence of expansion number 2 is expanded by the loop expansion method illustrated in FIG.

  FIG. 58 is a diagram showing an example of an initialization instruction sequence after loop expansion. The initialization instruction strings with the expansion numbers 1 and 2 are instructions added by the process of E52 in FIG. The initialization instruction sequence with the expansion number 3 is an instruction added by the process of E32 in FIG.

  FIG. 59 is a diagram illustrating an example of a converged instruction sequence after loop expansion. The convergence instruction sequences of the expansion numbers 1 and 2 are instructions added by the processes of E55 and E56 in FIG. The convergence instruction string of the expansion number 3 is an instruction added by the process of E34 in FIG.

  FIG. 60 is a diagram showing an example of a loop instruction sequence after loop expansion. The loop instruction sequence is corrected by the loop counter as in the first embodiment. FIG. 61 is a diagram showing an example of a loop instruction sequence after loop expansion. FIG. 61 is an example of a loop instruction sequence developed by the processing of FIG. The instruction sequence illustrated in FIG. 61 includes an initialization instruction sequence illustrated in FIG. 58, a loop operation instruction sequence illustrated in FIG. 57, a loop instruction sequence illustrated in FIG. 60, and a convergence instruction illustrated in FIG. It is a combination of columns. That is, the virtual register is initialized by the initialization instruction sequence illustrated in FIG. The loop operation instruction sequence illustrated in FIG. 57 is repeatedly executed by the loop instruction sequence illustrated by FIG. After the end of the loop, the convergence instruction sequence illustrated by FIG. 59 is executed.

In the first modification, instructions including regression operations are classified by instruction and operand types, and loop expansion is performed for each classification so that no dependency relationship occurs between the loops. As a result, according to the first modification, the loop expansion according to the first embodiment can be applied to the instruction sequence of the loop including the regression operation.

  The embodiments and modifications disclosed above can be combined.

<Others>
Regarding the embodiment including the above first modified example, the following additional notes are further disclosed.
(Appendix 1)
An extraction unit (220) for extracting the instruction sequence repeated by the repetition instruction upon detecting a repetition instruction instructing repetition of the instruction sequence in the input source file;
A first generation unit that converts an instruction included in the extracted instruction sequence into an integer instruction that performs an integer operation to generate an integer instruction sequence;
A second generation unit that generates a floating-point instruction sequence by converting an instruction included in the extracted instruction sequence into a floating-point instruction that performs a floating-point operation;
An output instruction sequence including the integer instruction sequence and the floating-point instruction sequence is generated based on the number of integer arithmetic units and the number of floating-point arithmetic units included in a processor that is an execution environment of an object compiled from the source file. A third generation unit,
Compiler device.
(Appendix 2)
A determination unit that determines the number of repetitions of the output instruction sequence by the repetition instruction based on the number of repetitions of the instruction sequence by the repetition instruction, the number of integer arithmetic units, and the number of the floating-point arithmetic units;
The compiler apparatus according to appendix 1.
(Appendix 3)
The determination unit sets a value obtained by dividing the number of repetitions of the instruction sequence by the repetition instruction by the sum of the number of integer arithmetic units and the number of floating point arithmetic units as the number of repetitions of the output instruction sequence by the repetition instructions. ,
The compiler apparatus according to attachment 2.
(Appendix 4)
A processor information storage unit for storing the number of integer arithmetic units and floating point arithmetic units for each processor type;
An arithmetic unit number acquisition unit that acquires the number of integer arithmetic units and floating-point arithmetic units included in a processor that is an execution environment of the object from the processor information storage unit;
The compiler apparatus according to any one of appendices 1 to 3.
(Appendix 5)
The instruction sequence extracted by the extraction unit is an instruction sequence not including a branch.
The compiler apparatus according to any one of appendices 1 to 4.
(Appendix 6)
Computer
When a repetition instruction that instructs repetition of an instruction sequence is detected in the input source file, the instruction sequence repeated by the repetition instruction is extracted,
Converting an instruction included in the extracted instruction sequence into an integer instruction for performing an integer operation to generate an integer instruction sequence;
Converting the instruction included in the extracted instruction sequence into a floating-point instruction for performing a floating-point operation to generate a floating-point instruction sequence;
An output instruction sequence including the integer instruction sequence and the floating-point instruction sequence is generated based on the number of integer arithmetic units and the number of floating-point arithmetic units included in a processor that is an execution environment of an object compiled from the source file. ,
Compilation method.
(Appendix 7)
Further executing a process of determining the number of repetitions of the output instruction sequence by the repetition instruction based on the number of repetitions of the instruction sequence by the repetition instruction, the number of integer arithmetic units and the number of floating-point arithmetic units,
The compiling method according to appendix 6.
(Appendix 8)
The determining process includes a value obtained by dividing the number of repetitions of the instruction sequence by the repetition instruction by the sum of the number of integer arithmetic units and the number of floating-point arithmetic units, and the number of repetitions of the output instruction sequence by the repetition instruction. Including processing to
The compiling method according to appendix 7.
(Appendix 9)
The computer includes a processor information storage unit that stores the number of integer arithmetic units and floating point arithmetic units for each processor type,
Further executing a process of acquiring from the processor information storage unit the number of integer arithmetic units and floating-point arithmetic units possessed by the processor that is the execution environment of the object;
The compiling method according to any one of appendices 6 to 8.
(Appendix 10)
The extracted instruction sequence is an instruction sequence that does not include a branch.
The compiling method according to any one of appendices 6 to 9.
(Appendix 11)
On the computer,
When a repetition instruction that instructs repetition of an instruction sequence is detected in the input source file, the instruction sequence repeated by the repetition instruction is extracted,
Converting an instruction included in the extracted instruction sequence to an integer instruction for performing an integer operation to generate an integer instruction sequence;
Converting the instruction included in the extracted instruction sequence into a floating-point instruction for performing a floating-point operation to generate a floating-point instruction sequence;
An output instruction sequence including the integer instruction sequence and the floating-point instruction sequence is generated based on the number of integer arithmetic units and the number of floating-point arithmetic units included in a processor that is an execution environment of an object compiled from the source file. ,
Compiler program.
(Appendix 12)
Further executing a process of determining the number of repetitions of the output instruction sequence by the repetition instruction based on the number of repetitions of the instruction sequence by the repetition instruction, the number of the integer arithmetic units, and the number of the floating point arithmetic units.
The compiler program according to attachment 11.
(Appendix 13)
The determination is performed by dividing the number of repetitions of the instruction sequence by the repetition instruction by the sum of the number of integer arithmetic units and the number of floating-point arithmetic units and the number of repetitions of the output instruction sequence by the repetition instruction. Including processing to
The compiler program according to attachment 12.
(Appendix 14)
The computer includes a processor information storage unit that stores the number of integer arithmetic units and floating point arithmetic units for each processor type,
Further executing a process of acquiring from the processor information storage unit the number of integer arithmetic units and floating point arithmetic units possessed by a processor serving as an execution environment of the object;
The compiler program according to any one of appendices 11 to 13.
(Appendix 15)
The extracted instruction sequence is an instruction sequence that does not include a branch.
The compiler program according to any one of appendices 11 to 14.

DESCRIPTION OF SYMBOLS 100 ... Information processing apparatus 101 ... Processor 101a ... Integer arithmetic unit 101b ... Floating point arithmetic unit 102 ... Main memory part 103 ... Auxiliary memory part 104 ... Communication part 10,500 ... Compiler device 201 ... Machine model 202 ... NFU number storage unit 203 ... NIU number storage unit 211 ... NIU acquisition unit 212 ... NFU acquisition unit 220 ... Instruction conversion unit 221 ..IU instruction conversion unit 222... FU instruction conversion unit 230... Instruction expansion unit 231... IU instruction expansion unit 232... FU instruction expansion unit 240... Loop instruction correction unit 261. Operation instruction sequence storage unit 262... FU conversion instruction sequence storage unit 263... IU conversion instruction sequence storage unit 264... FU output instruction sequence storage unit 265. Parts 266 ... output loop instruction sequence storage unit 301 ... FU conversion table 302 ... IU conversion table

Claims (7)

An extraction unit for extracting the instruction sequence repeated by the repetition instruction when detecting a repetition instruction instructing repetition of the instruction sequence in the input source file;
A first generation unit that converts an instruction included in the extracted instruction sequence into an integer instruction that performs an integer operation to generate an integer instruction sequence;
A second generation unit that generates a floating-point instruction sequence by converting an instruction included in the extracted instruction sequence into a floating-point instruction that performs a floating-point operation;
An output instruction sequence including the integer instruction sequence and the floating-point instruction sequence is generated based on the number of integer arithmetic units and the number of floating-point arithmetic units included in a processor that is an execution environment of an object compiled from the source file. A third generation unit,
Compiler device. A determination unit that determines the number of repetitions of the output instruction sequence by the repetition instruction based on the number of repetitions of the instruction sequence by the repetition instruction, the number of integer arithmetic units, and the number of the floating-point arithmetic units;
The compiler apparatus according to claim 1. The determination unit sets a value obtained by dividing the number of repetitions of the instruction sequence by the repetition instruction by the sum of the number of integer arithmetic units and the number of floating point arithmetic units as the number of repetitions of the output instruction sequence by the repetition instructions. ,
The compiler apparatus according to claim 2. A processor information storage unit for storing the number of integer arithmetic units and floating point arithmetic units for each processor type;
An arithmetic unit number acquisition unit that acquires the number of integer arithmetic units and floating-point arithmetic units included in a processor that is an execution environment of the object from the processor information storage unit;
The compiler apparatus as described in any one of Claim 1 to 3. The instruction sequence extracted by the extraction unit is an instruction sequence not including a branch.
The compiler apparatus as described in any one of Claim 1 to 4. Computer
When a repetition instruction that instructs repetition of an instruction sequence is detected in the input source file, the instruction sequence repeated by the repetition instruction is extracted,
Converting an instruction included in the extracted instruction sequence into an integer instruction for performing an integer operation to generate an integer instruction sequence;
Converting the instruction included in the extracted instruction sequence into a floating-point instruction for performing a floating-point operation to generate a floating-point instruction sequence;
Based on the number of integer arithmetic units included in the processor and the number of floating point arithmetic units, an output instruction sequence including the integer instruction sequence and the floating point instruction sequence is generated.
Compilation method. On the computer,
When a repetition instruction that instructs repetition of an instruction sequence is detected in the input source file, the instruction sequence repeated by the repetition instruction is extracted,
Converting an instruction included in the extracted instruction sequence to an integer instruction for performing an integer operation to generate an integer instruction sequence;
Converting the instruction included in the extracted instruction sequence into a floating-point instruction for performing a floating-point operation to generate a floating-point instruction sequence;
Based on the number of integer arithmetic units included in the processor and the number of floating point arithmetic units, an output instruction sequence including the integer instruction sequence and the floating point instruction sequence is generated.
Compiler program.

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