JP2000259423A - Method for compiling program and recording medium with method recorded thereon - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate even a program that frequently uses either an integer operation or a floating point operation without making hardware have redundancy. SOLUTION: This program compiling method decides whether or not a calculation operation included in a certain execution section on an input program is localized to an instruction belonging to a specified function unit (steps 401 and 402) and translates a part of the instruction into an alternate instruction string belonging to another function unit or translates it into library calling composed of alternative instruction strings including an instruction belonging to the other function unit (step 404).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer having a plurality of functional units, such as a superscaler or a VLIW, each of which can execute instructions in parallel in order to speed up program execution. In particular, the present invention relates to a program compiling method for making the workload of each functional unit comparable without giving hardware redundancy, and a recording medium recording the program compiling method.

[0002]

2. Description of the Related Art As means for speeding up the execution of a program, there is an improvement in the processing capability of a processor.
As a method of improving the processing capability of a processor, the performance of each hardware constituting the processor (processing speed,
There is a method of improving the processing amount) and a method of improving the performance not by improving the performance of the hardware itself but by simultaneously executing a plurality of instructions.

In the latter method, a processor having a plurality of functional units therein and capable of simultaneously executing instructions is used (see Hennessy, DA and Patterson,
JL, "Computer Architecture A Quantitative Approac
h second edition, "pp.278-289, Morgan Kaufmann pub
lishers, San Francisco, California, 1996 ").
In many cases, a processor used in this case has an executable instruction determined for each functional unit.

For example, a processor has two function units therein, one of which has a function of executing an integer operation (an integer operation unit) and the other of which has a function of executing a floating point operation. , The processor executes the integer instruction using the integer operation unit, and executes the floating point instruction using the floating point operation unit. At this time, the processor can simultaneously execute one integer instruction and one floating-point instruction using the respective functional units. However,
In order to execute a plurality of instructions at the same time, the workload of each functional unit to be executed within a certain unit time needs to be approximately the same. Therefore, a plurality of instructions cannot be executed at the same time, particularly when the calculation operation in the loop is biased toward instructions belonging to a specific functional unit.

Further, as a conventional technique for increasing the execution speed of a program by distributing the workload of each functional unit, a function of executing a frequently appearing instruction is added to a functional unit which is not usually used often. There is a way. For example, Proceeding of the ACM
Sigplan PDI (1998) 11th
Pages 8 to 129 (Sastry, SS, Palachada, S.
and Smith JE, "Exploiting Idle Floating Point
Resources For Integer Execution, "Proceedings of
In the method discussed in the ACM SIGPLAN PLDI 1998, pp. 118-129), a processor having two types of functional units, an integer operation unit executing an integer instruction and a floating point operation unit executing a floating point instruction, is used. By adding an integer operation function to the floating-point operation unit and adding redundancy to hardware, a program that makes heavy use of integer operation can be executed at high speed. In this case, the compiler for the computer separates the integer arithmetic processing on the source program into one to be executed by the integer arithmetic unit and one to execute the integer arithmetic function added to the floating-point arithmetic unit.

[0006]

The above-mentioned conventional method can be realized only by a computer having a redundancy in which an integer operation function is added to a floating-point operation unit. Also,
Many commonly used programs (compilers,
Editor, operating system) is a program that makes heavy use of integer arithmetic, so the conventional method of replacing the integer arithmetic unit with a floating-point arithmetic unit is effective, but a program that makes heavy use of floating-point arithmetic, such as scientific calculation Is not valid. In general, in a computer having a plurality of functional units and each functional unit can execute an instruction at the same time, in order for each functional unit to execute an instruction at the same time, the workload of each functional unit for a certain unit time is almost the same. There must be.

An object of the present invention is to record a program compiling method and a compiling method capable of accelerating a program that makes heavy use of both integer arithmetic and floating-point arithmetic without giving hardware redundancy. It is another object of the present invention to provide a recording medium that has been designed.

[0008]

According to the compile method of the present invention, in order to achieve the above object, first, at the time of program translation, a calculation operation included in a certain execution section on an input program (source program) is specified. It is determined whether or not the instruction belongs to the functional unit. As a result, when it is determined that the instruction is biased, in order to make the workload of each functional unit the same, a part of the instruction is translated into an alternative instruction sequence belonging to another functional unit, or
It translates into a library call composed of an alternative instruction sequence including instructions belonging to other functional units.

A recording medium according to the present invention is a computer-readable recording medium in which the processing of each step of the program compiling method described above is converted into a program code and recorded.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. However, it goes without saying that the present invention is not limited to the examples. FIG. 1 is a diagram showing an example of a computer system to which the compiling method of the present invention is applied. 1 includes a processor 101,
Main memory 102, disk device 103, reading device 10
4. It has a bus 105, and the reading device 104 can read programs and the like stored in the storage medium 106. A compiler utilizing the present invention is a disk device 103
Alternatively, after being stored in the storage medium 106 and taken into the main memory 102 via the bus 105, it is decoded and executed by the processor 101.

FIG. 2 is a diagram showing an example of a functional configuration of the processor 101. In the example of FIG.
Is the load store unit 201, the integer operation unit 2
02, a floating-point addition / subtraction / multiplication unit 203, and a floating-point division unit 204, each of which has a plurality of functional units, each of which can execute instructions in parallel at the same time.

FIG. 3 is a diagram showing an outline of a processing flow of the compiler in the present embodiment. Referring to FIG.
Is an input program (source program), 302 is a compiler, 303 is an optimization unit, 304 is a target program (object program), and 305 is a process to which the compile method according to the present invention is applied. The compiler 302 reads the input program 301, optimizes it by the optimizing unit 303, and translates it into the target program 304. The compiling method of the present invention is applied to the processing 305 in the optimizing unit 303. Since the processing 305 to which the compiling method of the present invention is applied is particularly effective when applied to a loop, the following description shows an example of application to a loop.

FIG. 4 is a specific flowchart of the process 305. The process 305 in the present embodiment estimates the workload of each functional unit possessed by the processor 101 for the calculation operation included in a certain execution section in the program, and among the instructions during the calculation operation of the execution section,
Calculate the number n of instructions whose work load is the same for each functional unit when translated into an alternative instruction sequence, and if n is 0, translate all instructions to the original instruction, and n is 1 or more In the case of, n are translated into an alternative instruction sequence.

Next, the flow of the process 305 will be described in detail with reference to FIG. First, the calculation operation of each loop execution is recognized as a processing unit to which the optimization is applied, and the workload of each functional unit is estimated (step 401). Next, in order to equalize the workload of each functional unit, step 4 is performed.
In the calculation operation recognized in step 01, the number n to translate the instruction belonging to the functional unit having the heaviest workload into the alternative instruction sequence is calculated (step 402). As a result of the calculation, if the number n to be translated is 0, all instructions are translated into original instructions (step 403). If the number n to be translated is 1 or more, the number n of instructions is translated into an alternative instruction sequence or a library call (step 404).

There are many types of calculation operations to which the present invention can be applied. In practice, an instruction having a long execution time such as division or square root in a loop is replaced with an instruction having a short execution time such as multiplication or addition. It is most effective to substitute with a combination of Here, as an embodiment, a case where “reciprocal operation f (x) = 1 / x”, which is a kind of division, is replaced by “multiplication and addition” will be described. It is assumed that a division instruction can be executed every 20 cycles, a multiply-add instruction can be executed every other cycle, and a floating-point number is expressed in a form divided into a sign part, an exponent part, and a mantissa part as in IEEE754. It is assumed that

A case where approximation by the Newton method shown below is used as an algorithm to be used will be described. Xn + 1 ≒ Xn + (1−x × Xn) × Xn First, at the start of calculation, the exponent part of the argument x is reduced to a certain range. The zero-order approximation X0 is obtained by subtracting a prepared table from the reduced value of x. Since Newton's method shows square convergence, an appropriate zero-order approximation with a few bits of precision will completely converge on an 8-byte floating point number at X3 or X4. Alternatively, by performing a check operation on the approximate value, it is possible to match the result of the calculation with the division instruction.

The amount of calculation required for one approximation step is 2 instructions for multiplication and 2 instructions for addition / subtraction. If a computer has a multiplication / addition instruction, it can be realized with 2 instructions. For example, it can be realized with eight instructions, but it is assumed here that ten instructions are required. On the other hand, the operation of the exponent part for reduction is realized by an integer operation, but this work load is relatively light and is ignored in this example. Therefore, using a division instruction to calculate the reciprocal occupies the division unit (204) for 20 cycles, and using the alternative instruction sequence occupies the addition / subtraction / multiplication unit (203) for 10 cycles.

Under the above conditions, if the number of division instructions in a certain execution section is p and the number of addition / subtraction / multiplication instructions is q, then if the number of division instructions to be translated into an alternative instruction sequence by a multiply-add instruction is n, When q is less than 20p, (pn)
* 20 = q + 10n, that is, n = (20p−q) / 30
On the other hand, when q is 20p or more, n = 0.
FIG. 5 shows a program example of a process for calculating the number n of division instructions to be translated into an alternative instruction sequence.

When the division instruction is replaced with a library call, when q is less than 20p, the library call is made by the number of cycles (20p-q) in which only the division unit is operating. Therefore, n = (20
p−q) / 20. On the other hand, when q is 20p or more, n = 0. 9 shows a program example of a process for calculating the number n of division instructions to be translated into a library call of an alternative instruction sequence.

This library is composed of codes for performing a reciprocal operation at a ratio of a division instruction 1 to an alternative instruction sequence 2 by a multiplication / addition instruction so that the workloads among the functional units are equal. When calling the library, it is necessary to pass an array of arguments, an array of results, and the number of operations, so that a temporary array may need to be generated when calling the library. As a specific example,
When the source program of B (n) = 1 / (5 * A (n)) shown in FIG. 7 is called as the library, the result is as shown in FIG. In FIG. 8, LIB (TMP, B, N) indicates a library, and TMP indicates a temporary array generated by a compiler (n = 1 to N). In any case, it is often effective to use an appropriate loop unrolling optimization in order to achieve an optimal work load balance.

Next, the process of translating the FORTRAN program fragment shown in FIG. 9 will be described with reference to the flowchart of the process 305 shown in FIG. The compiler recognizes the do loop of the FORTRAN program shown in FIG. 9 as an independent optimization unit, and estimates the workload of each functional unit (Step 401). When an alternative instruction sequence is used to make the load of each functional unit the same, the reciprocal operation n to be translated into the alternative instruction sequence is calculated by the calculation method shown in FIG. When a library is used, the reciprocal operation n to be calculated by the library is calculated by the calculation method shown in FIG. In any case, n becomes 1 or more (step 402).

In FIG. 9, the time required for one loop, that is, the calculation of one reciprocal, is 20 cycles when all are translated into the original division instruction, and 10 cycles when all are translated into the alternative instruction sequence. It is. Here, when the loop of FIG. 9 is expanded into four and three of the four reciprocals are translated into an alternative instruction sequence, the number of cycles is reduced to 7.5 cycles per reciprocal. In the case of translation into a library call, the number of reciprocals is about 6.7 cycles (step 404). It can be seen that in any case under the process of the present embodiment, a speed-up of twice or more can be achieved. In general,
The code in the library has the advantage that it can achieve perfect performance.

The program compiling method according to the present invention has been described in detail above. Each process of the compiling method is converted into a program code, recorded on a recording medium such as a CD-ROM or a flexible disk (FD), and distributed. Then, by obtaining and using the recording medium, the user can obtain a target program optimal for the processing performance (including hardware and OS) of his / her computer system.

Further, the software sales company generates a target program suitable for various computer systems (including hardware and OS) by using the program compiling method, and for example, generates a target program such as a CD-ROM or a flexible disk (FD). ), And can be distributed as software dedicated to various computer systems. In that case, the user obtains and uses the recording medium suitable for his computer system,
Processing performance of your computer system (hardware and OS
The computer system can be operated with the optimal target program.

[0025]

According to the program compiling method of the present invention, the workload of each functional unit can be made equal to each other without giving hardware redundancy, and a plurality of functional units can execute instructions at the same time. Like
The processing capability of the processor is improved, and the execution of the program can be accelerated. Further, by obtaining and using the recording medium according to the present invention, the user can obtain and execute the target program optimal for the performance of his / her computer system.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a computer system to which a compiling method of the present invention is applied.

FIG. 2 is a diagram illustrating an example of a functional configuration of a processor 101.

FIG. 3 is a diagram illustrating an outline of a processing flow of a compiler in the embodiment.

FIG. 4 is a specific flowchart of a process 305.

FIG. 5 is a program example of a process for calculating the number n of division instructions for which a reciprocal is to be translated into an alternative instruction sequence;

FIG. 6 is a program example of a process of calculating the number n of division instructions for which a reciprocal is to be translated into a library of alternative instruction strings.

FIG. 7 is an example of a source program that requires a temporary array when calling a library.

FIG. 8 is an example in which the source program of FIG. 7 is rewritten using a temporary array.

FIG. 9 shows a source program (FORT) utilizing the present invention.
RAN).

[Explanation of symbols]

 101: Processor, 102: Main Memory, 103: Disk Device, 104: Reading Device, 105: Bus, 106: Storage Medium, 201: Load Store Unit, 202: Integer Operation Unit, 203: Floating Point Addition / Subtraction / Multiplication Unit, 204: Floating point division unit 301: input program, 302: compiler, 303: target program, 305: processing (compile method of the present invention).

Claims (3)

[Claims] 1. A program compiling method for a computer having a plurality of functional units each capable of executing an instruction in parallel, wherein a calculation operation included in a certain execution section on an input program is executed by an instruction belonging to a specific functional unit. A first step of determining whether the instruction is biased, and, if determined to be biased by the first step, translating a part of the instruction to a substitute instruction sequence belonging to another functional unit or performing another Translating into a library call composed of a substitute instruction sequence including an instruction belonging to the functional unit. 2. The method according to claim 1, wherein the determination in the first step is performed by estimating a workload of each functional unit with respect to a calculation operation included in a certain execution section. Is the number of instructions that, when translated into the alternative instruction sequence belonging to another functional unit, of the instructions during the calculation operation, the workload becomes the same for each functional unit, or the alternative instruction sequence including the instruction belonging to another functional unit. 2. The method according to claim 1, further comprising calculating the number of instructions that translates into a structured library call and that results in the same workload in each functional unit.
The program compilation method described. 3. A computer-readable storage medium in which the processing of each step of the program compiling method according to claim 1 is converted into a program code and recorded.