JP3627905B2 - Program compilation method and recording medium recording the method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for speeding up the execution of a program in a computer having a plurality of functional units such as a superscaler or VLIW and capable of executing instructions simultaneously in parallel. The present invention relates to a program compilation method for making the workload of each functional unit comparable without giving redundancy to the wear, and a recording medium on which the program compilation method is recorded.
[0002]
[Prior art]
As a means for speeding up the execution of the program, there is an improvement in the processing capacity of the processor. As a method of improving the processing capacity of the processor, a method for improving the performance (processing speed and processing amount) of each hardware constituting the processor and a performance improvement of the hardware itself are executed, and a plurality of instructions are executed simultaneously. There is a method for improving the performance.
[0003]
The latter method uses a processor that has a plurality of functional units therein and each functional unit can execute instructions simultaneously (references “Hennessy, DA and Patterson, JL,” Computer Architecture A Quantitative Approach second). edition, "pp. 278-289, Morgan Kaufmann publishers, San Francisco, California, 1996"). The processor used in this case often has instructions that can be executed for each functional unit.
[0004]
For example, a processor has two functional units inside, one of which (integer arithmetic unit) has a function of executing integer arithmetic, and the other (floating point arithmetic unit) has a function of executing floating point arithmetic Then, the processor executes an integer instruction using the integer arithmetic unit, and executes a floating point instruction using the floating point arithmetic unit. At this time, the processor can execute one integer instruction and one floating point instruction simultaneously using the respective functional units. However, in order to execute a plurality of instructions at the same time, the workload of each functional unit to be executed within a certain unit time needs to be approximately the same. Therefore, a plurality of instructions cannot be executed at the same time, particularly when the calculation operation in the loop is biased to instructions belonging to a specific functional unit.
[0005]
In addition, as a conventional technique for increasing the execution speed of a program by distributing the work load of each functional unit, there is a method of adding a function for executing a command having a high appearance frequency to a functional unit that is not often used. . For example, Proceeding of the ICH Mig Plan PLD (1998), p. 118-129 (Sastry, S. S., Pallacha, S. and Smith J. E., "Exploding Idle Floating Point Restraining Point Re- , "Proceedings of the ACM SIGPLAN PLDI 1998, pp. 118-129), two types of functional units, an integer arithmetic unit that executes integer instructions and a floating point arithmetic unit that executes floating point instructions. By adding an integer arithmetic function to the floating point arithmetic unit and making the hardware redundant, The intensive programs several operations to run at high speed. The compiler for a computer in this case separates integer arithmetic processing on the source program into one that should be executed by the integer arithmetic unit and one that should execute the integer arithmetic function added to the floating point arithmetic unit.
[0006]
[Problems to be solved by the invention]
The above-described conventional method can be realized only by a redundant computer in which an integer arithmetic function is added to a floating point arithmetic unit. In addition, since many commonly used programs (compilers, editors, operating systems) are programs that heavily use integer arithmetic, the conventional method of taking over the integer arithmetic unit with a floating-point arithmetic unit is effective. It is not effective for programs that make heavy use of floating-point arithmetic, such as scientific and engineering calculations. In general, in a computer that has a plurality of functional units and each functional unit can execute instructions simultaneously, in order for each functional unit to actually execute instructions simultaneously, the workload of each functional unit for a certain unit time is approximately the same. There must be.
[0007]
An object of the present invention is to provide a program compiling method capable of accelerating a program that frequently uses both integer arithmetic and floating point arithmetic without providing hardware with redundancy, and a recording medium on which the compiling method is recorded Is to provide.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, in the compiling method of the present invention, first, at the time of program translation, is a calculation operation included in a certain execution section on the input program (source program) biased to an instruction belonging to a specific functional unit? Judge whether or not. As a result, if it is determined that it is biased, in order to make the workload of each functional unit the same, a part of the instruction is translated into an alternative instruction sequence belonging to another functional unit, or It is translated into a library call composed of alternative instruction sequences including instructions belonging to other functional units.
[0009]
The recording medium of the present invention is a computer-readable recording medium in which the processing of each step of the program compilation method is recorded as a program code.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. However, it goes without saying that the present invention is not limited to the examples.
FIG. 1 is a diagram showing an example of a computer system to which the compiling method of the present invention is applied. The computer shown in FIG. 1 includes a processor 101, a main memory 102, a disk device 103, a reading device 104, and a bus 105. The reading device 104 can read a program or the like stored in a storage medium 106. The compiler using the present invention is stored in the disk device 103 or the storage medium 106, is taken into the main memory 102 via the bus 105, is decoded, and is executed by the processor 101.
[0011]
FIG. 2 is a diagram illustrating an example of a functional configuration of the processor 101. In the example of FIG. 2, the processor 101 has a plurality of functional units including a load store unit 201, an integer arithmetic unit 202, a floating-point addition / subtraction / multiplication unit 203, and a floating-point division / division unit 204. The instruction can be executed.
[0012]
FIG. 3 is a diagram showing an overview of the processing flow of the compiler in this embodiment.
In the figure, reference numeral 301 denotes an input program (source program), 302 denotes a compiler, 303 denotes an optimization unit, 304 denotes a target program (object program), and 305 denotes processing to which the compiling method according to the present invention is applied.
The compiler 302 reads the input program 301, optimizes it by the optimization unit 303, and translates it into the target program 304. The compiling method of the present invention is applied to the processing 305 in the optimization unit 303. Since the processing 305 to which the compiling method of the present invention is applied is particularly effective when applied to a loop, an example of application to a loop is shown in the following description.
[0013]
FIG. 4 is a specific flowchart of the process 305.
The processing 305 in this embodiment estimates the workload for each functional unit that the processor 101 has for the calculation operation included in a certain execution section in the program, and among the instructions during the calculation operation in the execution section, Calculate the number n of instructions whose workload is the same for each functional unit when translated into an alternative instruction sequence. If n is 0, all instructions are translated into original instructions, and n is 1 or more In the case of n, n are translated into an alternative instruction sequence.
[0014]
Next, the flow of the process 305 will be described in detail with reference to FIG.
First, the calculation operation of each loop execution is recognized as the processing unit to be optimized and the workload of each functional unit is estimated (step 401).
Next, in order to make the work load of each functional unit approximately the same, the number n of instructions that belong to the functional unit with the heaviest work load in the calculation operation recognized in step 401 is to be translated into an alternative instruction sequence. (Step 402). If the number n to be translated is 0 as a result of the calculation, all instructions are translated into original instructions (step 403). If the number n to be translated is 1 or more, the number n of instructions is translated into an alternative instruction string or library call (step 404).
[0015]
There are many types of calculation operations to which the present invention can be applied. However, in practice, an instruction having a long execution time such as division or square root in a loop is combined with a combination of instructions having a short execution time such as multiplication or addition. Substitution is most effective. Here, as an example, a case where “reciprocal operation f (x) = 1 / x”, which is a kind of division, is replaced by “multiply addition” will be taken up. Also, as a premise, the division instruction can be executed every 20 cycles, and the multiplication and addition instruction can be executed every other cycle. It is assumed that
[0016]
The case where the approximation by the Newton method shown below is used as an arithmetic method to be used is shown.
Xn + 1≈Xn + (1−x × Xn) × Xn
First, when starting the calculation, the exponent part of the argument x is reduced to a certain range. The zero-order approximation X0 is obtained by subtracting a prepared table from the reduced x value. Since Newton's method shows square convergence, if there is a suitable zero-order approximation with several bits of precision, it will completely converge at X3 or X4 for an 8-byte floating point number. Alternatively, by adding a verification operation to the approximate value, it is possible to match the calculation result by the division instruction.
[0017]
The amount of calculation required for one approximation step is two multiplication instructions and two addition / subtraction instructions. Since a computer having a multiplication / addition instruction can be realized with two instructions, if it converges with X4, it is eight instructions. Here, it is assumed that 10 instructions are required. On the other hand, the operation of the exponent part for reduction is realized by integer arithmetic, but since this work load is relatively light, it is ignored in this example. Therefore, if the division instruction is used to calculate the reciprocal, the division unit (204) occupies 20 cycles, and if the above alternative instruction sequence is used, the addition / subtraction multiplication unit (203) occupies 10 cycles.
[0018]
Under the above conditions, if the number of division instructions in a certain execution section is p and the number of addition / subtraction multiplication instructions is q, then q is 20p when n is the number of division instructions to be translated into an alternative instruction sequence by multiplication / addition instructions. If it is less than (p−n) * 20 = q + 10n, that is, n = (20p−q) / 30, while if q is 20p or more, n = 0. FIG. 5 shows a program example of a process for calculating the number n of division instructions to be translated into an alternative instruction sequence.
[0019]
Further, when replacing the division instruction with a library call, when q is less than 20p, the library call is made for the number of cycles (20p-q) in which only the division unit is operating. Therefore, n = (20p−q) / 20. On the other hand, when q is 20p or more, n = 0. The example of a program of the process which calculates the division instruction number n which should translate a reciprocal number into the library call of an alternative instruction sequence is shown.
[0020]
This library is composed of codes for performing reciprocal calculation at a ratio of the alternative instruction sequence 2 by the multiplication and addition instruction to the division instruction 1 so that the workload between the functional units becomes equal. When calling a library, it is necessary to pass an array of arguments, an array of results, and the number of operations. Therefore, it may be necessary to generate a temporary array when calling the library. As a specific example, if the source program of B (n) = 1 / (5 * A (n)) shown in FIG. In FIG. 8, LIB (TMP, B, N) indicates a library, and TMP indicates a temporary array generated by the compiler (n = 1 to N).
In any case, it is often effective to use an appropriate loop expansion optimization in combination in order to realize an optimum work load balance.
[0021]
Next, the process of translating the FORTRAN program fragment shown in FIG. 9 will be described along the flowchart of the process 305 shown in FIG.
The compiler recognizes the doTRAN loop of the FORTRAN program shown in FIG. 9 as an independent optimization unit, and estimates the work load of each functional unit (step 401). When an alternative instruction sequence is used in order to make the load of each functional unit comparable, the reciprocal operation n to be translated into the alternative instruction sequence is calculated by the calculation method shown in FIG. When a library is used, the reciprocal operation n to be calculated by the library is calculated by the calculation method shown in FIG. In either case, n is 1 or more (step 402).
[0022]
In FIG. 9, the time required to calculate one loop, that is, one reciprocal, is 20 cycles when all are translated into original division instructions, and 10 cycles when all are translated into alternative instruction sequences. Here, when the loop of FIG. 9 is developed four times and three of the four reciprocals are translated into alternative instruction strings, the number of reciprocals is shortened to 7.5 cycles. When translated into a library call, it takes about 6.7 cycles per reciprocal (step 404).
Under the process of this embodiment, it can be seen that in any case, a speed increase of twice or more can be achieved. In general, the code in the library has the advantage of being able to achieve perfect performance.
[0023]
The program compiling method according to the present invention has been described above in detail. However, if each process of the compiling method is converted into a program code and recorded on a recording medium such as a CD-ROM or a flexible disk (FD), it is distributed. By obtaining and using the recording medium, the user can obtain a target program optimum for the processing performance (including hardware and OS) of his computer system.
[0024]
Further, the software sales company uses this program compilation method to generate a target program suitable for various computer systems (including hardware and OS), for example, a CD-ROM or a flexible disk (FD). It can be recorded on a recording medium and distributed as software dedicated to various computer systems. In that case, the user operates the computer system with the target program that is optimal for the processing performance (including hardware and OS) of the user's computer system by obtaining and using a recording medium suitable for the user's computer system. Can be made.
[0025]
【The invention's effect】
According to the program compiling method of the present invention, the work load of each functional unit can be made comparable without giving redundancy to the hardware, and a plurality of functional units can execute instructions simultaneously. The processing capability of the program is improved, and the execution of the program can be accelerated. Further, by obtaining and using the recording medium according to the present invention, the user can obtain and execute an objective program optimum for the performance of his computer system.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example of a computer system to which a compiling method of the present invention is applied.
2 is a diagram illustrating an example of a functional configuration of a processor 101. FIG.
FIG. 3 is a diagram showing an outline of a processing flow of a compiler in the present embodiment.
FIG. 4 is a specific flowchart of processing 305;
FIG. 5 is a program example of a process for calculating the number of division instructions n to be translated into an alternative instruction sequence.
FIG. 6 is a program example of processing for calculating the number n of division instructions to be translated into a library of alternative instruction sequences.
FIG. 7 is an example of a source program that requires a temporary arrangement when a library is called.
8 is an example in which the source program of FIG. 7 is rewritten using a temporary arrangement.
FIG. 9 is an example of a source program (FORTRAN) using the present invention.
[Explanation of symbols]
101: processor,
102: Main memory
103: Disk device,
104: Reading device,
105: Bus
106: storage medium,
201: Load store unit,
202: integer arithmetic unit,
203: Floating point addition / subtraction unit
204: Floating point division unit 301: Input program,
302: Compiler,
303: Objective program,
305: Processing (the compiling method of the present invention).

Claims (2)

In a program compiling method for a computer having a plurality of functional units capable of executing instructions in parallel, a specific functional unit is estimated by estimating a work load of each functional unit for a calculation operation included in a certain execution section on the input program The number of instructions that causes the workload to be the same in each functional unit when translated to an alternative instruction sequence belonging to another functional unit among the instructions being calculated in the execution section. a first step you calculate the number of instructions to alternative instruction sequence to translate configured library calls in the workload including instructions belonging to other functional units is similar in each functional unit,
If it is determined that the first step is biased, the number of instructions calculated in the first step among the instructions is translated into an alternative instruction sequence belonging to another functional unit or belongs to another functional unit A program compiling method comprising: a second step of translating into a library call composed of an alternative instruction sequence including instructions. A computer-readable storage medium in which processing of each step of the program compiling method according to claim 1 is recorded as program code.

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