JP6897213B2 - Code generator, code generator and code generator - Google Patents

Description

The present disclosure relates to techniques for generating code that can be executed on a processor.

In recent information processing devices (computers and the like), a processor capable of executing SIMD (Single Instruction Multiple Data) instructions may be used. The SIMD (Single Instruction Multiple Data) instruction is an instruction (parallel execution instruction) capable of executing the same arithmetic processing in parallel for a plurality of data. The use of SIMD instructions makes it possible to perform operations on multiple data with a small number of instructions.

The following techniques are known as techniques that use SIMD operation instructions.

Patent Document 1 describes a technique of finding a place where the same operation is applied to different data in the process of converting a source code written using a high-level language into an intermediate representation, and replacing it with a SIMD instruction. There is.

In Patent Document 2, a calculation tree showing the dependency of the source code is generated, a common sub-operation string is extracted from the operation sequence in which the operation instructions included in each operation tree are arranged, and the instructions included in the sub-operation string are used. Techniques for generating SIMD instructions in combination are described.

Patent Document 3 describes a technique of generating a tree showing the dependency between instructions when compiling a source code and replacing a part of the tree with a compound operation instruction.

Japanese Unexamined Patent Publication No. 2003-20291 Japanese Unexamined Patent Publication No. 2013-206289 Japanese Unexamined Patent Publication No. 2015-143939

In a certain program, it is assumed that a plurality of arithmetic instructions of the same type have no dependency (for example, a relation in which the result of one arithmetic instruction is referred to by another arithmetic instruction) and can be executed in parallel. In this case, these instructions can be combined to generate a SIMD instruction. For example, in Patent Document 1, when the same operation instruction is executed for a plurality of data, the instruction is replaced with a SIMD instruction.

On the other hand, for example, in a program, when there is a dependency between the same type of arithmetic instructions, or when different arithmetic instructions (for example, addition / subtraction and multiplication) are executed consecutively, these arithmetic instructions are used. It is not always possible to simply replace it with a SIMD instruction.

Further, in the method described in Patent Documents 2 and 3, a product-sum instruction is a combination of a specific instruction (a combination of a multiplication instruction and an addition instruction that refers to the multiplication result) included in the program. The FMA instruction can be executed in parallel as a SIMD instruction only when it can be replaced with (FMA (Fused Programy and added) instruction). That is, when these techniques are adopted, the instructions that can be converted into SIMD instructions are limited. From the above, there is a problem that it may be difficult to improve the execution efficiency by using, for example, the SIMD instruction for the part including different instructions in the program.

The technology according to the present disclosure was conceived in view of the above circumstances. One of the main purposes of the technique according to the present disclosure is to provide a technique for improving the execution efficiency of a program including a plurality of different types of instructions.

The code generator, which is one aspect of the technique according to the present disclosure, is based on the dependency between the operation instructions of different types among one or more operation instructions included in the analysis target code which is a computer program. A code analysis unit that determines whether or not a fusion operation instruction that can execute different types of operations as one instruction can be converted into a parallel execution instruction that can be executed in parallel for a plurality of data, and the above code analysis. After converting the operation instruction determined to be convertible to the parallel execution instruction by the unit into the fusion operation instruction, the operand of the fusion operation instruction is arranged in a format that can be executed as the parallel execution instruction. It includes an instruction generation unit that generates the parallel execution instruction that executes the fusion operation instruction in parallel by generating the generated data.

In the code generation method, which is one aspect of the technique according to the present disclosure, one or more arithmetic instructions included in the analysis target code, which is a computer program composed of a plurality of arithmetic instructions, are divided into the above operation instruction types and the above Whether or not a fusion operation instruction that can execute different types of operations as one instruction can be converted into a parallel execution instruction that can be executed in parallel for a plurality of data based on the dependency between the operation instructions. Judge,
Data in which the operand of the fusion operation instruction is arranged in a format that can be executed as the parallel execution instruction after the operation instruction determined to be convertible to the parallel execution instruction is converted into the fusion operation instruction. Is included to generate the parallel execution instruction that executes the fusion operation instruction in parallel.

The above object is also achieved by a code generator having the above configuration, a computer program that realizes the corresponding code generation method by a computer, and a computer-readable storage medium in which the computer program is stored. Will be done.

According to the technique according to the present disclosure, it is possible to improve the execution efficiency of a program including a plurality of different types of instructions.

FIG. 1 is an explanatory diagram showing an example of processing by the SIMD instruction. FIG. 2 is an explanatory diagram showing one specific example of converting a plurality of instructions into one SIMD instruction. FIG. 3 is an explanatory diagram showing specific examples of a plurality of different instructions. FIG. 4 is a block diagram illustrating a functional configuration of the code generation device according to the first embodiment of the present disclosure. FIG. 5A is a flowchart (1/2) showing a specific example of the operation of the code generation device. FIG. 5B is a flowchart (2/2) showing a specific example of the operation of the code generation device. FIG. 6 is an explanatory diagram illustrating a method of converting a simple arithmetic operation into an FMA operation. FIG. 7 is an explanatory diagram showing an outline of a process of generating a SIMD instruction for executing a plurality of FMA operations in parallel from a simple arithmetic operation instruction included in the analysis target code. FIG. 8 is an explanatory diagram showing a specific example of the analysis target code. FIG. 9 is an explanatory diagram illustrating the dependency relationship of the instructions included in the specific example of the analysis target code illustrated in FIG. FIG. 10 is an explanatory diagram illustrating a SIMD instruction converted from an instruction included in the analysis target code illustrated in FIG. FIG. 11 is an explanatory diagram showing a specific example of an FMA operation converted from a certain arithmetic operation using two methods. It is a block diagram which illustrates the structure of the information processing apparatus which can execute the object code generated from the analysis target code in each embodiment of this disclosure. It is a block diagram which illustrates the functional structure of the code generation apparatus in the 2nd Embodiment of this disclosure. FIG. 14 is an explanatory diagram illustrating a hardware configuration that can realize each embodiment.

First, the technical matters to be examined regarding the present disclosure will be described in more detail.

In general, the SIMD instruction can execute the same arithmetic processing in parallel (simultaneously) with one instruction for a plurality of data as illustrated in FIG. In the case of the specific example shown in FIG. 1, one SIMD instruction executes addition processing for four data.

In this way, by using the SIMD instruction, it is possible to execute arithmetic processing on a plurality of data using a small number of instructions. This reduces the code size and improves the execution time of the program.

For example, as illustrated in FIG. 2, if a code contains two add instructions, some compilers may convert these instructions into SIMD instructions that execute the two additions in parallel (simultaneously). Is possible. On the other hand, as illustrated in FIG. 3, for a set of different instructions (in the case of FIG. 3, an addition instruction and a multiplication instruction), it may not be possible to directly convert these instructions into SIMD instructions. There are many. In this case, each instruction is executed sequentially. That is, in this case, it is difficult to improve the execution efficiency of the program by using the SIMD instruction.

The technology according to the present disclosure is inspired by the above circumstances, and is coded by generating code (for example, a program such as object code or execution code) that can execute different types of instructions as SIMD instructions. Reduce the size of. This also improves the execution time of the program.

Using each of the following embodiments, a code generation device, a code generation method, and the like that can realize the technique according to the present disclosure will be described in detail below using each embodiment.

In each of the following embodiments, an arithmetic unit capable of executing SIMD instructions, more specifically, an arithmetic unit capable of executing SIMD-type fusion operations (for example, FMA operations) (for example, SIMD-type FMA arithmetic units). The technique for generating the code (object code, execution code, etc.) for the processor having the above will be described.

The fusion operation is an operation that executes a plurality of types of operations as one operation, such as an FMA operation. An arithmetic unit capable of executing a SIMD type fusion operation can execute an instruction representing a fusion operation (fusion operation instruction) as one instruction. In the following, for convenience of explanation, a configuration in which the FMA operation is used as the fusion operation will be illustrated. The technique according to the present disclosure is not limited to this, and a fusion operation other than the FMA operation may be used. Hereinafter, an instruction using a SIMD type FMA arithmetic unit may be described as a SIMD-FMA instruction.

The FMA arithmetic unit is configured to include a multiplier and an adder, and is an arithmetic unit capable of executing a product-sum operation with one instruction. The product-sum operation is, for example, an operation of the form ((A * B) + C) (an operation of adding the results of multiplication). The SIMD type FMA arithmetic unit is an arithmetic unit capable of processing a plurality of (for example, two) sets of FMA operations with one instruction.

Whether or not the technique according to the present disclosure can convert those arithmetic instructions into SIMD-FMA instructions according to, for example, the types and dependencies of the arithmetic instructions included in the code to be analyzed (for example, source code, etc.). Can be determined. Then, based on the determination result, it is possible to convert those arithmetic instructions into SIMD-FMA instructions. Further, at this time, the technique according to the present disclosure can collect (pack) the data (operand) processed by the SIMD-FMA instruction in a format that can be arranged in the register referenced by the SIMD-FMA instruction. is there.

Hereinafter, embodiments in which the technology according to the present disclosure can be realized will be described. The configurations of the devices and the like described in each of the following embodiments are examples, and the scope of the technology according to the present disclosure is not limited thereto. The division of the components constituting the apparatus in each of the following embodiments (for example, division by functional units) is an example in which the technique according to the present disclosure can be realized. In realizing the technology according to the present disclosure, various configurations are assumed without being limited to the following examples. That is, each component illustrated in each of the following embodiments may be further divided. In addition, one or more components in each of the following embodiments may be integrated.

The technique according to the present disclosure may be realized by using a single device (physical and virtual device), or may be realized by using a plurality of separated devices (physical and virtual device). .. When the technology according to the present disclosure is realized by a plurality of devices, each device may be communicably connected by a communication network that is wired, wireless, or a combination thereof. The communication network may be a physical communication network or a virtual communication network. The hardware configuration that can realize each of the embodiments described below will be described later.

<First Embodiment>
Hereinafter, the first embodiment of the technique according to the present disclosure will be described.

[Constitution]
FIG. 4 is a block diagram illustrating a functional configuration of the code generation device 100 according to the present embodiment. As illustrated in FIG. 4, the code generation device 100 includes a compiler 101. The code generation device 100 may further include a file management unit 104. These components constituting the code generation device 100 are communicably connected to each other by using appropriate methods (for example, interprocess communication, shared memory, various APIs (Application Programming Interfaces), etc.). May be good. Hereinafter, each component will be described.

The compiler 101 receives the source code as input and executes lexical analysis processing, syntax analysis processing, semantic analysis processing, object code generation processing, and the like. As a result, the compiler 101 converts (compiles) the source code into the object code. At this time, the compiler 101 can execute the optimization process for the purpose of reducing the size of the object code, improving the execution speed of the execution code finally generated from the object code, and the like. Hereinafter, the components capable of executing the optimization process will be described.

The compiler 101 includes a code analysis unit 102 and an instruction generation unit 103.

Hereinafter, a configuration in which the code analysis unit 102 analyzes the source code or the intermediate code (code generated by performing syntactic analysis processing, lexical analysis processing, semantic analysis processing, etc. on the source code) will be described. In the following, the source code and the intermediate code may be collectively referred to as the analysis target code.

The code analysis unit 102 analyzes the analysis target code and determines whether or not the arithmetic instruction included in the analysis target code can be converted into a SIMD instruction. The code analysis unit 102 can determine, for example, whether or not the operation inside the loop processing (repetition processing) included in the analysis target code can be converted into a SIMD instruction. Further, the code analysis unit 102 can determine, for example, whether or not the operations sequentially executed in the analysis target code can be converted into SIMD instructions.

The code analysis unit 102 includes a search unit 102a that searches for operations (for example, addition / subtraction, multiplication, division, FMA operation, etc.) included in the analysis target code. The search unit 102a can search, for example, the operation inside the loop processing included in the analysis target code. The search unit 102a may provide the search result to the dependency analysis unit 102b (described later).

The code analysis unit 102 also includes a dependency analysis unit 102b that analyzes the dependencies between the operations searched by the search unit 102a and determines whether or not those operations can be converted into SIMD instructions. The dependency analysis unit 102b can analyze, for example, the dependency relationships of the operations inside the loop processing searched by the search unit 102a, and determine whether those operations can be converted into SIMD instructions.

The instruction generation unit 103 converts the operation included in the analysis target code into a SIMD instruction according to the analysis result of the analysis target code in the code analysis unit 102.

The instruction generation unit 103 includes an operation conversion unit 103a that converts an operation instruction (for example, an addition instruction, a subtraction instruction, a multiplication instruction, etc.) into an FMA operation format. The instruction generation unit 103 also includes a SIMD instruction generation unit 103b. The SIMD instruction generation unit 103b selects two FMA operations that can be combined based on the dependency between a plurality of FMA operations, forms (packs) data representing the operands of the SIMD instruction, and generates a SIMD-FMA instruction. Execute the process to be performed.

The code analysis unit 102 and the instruction generation unit 103 may be implemented as components that execute a part of the optimization process in the compiler 101. In addition to this, the compiler 101 may be configured to execute typical processes such as lexical analysis, syntactic analysis, semantic analysis, and object generation. These typical processes may be implemented, for example, using well-known techniques.

The file management unit 104 is configured to store and manage source code, object code, and the like. In the present embodiment, the file management unit 104 may manage the source code, the object code, and the like in the file format. In this case, the file management unit 104 may be realized by using a file system. The present embodiment is not limited to this, and the file management unit 104 may be realized by using a technique other than the file system, such as a database.

The code generation device 100 may generate object code executed by the code generation device 100 itself, for example. Further, the code generation device 100 may generate an object code that can be executed by another information processing device 1200 as illustrated in FIG. 12, for example. The information processing device 1200 may be, for example, a computer composed of a processor 1201, a memory 1202, a storage 1203, and the like.

The processor 1201 is a CPU (Central Processing Unit) or MPU (Micro Processing Unit) including at least a SIMD type FMA arithmetic unit and a register (sometimes referred to as a SIMD-FMA register) capable of storing operands used in SIMD arithmetic. Unit) may be used. In addition to the above, the processor 1201 may have a configuration capable of executing typical calculation processing of today. The memory 1202 is a storage device that can be referred to by the processor 1201 and can store the object code executed by the processor 1201. The storage 1203 is composed of, for example, a non-volatile storage device (hard disk drive, semiconductor flash memory, etc.) and can store an object code. The configuration of the information processing apparatus 1200 illustrated in FIG. 12 is a specific example, and the present embodiment is not limited thereto.

[motion]
Hereinafter, the operation of the code generation device 100 configured as described above will be described.

FIG. 5A is a flowchart showing an example of processing in the code analysis unit 102. The code analysis unit 102 analyzes the analysis target code and uses the function of the search unit 102a to specify the type of operation included in the analysis target code (step S501). For example, the code analysis unit 102 may analyze the loop processing in the code to be analyzed and use the function of the search unit 102a to specify the type of operation included in the loop processing.

The search unit 102a selects addition / subtraction and multiplication from the operations included in the analysis target code, and searches for a pattern of a combination of operations that can be converted into a SIMD instruction (step S502). At this time, the search unit 102a may search for a combination of the addition / subtraction instruction and the multiplication instruction having the same operand type and accuracy, for example.

The dependency analysis unit 102b analyzes whether or not there is a dependency relationship with respect to the combination of operations searched by the search unit 102a. Depending on the result of this analysis, the dependency analysis unit 102b determines whether or not these instructions can be converted into SIMD instructions (step S503). For example, when a plurality of operations are included in the same loop processing and there is no dependency between the operations, the dependency analysis unit 102b determines that there is no dependency for the combination of those operations. May be good.

If it is determined that there is a dependency as a result of the determination in step S503 (YES in step S504), the code analysis unit 102 determines that those instructions are not converted into SIMD instructions. This is because when an instruction having a dependency is converted into a SIMD instruction, the value of the calculation result may change. The code analysis unit 102 may exclude those instructions from the candidates for instructions to be converted into SIMD instructions (step S505).

If it is determined as a result of the above analysis that there is no dependency (NO in step S504), the code analysis unit 102 determines that these instructions can be converted into SIMD instructions.
In this case, the code analysis unit 102 may provide the result of the above processing to the instruction generation unit 103, for example.

The instruction generation unit 103 converts a combination of operations having no dependency into a SIMD instruction (more specifically, a SIMD-FMA instruction) (step S506). Hereinafter, the process in step S506 will be described with reference to the flowchart illustrated in FIG. 5B. FIG. 5B is a flowchart illustrating an example of processing in the instruction generation unit 103.

The instruction generation unit 103 converts addition / subtraction and multiplication into an FMA operation format by using the function of the operation conversion unit 103a (step S508).

Hereinafter, a method of converting a non-FMA operation (for example, a simple arithmetic operation such as addition, subtraction, multiplication, division, etc.) included in the analysis target code into an FMA operation will be described with reference to an explanatory diagram illustrated in FIG. To do. The instruction generation unit 103 multiplies (multiplies) one operand by the value "1" as a dummy multiplication (a fake multiplication that does not affect the result) for the addition included in the analysis target code. As a result, the instruction generation unit 103 converts the addition into an FMA operation (601 in FIG. 6). Hereinafter, the process of converting the addition into the FMA operation may be described as the first operation conversion. The dummy operand (“1” in this specific example) used when converting the addition to the FMA operation may be described as the first dummy operand.

The instruction generation unit 103 multiplies (multiplies) one operand by the value "1" as a dummy multiplication, and inverts the sign of the decimal operand to perform the subtraction. Convert to FMA operation (602 in FIG. 6). Hereinafter, the process of converting the subtraction into the FMA operation may be described as the second operation conversion. The dummy operand (“1” in this specific example) used when converting the subtraction into the FMA operation may be described as the second dummy operand.

The instruction generation unit 103 converts the multiplication into an FMA operation by adding a dummy addition (a fake addition that does not affect the result) that adds the value "0" to the result of the multiplication for the multiplication included in the analysis target code. (603 in FIG. 6). Hereinafter, the process of converting multiplication into FMA operation may be described as a third operation conversion. Hereinafter, a dummy operand (“0” in this specific example) used when converting multiplication into an FMA operation may be described as a third dummy operand.

By the method as described above, the instruction generation unit 103 can convert addition, subtraction, and multiplication into an FMA operation by the first, second, and third operation conversions without changing the result of the operation. By such conversion, for example, the addition (or subtraction), multiplication, and combination determined by the code analysis unit 102 to be SIMD-instructed can be obtained from a set of two FMA operations (one is addition (or subtraction)). The converted FMA operation, the other is the converted FMA operation from multiplication).

The SIMD instruction generation unit 103b generates a SIMD instruction (SIMD-FMA instruction) capable of executing the above two sets of FMA operations at the same time (in parallel) (step S508). At this time, the SIMD instruction generation unit 103b generates data representing the operands of the SIMD-FMA instruction so that the operands of each FMA operation are packed (arranged) in the high-order bits and the low-order bits of the SIMD register. As a result, the SIMD instruction generation unit 103b generates the SIMD-FMA instruction.

The processing of the instruction generation unit 103 will be described with reference to a specific example illustrated in FIG. In the specific example illustrated in FIG. 7, since the analysis target code (source code) includes different types of operations (addition and multiplication), it is difficult to simply replace these instructions with SIMD instructions. Is.

The instruction generation unit 103 (specifically, the operation conversion unit 103a) converts the addition and multiplication included in the source code into an FMA operation. The instruction generation unit 103 (specifically, the SIMD instruction generation unit 103b) converts the FMA operation into a SIMD instruction (SIMD-FMA instruction). At this time, the SIMD instruction generation unit 103b generates data representing the operands of the SIMD-FMA instruction so that each operand of the FMA operation is packed into the high-order bit and the low-order bit of the SIMD register. As a result, when the object code converted from the source code is executed, the addition process of "A1 + B1" is executed in the upper bits of the SIMD register, and the multiplication process of "A2 * B2" is executed in the lower bits. It is possible to perform arithmetic processing as if.

FIG. 7 illustrates a specific example of executing two FMA instructions as SIMD instructions, but the present embodiment is not limited thereto. The code generator 100 may generate a SIMD-FMA instruction that executes three or more FMA instructions as SIMD instructions according to the environment in which the generated object code is executed (for example, the configuration of the processor 1201).

Hereinafter, a case where the code generator 100 generates SIMD instructions (SIMD-FMA instructions) capable of executing n FMA instructions (n is an integer of 2 or more) in parallel will be described.

In this case, the instruction generation unit 103 arranges n operands of the FMA instruction in each area of the SIMD-FMA register divided into n equal parts in the environment in which the object code is executed (for example, processor 1201). SIMD-FMA instructions may be generated. For example, when the SIMD-FMA register is 64 bits wide and the operand of the FMA instruction is single-precision floating small number electric data (32 bits), two FMA instructions may be executed in parallel as the SIMD-FMA instruction. In this case, the instruction generation unit divides the SIMD-FMA register into two areas (upper 32 bits and lower 32 bits), and arranges two operands of the FMA operation in each area. For example, when the SIMD-FMA register is 64 bits wide and the operand of the FMA instruction is semi-precision floating small number electric data (16 bits), four FMA instructions may be executed in parallel as SIMD-FMA instructions. In this case, the instruction generator divides the SIMD-FMA register into four areas (16 bits each), and arranges four FMA operation operands in each area.

An example of the effect obtained when the code generation device 100 is used will be described with reference to the specific examples shown in FIGS. 8 to 10. The specific examples shown in FIGS. 8 to 10 are merely examples, and the present embodiment is not limited thereto.

FIG. 8 is an explanatory diagram showing an example of an instruction sequence appearing in a loop included in the analysis target code (source code). It is assumed that all the operands of the arithmetic processing illustrated in FIG. 8 represent single-precision floating-point data (32 bits). Further, it is assumed that the processor of the execution environment (for example, the information processing device illustrated in FIG. 12) has a SIMD type FMA arithmetic unit. Further, it is assumed that the processor can calculate two single-precision floating-point numbers at the same time by a 64-bit wide SIMD instruction, and can execute up to four single-precision floating-point operations per clock.

In the case of the specific example shown in FIG. 8, the analysis target code includes the instructions (801) to (808). Addition is performed in the instructions (801) to (804), and multiplication is performed in the instructions (805) to (808). As illustrated in FIG. 9, since the instruction (802) refers to the operation result (“A1”) of the instruction (801), there is a dependency relationship between the instruction (802) and the instruction (801). is there. Similarly, with respect to the instructions (803) and (804), since the result of the previous instruction is referred to, there is a dependency relationship between the addition instructions (801) to (804).

Further, since the instruction (806) refers to the operation result (“X1”) of the instruction (805), there is a dependency relationship between the instruction (805) and the instruction (806). Similarly, for the instruction (807) and the instruction (808), since the result of the previous instruction is referred to, there is a dependency relationship between the multiplication instructions (805) to (808). That is, there is a dependency between the additions of the instructions (801) to (804), which are the same type of arithmetic instructions, and the multiplications of the instructions (805) to (808).

On the other hand, the multiplication instructions of the instructions (805) to (808) do not refer to the result of the addition instructions of the instructions (801) to (804). That is, there is no dependency between the addition instructions of the instructions (801) to (804) and the multiplication instructions of the instructions (805) to (808).

Typically, the same type of operation can be converted to a SIMD instruction if there are no dependencies between the operations. On the other hand, it is difficult to simply replace an instruction with a different operation type (for example, an addition instruction and a multiplication item example) with a SIMD instruction.

In the case of the instruction sequence as illustrated in FIG. 8, since there is a dependency between the same type of operation instructions, it cannot be simply converted into a SIMD instruction. In this case, eight instructions are executed sequentially, and sufficient execution performance cannot be obtained. Further, in this case, since the processor can execute only one operation in one clock, sufficient execution efficiency cannot be obtained for the peak performance in which a maximum of four operations can be executed simultaneously.

On the other hand, the code generation device 100 in the present embodiment described above converts the instructions (801) to (808) into FMA operations (f1) to (f8), respectively, as illustrated in FIG. Can be done. The code generation device 100 executes (f1) and (f5), (f2) and (f6), (f3) and (f7), (f4) and (f8) having no dependency at the same time (in parallel). Judge that it is a set of possible instructions. The code generation device 100 can convert these instructions into SIMD-FMA instructions and generate instructions (s1) to (s4).

The code generator 100 packs the operand of the original addition instruction into the upper bit (upper 32 bits) of the SIMD register and the operand of the original multiplication instruction into the lower bit (lower 32 bits) of the SIMD register. Generate an FMA instruction. As a result, in the instructions (s1) to (s4), the addition instructions corresponding to the instructions (f1) to (f4) are executed in the upper bits of the SIMD register, and the instructions (f5) to (f5) to the lower bits are executed. The arithmetic processing is executed as if the multiplication instruction corresponding to (f8) is executed.

In the specific example shown in FIG. 8, the code generation device 100 can reduce the number of instructions to 1/2 (from 8 instructions to 4 instructions) as compared with the case where the SIMD instruction cannot be converted. In addition, the execution performance is doubled.

The code generation device 100 can generate a code (object code) that simultaneously issues two FMA operation instructions as SIMD instructions. From this, the processor that executes the code generated by the code generation device 100 can execute substantially four operations (multiplication and addition / subtraction) in one clock. As a result, the execution efficiency with respect to the peak performance is quadrupled as compared with the case where the SIMD instruction cannot be converted.

Another example of the effect obtained when the code generation device 100 configured as described above is used will be described with reference to the specific example shown in FIG. The specific example shown in FIG. 11 is only an example, and the present embodiment is not limited thereto.

In the analysis target code (part (a) of FIG. 11) illustrated in FIG. 11, the result of multiplication (“A0”) in the operation instruction (1101) is referred to the other subsequent instructions (1102) to (1103). Will be done. Since the instruction (1101) is addition and the instructions (1102) to (1103) are addition and multiplication, it is difficult to simply convert these instructions into instructions for FMA operation.

As a method different from the present embodiment described above, for example, it is conceivable to convert the instruction (1101) and another instruction (1102-1104) into an FMA operation by simply combining them. Such a method is, for example, searching for a combination of instructions that can be directly converted into an FMA operation without using the first, second, and third dummy operations described above, and performing an FMA operation on the searched instructions. It may include converting to and generating a SIMD-FMA instruction that executes the converted FMA operation. When such a method is used, the instructions (1101) to (1104) are converted into, for example, the instructions (1105) to (1108) shown in the portion (b) of FIG. Instructions (1106) and (1108) are FMA instructions, and in these instructions, the operation "B0 * C0" is executed a plurality of times. That is, the cost (latency, etc.) required for the process for executing this operation (for example, reading the operand) may occur a plurality of times. Further, when such a method is used, the number of multiplication instructions is smaller when "A0" is calculated first without converting to FMA calculation.

On the other hand, the code generation device 100 in the present embodiment does not generate an FMA operation by combining a plurality of operations that can be directly converted into an FMA operation, but converts an instruction having no dependency into an FMA instruction. Convert. In the case of the specific example shown in FIG. 11, the code generator 100 can generate the instructions (1109) to (1112) from the instructions (1101) to (1104) shown in FIG. In this case, since "A0" is calculated first in the instruction (1109), the cost of executing the operation "B0 * C0" is incurred only once.

Further, the first and second dummy operands included in the instructions (1110) to (1112) are all immediate values. Therefore, the cost required to execute the operation related to the dummy operand is considered to be relatively low. Further, the code generation device 100 can convert two of the instructions (1110) to (1112) into SIMD-FMA instructions. As a result, the code generation device 100 can reduce the number of instructions.

As described above, the code generation device 100 in the present embodiment can reduce the code size of the code to be analyzed. Further, the code generation device 100 can improve the execution speed of the code to be analyzed. The reason is as follows.

The code generation device 100 can convert instruction sequences representing different types of operations included in the code to be analyzed into instructions (SIMD instructions) that can execute operations related to a plurality of operands in parallel (simultaneously). More specifically, the code generation device 100 can determine whether or not the operations can be executed by converting them into SIMD instructions by determining the dependency of the operations included in the analysis target code. The code generation device 100 can convert the operations (for example, addition / subtraction and multiplication) included in the analysis target code into FMA operations by using dummy operands. The code generation device 100 can convert an FMA operation having no dependency into a SIMD instruction (SIMD-FMA instruction). As described above, the code generation device 100 can reduce the code size by converting a part of the analysis target code into the SIMD-FMA instruction as compared with the case where it cannot be converted into the SIMD instruction. Further, by using the SIMD-FMA instruction, the execution speed of the code (specifically, the object code generated from the analysis target code) is improved.

For example, in the field of scientific computing, a program may be executed in which a large amount of data stored in an array is processed by a loop and a recurrence formula having a dependency relationship is calculated for each iteration of the loop. For example, as shown in FIG. 8, A (n) = A (n-1) + B (n), X (n) = X (n-1) + Y (n) (A, B, X, Y are sequences, n Is an array index) is also considered to be an example of such a recurrence formula. In this case, the execution of the program issues many arithmetic (for example, addition, multiplication, etc.) instructions. However, for example, in a recurrence formula, there are often dependencies between operations of the same type (for example, additions and multiplications). Therefore, it is difficult to replace these instructions with SIMD instructions as they are. As described above, even if the same type of operation instruction existing in the loop cannot be simply replaced with the SIMD instruction, the code generation device 100 in the present embodiment combines different types of instructions to form a SIMD instruction (SIMD instruction). -FMA instruction) can be generated. Thereby, the code generation device 100 can reduce the code size even in a program including, for example, a recurrence formula. In addition, the code generation device 100 can improve the execution speed of such a program.

For example, in a system such as an embedded system in which the memory size is limited, it is required to reduce the code size. It is considered that the method described in the present embodiment is highly useful also in such a field.

[Modification example]
Hereinafter, a modified example of the present embodiment will be described. The functional configuration of the code generation device in this modification may be the same as that of the first embodiment.

The code generation device 100 in the first embodiment can convert a combination of addition / subtraction and multiplication into a SIMD instruction (specifically, a SIMD-FMA instruction) according to the dependency between them.

In this modification, in addition to the above, the code generator 100 is configured so that the combination of addition / subtraction and division can be converted into a SIMD-FMA instruction. In floating-point arithmetic, division can be converted to multiplication by finding the reciprocal of the divisor. Therefore, in this modification, the code generator 100 generates a SIMD-FMA instruction from a combination of addition / subtraction and division by, for example, converting division into multiplication and then converting it into an FMA instruction. Is possible.

<Second embodiment>
Hereinafter, a second embodiment, which is a basic embodiment of the technique according to the present disclosure, will be described.

FIG. 13 is a block diagram illustrating a functional configuration of the code generation device 1300 according to the present embodiment. As illustrated in FIG. 13, the code generation device 1300 includes a code analysis unit 1301 (code analysis means) and an instruction generation unit 1302 (instruction generation means).

The code analysis unit 1301 and the instruction generation unit 1302 may be realized as a part of a compiler that generates object code from source code, as in the first embodiment.

The code generation device 1300 may generate object code executed by the code generation device 1300 itself, as in the code generation device 100 in the first embodiment, for example. Further, the code generation device 1300 may generate an object code that can be executed by another information processing device 1200 as illustrated in FIG. 12, for example.

Hereinafter, each component constituting the code generation device 1300 will be described.

The code analysis unit 1301 executes one or more arithmetic instructions included in the analysis target code, which is a computer program composed of a plurality of arithmetic instructions, based on the type of the arithmetic instructions and the dependency between the arithmetic instructions. , Determines whether the fusion operation instruction can be converted into a parallel execution instruction that can be executed in parallel. The code analysis unit 1301 may, for example, confirm the dependency between operation instructions of different types of instructions and determine whether or not those instructions can be converted into parallel execution instructions.

A fusion operation instruction is an instruction that can execute different types of operations as one instruction for a plurality of data. The fusion operation instruction may be, for example, an instruction that executes an FMA operation.

A parallel execution instruction is an instruction that can execute operations related to a plurality of data in parallel with one instruction. The parallel execution instruction may be, for example, a SIMD instruction. Further, the parallel execution instruction capable of executing the fusion operation instruction in parallel may be a SIMD-FMA instruction.

The instruction generation unit 1302 converts an operation instruction determined by the code analysis unit 1301 to be a parallel execution instruction into a fusion operation instruction. The instruction generation unit 1302 generates a parallel execution instruction that executes the fusion operation instruction in parallel by generating data in which the operands of the converted fusion operation instruction are arranged in a format that can be executed as a parallel execution instruction.

As an example, it is assumed that the code operation instruction is an FMA instruction and the parallel execution instruction is a SIMD instruction (more specifically, a SIMD-FMA instruction). In this case, the code analysis unit 1301 confirms the dependency between different types of operation (for example, addition and multiplication, subtraction and multiplication, etc.) instructions included in the code to be analyzed, and the dependency relationship is determined. You can select no combination of arithmetic instructions. The instruction generation unit 1302 may, for example, convert different types of operations having no dependency selected by the code analysis unit 1301 into FMA operation instructions, and combine the FMA operation instructions to generate a SIMD-FMA instruction. .. In this case, the instruction generation unit 1302 represents, for example, the operand of the SIMD-FMA instruction so that the operand of the FMA instruction executed in parallel is assigned to the area where the register used for executing the SIMD-FMA instruction is divided. Data may be generated.

In the present embodiment, the code analysis unit 1301 may be configured in the same manner as the code analysis unit 102 in the first embodiment, and the instruction generation unit 1302 may be configured in the same manner as the instruction generation unit 103 in the first embodiment. May be done.

According to the code generation device 1300 configured as described above, it is possible to improve the execution efficiency of a program including different instructions. The reason is that the code analysis unit 1301 determines the dependency between different types of operation instructions, and the instruction generation unit converts the operation instruction having no dependency into a parallel execution instruction that executes the fusion operation instruction in parallel. Because. The code generation device 1300 can generate an object code obtained by converting, for example, addition and multiplication, subtraction and multiplication, which are different types of operations included in the code to be analyzed, into a SIMD-FMA instruction. As a result, the code generation device 1300 can reduce the size of the object code and improve the execution speed.

<Structure of hardware and software programs (computer programs)>
Hereinafter, a hardware configuration capable of realizing each of the above embodiments will be described.

In the following description, the code generators (100, 1300) in each of the above embodiments are collectively referred to as "code generator". Further, each component of the code generation device is simply described as "component of the code generation device".

The code generation device described in each of the above embodiments may be composed of one or a plurality of dedicated hardware devices. In that case, each component shown in each of the above figures may be realized as hardware in which a part or all of them are integrated (a circuit configuration (circuit configuration (circuit configuration) in which processing logic is implemented)).

For example, when the code generation device is realized by hardware, the components of the code generation device may be realized by SoC (System on a Chip) or the like that implements a circuit configuration capable of providing each function. In this case, for example, the data held by the components of the code generator may be stored in a RAM (Random Access Memory) area, a ROM (Read Only Memory) area, a flash memory area, or the like integrated in the SoC. The circuit configuration is one specific embodiment, and various variations are expected in mounting.

A well-known communication bus or communication network may be adopted as the communication line for connecting each component of the code generation device. Further, the communication line connecting each component may be connected peer-to-peer between the respective components. When the code generation device is composed of a plurality of hardware devices, the respective hardware devices may be communicably connected by an appropriate communication method (wired, wireless, or a combination thereof).

The code generation device described above may be composed of a general-purpose hardware device 1400 as illustrated in FIG. 14 and various software programs (computer programs, for example, a compiler) executed by the hardware device 1400. Good. In this case, the code generation device may be composed of a plurality of hardware devices 1400 and software programs.

The processor 1401 in FIG. 14 is an arithmetic processing device such as a general-purpose CPU (Central Processing Unit) or a microprocessor. The processor 1401 may read, for example, various software programs stored in the non-volatile storage device 1403 described later into the memory 1402 and execute processing according to the software programs. Note that the processor 1401 may include an arithmetic unit capable of executing SIMD-FMA instructions, similar to the processor 1201 illustrated in FIG.

In this case, the components of the code generator in each of the above embodiments can be realized as, for example, a software program executed by the processor 1401. Various variations are expected in the implementation of such software programs.

The memory 1402 is a memory device such as a RAM that can be referred to by the processor 1401 and stores software programs, various data, and the like. The memory 1402 may be a volatile memory device.

The non-volatile storage device 1403 is a non-volatile storage device such as a magnetic disk drive or a semiconductor storage device using a flash memory. The non-volatile storage device 1403 can store various software programs, data, and the like.

For example, the file management unit (104) in each of the above embodiments may hold data in the non-volatile storage device 1403.

The drive device 1404 is, for example, a device that processes data reading and writing to the recording medium 1405 described later.

The recording medium 1405 is a recording medium capable of recording data, such as an optical disk, a magneto-optical disk, and a semiconductor flash memory.

The code generation device described by taking each of the above-described embodiments as an example is, for example, a software program (for example, a compiler) capable of realizing the functions described in each of the above-described embodiments with respect to the hardware device 1400 illustrated in FIG. May be realized by supplying. More specifically, for example, the technology according to the present disclosure may be realized by the processor 1401 executing the software program supplied to the device. In this case, the operating system running on the hardware device 1400, middleware such as database management software and network software may execute a part of each process.

In each of the above-described embodiments, each part shown in each of the above-mentioned figures (for example, FIGS. 4 and 13) is realized as a software module which is a function (processing) unit of a software program executed by the above-mentioned hardware. You may. However, the division of each software module shown in these drawings is an example, and various other configurations can be assumed at the time of implementation.

For example, when each of the above parts is realized as a software module, these software modules may be stored in the non-volatile storage device 1403. Then, when the processor 1401 executes each process, these software modules may be read into the memory 1402.

Further, these software modules may be configured so that various data can be transmitted to each other by shared memory, interprocess communication, or the like. With such a configuration, these software modules can be connected to each other so as to be able to communicate with each other.

Further, each of the above software programs may be recorded on the recording medium 1405. In this case, each of the software programs may be configured to be appropriately stored in the non-volatile storage device 1403 through the drive device 1404 at the shipping stage, the operation stage, or the like of the communication device or the like.

In the above case, as a method of supplying various software programs to the code generator, the device is used by using an appropriate jig (tool) at the manufacturing stage before shipment, the maintenance stage after shipment, or the like. You may adopt the method of installing in. Further, as a method of supplying various software programs, a general procedure may be adopted at present, such as a method of downloading from the outside via a communication line such as the Internet.

In such a case, the technology according to the present disclosure can be regarded as being composed of a code constituting the software program or a computer-readable recording medium on which the code is recorded. In this case, the recording medium is not limited to a medium independent of the hardware device 1400, but includes a storage medium in which a software program transmitted via a LAN, the Internet, or the like is downloaded and stored or temporarily stored.

Further, the above-mentioned code generation device or a component of the code generation device includes a virtual environment in which the hardware device 1400 illustrated in FIG. 14 is virtualized, and various software programs executed in the virtual environment ( It may be configured by a computer program). In this case, the components of the hardware device 1400 illustrated in FIG. 14 are provided as virtual devices in the virtualized environment. In this case as well, the technique according to the present disclosure can be realized with the same configuration as when the hardware device 1400 illustrated in FIG. 14 is configured as a physical device.

The techniques according to the present disclosure have been described above as examples of application to the above-mentioned exemplary embodiments. However, the technical scope of the present disclosure is not limited to the scope described in each of the above-described embodiments and modifications. It will be apparent to those skilled in the art that various changes or improvements can be made to such embodiments. In such cases, new embodiments with such modifications or improvements may also be included in the technical scope of the present disclosure. Further, the technical scope of the present disclosure may also include embodiments in which the above-described embodiments and modifications, as well as new embodiments with such modifications or improvements, are combined. And this is clear from the matters stated in the claims.

100 Code generator 101 Compiler 102 Code analysis unit 103 Instruction generation unit 104 File management unit 1200 Information processing device 1201 Processor 1202 Memory 1203 Storage 1300 Code generator 1301 Code analysis unit 1302 Instruction generation unit 1401 Processor 1402 Memory 1403 Non-volatile storage device 1404 Drive device 1405 Recording medium

Claims (10)

A code that selects a combination of operation instructions that have no dependency by analyzing the dependency between the operation instructions of different types among one or more operation instructions included in the analysis target code that is a computer program. Analytical means and
For each combination of the dependency is no operation instruction, convert the fusion operation instruction consisting operation instruction combination of addition and subtraction and multiplication, to produce a parallel execution instructions that perform pre Symbol fusion calculation instructions in parallel With instruction generation means ,
The instruction generation means is composed of an arithmetic instruction of a combination of addition / subtraction and division having no dependency, and an arithmetic instruction of a combination of addition / subtraction and multiplication by converting the division into multiplication by obtaining the reciprocal of the divisor. A code generator that converts to the fusion operation instruction. The code analysis means determines whether or not there is a dependency between the addition instruction and the multiplication instruction, which are the operation instructions having different operation types, among the operation instructions included in the analysis target code, and the subtraction instruction. Determine if there is a dependency between and the multiplication instruction,
The code generation device according to claim 1, wherein the instruction generation means converts the operation instructions of different types, which are determined by the code analysis means to have no dependency, into the fusion operation instructions. The instruction generation means converts all of the operation instructions of different types determined to have no dependency by the code analysis means into the fusion operation instruction, and combines the converted fusion operation instructions. The code generator according to claim 2, wherein the parallel execution instruction for executing the fusion operation instruction in parallel is generated. The fusion operation instruction is an FMA (Fused Multiply and added) operation instruction that executes a product-sum operation with one instruction.
The parallel execution instruction is a SIMD (Single Instruction Multiply Data) -FMA instruction capable of executing an FMA operation instruction in parallel for a plurality of data.
The instruction generation means converts the operation instruction determined to have no dependency into an FMA operation instruction according to the result of the determination in the code analysis means, and combines the converted FMA operation instructions. The code generator according to claim 2 or 3, which generates the SIMD-FMA instruction. The instruction generation means
When the arithmetic instruction is an addition instruction, the addition instruction is FMA by adding an instruction to multiply one operand of the addition instruction by a first dummy operand having a value that does not affect the result of addition as an immediate value. Convert to arithmetic instructions
When the operation instruction is a subtraction instruction, an instruction to multiply one operand of the subtraction instruction by a second dummy operand having a value having a value that does not affect the result of the subtraction as an immediate value is added, and the other operand of the subtraction instruction is added. By inverting the sign of, the subtraction instruction is converted into an FMA operation instruction.
When the operation instruction is a multiplication instruction, the subtraction instruction is converted into an FMA operation instruction by adding an instruction for adding a third dummy operand having a value that does not affect the result of multiplication as an immediate value.
The code generator according to claim 4. When the SIMD-FMA instruction can execute two FMA operation instructions in parallel,
The instruction generation means
Of the areas in which the register for storing the operands related to the SIMD-FMA instruction is divided into two, one of the areas contains the operands related to the addition instruction or the subtraction instruction among the operation instructions before being converted into the FMA operation instruction. Place and
The code according to claim 5, which generates data representing an operand of the SIMD-FMA instruction so as to arrange an operand related to a multiplication instruction among the operation instructions before being converted into an FMA operation instruction in the other area. Generator. By analyzing the dependency between the operation instructions having different types of instructions from one or more operation instructions included in the analysis target code which is a computer program, a combination of operation instructions having no dependency is selected .
Wherein for each combination of dependency is not operation instruction, convert the fusion operation instruction consisting operation instruction combination of addition and subtraction and multiplication, to produce a parallel execution instructions that perform pre Symbol fusion calculation instructions in parallel ,
When the parallel execution instruction is generated, the reciprocal of the divisor is obtained to convert the division to multiplication, so that the operation instruction of the combination of addition / subtraction and division having no dependency can be obtained from the combination of addition / subtraction and multiplication. A code generation method for converting into the fusion operation instruction consisting of an operation instruction. It is determined whether or not there is a dependency between the operation instructions of different types among the one or more operation instructions, and the operation instruction of a different type determined to have no dependency is used as the fusion operation instruction. The code generation method according to claim 7, further comprising converting. On the computer
Analysis that selects a combination of arithmetic instructions that have no dependency by analyzing the dependency between the arithmetic instructions of different types among one or more arithmetic instructions included in the code to be analyzed, which is a computer program. Processing and
For each combination of the dependency is no operation instruction, convert the fusion operation instruction consisting operation instruction combination of addition and subtraction and multiplication, to produce a parallel execution instructions that perform pre Symbol fusion calculation instructions in parallel Execute the instruction generation process ,
In the instruction generation process, the reciprocal of the divisor is obtained, and the division is converted into multiplication, so that the operation instruction of the combination of addition / subtraction and division having no dependency is composed of the operation instruction of the combination of addition / subtraction and multiplication. A code generation program that converts to the fusion operation instruction. The analysis process includes a process of determining whether or not there is a dependency between the operation instructions of different types among the one or more operation instructions.
The code generation program according to claim 9, wherein the instruction generation process includes a process of converting the operation instruction of a different type determined to have no dependency into the fusion operation instruction.

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