JP2017010999A - Solid-state image pickup element and manufacturing method for the same - Google Patents

Solid-state image pickup element and manufacturing method for the same Download PDF

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JP2017010999A
JP2017010999A JP2015122427A JP2015122427A JP2017010999A JP 2017010999 A JP2017010999 A JP 2017010999A JP 2015122427 A JP2015122427 A JP 2015122427A JP 2015122427 A JP2015122427 A JP 2015122427A JP 2017010999 A JP2017010999 A JP 2017010999A
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JP6619956B2 (en
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健司 菊地
Kenji Kikuchi
健司 菊地
萩原 啓
Hiroshi Hagiwara
啓 萩原
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Japan Broadcasting Corp
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Abstract

PROBLEM TO BE SOLVED: To provide an imaging element having small dark current and high sensitivity by enhancing flatness of the interface between an n-type semiconductor layer and a chalcopyrite semiconductor (hereinafter referred to as CIGS) film, etc. when a CIGS film or a crystal selenium film is formed.SOLUTION: A method of manufacturing a solid-state image pickup device in which a CIGS film 2 made of crystal selenium is formed above a signal readout circuit substrate 1 for performing signal readout processing, first forms the CIGS film 2 above a dummy film formation substrate 11 having surface flatness, bonds a front-side surface of the signal reading circuit board 1 to the upper surface of the CIGS film 2 to form a conjugate, next, removes the film-formed substrate 11 from the conjugate, and laminates at least an n-type semiconductor layer 3 and a transparent conductive film 4 in this order on the surface of the conjugate from which the film-forming substrate 11 has been removed, thereby manufacturing a solid-state image pickup device 10.SELECTED DRAWING: Figure 1

Description

本発明は、固体撮像素子およびその製造方法に関し、特に光電変換部にカルコパイライト構造の化合物半導体膜、例えば、CIGS膜(Cuと、InまたはGaまたはその両方と、SまたはSeまたはその両方と、を含む化合物半導体)や、結晶セレン(cSe)膜を備え
た固体撮像素子およびその製造方法に関する。
The present invention relates to a solid-state imaging device and a method for manufacturing the same, and particularly to a compound semiconductor film having a chalcopyrite structure in a photoelectric conversion portion, such as a CIGS film (Cu and In or Ga or both, S or Se or both, And a manufacturing method thereof.

近年、固体撮像素子の高解像度化が進み、それに伴って光電変換部の面積が縮小したことにより受光感度低下の問題が顕在化するようになってきている。これを解決するための手法として、CMOS固体撮像素子の裏面から光を照射する構造を備えた従来技術が知られている(非特許文献1を参照)。   In recent years, the resolution of solid-state imaging devices has been increased, and the area of the photoelectric conversion unit has been reduced accordingly, and the problem of a decrease in light receiving sensitivity has become apparent. As a technique for solving this problem, a conventional technique having a structure in which light is irradiated from the back surface of a CMOS solid-state imaging device is known (see Non-Patent Document 1).

しかし、同手法は光電変換部への光の到達率を高めることが目的であり、光電変換部の材料に用いられたSiの物性である量子効率や光吸収係数に基づく受光感度を超えることはできない。したがって、将来のさらなる高解像度化に伴う受光感度低下の問題を解決するためには、光電変換部に、量子効率や光吸収係数の点でSiを超える材料を用いる手法の開発が不可欠となる。   However, the purpose of this method is to increase the arrival rate of light to the photoelectric conversion unit, and it does not exceed the light receiving sensitivity based on the quantum efficiency and light absorption coefficient which are the physical properties of Si used for the material of the photoelectric conversion unit. Can not. Therefore, in order to solve the problem of reduction in light receiving sensitivity due to further higher resolution in the future, it is indispensable to develop a method using a material that exceeds Si in terms of quantum efficiency and light absorption coefficient in the photoelectric conversion unit.

こうした材料は主に有機材料(非特許文献2を参照)と無機材料に大別されるが、無機材料としては、CuInSe2とCuGaSe2の混晶であるCIGS(非特許文献3を参照)やcSe(非特
許文献4を参照)が知られている。
Such materials are mainly classified into organic materials (see Non-Patent Document 2) and inorganic materials. As inorganic materials, CIGS (see Non-Patent Document 3) which is a mixed crystal of CuInSe 2 and CuGaSe 2 is used. cSe (see Non-Patent Document 4) is known.

特に、上述したCIGSは優れた量子効率、光吸収係数および安定性を兼ね備えており、将来の固体撮像素子の光電変換部用材料として期待されている。膜厚が薄くても光を十分に吸収することができるため、印加電圧が低くても高い内部電界を与えることが可能である。このことは、膜中でのキャリア増倍動作を可能とし、さらなる高感度化をもたらす。CIGSの固体撮像素子への応用は1993年に提案され(非特許文献5を参照)、現在では車載や防犯、生体認証用途への応用に向けて実用化の研究が進められている(非特許文献6を参照)。   In particular, the CIGS described above has excellent quantum efficiency, light absorption coefficient, and stability, and is expected as a material for a photoelectric conversion part of a future solid-state imaging device. Even when the film thickness is thin, light can be sufficiently absorbed, so that a high internal electric field can be applied even when the applied voltage is low. This enables carrier multiplication operation in the film, resulting in higher sensitivity. Application of CIGS to a solid-state imaging device was proposed in 1993 (see Non-Patent Document 5), and research into practical application is currently underway for applications in vehicles, crime prevention, and biometric authentication (Non-Patent Document 5). Reference 6).

従来技術に係る、CIGSを用いた固体撮像素子およびその製造方法を図4を用いて説明する。
同撮像素子は、例えば、図4(B)に示すように、CMOSで構成された信号読出回路を付設した基板101上に、CIGS膜102を設け、さらに、n型半導体層103および透明導電膜(ITO層)104を備えてなる。
A solid-state imaging device using CIGS and a manufacturing method thereof according to the prior art will be described with reference to FIG.
For example, as shown in FIG. 4B, the image pickup element is provided with a CIGS film 102 on a substrate 101 provided with a signal readout circuit composed of CMOS, and further includes an n-type semiconductor layer 103 and a transparent conductive film. (ITO layer) 104 is provided.

また、従来技術に係る固体撮像素子の製造方法は、例えば、図4(A)、(B)の順で製造していく方法であり、信号読出回路を形成した信号読出回路基板101上に、CIGS膜102をスパッタリングや蒸着を用いて成膜し、その後、スパッタリングや蒸着を用いて、順次、n型半導体層103および透明導電膜104を成膜する。   Further, the manufacturing method of the solid-state imaging device according to the prior art is, for example, a method of manufacturing in the order of FIGS. 4A and 4B, and on the signal readout circuit substrate 101 on which the signal readout circuit is formed, The CIGS film 102 is formed by sputtering or vapor deposition, and then the n-type semiconductor layer 103 and the transparent conductive film 104 are sequentially formed by sputtering or vapor deposition.

S.Iwabuchi, Y.Maruyama, Y.Ohgishi, M.Muramatsu, N.Karasawa and T.Hirayama, ISSCC 2006 Dig.Tech.Papers, 1171 (2006).S. Iwabuchi, Y. Maruyama, Y. Ohgishi, M. Muramatsu, N. Karasawa and T. Hirayama, ISSCC 2006 Dig. Tech. Papers, 1171 (2006). 林誠之, 映情学技報, 37(40), 5 (2013).Hayashi, Masayuki, Eijiho Technical Report, 37 (40), 5 (2013). Kenji Kikuchi, S.Imura, K.Miyakawa, H.Ohtake, M.Kubota and E.Ohta, Sensors and Acutuators A:Physical, 224, 24 (2015).Kenji Kikuchi, S. Imura, K. Miyakawa, H. Ohtake, M. Kubota and E. Ohta, Sensors and Acutuators A: Physical, 224, 24 (2015). S.Imura, K.Kikuchi, K.Miyakawa, H.Ohtake and M.Kubota, Appl. Phys.Lett. 104, 242101 (2014).S. Imura, K. Kikuchi, K. Miyakawa, H. Ohtake and M. Kubota, Appl. Phys. Lett. 104, 242101 (2014). K.Tanaka, M.Kosugi, F.Ando, T.Ushiki, H.Usui and K.Sato, Jpn.J.Appl.Phys., 32(32-33), 113 (1993).K. Tanaka, M. Kosugi, F. Ando, T. Ushiki, H. Usui and K. Sato, Jpn. J. Appl. Phys., 32 (32-33), 113 (1993). O.Matsushima, K.Miyazaki, M.Takaoka, T.Maekawa, H.Sekiguchi, H.Fuchikami, M.Moriwake, H.Takasu, S.Ishizuka, K.Sakurai, A. Yamada, and S.Niki, IEDM Tech.Dig., 267 (2008).O.Matsushima, K.Miyazaki, M.Takaoka, T.Maekawa, H.Sekiguchi, H.Fuchikami, M.Moriwake, H.Takasu, S.Ishizuka, K.Sakurai, A. Yamada, and S.Niki, IEDM Tech.Dig., 267 (2008).

しかしながら、成膜されたCIGS等のカルコパイライト型半導体膜やcSe膜の表面平面性
は良好とは言えない。図2に走査型電子顕微鏡(Scanning Electron Microscope:SEM)
によるCIGS膜の表面(A)および断面(B)の観察結果を示す(図2は本発明の実施形態に係るCIGS膜の状態を表すものであるが、従来技術によるCIGS膜も同様の状態である)。この図2(A)、(B)からも明らかなように、CIGS膜102は多結晶膜であり、微小なグレインが集合しているため膜の表面における平面性は低い。
このため、CIGS膜102(やcSe膜等のp型半導体層)とn型半導体層103との界面
の平面性もまた、下地となるCIGS膜102の凹凸の影響を受けて低下し、CIGS膜102とn型半導体層103とで形成されるpn接合フォトダイオードのpn界面には大きな凹凸が存在することになる。この結果、暗電流値や感度等のフォトダイオード特性が大幅に低下していた。
なお、CIGS膜102の表面の凹凸を直接削って、CIGS膜102の表面の平面性を高めることが考えられるが、この場合には光電変換面にクラックが生じてしまい、光電変換特性が大幅に劣化してしまう。
However, the surface planarity of the chalcopyrite semiconductor film such as CIGS or the cSe film formed is not good. Figure 2 shows a scanning electron microscope (SEM).
(FIG. 2 shows the state of the CIGS film according to the embodiment of the present invention, but the CIGS film according to the prior art is also in the same state) is there). As is clear from FIGS. 2A and 2B, the CIGS film 102 is a polycrystalline film, and since fine grains are aggregated, the planarity on the film surface is low.
For this reason, the planarity of the interface between the CIGS film 102 (or a p-type semiconductor layer such as a cSe film) and the n-type semiconductor layer 103 also decreases due to the unevenness of the CIGS film 102 serving as a base, and the CIGS film Large irregularities exist at the pn interface of the pn junction photodiode formed by the n-type semiconductor layer 103 and the n-type semiconductor layer 103. As a result, the photodiode characteristics such as the dark current value and the sensitivity are greatly deteriorated.
Note that it is conceivable that the surface roughness of the CIGS film 102 is improved by directly cutting the irregularities on the surface of the CIGS film 102. In this case, however, the photoelectric conversion surface is cracked and the photoelectric conversion characteristics are greatly improved. It will deteriorate.

本発明は、これらの課題を解決するためになされたもので、CIGS等のカルコパイライト型半導体や結晶セレン(以下、CIGS膜等と称する)を成膜した際に、このCIGS膜等とn型半導体層の界面の平面性を高めて、暗電流が小さく、感度の高い撮像素子を実現し得る固体撮像素子および、その製造方法を提供することを目的とするものである。   The present invention has been made to solve these problems. When a chalcopyrite semiconductor such as CIGS or crystalline selenium (hereinafter referred to as a CIGS film or the like) is formed, the CIGS film or the like and the n-type are formed. It is an object of the present invention to provide a solid-state imaging device capable of realizing an imaging device with high darkness and high sensitivity by improving the planarity of the interface of the semiconductor layer, and a manufacturing method thereof.

以上の目的を達成するため、本発明の固体撮像素子およびその製造方法は以下のような構成とされている。
すなわち、本発明の固体撮像素子の製造方法は、
信号の読出処理を行う信号読出回路部を付設した信号読出回路基板の上方にカルコパイライト型半導体または結晶セレンからなるp型半導体層を成膜する固体撮像素子の製造方法において、
まず、表面平面性を有するダミーのベース体の上面に、前記p型半導体層を成膜し、このp型半導体層の上面に、前記信号読出回路基板の表側の面を接合して接合体を形成し、
次に、前記接合体から前記ベース体を除去し、除去された該ベース体が当接していた該接合体の面上に、少なくとも、n型の半導体層および透明導電膜をこの順に積層して固体撮像素子を作製することを特徴とするものである。
In order to achieve the above object, the solid-state imaging device and the manufacturing method thereof of the present invention are configured as follows.
That is, the manufacturing method of the solid-state imaging device of the present invention,
In a method for manufacturing a solid-state imaging device, a p-type semiconductor layer made of chalcopyrite semiconductor or crystalline selenium is formed above a signal readout circuit board provided with a signal readout circuit section for performing signal readout processing.
First, the p-type semiconductor layer is formed on the upper surface of a dummy base body having surface flatness, and the surface of the signal readout circuit board is bonded to the upper surface of the p-type semiconductor layer to form a bonded body. Forming,
Next, the base body is removed from the joined body, and at least an n-type semiconductor layer and a transparent conductive film are stacked in this order on the surface of the joined body on which the removed base body is in contact. A solid-state imaging device is manufactured.

また、前記p型半導体層を構成するカルコパイライト型半導体がCIGS(Cuと、InまたはGaまたはその両方と、SまたはSeまたはその両方と、を含む化合物半導体)により作製されることが好ましい。
また、前記ベース体を、Si、Ge、サファイヤおよびガラスの中から選択される材料により作製することが好ましい。
Moreover, it is preferable that the chalcopyrite semiconductor constituting the p-type semiconductor layer is made of CIGS (a compound semiconductor containing Cu and / or In and / or Ga and / or S and / or Se).
The base body is preferably made of a material selected from Si, Ge, sapphire, and glass.

また、前記接合体から前記ベース体を除去する工程では、該ベース体を厚み方向に削る速度が大きい第1研削段階と、該ベース体を厚み方向に削る速度が小さい第2研削段階とをこの順に行うことが好ましい。
また、前記p型半導体層の上面に、前記信号読出回路部を付設した信号読出回路基板の表側の面を接合する工程において、前処理として前記p型半導体層の上面に平面化処理を施すことが好ましい。
Further, in the step of removing the base body from the joined body, a first grinding stage in which the speed of cutting the base body in the thickness direction is high and a second grinding stage in which the speed of cutting the base body in the thickness direction is low. It is preferable to carry out in order.
Further, in the step of bonding the front side surface of the signal readout circuit substrate provided with the signal readout circuit unit to the upper surface of the p-type semiconductor layer, a planarization process is performed on the upper surface of the p-type semiconductor layer as a pretreatment. Is preferred.

さらに、上述したいずれかの固体撮像素子の製造方法により製造された固体撮像素子であって、
前記信号読出回路基板の上方に、少なくとも、カルコパイライト型半導体または結晶セレンからなるp型半導体層、n型半導体層および透明導電膜をこの順に設けてなり、
前記p型半導体層と前記n型半導体層の界面の平面度(平均面粗さ)が、5nm以下であることを特徴とするものである。
また、前記固体撮像素子をCMOSとすることができる。
Furthermore, a solid-state imaging device manufactured by any one of the above-described solid-state imaging device manufacturing method,
Above the signal readout circuit board, at least a p-type semiconductor layer made of chalcopyrite semiconductor or crystalline selenium, an n-type semiconductor layer and a transparent conductive film are provided in this order,
The flatness (average surface roughness) of the interface between the p-type semiconductor layer and the n-type semiconductor layer is 5 nm or less.
The solid-state image sensor can be a CMOS.

固体撮像素子の製造工程において、光電変換膜であるp型半導体層、特にCIGS膜等の成膜を行う際に、信号読出回路基板(特にCMOS基板)の上方にCIGS膜等を形成しようとすると、このCIGS膜等の成膜処理時の熱によって半導体基板に付設された信号回路部が損傷を受けてしまう。   When forming a p-type semiconductor layer that is a photoelectric conversion film, particularly a CIGS film, in the manufacturing process of a solid-state imaging device, when trying to form a CIGS film or the like above a signal readout circuit board (especially a CMOS substrate) The signal circuit portion attached to the semiconductor substrate is damaged by heat during the film forming process of the CIGS film or the like.

そこで、本発明の固体撮像素子の製造方法においては、膜転写技術(Layer Transfer
)を用いて、このような問題を解決している。
Therefore, in the manufacturing method of the solid-state imaging device of the present invention, the film transfer technology (Layer Transfer technology)
) Is used to solve such problems.

すなわち、この膜転写技術は、高い温度をかけることが可能なダミー基板上に、十分に高い温度をかけて高品質なCIGS膜等を成膜し、このCIGS膜等の上に本来の信号読出回路基板を接合し、この後ダミー基板を除去しているので、CIGS膜等の成膜処理時の熱によって、基板に付設された信号回路部が損傷を受けるという事態を回避することができる。   In other words, this film transfer technology forms a high-quality CIGS film on a dummy substrate that can be subjected to a high temperature by applying a sufficiently high temperature and reads the original signal on the CIGS film. Since the circuit board is bonded and the dummy board is removed thereafter, it is possible to avoid a situation in which the signal circuit portion attached to the board is damaged by the heat during the film forming process of the CIGS film or the like.

本発明の実施形態に係る固体撮像素子の製造方法を示す図である。It is a figure which shows the manufacturing method of the solid-state image sensor which concerns on embodiment of this invention. 本発明の実施形態に係る固体撮像素子のCIGS膜の表面(A)および断面(B)の状態を示す電子顕微鏡写真である。It is an electron micrograph which shows the state of the surface (A) and cross section (B) of the CIGS film | membrane of the solid-state image sensor which concerns on embodiment of this invention. 小工程a〜dの各工程において、蒸着処理における各蒸着物質の蒸発量を示すグラフである。It is a graph which shows the evaporation amount of each vapor deposition substance in a vapor deposition process in each process of small process ad. 従来技術に係る固体撮像素子の製造方法を示す図である。It is a figure which shows the manufacturing method of the solid-state image sensor concerning a prior art.

以下、本発明の実施形態に係る固体撮像素子およびその製造方法について図面を用いて説明する。
まず、実施形態に係る固体撮像素子、およびその製造方法について図1を用いて説明する。
Hereinafter, a solid-state imaging device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.
First, a solid-state imaging device according to an embodiment and a manufacturing method thereof will be described with reference to FIG.

<実施形態>
図1(D)に示すように、本実施形態にかかる固体撮像素子10は、信号読出回路部を付設した信号読出回路基板1、CIGS膜(p型半導体層)2、n型半導体層3および透明導電膜4を、この順に積層して構成されている。
<Embodiment>
As shown in FIG. 1D, the solid-state imaging device 10 according to the present embodiment includes a signal readout circuit substrate 1 provided with a signal readout circuit unit, a CIGS film (p-type semiconductor layer) 2, an n-type semiconductor layer 3, and The transparent conductive film 4 is laminated in this order.

ここで、CIGS膜2には、固体撮像素子10の裏面電極と透明電極間に電圧が印加される。
CIGSは、カルコパイライト型半導体(例えば、CuIn1-xGaxSe1-ySy等)に含まれ、
本発明において、結晶セレン(以下、cSeと称する)によって代替されても同様の効果を
得ることができる。ここで、CuIn1-xGaxSe1-ySyにおけるxは0〜1(0≦x≦1)、yは0〜1
(0≦y≦1)の範囲内における値をとり得る。
なお、以下においてCIGS膜2について記載されている部分は基本的にcSeに置き換
えることが可能であり、それによっても同様の効果が得られる。
Here, a voltage is applied to the CIGS film 2 between the back electrode and the transparent electrode of the solid-state imaging device 10.
CIGS is included in the chalcopyrite semiconductor (e.g., CuIn 1-x Ga x Se 1-y S y , etc.),
In the present invention, the same effect can be obtained even if it is replaced by crystalline selenium (hereinafter referred to as cSe). Here, x in CuIn 1-x Ga x Se 1-y S y is 0 to 1 (0 ≦ x ≦ 1), and y is 0 to 1.
It can take a value within the range of (0 ≦ y ≦ 1).
In the following description, the part described for the CIGS film 2 can be basically replaced with cSe, and the same effect can be obtained.

し型半導体層3は、透明導電膜4からCIGS膜2への正孔の注入を阻止する(抑制する)層であり、例えば、ワイドギャップのn型半導体である酸化ガリウム(Ga2O3)によ
り構成される。
The n-type semiconductor layer 3 is a layer that blocks (suppresses) the injection of holes from the transparent conductive film 4 to the CIGS film 2. For example, gallium oxide (Ga 2 O 3 ), which is a wide-gap n-type semiconductor, is used. Consists of.

透明導電膜4は、例えば、ITO(Indium Oxide:Sn 10wt%)膜で構成される。ITO膜は、スパッタリング法や蒸着法等によってn型半導体層3の上に形成される。透明導電膜4は、正極性電極として用いられる。なお、透明導電膜4としては、金からなる薄膜など他の金属薄膜を用いてもよい。   The transparent conductive film 4 is made of, for example, an ITO (Indium Oxide: Sn 10 wt%) film. The ITO film is formed on the n-type semiconductor layer 3 by sputtering or vapor deposition. The transparent conductive film 4 is used as a positive electrode. The transparent conductive film 4 may be another metal thin film such as a thin film made of gold.

次に、図1(A)〜(D)の各工程は、このような固体撮像素子10を製造するために順次、行われる工程であって、本実施形態に係る固体撮像素子の製造方法を示すものである。
この製造方法を概念的に説明すると、平面性が良好な成膜基板11上にCIGS膜2を形成し、このCIGS膜2上に信号読出回路基板1の表面を接合し、この状態で成膜基板11を剥離し、成膜基板11が当接していた、平面性が良好なCIGS膜2の表面を、n型半導体層3を形成するための下地として使用することで、暗電流を低減し得るとともに高い感度を有する固体撮像素子10を得ることができる。
Next, each step of FIGS. 1A to 1D is a step that is sequentially performed in order to manufacture such a solid-state imaging device 10. It is shown.
This manufacturing method will be conceptually described. A CIGS film 2 is formed on a film-forming substrate 11 with good flatness, and the surface of the signal readout circuit substrate 1 is bonded onto the CIGS film 2, and the film is formed in this state. The dark current can be reduced by using the surface of the CIGS film 2 with good flatness, which is peeled off from the substrate 11 and in contact with the film formation substrate 11, as a base for forming the n-type semiconductor layer 3. In addition, the solid-state imaging device 10 having high sensitivity can be obtained.

なお、CIGSやcSeの多結晶薄膜の平均面粗さRaは、例えば、数十nmであり、所定の添加
物を加えるによって平面性を向上させることができるが、それでも平均面粗さRaは、高々8 nm程度まで小さくできるにすぎない。
これに対し、平坦なガラス基板の平均面粗さRaは、例えば0.1〜0.2 nm(コーニング社
製EAGLE-XG等)であり、これを下地層として用いる本実施例の製造手法によれば、少なくとも、平均面粗さRaを5 nm以下とすることができる。さらに、平均面粗さRaを例えば1 nm以下とすることも可能と考えられる。
The average surface roughness Ra of the polycrystalline thin film of CIGS or cSe is, for example, several tens of nanometers, and the planarity can be improved by adding a predetermined additive, but the average surface roughness Ra is still It can only be as small as 8 nm.
On the other hand, the average surface roughness Ra of the flat glass substrate is, for example, 0.1 to 0.2 nm (such as EAGLE-XG manufactured by Corning), and at least according to the manufacturing method of this example using this as an underlayer, The average surface roughness Ra can be 5 nm or less. Furthermore, the average surface roughness Ra is considered to be 1 nm or less, for example.

(1)工程1
まず、ダミー基板としてSi、Ge、サファイヤ、ガラス等からなる平面性の良い成膜基板11を用意する。例えば、基板サイズが4インチ角で、厚さが400μmのものを用いることができる。最終的には除去されるダミー基板であるから、不純物の濃度や、p型/n
型のいずれか等の内容的な条件は不問とされる。
(1) Step 1
First, a film-forming substrate 11 having good flatness made of Si, Ge, sapphire, glass or the like is prepared as a dummy substrate. For example, a substrate having a substrate size of 4 inches square and a thickness of 400 μm can be used. Since the dummy substrate is finally removed, the impurity concentration and p-type / n
Content conditions such as any of the types are unquestioned.

次に、カルコパイライト型半導体に含まれるCIGS膜2は、例えば、多元蒸着法(三段階法など)やスパッタリング法等により、成膜基板11の上に形成することができ、膜厚は、例えば,0.2〜3μm程度とされる。   Next, the CIGS film 2 included in the chalcopyrite semiconductor can be formed on the film formation substrate 11 by, for example, multi-source deposition (such as a three-step method) or sputtering, and the film thickness is, for example, , About 0.2 to 3 μm.

上述した多元蒸着法でCIGS(膜厚1μm)を成膜する場合の蒸着プロセスの一例を図3
に示す。
すなわち、多元蒸着法は、Cu、In、Ga、およびSeの各材料を個別にルツボに充填して加熱して蒸発させ、基板上に成膜する手法である。
An example of the vapor deposition process when CIGS (film thickness 1μm) is formed by the multi-source vapor deposition method described above is shown in FIG.
Shown in
That is, the multi-source deposition method is a method in which each material of Cu, In, Ga, and Se is individually filled in a crucible, heated and evaporated to form a film on a substrate.

この多元蒸着法では、この工程1中の、小工程a(蒸着流のシャッタを開状態とする操作により開始される)において、基板温度を350〜400℃とし、In、GaおよびSe(ルツボ温
度は、In について880℃、Ga について1000℃、Se について210℃)の蒸着流を成膜基板
11上に12分間に亘って照射する。
次に、小工程bにおいて、基板温度を450℃に昇温させながらCuおよびSe(ルツボ温度
は、Cu について1150℃、Se について210℃)の蒸着流を8分間に亘って照射する。
次に、小工程cにおいて、In、Ga、Se(ルツボ温度は、Inについては 860℃、Ga につ
いては 975℃、Se については 210℃)の蒸着流を2分間に亘って再度照射する。
最後に、小工程d(蒸着流のシャッタを閉状態とする操作により終了する)において、基板温度を200℃以下まで降下させながらSe(ルツボ温度Se 170℃)の蒸着流を約30分間
に亘って照射する。
In this multi-source vapor deposition method, the substrate temperature is set to 350 to 400 ° C. in the small step a (initiated by opening the shutter of the vapor deposition flow) in this step 1, and In, Ga, and Se (crucible temperature) Irradiates the deposition substrate 11 with a deposition flow of 880 ° C. for In, 1000 ° C. for Ga, and 210 ° C. for Se for 12 minutes.
Next, in the small step b, the deposition temperature of Cu and Se (crucible temperature is 1150 ° C. for Cu and 210 ° C. for Se) is irradiated for 8 minutes while raising the substrate temperature to 450 ° C.
Next, in a small step c, the vapor deposition flow of In, Ga, and Se (crucible temperature is 860 ° C. for In, 975 ° C. for Ga, and 210 ° C. for Se) is irradiated again for 2 minutes.
Finally, in the small step d (finished by the operation of closing the deposition flow shutter), the deposition flow of Se (crucible temperature Se 170 ° C.) is continued for about 30 minutes while lowering the substrate temperature to 200 ° C. or less. Irradiate.

このようにして形成されたCIGS膜2においては、図1(A)に示すように、成膜基板11上に成膜された表面(図1(A)では上面)には、凹凸が生じているが、CIGS膜2の逆側の表面(図1(A)では下面:成膜基板11側の界面)は、成膜基板11の表面の良好な平面性が転写されたものであり、高い平面性を有している。   In the CIGS film 2 formed in this way, as shown in FIG. 1A, the surface formed on the film formation substrate 11 (the upper surface in FIG. 1A) is uneven. However, the surface on the opposite side of the CIGS film 2 (the lower surface in FIG. 1A: the interface on the film formation substrate 11 side) is a transfer of the good flatness of the surface of the film formation substrate 11 and is high. It has flatness.

(2)工程2
次に、図1(B)に示すように、CIGS膜2を信号読出回路を付設した信号読出回路基板1に接合する。このとき、CIGS膜2と信号読出回路基板1との接合強度を良好なものとするために、CIGS膜2の表面を平面化することが望ましい。平面化処理としては、Ar、Kr、Xeなどの希ガスを用いたプラズマ処理、イオンビーム処理、高速原子ビーム処理、バフ研磨、CMPなどを用いることができる。例えばArガスによるプラズマ処理により、上記平面
化処理を行う場合、電力をRF300W、圧力を60Pa、流量が100sccmの条件で10分以上の処理
を行うことで、表面を平面化することができる。
(2) Step 2
Next, as shown in FIG. 1B, the CIGS film 2 is bonded to a signal readout circuit board 1 provided with a signal readout circuit. At this time, it is desirable to planarize the surface of the CIGS film 2 in order to improve the bonding strength between the CIGS film 2 and the signal readout circuit board 1. As the planarization treatment, plasma treatment using a rare gas such as Ar, Kr, or Xe, ion beam treatment, high-speed atomic beam treatment, buff polishing, CMP, or the like can be used. For example, when the planarization process is performed by plasma treatment using Ar gas, the surface can be planarized by performing the process for 10 minutes or more under the conditions of power of RF300W, pressure of 60Pa, and flow rate of 100sccm.

CIGS膜2と信号読出回路基板1を接合する際には、加圧装置等を利用してCIGS膜2と信号読出回路基板1の表面同士を対向させた状態で両者が互いに接合される方向に加圧する。この際、接合強度を良好なものとするために、少なくとも1MPa,望ましくは5MPa以上の圧力をかけることが好ましい。   When the CIGS film 2 and the signal readout circuit board 1 are joined, the surfaces of the CIGS film 2 and the signal readout circuit board 1 are opposed to each other using a pressurizing device or the like. Pressurize. At this time, in order to improve the bonding strength, it is preferable to apply a pressure of at least 1 MPa, preferably 5 MPa or more.

次に、上記加圧をした状態で加熱する。加熱する温度は、少なくとも100℃以上、望ま
しくは200℃以上である。ただし、加熱により信号読出回路の性能が劣化しないように、
上記加熱温度を400℃以下に設定することが必要である。
なお、加圧している時間は、少なくとも5分以上、望ましくは60分以上である。
Next, it heats in the state which applied the said pressurization. The heating temperature is at least 100 ° C. or higher, desirably 200 ° C. or higher. However, in order not to deteriorate the performance of the signal readout circuit due to heating,
It is necessary to set the heating temperature to 400 ° C. or lower.
The pressurizing time is at least 5 minutes or more, preferably 60 minutes or more.

(3)工程3
次に、図1(C)に示すように、CIGS膜2と信号読出回路基板1を接合した接合体から、成膜基板11を除去する。この成膜基板11の除去には、この成膜基板11を構成している材料に応じて、機械的あるいは化学的な各種手法のうち、適切なものを選択して用いることができる。例えば、成膜基板11の材料としてSiを用いた場合は、ダイヤモンドホイールによる研削とXeF2によるエッチングを利用して行うことができる。
(3) Process 3
Next, as illustrated in FIG. 1C, the film formation substrate 11 is removed from the bonded body in which the CIGS film 2 and the signal readout circuit substrate 1 are bonded. For removal of the film formation substrate 11, an appropriate one of various mechanical or chemical methods can be selected and used according to the material constituting the film formation substrate 11. For example, in the case of using Si as a material of the deposition substrate 11, it can be carried out using an etching by grinding and XeF 2 with a diamond wheel.

なお、研削工程においては、接合部のダメージを緩和するために、2段階研削を行うことが好ましい。
すなわち、最初の研削工程では、例えば、ホイール回転数を3000rpm、研削速度を5μm/secとして研削を行い、成膜基板11の残りの厚みが100μm以下になったら研削を停止
する。
In the grinding process, it is preferable to perform two-stage grinding in order to reduce damage to the joint.
That is, in the first grinding process, for example, grinding is performed at a wheel rotation speed of 3000 rpm and a grinding speed of 5 μm / sec. When the remaining thickness of the film formation substrate 11 becomes 100 μm or less, the grinding is stopped.

次に、第2の研削工程では、回転数は最初の研削工程の状態を維持した状態で、研削速度を0.5μm/secまで低下させて研削を行い、成膜基板11の残りの厚みが30μm程度に
なったところで研削を停止する。このように、基板厚みがかなり薄くなったところまで研
削したところで、研削速度を落とす2段階研削を採用しているので、研削時間を短縮しつつ、研削し過ぎて接合部にダメージを与えてしまう虞を防止することができる。
Next, in the second grinding process, the number of revolutions is maintained in the state of the first grinding process, the grinding speed is reduced to 0.5 μm / sec, and the remaining thickness of the film formation substrate 11 is 30 μm. Stop grinding when the level is reached. In this way, when the substrate is ground until the substrate thickness is considerably reduced, the two-step grinding is used to reduce the grinding speed, so that the grinding time is shortened and the grinding is excessively caused to damage the joint portion. The fear can be prevented.

次に、XeF2を用いて、残った成膜基板11を完全に除去する。XeF2はCIGS膜やcSe膜に
対して極めて大きな選択比を有しているため、XeF2によりSiからなる成膜基板11を除去しても、CIGS膜2がエッチングされる状況を阻止することができる。
例えば、基板サイズが20mm角で、厚みが30μmのSi基板であれば、圧力を400Paとし
、30secのエッチングサイクルを75回繰り返すことで完全にSi基板を除去することがで
きる。
Next, the remaining film formation substrate 11 is completely removed using XeF 2 . Since XeF 2 has a very large selection ratio with respect to the CIGS film and the cSe film, the situation where the CIGS film 2 is etched even if the Si deposition substrate 11 made of XeF 2 is removed is prevented. Can do.
For example, in the case of a Si substrate having a substrate size of 20 mm square and a thickness of 30 μm, the Si substrate can be completely removed by repeating the etching cycle of 30 sec 75 times with a pressure of 400 Pa.

(4)工程4
次に、図1(D)に示すように、CIGS膜2上にn型半導体層3および透明導電膜4を形成する。
n型半導体層3は、透明導電膜4からCIGS膜2への正孔の注入を阻止する(抑制する)機能を有し、例えば、ワイドギャップn型半導体である酸化ガリウム(Ga2O3)で構成さ
れる。ターゲット材料としてはGa2O3を使用し、スパッタリング法で成膜する。成膜時の
基板温度は室温から400℃、酸素分圧PDは、0 Pa< PD <1 Pa、の各範囲とするのがよい
(4) Step 4
Next, as shown in FIG. 1D, an n-type semiconductor layer 3 and a transparent conductive film 4 are formed on the CIGS film 2.
The n-type semiconductor layer 3 has a function of preventing (suppressing) injection of holes from the transparent conductive film 4 to the CIGS film 2, for example, gallium oxide (Ga 2 O 3 ) which is a wide gap n-type semiconductor. Consists of. Ga 2 O 3 is used as a target material, and a film is formed by sputtering. The substrate temperature in film formation 400 ° C. from room temperature, the oxygen partial pressure P D, 0 Pa <preferably set to P D <1 Pa, the range of.

透明導電膜4は、例えば、ITO(Indium Oxide:Sn 10wt%)膜で構成される。透明導電
膜4は、スパッタリング法や蒸着法等によってn型半導体層3の上に形成される。
なお、透明導電膜4は、正極性電極として用いられる。また、透明導電膜4としては、金薄膜などの他の金属薄膜を用いることも可能である。
The transparent conductive film 4 is made of, for example, an ITO (Indium Oxide: Sn 10 wt%) film. The transparent conductive film 4 is formed on the n-type semiconductor layer 3 by sputtering or vapor deposition.
The transparent conductive film 4 is used as a positive electrode. Further, as the transparent conductive film 4, other metal thin films such as a gold thin film can be used.

このようにして製造された、固体撮像素子10は、暗電流が小さく、感度が高いという特性を備えたものとすることができる。   The solid-state imaging device 10 manufactured in this way can be provided with the characteristics that the dark current is small and the sensitivity is high.

<変更態様>
本発明の固体撮像素子およびその製造方法としては、上記実施形態のものに限られるものではなく、その他の種々の態様の変更が可能である。例えば、上記実施形態においては、信号読出回路基板1の上方に、CIGS膜2(またはcSe層)、n型半導体層3および透明
導電膜4を、この順に設けるようにしている。また、n型半導体層3および透明導電膜4の間や、透明導電膜4の上方に、他の層を設けてもよい。また、n型半導体層3にバッファ層を含めるようにしてもよい。
<Modification>
The solid-state imaging device and the manufacturing method thereof according to the present invention are not limited to those of the above-described embodiment, and various other modes can be changed. For example, in the above embodiment, the CIGS film 2 (or cSe layer), the n-type semiconductor layer 3 and the transparent conductive film 4 are provided in this order above the signal readout circuit board 1. Further, another layer may be provided between the n-type semiconductor layer 3 and the transparent conductive film 4 or above the transparent conductive film 4. Further, the n-type semiconductor layer 3 may include a buffer layer.

また、成膜基板11はSiによるものでなくてもよいが、エッチングによって除去できるものであることが好ましい。
また、上記成膜基板11としては、上述したようにSi、Ge、サファイヤ、ガラス等からなる平面性の良い成膜基板11を用いることができるが、この成膜基板11の上に、非晶質SiやAlなどの金属をスパッタリングなどを用いて成膜したもの全体をダミー基板として扱うようにしてもよい。ただし、非晶質SiやAlなどの金属を成膜してなるもの全体を成膜表面の平面性を良好なものとする必要がある。
この場合には、非晶質SiやAl等の金属を成膜基板11の表面に成膜してなるもの全体を、ダミー基板としてCIGS膜2(またはcSe層)から剥離することになる。
Further, the film formation substrate 11 may not be made of Si but is preferably removable by etching.
As the film formation substrate 11, as described above, the film formation substrate 11 having good flatness made of Si, Ge, sapphire, glass, or the like can be used. The whole of the film formed by sputtering or the like of metal such as high-quality Si or Al may be handled as a dummy substrate. However, it is necessary that the entire surface formed by depositing a metal such as amorphous Si or Al has a good flatness on the film formation surface.
In this case, the entire metal film such as amorphous Si or Al formed on the surface of the film formation substrate 11 is peeled off from the CIGS film 2 (or cSe layer) as a dummy substrate.

また、信号読出回路基板1に付設される電極としては、Au電極であれば酸化されない等の利点があるが、例えばIn電極等の他の電極を用いることも可能である。   The electrode attached to the signal readout circuit board 1 has an advantage that it is not oxidized if it is an Au electrode, but other electrodes such as an In electrode can also be used.

1、101 信号読出回路基板
2、102 CIGS膜(p型半導体層)
3、103 n型半導体層
4、104 透明導電膜
11 成膜基板
1, 101 Signal reading circuit board 2, 102 CIGS film (p-type semiconductor layer)
3, 103 n-type semiconductor layer 4, 104 transparent conductive film 11 deposition substrate

Claims (7)

信号の読出処理を行う信号読出回路部を付設した信号読出回路基板の上方にカルコパイライト型半導体または結晶セレンからなるp型半導体層を成膜する固体撮像素子の製造方法において、
まず、表面平面性を有するダミーのベース体の上面に、前記p型半導体層を成膜し、このp型半導体層の上面に、前記信号読出回路基板の表側の面を接合して接合体を形成し、
次に、前記接合体から前記ベース体を除去し、除去された該ベース体が当接していた該接合体の面上に、少なくとも、n型の半導体層および透明導電膜をこの順に積層して固体撮像素子を作製することを特徴とする固体撮像素子の製造方法。
In a method for manufacturing a solid-state imaging device, a p-type semiconductor layer made of chalcopyrite semiconductor or crystalline selenium is formed above a signal readout circuit board provided with a signal readout circuit section for performing signal readout processing.
First, the p-type semiconductor layer is formed on the upper surface of a dummy base body having surface flatness, and the surface of the signal readout circuit board is bonded to the upper surface of the p-type semiconductor layer to form a bonded body. Forming,
Next, the base body is removed from the joined body, and at least an n-type semiconductor layer and a transparent conductive film are stacked in this order on the surface of the joined body on which the removed base body is in contact. A method of manufacturing a solid-state image sensor, comprising producing a solid-state image sensor.
前記p型半導体層を構成するカルコパイライト型半導体がCIGS(Cuと、InまたはGaまたはその両方と、SまたはSeまたはその両方と、を含む化合物半導体)により作製されることを特徴とする請求項1記載の固体撮像素子の製造方法。   The chalcopyrite semiconductor constituting the p-type semiconductor layer is made of CIGS (a compound semiconductor containing Cu and / or In and / or Ga, and / or S and / or Se). A method for producing a solid-state imaging device according to 1. 前記ベース体を、Si、Ge、サファイヤおよびガラスの中から選択される材料により作製することを特徴とする請求項1または2に記載の固体撮像素子の製造方法。   The method of manufacturing a solid-state imaging device according to claim 1, wherein the base body is made of a material selected from Si, Ge, sapphire, and glass. 前記接合体から前記ベース体を除去する工程では、該ベース体を厚み方向に削る速度が大きい第1研削段階と、該ベース体を厚み方向に削る速度が小さい第2研削段階とをこの順に行うことを特徴とする請求項1〜3のうちいずれか1項記載の固体撮像素子の製造方法。   In the step of removing the base body from the joined body, a first grinding stage in which the base body is sharpened in the thickness direction and a second grinding stage in which the base body is shaved in the thickness direction are performed in this order. The manufacturing method of the solid-state image sensor of any one of Claims 1-3 characterized by the above-mentioned. 前記p型半導体層の上面に、前記信号読出回路基板の表側の面を接合する工程において、前処理として前記p型半導体層の上面に平面化処理を施すことを特徴とする請求項1〜4のうちいずれか1項記載の固体撮像素子の製造方法。   5. The planarization process is performed on the upper surface of the p-type semiconductor layer as a pretreatment in the step of bonding the upper surface of the signal readout circuit board to the upper surface of the p-type semiconductor layer. The manufacturing method of the solid-state image sensor of any one of these. 請求項1〜5のうちいずれか1項記載の固体撮像素子の製造方法により製造された固体撮像素子であって、
前記信号読出回路基板の上方に、少なくとも、カルコパイライト型半導体または結晶セレンからなるp型半導体層、n型半導体層および透明導電膜をこの順に設けてなり、
前記p型半導体層と前記n型半導体層の界面の平面度(平均面粗さ)が、5nm以下であることを特徴とする固体撮像素子。
A solid-state imaging device manufactured by the method for manufacturing a solid-state imaging device according to any one of claims 1 to 5,
Above the signal readout circuit board, at least a p-type semiconductor layer made of chalcopyrite semiconductor or crystalline selenium, an n-type semiconductor layer and a transparent conductive film are provided in this order,
A solid-state imaging device, wherein flatness (average surface roughness) of an interface between the p-type semiconductor layer and the n-type semiconductor layer is 5 nm or less.
CMOSからなることを特徴とする請求項6に記載の固体撮像素子。
The solid-state imaging device according to claim 6, comprising a CMOS.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010524208A (en) * 2007-03-31 2010-07-15 アドバンスド テクノロジー マテリアルズ,インコーポレイテッド Method for stripping material for wafer reclamation
JP2011119620A (en) * 2009-12-07 2011-06-16 Canon Inc Method for manufacturing solid-state imaging apparatus
JP2012124318A (en) * 2010-12-08 2012-06-28 Sony Corp Method of manufacturing solid state imaging device, solid state image sensor, and electronic apparatus
WO2013158986A2 (en) * 2012-04-19 2013-10-24 Carnegie Mellon University A metal-semiconductor-metal (msm) heterojunction diode
JP2014011417A (en) * 2012-07-03 2014-01-20 Sony Corp Solid-state imaging device and electronic apparatus
JP2014067951A (en) * 2012-09-27 2014-04-17 Seiko Epson Corp Photoelectric conversion element, photoelectric conversion element manufacturing method and electronic apparatus
JP2014209538A (en) * 2013-03-27 2014-11-06 日本放送協会 Photoelectric conversion element and method for manufacturing the same
JP2015060980A (en) * 2013-09-19 2015-03-30 日本放送協会 Method of manufacturing stacked image sensor and stacked image sensor

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010524208A (en) * 2007-03-31 2010-07-15 アドバンスド テクノロジー マテリアルズ,インコーポレイテッド Method for stripping material for wafer reclamation
JP2011119620A (en) * 2009-12-07 2011-06-16 Canon Inc Method for manufacturing solid-state imaging apparatus
JP2012124318A (en) * 2010-12-08 2012-06-28 Sony Corp Method of manufacturing solid state imaging device, solid state image sensor, and electronic apparatus
WO2013158986A2 (en) * 2012-04-19 2013-10-24 Carnegie Mellon University A metal-semiconductor-metal (msm) heterojunction diode
JP2014011417A (en) * 2012-07-03 2014-01-20 Sony Corp Solid-state imaging device and electronic apparatus
JP2014067951A (en) * 2012-09-27 2014-04-17 Seiko Epson Corp Photoelectric conversion element, photoelectric conversion element manufacturing method and electronic apparatus
JP2014209538A (en) * 2013-03-27 2014-11-06 日本放送協会 Photoelectric conversion element and method for manufacturing the same
JP2015060980A (en) * 2013-09-19 2015-03-30 日本放送協会 Method of manufacturing stacked image sensor and stacked image sensor

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
T.ANEGAWA: "Comparison of lift-off processes and rear-surface characterization of Cu(In,Ga)Se2 thin films for so", JOURNAL OF CRYSTAL GROWTH, vol. 311, JPN7019000444, 2009, pages 742 - 745, XP025947280, ISSN: 0004120008, DOI: 10.1016/j.jcrysgro.2008.09.136 *
TAKASHI MINEMOTO: "Layer Transfer of Cu(In,Ga)Se2 Thin Film and Solar Cell Fabrication", JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 49, JPN6019005600, 2010, pages 012301 - 1, ISSN: 0004120009 *

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