JP2017010297A - Clock signal generation circuit, semiconductor integrated circuit device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a high accurate oscillation frequency even when a temperature and a power source voltage vary in a clock signal generation circuit comprising an oscillator circuit using a vibrator and a CR oscillator circuit.SOLUTION: A circuit includes: a first oscillator circuit generating a first clock signal by performing oscillation operation using a vibrator; a temperature compensation circuit compensating an oscillation frequency of the first oscillator circuit on the basis of an output voltage of a temperature sensor; a count circuit counting the first clock signal and outputting a first count value; a second oscillator circuit generating a second clock signal by performing the oscillation operation using a CR; a trimming circuit switching a value of the CR according to a trimming value; a count circuit counting the second clock signal and outputting a second count value; and a frequency adjustment circuit adjusting an oscillation frequency of the second oscillator circuit by setting the trimming value on the basis of the first and second count values.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a clock signal generation circuit that generates a clock signal using an oscillation circuit. Furthermore, the present invention relates to a semiconductor integrated circuit device and an electronic device provided with such a clock signal generation circuit.

  For example, in an MCU (microcontroller unit) in which an input / output circuit necessary for controlling an electronic device and a memory for storing programs and data are built in one semiconductor integrated circuit device, a capacitor and A CR oscillation circuit that performs an oscillation operation according to a time constant of a resistor is used. The CR oscillation circuit does not require any external parts, but the oscillation frequency varies greatly depending on process variations, temperature, and power supply voltage. Therefore, the oscillation frequency of the CR oscillation circuit is controlled based on the oscillation frequency of the crystal oscillation circuit or the like.

  As a related technique, Patent Document 1 discloses that the frequency of the internal clock signal is not required even if an oscillation characteristic of the oscillation circuit occurs due to process variations without requiring an external crystal oscillator input or an external clock signal input. A semiconductor integrated circuit that can match the frequency of an external clock signal is disclosed. The semiconductor integrated circuit generates a memory circuit, an oscillation circuit that generates an internal clock signal based on control information held in the memory circuit, and control information that matches the frequency of the internal clock signal with the frequency of the external clock signal A logic circuit and an electric fuse circuit or a blown fuse circuit capable of storing control information generated by the logic circuit are used, and an internal clock signal is used for a synchronous operation of the internal circuit.

  Patent Document 2 discloses a time measuring device that can perform highly accurate time measurement at a low cost during high-speed operation using a timer provided in a computer device. The time measuring apparatus includes a counting unit for counting the number of clocks of the first basic clock signal, and a counting unit for a predetermined period of the second basic clock signal having a lower oscillation frequency and higher oscillation accuracy than the first basic clock signal. Counting using the number of clocks of the first basic clock signal counted by the above and the number of reference clocks previously counted as the number of clocks of the first basic clock signal corresponding to the predetermined period of the second basic clock signal Deriving means for deriving a physical quantity indicating a variation amount of the clock number counted by the means with respect to the reference clock number, and the number of clocks of the first basic clock signal corresponding to the time to be measured according to the physical quantity derived by the deriving means And a correction period in which the number of clocks of the first basic clock signal counted by the counting means is corrected by the correcting means. When it reaches the count value, and output means for outputting the time information indicating that reached the correct expected measurement value.

Japanese Patent Laying-Open No. 2006-39830 (Abstract, FIG. 2) JP 2013-117785 A (paragraphs 0030-0031, FIG. 1)

  A CR oscillation circuit that does not use a resonator such as a crystal resonator is advantageous in reducing the circuit area, current consumption, or the number of external connection terminals in a semiconductor integrated circuit device such as an MCU. Even if the frequency is adjusted by trimming, the oscillation frequency varies greatly depending on the temperature and the power supply voltage. Therefore, it is effective to adjust the oscillation frequency of the CR oscillation circuit based on the frequency of the external clock signal by using the technique disclosed in Patent Document 1 or Patent Document 2.

  On the other hand, an electronic device having a timekeeping function includes an oscillation circuit that performs accurate oscillation at a relatively low frequency using a vibrator such as a crystal vibrator in order to measure time. It is possible to adjust the oscillation frequency of the CR oscillation circuit based on the oscillation frequency of the circuit.

  However, even in an oscillation circuit using a vibrator, the oscillation frequency varies depending on the temperature. Accordingly, the oscillation frequency of the CR oscillation circuit also varies depending on the temperature. Accordingly, a first object of the present invention is to realize a highly accurate oscillation frequency even when the temperature or power supply voltage changes in a clock signal generation circuit including an oscillation circuit using a vibrator and a CR oscillation circuit. . A second object of the present invention is to provide a semiconductor integrated circuit device or an electronic device provided with such a clock signal generation circuit.

  In order to solve at least a part of the above-described problems, a clock signal generation circuit according to a first aspect of the present invention generates a first clock signal by performing an oscillation operation using a vibrator. A circuit, a temperature sensor that detects the temperature and generates an output voltage, a temperature compensation circuit that compensates the oscillation frequency of the first oscillation circuit based on the output voltage of the temperature sensor, and in synchronization with the first clock signal A first count circuit that outputs a first count value by performing a count operation; a second oscillation circuit that generates a second clock signal by performing an oscillation operation using a capacitor and a resistor; and a trimming value And a trimming circuit that switches the value of the capacitor or resistor of the second oscillation circuit according to the second count signal by performing a count operation in synchronization with the second clock signal. It comprises a second counting circuit which outputs a value, by setting the trimming value based on the first and second count values, and a frequency adjusting circuit for adjusting the oscillation frequency of the second oscillation circuit.

  According to the first aspect of the present invention, the oscillation frequency of the second oscillation circuit is adjusted on the basis of the oscillation frequency of the first oscillation circuit that has been temperature compensated. An accurate oscillation frequency can be realized.

  In the clock signal generation circuit according to the second aspect of the present invention, the frequency adjustment circuit activates the normal end signal when the oscillation frequency of the second oscillation circuit is within a predetermined range. As a result, other circuit blocks (for example, the communication unit) to which the second clock signal generated by the second oscillation circuit is supplied can be used after the frequency of the second clock signal falls within a predetermined range. The operation can be started promptly.

  For example, the frequency adjustment circuit sets a frequency measurement period for measuring the oscillation frequency of the second oscillation circuit based on the second count value, and the first count value is within a predetermined range at the end of the frequency measurement period. If it is, the normal end signal is activated. Accordingly, the normal end signal can be generated by effectively using the first count circuit and the second count circuit.

  In the second aspect of the present invention, the frequency adjustment circuit holds the trimming value when the normal end signal is activated, and after the predetermined period has elapsed after the normal end signal is activated, A new trimming value may be set based on the first and second count values respectively output from the second count circuit. Thereby, the oscillation frequency of the second oscillation circuit is adjusted intermittently, so that power consumption in the clock signal generation circuit can be reduced.

  Further, the frequency adjustment circuit holds the trimming value when the normal end signal is activated, and when the output voltage of the temperature sensor changes more than a predetermined value after the normal end signal is activated, A new trimming value may be set based on the first and second count values output from the first and second count circuits, respectively. Thereby, even when the adjustment of the oscillation frequency of the second oscillation circuit is performed intermittently, it is possible to cope with a rapid change in temperature.

  Further, the frequency adjustment circuit holds the trimming value when the normal end signal is activated, and the first and second frequency adjustment circuits when the power supply voltage changes more than a predetermined value after the normal end signal is activated. A new trimming value may be set based on the first and second count values respectively output from the two count circuits. Thereby, even when the oscillation frequency of the second oscillation circuit is adjusted intermittently, it is possible to cope with a sudden change in the power supply voltage.

  A semiconductor integrated circuit device according to one aspect of the present invention includes any one of the clock signal generation circuits described above. As a result, the clock signal generation circuit can be reduced in size. An electronic device according to one aspect of the present invention communicates with the outside using the clock signal generation circuit according to the second aspect of the present invention and the second clock signal generated by the second oscillation circuit. Control the frequency adjustment circuit to adjust the oscillation frequency of the second oscillation circuit when receiving a transmission command from the operation unit, the operation unit used to operate the electronic device, and the operation unit, And a control unit that controls the communication unit to perform a transmission operation after the end signal is activated. Thus, it is possible to provide an electronic device that uses a CR oscillation circuit to generate a communication clock signal and quickly starts a transmission operation after the frequency of the communication clock signal falls within a predetermined range. it can.

The figure which shows the structural example of the clock signal generation circuit which concerns on one Embodiment of this invention. FIG. 2 is a circuit diagram showing a configuration example of a first oscillation circuit shown in FIG. 1. The figure which shows the structural example of the temperature sensor and temperature compensation circuit which are shown in FIG. The figure which shows the example of the temperature compensation information used in the temperature compensation circuit shown in FIG. FIG. 3 is a diagram showing temperature characteristics of the first oscillation circuit shown in FIG. 2. FIG. 3 is a diagram showing a first configuration example of a second oscillation circuit and a trimming circuit shown in FIG. 1. FIG. 4 is a diagram showing a second configuration example of the second oscillation circuit and the trimming circuit shown in FIG. 1. The block diagram which shows the 1st structural example of the periphery of the frequency adjustment circuit shown in FIG. 9 is a timing chart for explaining the operation of the frequency adjustment circuit shown in FIG. 8. The block diagram which shows the 2nd structural example of the periphery of the frequency adjustment circuit shown in FIG. 1 is a block diagram illustrating a configuration example of an electronic device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and the overlapping description is abbreviate | omitted.
FIG. 1 is a block diagram showing a configuration example of a clock signal generation circuit according to an embodiment of the present invention. As shown in FIG. 1, the clock signal generation circuit includes a first oscillation circuit 10, a temperature sensor 20, a temperature compensation circuit 30, a second oscillation circuit 40, a trimming circuit 50, and a first count. The circuit 60, the 2nd count circuit 70, the frequency adjustment circuit 80, the power supply voltage detection circuit 90, and vibrator | oscillators, such as crystal oscillator XTAL, are included.

  Here, the second oscillation circuit 40 to the power supply voltage detection circuit 90 may be incorporated in a semiconductor integrated circuit device such as an MCU (microcontroller unit). Alternatively, the first oscillation circuit 10 to the power supply voltage detection circuit 90 may be built in the semiconductor integrated circuit device. As a result, the clock signal generation circuit can be reduced in size. In that case, the vibrator may be built in the semiconductor integrated circuit device or may be an external component of the semiconductor integrated circuit device.

<First oscillation circuit>
The first oscillation circuit 10 generates a clock signal CK1 by performing an oscillation operation using a vibrator such as a crystal vibrator, a ceramic vibrator, or a SAW (Surface Acoustic Wave) resonator. . The oscillation frequency of the first oscillation circuit 10 is controlled using, for example, a variable capacitance element. The reference oscillation frequency f1 of the first oscillation circuit 10 is set to 32 kHz, for example.

  FIG. 2 is a circuit diagram showing a configuration example of the first oscillation circuit shown in FIG. In this example, the first oscillation circuit 10 performs an oscillation operation using a crystal resonator XTAL as a vibrator, and the oscillation frequency is controlled using a variable capacitance diode 11 as a variable capacitance element. The first oscillation circuit 10 and the temperature sensor 20 and the temperature compensation circuit 30 shown in FIG. 1 constitute a temperature compensated crystal oscillator (TCXO) capable of temperature compensation of the oscillation frequency.

  As shown in FIG. 2, the first oscillation circuit 10 includes a variable capacitance diode 11, resistors 12 and 13, capacitors 14 and 15, and an inverter 16. The inverter 16 has an input terminal and an output terminal connected to both ends of the crystal resonator XTAL via connection terminals S1 and S2, respectively, and functions as an amplifying element. The inverter 16 operates by being supplied with the power supply potential VDD on the high potential side and the power supply potential VSS on the low potential side (in this embodiment, the ground potential is 0 V), and inverts and amplifies the signal input to the input terminal. The amplified signal is output from the output terminal.

  A capacitor 14 and the variable capacitance diode 11 are connected in series between the input terminal of the inverter 16 and the wiring of the power supply potential VSS. The cathode of the variable capacitance diode 11 is connected to the control terminal via the resistor 12, and the anode of the variable capacitance diode 11 is connected to the wiring of the power supply potential VSS.

  A capacitor 15 is connected between the output terminal of the inverter 16 and the wiring of the power supply potential VSS. A resistor (feedback resistor) 13 is connected between the input terminal and the output terminal of the inverter 16, and the output terminal of the inverter 16 is connected to the output terminal of the first oscillation circuit 10.

  The capacitance value of the variable capacitance diode 11 changes according to the control voltage VC applied to the control terminal. The first oscillation circuit 10 oscillates at an oscillation frequency corresponding to the capacitance value of the variable capacitance diode 11. The clock signal CK1 generated by the oscillation operation of the first oscillation circuit 10 is output from the output terminal of the first oscillation circuit 10 to the outside.

<Temperature compensation of first oscillation circuit>
FIG. 3 is a diagram illustrating a configuration example of the temperature sensor and the temperature compensation circuit illustrated in FIG. The temperature sensor 20 is disposed in the vicinity of the first oscillation circuit 10 (FIG. 2), detects the temperature, and generates an output voltage. As shown in FIG. 3, the temperature sensor 20 includes resistors 21 to 23, PNP transistors 24 and 25, and an operational amplifier 26.

  The operational amplifier 26 has a non-inverting input terminal, an inverting input terminal, and an output terminal, and operates by being supplied with the power supply potential VDD and the power supply potential VSS. The resistor 21 is connected between the output terminal of the operational amplifier 26 and the emitter of the transistor 24. The resistors 22 and 23 are connected in series between the output terminal of the operational amplifier 26 and the emitter of the transistor 25. The collectors and bases of the transistors 24 and 25 are connected to the wiring of the power supply potential VSS. Accordingly, each of the transistors 24 and 25 is equivalent to a PN junction diode.

  A current flows from the output terminal of the operational amplifier 26 to the transistor 24 via the resistor 21, and the voltage between the emitter and the collector of the transistor 24 becomes equal to the forward voltage of the PN junction diode. Further, current flows from the output terminal of the operational amplifier 26 to the transistor 25 through the resistors 22 and 23, and the voltage between the emitter and the collector of the transistor 25 becomes equal to the forward voltage of the PN junction diode. Due to the temperature characteristics of the forward voltage of the PN junction diode, the voltage between the emitter and collector of the transistors 24 and 25 varies depending on the temperature.

  The non-inverting input terminal of the operational amplifier 26 is connected to the emitter of the transistor 24, and the inverting input terminal is connected to a connection point between the resistor 22 and the resistor 23. The operational amplifier 26 amplifies the difference between the emitter potential of the transistor 24 and the potential obtained by dividing the emitter potential of the transistor 25 by the resistor 22 and the resistor 23, thereby generating an output voltage that changes depending on the temperature.

  The temperature compensation circuit 30 includes an A / D conversion circuit 31, a data conversion circuit 32, a storage unit 33, and a D / A conversion circuit 34, and the first oscillation circuit 10 based on the output voltage of the temperature sensor 20. The oscillation frequency of is compensated.

  The A / D conversion circuit 31 converts the output voltage of the temperature sensor 20 into a digital value (temperature detection data) DT. The data conversion circuit 32 is constituted by, for example, a logic circuit including a combinational circuit or a sequential circuit. Based on the temperature compensation information stored in the storage unit 33, the data conversion circuit 32 converts the temperature detection data DT into the first oscillation circuit 10 (FIG. The oscillation frequency of 2) is converted into temperature compensation data DF for temperature compensation.

  FIG. 4 is a diagram showing an example of temperature compensation information used in the temperature compensation circuit shown in FIG. In this example, the temperature compensation information includes temperature detection data DT1, DT2,..., DTL representing the output voltage value of the temperature sensor 20, and a control voltage value for temperature compensation of the oscillation frequency of the first oscillation circuit 10. , DFL, which defines the correspondence relationship with the temperature compensation data DF1, DF2,.

  For example, in the inspection process of the first oscillation circuit 10, the output voltage of the temperature sensor 20 and the oscillation frequency of the first oscillation circuit 10 are measured under a plurality of temperatures, and the oscillation frequency of the first oscillation circuit 10 and the reference The temperature compensation information is created by calculating the temperature compensation data DF necessary for correcting the error from the oscillation frequency f1. The created temperature compensation information is stored in the storage unit 33 configured by a nonvolatile memory or the like.

  When the clock signal generation circuit is incorporated and used in an electronic device, the data conversion circuit 32 converts the temperature detection data DT into temperature compensation data DF by referring to the temperature compensation information stored in the storage unit 33. To do. When the output voltage value represented by the temperature detection data DT is a voltage value not defined in the temperature compensation information, the data conversion circuit 32 calculates the temperature compensation data DF by interpolation calculation. As the data amount of the temperature compensation information is larger, the accuracy of the oscillation frequency of the first oscillation circuit 10 is improved. However, since the circuit area and cost are also increased, the minimum amount of data that satisfies the required accuracy of the oscillation frequency is required. The temperature compensation information may be stored in the storage unit 33.

  The D / A conversion circuit 34 converts the temperature compensation data DF output from the data conversion circuit 32 into an analog signal, that is, a control voltage VC for temperature compensating the oscillation frequency of the first oscillation circuit 10. The control voltage VC output from the D / A conversion circuit 34 is applied to the control terminal of the first oscillation circuit 10 shown in FIG. 2, and the capacitance value of the variable capacitance diode 11 is controlled. Thus, temperature compensation is performed so that the oscillation frequency of the first oscillation circuit 10 approaches the reference oscillation frequency f1.

  FIG. 5 is a diagram showing temperature characteristics of the first oscillation circuit shown in FIG. In FIG. 5, the horizontal axis represents the temperature (° C.), and the vertical axis represents the frequency deviation (ppm) with respect to the oscillation frequency at the representative temperature Ti (for example, + 25 ° C.).

  The broken line shown in FIG. 5 indicates the temperature characteristic of the first oscillation circuit 10 when temperature compensation is not performed. Since the control voltage VC is constant, the oscillation frequency of the first oscillation circuit 10 changes according to the temperature characteristics of the crystal unit XTAL. Even if the control voltage VC is adjusted so that the oscillation frequency coincides with the reference oscillation frequency f1 at the representative temperature Ti, when the temperature reaches + 70 ° C., the oscillation frequency deviation exceeds −70 ppm.

  On the other hand, the solid line shown in FIG. 5 shows the temperature characteristics of the first oscillation circuit 10 when temperature compensation is performed. The temperature compensation circuit 30 compensates the oscillation frequency of the first oscillation circuit 10 based on the output voltage of the temperature sensor 20, so that the oscillation frequency of the first oscillation circuit 10 can be set in the temperature range of −20 ° C. to + 70 ° C. The deviation can be kept within ± 5 ppm, and the accuracy of the oscillation frequency is greatly improved. Further, the oscillation frequency of the first oscillation circuit 10 is not easily affected by fluctuations in the power supply voltage.

<Second oscillation circuit>
Referring to FIG. 1 again, the second oscillation circuit 40 generates a clock signal CK2 by performing an oscillation operation using a capacitor and a resistor. When the second oscillation circuit 40 is built in the semiconductor integrated circuit device, the capacitor and the resistor can also be built in the semiconductor integrated circuit device. The trimming circuit 50 switches the value of the capacitor or resistance of the second oscillation circuit 40 according to the trimming value supplied from the frequency adjustment circuit 80. The reference oscillation frequency f2 of the second oscillation circuit 40 is higher than the reference oscillation frequency f1 of the first oscillation circuit 10, and is set to 1 MHz to 8 MHz, for example.

  FIG. 6 is a diagram illustrating a first configuration example of the second oscillation circuit and the trimming circuit illustrated in FIG. 1. In this example, the second oscillation circuit 40 is a ring oscillator including a NAND circuit 41, a plurality of inverters 42 to 44, capacitors C0, C1, C2,..., And a resistor R0. The trimming circuit 50 includes a plurality of switch circuits SW1, SW2,... That switch the value of the capacitor of the second oscillation circuit 40, and a switch control circuit 51 that controls these switch circuits.

  Specifically, the output terminal of the NAND circuit 41 is connected to the input terminal of the inverter 42, the output terminal of the inverter 42 is connected to the input terminal of the inverter 43, and the output terminal of the inverter 43 is connected to the input terminal of the inverter 44. ing. The output terminal of the inverter 44 is connected to the output terminal of the second oscillation circuit 40. A resistor R 0 is connected between the first input terminal of the NAND circuit 41 and the output terminal of the inverter 43. The second input terminal of the NAND circuit 41 is supplied with an enable signal EN for controlling on / off of the oscillation operation from a control unit or the like that controls the system.

  A capacitor C0 is connected between the first input terminal of the NAND circuit 41 and the output terminal of the inverter 42, and the capacitors C1, C2,... Are connected via the switch circuits SW1, SW2,. It is connected. The switch control circuit 51 is composed of, for example, a logic circuit including a combinational circuit, and turns on the switch circuits SW1, SW2,... According to the trimming value supplied from the frequency adjustment circuit 80 shown in FIG. Control to off state.

  The second oscillation circuit 40 includes a capacitor electrically connected between the first input terminal of the NAND circuit 41 and the output terminal of the inverter 42 when the enable signal EN is activated to a high level. The oscillation operation is performed at an oscillation frequency determined by the capacitance value and the resistance value of the resistor R0. The clock signal CK2 generated by the oscillation operation of the second oscillation circuit 40 is output to the outside from the output terminal.

  FIG. 7 is a diagram illustrating a second configuration example of the second oscillation circuit and the trimming circuit illustrated in FIG. 1. In this example, the second oscillation circuit 40 is a ring oscillator including a NAND circuit 41, a plurality of inverters 42 to 44, a capacitor C0, and resistors R0, R1, R2,. The trimming circuit 50 includes a plurality of switch circuits SW1, SW2,... That switch the resistance value of the second oscillation circuit 40, and a switch control circuit 51 that controls these switch circuits.

  Specifically, the output terminal of the NAND circuit 41 is connected to the input terminal of the inverter 42, the output terminal of the inverter 42 is connected to the input terminal of the inverter 43, and the output terminal of the inverter 43 is connected to the input terminal of the inverter 44. ing. The output terminal of the inverter 44 is connected to the output terminal of the second oscillation circuit 40. A capacitor C 0 is connected between the first input terminal of the NAND circuit 41 and the output terminal of the inverter 42. The second input terminal of the NAND circuit 41 is supplied with an enable signal EN for controlling on / off of the oscillation operation from a control unit or the like that controls the system.

  A resistor R0 is connected between the first input terminal of the NAND circuit 41 and the output terminal of the inverter 43, and the resistors R1, R2,... Are connected via the switch circuits SW1, SW2,. It is connected. The switch control circuit 51 is composed of, for example, a logic circuit including a combinational circuit, and turns on the switch circuits SW1, SW2,... According to the trimming value supplied from the frequency adjustment circuit 80 shown in FIG. Control to off state.

  The second oscillation circuit 40 is electrically connected between the capacitance value of the capacitor C0 and the first input terminal of the NAND circuit 41 and the output terminal of the inverter 43 when the enable signal EN is activated to a high level. Oscillates at an oscillating frequency determined by the resistance value of the connected resistor. The clock signal CK2 generated by the oscillation operation of the second oscillation circuit 40 is output to the outside from the output terminal.

<Frequency adjustment of second oscillation circuit>
Referring to FIG. 1 again, the first count circuit 60 outputs a first count value by performing a count operation in synchronization with the clock signal CK1 output from the first oscillation circuit 10. The second count circuit 70 outputs a second count value by performing a count operation in synchronization with the clock signal CK2 output from the second oscillation circuit 40.

  The frequency adjustment circuit 80 sets the trimming value based on the first count value output from the first count circuit 60 and the second count value output from the second count circuit 70, thereby The oscillation frequency of the second oscillation circuit 40 is adjusted.

  FIG. 8 is a block diagram showing a first configuration example around the frequency adjustment circuit shown in FIG. As shown in FIG. 8, the frequency adjustment circuit 80 includes comparison circuits 81 and 82, storage units 83 and 84, and a trimming value setting circuit 85. The trimming value setting circuit 85 is constituted by a logic circuit including a combinational circuit or a sequential circuit, for example.

  The first count circuit 60 resets the count value to zero when the reset signal RS1 supplied from the trimming value setting circuit 85 is activated. The second count circuit 70 resets the count value to zero when the reset signal RS2 supplied from the trimming value setting circuit 85 is activated.

  When the reset signals RS1 and RS2 are deactivated, the first count circuit 60 and the second count circuit 70 simultaneously start the count operation. The first count circuit 60 counts the number of pulses included in the clock signal CK1 and increments the first count value by one. The second count circuit 70 counts the number of pulses included in the clock signal CK2 and increments the second count value by one.

  The storage unit 83 includes, for example, a nonvolatile memory or a register, and stores setting values A1 and B1 related to the first count circuit 60 and setting values A2 and B2 related to the second count circuit 70. The set value A2 represents the count value of the second count circuit 70 used for setting the frequency measurement period for measuring the oscillation frequency of the second oscillation circuit 40 shown in FIG. The set value B2 represents the count value of the second count circuit 70 used for setting a count period for performing a series of count operations. The set values A1 and B1 are the first counts corresponding to the set values A2 and B2 when the first oscillation circuit 10 and the second oscillation circuit 40 shown in FIG. 1 oscillate at the reference oscillation frequencies f1 and f2, respectively. The count value of the circuit 60 is represented.

  The comparison circuit 81 compares the first count value output from the first count circuit 60 with the set values A1 and B1, and outputs comparison result signals CA1 and CB1 representing the respective comparison results. Further, the comparison circuit 82 compares the second count value output from the second count circuit 70 with the set values A2 and B2, thereby outputting comparison result signals CA2 and CB2 representing the respective comparison results. .

  The storage unit 84 is configured by, for example, a nonvolatile memory or a register, and stores a trimming value. Immediately after the power is turned on, the initial value of the trimming value is stored in the storage unit 84. The trimming value setting circuit 85 sets a trimming value in each frequency measurement period, adds the set trimming value to the previous trimming value, calculates a new trimming value, and stores it in the storage unit 84.

  FIG. 9 is a timing chart for explaining an operation example of the frequency adjustment circuit shown in FIG. As shown in FIG. 9, the first count value output from the first count circuit 60 is incremented by one from zero. The second count value output from the second count circuit 70 is also incremented by 1 from zero. When the second count value reaches the count value n equal to the set value A2, the first count value is the count value m.

  Here, when the count value m is equal to the set value A1, the oscillation frequency of the second oscillation circuit 40 is substantially equal to the reference oscillation frequency f2. When the count value m is larger than the set value A1, the oscillation frequency of the second oscillation circuit 40 is lower than the reference oscillation frequency f2, and when the count value m is smaller than the set value A1. The oscillation frequency of the second oscillation circuit 40 is higher than the reference oscillation frequency f2.

  When the comparison result signal CA2 indicating that the second count value is equal to the set value A2 is input to the trimming value setting circuit 85, the comparison result signal obtained by comparing the first count value with the set value A1. CA1 is held and a trimming value is set based on the comparison result signal CA1. For example, the trimming value setting circuit 85 sets the trimming value to “0” when the first count value is equal to the setting value A1. The trimming value setting circuit 85 sets the trimming value to “+1” when the first count value is larger than the set value A1, and sets the trimming value when the first count value is smaller than the set value A1. Set to “−1”.

  The trimming value setting circuit 85 calculates a new trimming value by adding the set trimming value to the previous trimming value stored in the storage unit 84 and stores it in the storage unit 84. The trimming circuit 50 shown in FIG. 1 switches the value of the capacitor or resistance of the second oscillation circuit 40 in accordance with the latest trimming value stored in the storage unit 84. Thereby, the oscillation frequency of the second oscillation circuit 40 is brought close to the reference oscillation frequency f2.

  Thereafter, the first count value reaches the count value M, and the second count value reaches the count value N equal to the set value B2. When the comparison result signal CB2 indicating that the second count value is larger than the set value B2 is input, the trimming value setting circuit 85 immediately activates the reset signals RS1 and RS2. Thereby, the first count circuit 60 and the second count circuit 70 are reset, and the first and second count values become zero.

  By repeating the above operation, the oscillation frequency of the second oscillation circuit 40 is measured and adjusted in a plurality of frequency measurement periods. According to the present embodiment, the oscillation frequency of the second oscillation circuit 40 is adjusted with reference to the oscillation frequency of the first oscillation circuit 10 that has been temperature compensated. An oscillation frequency can be realized.

  The frequency adjustment circuit 80 may activate the normal end signal (flag) F1 when the oscillation frequency of the second oscillation circuit 40 is within a predetermined range. Accordingly, other circuit blocks (for example, the communication unit) to which the clock signal CK2 generated by the second oscillation circuit 40 is supplied immediately after the frequency of the clock signal CK2 falls within a predetermined range. The operation can be started.

  For example, the frequency adjustment circuit 80 sets a frequency measurement period in which the oscillation frequency of the second count circuit 70 is measured based on the second count value output from the second count circuit 70. The frequency adjustment circuit 80 is normal when the first count value output from the first count circuit 60 is within a predetermined range (for example, within ± 0 count or ± 1 count) at the end of the frequency measurement period. The end signal F1 may be activated to “1”. Accordingly, the normal count signal F1 can be generated by effectively using the first count circuit 60 and the second count circuit 70.

  For this purpose, for example, the comparison circuit 82 outputs a comparison result signal CA1 representing the difference between the first count value and the set value A1. When the comparison result signal CA2 indicating that the second count value is equal to the set value A2 is input, the trimming value setting circuit 85 holds the comparison result signal CA1 and based on the comparison result signal CA1, the normal end signal F1 is generated.

  The trimming value setting circuit 85 receives the comparison result signal CB1 indicating that the first count value is larger than the set value B1 due to malfunction of one of the circuits, or the second count value. When the comparison result signal CB2 indicating that is greater than the set value B2 is input, the abnormal end signal (flag) F2 may be activated to “1” to stop the operation. As a result, a control unit or the like that controls the system can grasp that an abnormality has occurred in the clock signal generation circuit and perform a system reset or the like.

  The adjustment of the oscillation frequency of the second oscillation circuit 40 (FIG. 1) may be performed intermittently. For example, the frequency adjustment circuit 80 holds the trimming value when the normal end signal F1 is activated, and keeps at least the second count circuit 70 in the reset state. After a lapse of a predetermined period from the activation of the normal end signal F1, the frequency adjustment circuit 80 operates the first count circuit 60 and the second count circuit 70, and the first count circuit 60 and the second count circuit 70 are activated. A new trimming value is set based on the first and second count values output from the second count circuit 70, respectively. As a result, the oscillation frequency of the second oscillation circuit 40 is adjusted intermittently (for example, once every 10 seconds), so that power consumption in the clock signal generation circuit can be reduced.

  For this purpose, for example, the trimming value setting circuit 85 once resets the first count circuit 60 when the normal end signal F1 is activated, and then the first count output from the first count circuit 60. Timekeeping is performed based on the value. When a predetermined period elapses after the activation of the normal end signal F1, the trimming value setting circuit 85 temporarily resets the first count circuit 60 and then measures the oscillation frequency of the second oscillation circuit 40. In addition, the reset of the first count circuit 60 and the second count circuit 70 is released to start the count operation.

  Further, the adjustment of the oscillation frequency of the second oscillation circuit 40 (FIG. 1) may be performed according to a change in temperature. For example, the frequency adjustment circuit 80 holds the trimming value when the normal end signal F1 is activated, and keeps at least the second count circuit 70 in the reset state. When the output voltage of the temperature sensor 20 changes more than a predetermined value after the activation of the normal end signal F1, the frequency adjustment circuit 80 operates the first count circuit 60 and the second count circuit 70. Thus, a new trimming value is set based on the first and second count values output from the first count circuit 60 and the second count circuit 70, respectively. Thereby, even when the adjustment of the oscillation frequency of the second oscillation circuit 40 is performed intermittently, it is possible to cope with a rapid change in temperature.

  For this purpose, for example, the temperature compensation circuit 30 shown in FIG. 3 outputs the temperature detection data DT obtained based on the output voltage of the temperature sensor 20 to the frequency adjustment circuit 80. In the frequency adjustment circuit 80, the trimming value setting circuit 85 determines whether or not a change in the value of the temperature detection data DT after the normal end signal F1 is activated is greater than a predetermined value. When the change in the value of the temperature detection data DT is larger than a predetermined value, the trimming value setting circuit 85 uses the first count circuit 60 and the second count circuit 60 to measure the oscillation frequency of the second oscillation circuit 40. The reset of the count circuit 70 is released and the count operation is started.

  Further, the adjustment of the oscillation frequency of the second oscillation circuit 40 (FIG. 1) may be performed according to a change in the power supply voltage. For example, the frequency adjustment circuit 80 holds the trimming value when the normal end signal F1 is activated, and keeps at least the second count circuit 70 in the reset state. When the power supply voltage changes more than a predetermined value after the normal end signal F1 is activated, the frequency adjustment circuit 80 operates the first count circuit 60 and the second count circuit 70 to operate the first count circuit 60. A new trimming value is set based on the first and second count values output from the count circuit 60 and the second count circuit 70, respectively. Thereby, even when the oscillation frequency of the second oscillation circuit 40 is adjusted intermittently, it is possible to cope with a sudden change in the power supply voltage.

  For this purpose, for example, the power supply voltage detection circuit 90 shown in FIG. 1 detects the power supply voltage supplied to the clock signal generation circuit, and supplies the power supply voltage detection data DV representing the value of the detected power supply voltage to the frequency adjustment circuit 80. Output. In the frequency adjustment circuit 80, the trimming value setting circuit 85 determines whether or not the change in the value of the power supply voltage detection data DV after the normal end signal F1 is activated is greater than a predetermined value. When the change in the value of the power supply voltage detection data DV is larger than a predetermined value, the trimming value setting circuit 85 uses the first count circuit 60 and the second count circuit 60 to measure the oscillation frequency of the second oscillation circuit 40. The count circuit 70 is reset and the count operation is started.

  FIG. 10 is a block diagram showing a second configuration example around the frequency adjustment circuit shown in FIG. In the second configuration example, the second count circuit 70 divides the clock signal CK2 generated by the second oscillation circuit 40 shown in FIG. 1 and outputs a divided clock signal 71. Contains.

  The frequency dividing ratio of the frequency dividing circuit 71 is set so that the frequency of the divided clock signal is substantially equal to the reference oscillation frequency f1 when the oscillation frequency of the second oscillation circuit 40 is the reference oscillation frequency f2. Therefore, the frequency adjustment circuit 80 adjusts the oscillation frequency of the second oscillation circuit 40 so that the frequency of the divided clock signal approaches the reference oscillation frequency f1.

  When the reset signals RS1 and RS2 are deactivated, the first count circuit 60 and the second count circuit 70 simultaneously start the count operation. The first count circuit 60 counts the number of pulses included in the clock signal CK1 and increments the first count value by one. The second count circuit 70 counts the number of pulses included in the divided clock signal and increments the second count value by one.

  The storage unit 83 stores, for example, setting values A and B related to the first count circuit 60. The set value A represents the count value of the first count circuit 60 used to set the frequency measurement period for measuring the oscillation frequency of the second oscillation circuit 40 shown in FIG. The set value B represents the count value of the first count circuit 60 used for setting a count period for performing a series of count operations.

  The comparison circuit 81 compares the first count value output from the first count circuit 60 with the set values A and B, and outputs comparison result signals CA and CB representing the respective comparison results. In addition, the comparison circuit 82 compares the first count value output from the first count circuit 60 with the second count value output from the second count circuit 70, thereby indicating a comparison result representing the comparison result. The signal CC is output.

  When the comparison result signal CA indicating that the first count value is equal to the set value A is input, the trimming value setting circuit 85 compares the first count value with the second count value. The result signal CC is held and a trimming value is set based on the comparison result signal CC. For example, the trimming value setting circuit 85 sets the trimming value to “0” when the first count value is equal to the second count value. The trimming value setting circuit 85 sets the trimming value to “+1” when the first count value is larger than the second count value, and the first count value is smaller than the second count value. Set the trimming value to “−1”.

  The trimming value setting circuit 85 calculates a new trimming value by adding the set trimming value to the previous trimming value stored in the storage unit 84 and stores it in the storage unit 84. The trimming circuit 50 shown in FIG. 1 switches the value of the capacitor or resistance of the second oscillation circuit 40 in accordance with the latest trimming value stored in the storage unit 84. Thereby, the oscillation frequency of the second oscillation circuit 40 is brought close to the reference oscillation frequency f2.

  After that, when the comparison result signal CB indicating that the first count value is larger than the set value B is input, the trimming value setting circuit 85 immediately activates the reset signals RS1 and RS2. Thereby, the first count circuit 60 and the second count circuit 70 are reset, and the first and second count values become zero.

  By repeating the above operation, the oscillation frequency of the second oscillation circuit 40 is measured and adjusted in a plurality of frequency measurement periods. Alternatively, instead of providing the frequency divider circuit 71, the second count circuit 70 calculates the second count by dividing the value obtained by counting the number of pulses included in the clock signal CK2 by a predetermined number. A value may be generated. Further, the second count circuit 70 may output only a predetermined number of bits higher than the value obtained by counting the number of pulses included in the clock signal CK2 as the second count value. .

  Thereby, when the first oscillation circuit 10 and the second oscillation circuit 40 shown in FIG. 1 oscillate at the reference oscillation frequencies f1 and f2, respectively, the first count value and the second count value obtained in the frequency measurement period are obtained. The value can be made equal. Regarding other points, the second configuration example shown in FIG. 10 is the same as the first configuration example shown in FIG.

<Electronic equipment>
Next, an electronic apparatus according to an embodiment of the present invention will be described with reference to FIG.
FIG. 11 is a block diagram illustrating a configuration example of an electronic device according to an embodiment of the present invention. The electronic device 100 includes a clock signal generation circuit 110, a clock unit 120, a communication unit 130, an operation unit 140, a control unit 150, a display unit 160, a sound output unit 170, and a clock signal generation circuit 110 according to an embodiment of the present invention. May be included. Note that some of the components shown in FIG. 11 may be omitted or changed, or other components may be added to the components shown in FIG.

  FIG. 11 shows a first oscillation circuit 10, a second oscillation circuit 40, a trimming circuit 50, and a frequency adjustment circuit 80 as a part of the clock signal generation circuit 110. The timekeeping unit 120 includes a counter and the like, and performs timekeeping operation in synchronization with the clock signal CK1 output from the first oscillation circuit 10, thereby generating timekeeping data representing the current time. The communication unit 130 includes, for example, an analog circuit and a digital circuit, and performs communication such as serial communication with an external device using the clock signal CK2 output from the second oscillation circuit 40.

  The operation unit 140 is an input device including, for example, operation keys and button switches, and is used to operate the electronic device 100. The operation unit 140 outputs an operation signal corresponding to the operation by the user to the control unit 150.

  The control unit 150 includes, for example, a CPU 151, a ROM (Read Only Memory) 152, and a RAM (Random Access Memory) 153. The ROM 152 stores programs, data, and the like for the CPU 151 to perform various arithmetic processes and control processes. The RAM 153 is used as a work area of the CPU 151 and temporarily stores programs and data read from the ROM 152, data input using the operation unit 140, calculation results executed by the CPU 151 according to the programs, and the like. To do.

  When receiving a transmission command from the operation unit 140, the control unit 150 controls the frequency adjustment circuit 80 so as to adjust the oscillation frequency of the second oscillation circuit 40, and after the normal end signal F1 is activated, The communication unit 130 is controlled to perform a transmission operation. Thus, it is possible to provide an electronic device that uses a CR oscillation circuit to generate a communication clock signal and quickly starts a transmission operation after the frequency of the communication clock signal falls within a predetermined range. it can.

  The display unit 160 includes, for example, an LCD (liquid crystal display device) or the like, and displays various types of information based on a display signal supplied from the CPU 151. The audio output unit 170 includes, for example, a speaker and outputs sound based on an audio signal supplied from the CPU 151.

  The electronic device 100 corresponds to, for example, a watch-type terminal, a smartphone, or a mobile terminal in which a sensor function for measuring temperature, pressure, geomagnetism, or the like is added to the timekeeping function. Other than that, calculators, electronic dictionaries, electronic game devices, mobile terminals such as mobile phones, digital still cameras, digital movies, TVs, videophones, security TV monitors, head mounted displays, personal computers, printers, network devices , Car navigation devices, measuring devices, medical devices (for example, electronic thermometers, blood pressure monitors, blood glucose meters, electrocardiogram measuring devices, ultrasonic diagnostic devices, and electronic endoscopes).

  In the above-described embodiment, the description has been given of the case where the variable capacitance element is used to control the oscillation frequency of the first oscillation circuit 10 and the trimming circuit 50 is used to control the oscillation frequency of the second oscillation circuit 40. However, any method may be used to control the oscillation frequency of the first oscillation circuit 10 and the second oscillation circuit 40. Thus, the present invention is not limited to the embodiments described above, and many modifications can be made within the technical idea of the present invention by those who have ordinary knowledge in the technical field.

  DESCRIPTION OF SYMBOLS 10 ... 1st oscillation circuit, 11 ... Variable capacity diode, 12, 13 ... Resistor, 14, 15 ... Capacitor, 16 ... Inverter, 20 ... Temperature sensor, 21-23 ... Resistor, 24, 25 ... PNP transistor, 26 ... Operational amplifier, 30 ... temperature compensation circuit, 31 ... A / D conversion circuit, 32 ... data conversion circuit, 33 ... storage unit, 34 ... D / A conversion circuit, 40 ... second oscillation circuit, 41 ... NAND circuit, 42- 44 ... Inverter, 50 ... Trimming circuit, 51 ... Switch control circuit, 60 ... First count circuit, 70 ... Second count circuit, 71 ... Frequency divider, 80 ... Frequency adjustment circuit, 81, 82 ... Comparison circuit, 83, 84 ... Storage unit, 85 ... Trimming value setting circuit, 90 ... Power supply voltage detection circuit, 100 ... Electronic device, 110 ... Clock signal generation circuit, 120 ... Timing unit, 1 DESCRIPTION OF SYMBOLS 0 ... Communication part, 140 ... Operation part, 150 ... Control part, 151 ... CPU, 152 ... ROM, 153 ... RAM, 160 ... Display part, 170 ... Audio | voice output part, XTAL ... Crystal oscillator, S1, S2 ... Connection terminal , C0, C1, C2 ... capacitors, R0, R1, R2 ... resistors, SW1, SW2 ... switch circuits

Claims (8)

A first oscillation circuit that generates a first clock signal by performing an oscillation operation using a vibrator;
A temperature sensor that detects the temperature and generates an output voltage;
A temperature compensation circuit for compensating an oscillation frequency of the first oscillation circuit based on an output voltage of the temperature sensor;
A first count circuit that outputs a first count value by performing a count operation in synchronization with the first clock signal;
A second oscillation circuit that generates a second clock signal by performing an oscillation operation using a capacitor and a resistor;
A trimming circuit that switches a value of a capacitor or a resistor of the second oscillation circuit according to a trimming value;
A second count circuit that outputs a second count value by performing a count operation in synchronization with the second clock signal;
A frequency adjustment circuit for adjusting an oscillation frequency of the second oscillation circuit by setting the trimming value based on the first and second count values;
A clock signal generation circuit comprising:   The clock signal generation circuit according to claim 1, wherein the frequency adjustment circuit activates a normal end signal when an oscillation frequency of the second oscillation circuit is within a predetermined range.   The frequency adjustment circuit sets a frequency measurement period for measuring the oscillation frequency of the second oscillation circuit based on the second count value, and the first count value is predetermined at the end of the frequency measurement period. The clock signal generation circuit according to claim 1 or 2, wherein the clock signal generation circuit activates the normal end signal when the value is within the range.   The frequency adjustment circuit holds a trimming value when the normal end signal is activated, and the first and second count circuits after a predetermined period has elapsed since the normal end signal was activated 4. The clock signal generation circuit according to claim 2, wherein a new trimming value is set based on the first and second count values respectively output from.   The frequency adjustment circuit holds a trimming value when the normal end signal is activated, and when the output voltage of the temperature sensor changes more than a predetermined value after the normal end signal is activated 5. The clock signal generation circuit according to claim 2, wherein a new trimming value is set based on first and second count values output from the first and second count circuits, respectively. .   The frequency adjustment circuit holds a trimming value when the normal end signal is activated, and the first voltage is changed when the power supply voltage changes more than a predetermined value after the normal end signal is activated. 6. The clock signal generation circuit according to claim 2, wherein a new trimming value is set based on the first and second count values output from the second count circuit and the second count circuit, respectively.   A semiconductor integrated circuit device comprising the clock signal generation circuit according to claim 1. A clock signal generation circuit according to any one of claims 2 to 6,
A communication unit that communicates with the outside using a second clock signal generated by the second oscillation circuit;
An operation unit used to operate the electronic device;
When receiving a transmission command from the operation unit, the frequency adjustment circuit is controlled to adjust the oscillation frequency of the second oscillation circuit, and the transmission operation is performed after the normal end signal is activated. A control unit for controlling the communication unit;
Electronic equipment comprising.

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