JP2016534484A5 - - Google Patents

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Publication number
JP2016534484A5
JP2016534484A5 JP2016544034A JP2016544034A JP2016534484A5 JP 2016534484 A5 JP2016534484 A5 JP 2016534484A5 JP 2016544034 A JP2016544034 A JP 2016544034A JP 2016544034 A JP2016544034 A JP 2016544034A JP 2016534484 A5 JP2016534484 A5 JP 2016534484A5
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JP
Japan
Prior art keywords
memory
bus
channel
width
soc
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JP2016544034A
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English (en)
Japanese (ja)
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JP6239130B2 (ja
JP2016534484A (ja
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Priority claimed from US14/033,233 external-priority patent/US9430434B2/en
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Publication of JP2016534484A5 publication Critical patent/JP2016534484A5/ja
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JP2016544034A 2013-09-20 2014-09-19 作業負荷に従ってメモリバス帯域幅を低減するためのシステムおよび方法 Active JP6239130B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/033,233 2013-09-20
US14/033,233 US9430434B2 (en) 2013-09-20 2013-09-20 System and method for conserving memory power using dynamic memory I/O resizing
PCT/US2014/056659 WO2015042469A1 (en) 2013-09-20 2014-09-19 System and method for conserving memory power using dynamic memory i/o resizing

Publications (3)

Publication Number Publication Date
JP2016534484A JP2016534484A (ja) 2016-11-04
JP2016534484A5 true JP2016534484A5 (OSRAM) 2017-07-20
JP6239130B2 JP6239130B2 (ja) 2017-11-29

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ID=51703397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016544034A Active JP6239130B2 (ja) 2013-09-20 2014-09-19 作業負荷に従ってメモリバス帯域幅を低減するためのシステムおよび方法

Country Status (7)

Country Link
US (1) US9430434B2 (OSRAM)
EP (1) EP3047352B1 (OSRAM)
JP (1) JP6239130B2 (OSRAM)
KR (1) KR101914350B1 (OSRAM)
CN (1) CN105556421B (OSRAM)
TW (1) TWI627526B (OSRAM)
WO (1) WO2015042469A1 (OSRAM)

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US9324397B1 (en) * 2015-01-16 2016-04-26 Qualcomm Incorporated Common die for supporting different external memory types with minimal packaging complexity
CN116560563A (zh) 2015-10-01 2023-08-08 拉姆伯斯公司 具有高速缓存的存储器模块操作的存储器系统
US10222853B2 (en) * 2016-03-03 2019-03-05 Qualcomm Incorporated Power saving techniques for memory systems by consolidating data in data lanes of a memory bus
US10126979B2 (en) * 2016-10-04 2018-11-13 Qualcomm Incorporated Bus encoding using metadata
US10152379B1 (en) * 2016-12-27 2018-12-11 EMC IP Holding Company LLP Efficient garbage collection for distributed storage with forward error correction
US10409513B2 (en) 2017-05-08 2019-09-10 Qualcomm Incorporated Configurable low memory modes for reduced power consumption
US20180335828A1 (en) * 2017-05-19 2018-11-22 Qualcomm Incorporated Systems and methods for reducing memory power consumption via device-specific customization of ddr interface parameters
CN109032973B (zh) * 2018-07-09 2020-10-16 芯来科技(武汉)有限公司 Icb总线系统
KR102731057B1 (ko) * 2018-09-21 2024-11-15 삼성전자주식회사 메모리 장치와 통신하는 데이터 처리 장치 및 방법
US11693794B2 (en) * 2020-08-31 2023-07-04 Sandisk Technologies Llc Tunable and scalable command/address protocol for non-volatile memory
KR20230047823A (ko) 2021-10-01 2023-04-10 삼성전자주식회사 시스템 온 칩 및 어플리케이션 프로세서
US11893240B2 (en) * 2021-10-28 2024-02-06 Qualcomm Incorporated Reducing latency in pseudo channel based memory systems
CN117519451A (zh) * 2022-07-28 2024-02-06 华为技术有限公司 数据读写的方法、控制器和存储设备
KR20240157385A (ko) 2023-04-25 2024-11-01 삼성전자주식회사 메모리 장치 및 이를 포함하는 전자 장치
US20250068574A1 (en) * 2023-08-23 2025-02-27 Qualcomm Incorporated Efficiency mode in a memory system

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US6330639B1 (en) 1999-06-29 2001-12-11 Intel Corporation Method and apparatus for dynamically changing the sizes of pools that control the power consumption levels of memory devices
US6727533B2 (en) * 2000-11-29 2004-04-27 Fujitsu Limited Semiconductor apparatus having a large-size bus connection
US7469311B1 (en) * 2003-05-07 2008-12-23 Nvidia Corporation Asymmetrical bus
US7188198B2 (en) 2003-09-11 2007-03-06 International Business Machines Corporation Method for implementing dynamic virtual lane buffer reconfiguration
US7694060B2 (en) 2005-06-17 2010-04-06 Intel Corporation Systems with variable link widths based on estimated activity levels
US7539809B2 (en) * 2005-08-19 2009-05-26 Dell Products L.P. System and method for dynamic adjustment of an information handling systems graphics bus
US20070101168A1 (en) 2005-10-31 2007-05-03 Lee Atkinson Method and system of controlling data transfer speed and power consumption of a bus
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US7949817B1 (en) 2007-07-31 2011-05-24 Marvell International Ltd. Adaptive bus profiler
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US9798370B2 (en) * 2009-03-30 2017-10-24 Lenovo (Singapore) Pte. Ltd. Dynamic memory voltage scaling for power management
US8412971B2 (en) 2010-05-11 2013-04-02 Advanced Micro Devices, Inc. Method and apparatus for cache control
US8762760B2 (en) * 2010-09-14 2014-06-24 Xilinx, Inc. Method and apparatus for adaptive power control in a multi-lane communication channel
JP5630348B2 (ja) 2011-03-18 2014-11-26 株式会社リコー メモリモジュールおよびメモリシステム
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