JP2016533085A5 - - Google Patents

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Publication number
JP2016533085A5
JP2016533085A5 JP2016532189A JP2016532189A JP2016533085A5 JP 2016533085 A5 JP2016533085 A5 JP 2016533085A5 JP 2016532189 A JP2016532189 A JP 2016532189A JP 2016532189 A JP2016532189 A JP 2016532189A JP 2016533085 A5 JP2016533085 A5 JP 2016533085A5
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JP
Japan
Prior art keywords
uplink
subframe
downlink
transmission
downlink configuration
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JP2016532189A
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English (en)
Japanese (ja)
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JP6308506B2 (ja
JP2016533085A (ja
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Priority claimed from PCT/CN2013/081221 external-priority patent/WO2015018084A1/en
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Publication of JP2016533085A5 publication Critical patent/JP2016533085A5/ja
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JP2016532189A 2013-08-09 2013-08-09 Ｔｄｄのアップリンク／ダウンリンク再構成メカニズム Active JP6308506B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2013/081221 WO2015018084A1 (en) 2013-08-09 2013-08-09 Tdd uplink/downlink re-configuration mechanism

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2018038640A Division JP6481988B2 (ja) 2018-03-05 2018-03-05 集積回路

Publications (3)

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JP2016533085A JP2016533085A (ja) 2016-10-20
JP2016533085A5 true JP2016533085A5 (enExample) 2017-12-14
JP6308506B2 JP6308506B2 (ja) 2018-04-11

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JP2016532189A Active JP6308506B2 (ja) 2013-08-09 2013-08-09 Ｔｄｄのアップリンク／ダウンリンク再構成メカニズム

Country Status (5)

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US (6) US9876628B2 (enExample)
EP (3) EP3031160B1 (enExample)
JP (1) JP6308506B2 (enExample)
CN (2) CN105612709B (enExample)
WO (1) WO2015018084A1 (enExample)

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