JP2016532180A5 - - Google Patents

Download PDF

Info

Publication number
JP2016532180A5
JP2016532180A5 JP2016518666A JP2016518666A JP2016532180A5 JP 2016532180 A5 JP2016532180 A5 JP 2016532180A5 JP 2016518666 A JP2016518666 A JP 2016518666A JP 2016518666 A JP2016518666 A JP 2016518666A JP 2016532180 A5 JP2016532180 A5 JP 2016532180A5
Authority
JP
Japan
Prior art keywords
warps
warp
true
boolean
active threads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2016518666A
Other languages
English (en)
Japanese (ja)
Other versions
JP6411477B2 (ja
JP2016532180A (ja
Filing date
Publication date
Priority claimed from US14/043,562 external-priority patent/US9652284B2/en
Application filed filed Critical
Publication of JP2016532180A publication Critical patent/JP2016532180A/ja
Publication of JP2016532180A5 publication Critical patent/JP2016532180A5/ja
Application granted granted Critical
Publication of JP6411477B2 publication Critical patent/JP6411477B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2016518666A 2013-10-01 2014-09-10 Ｇｐｕ発散バリア Active JP6411477B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/043,562 2013-10-01
US14/043,562 US9652284B2 (en) 2013-10-01 2013-10-01 GPU divergence barrier
PCT/US2014/054966 WO2015050681A1 (en) 2013-10-01 2014-09-10 Gpu divergence barrier

Publications (3)

Publication Number Publication Date
JP2016532180A JP2016532180A (ja) 2016-10-13
JP2016532180A5 true JP2016532180A5 (enExample) 2017-09-21
JP6411477B2 JP6411477B2 (ja) 2018-10-24

Family

ID=51619301

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016518666A Active JP6411477B2 (ja) 2013-10-01 2014-09-10 Ｇｐｕ発散バリア

Country Status (6)

Country Link
US (1) US9652284B2 (enExample)
EP (1) EP3053038B1 (enExample)
JP (1) JP6411477B2 (enExample)
KR (1) KR102253426B1 (enExample)
CN (1) CN105579967B (enExample)
WO (1) WO2015050681A1 (enExample)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150019349A (ko) * 2013-08-13 2015-02-25 삼성전자주식회사 다중 쓰레드 실행 프로세서 및 이의 동작 방법
US10133572B2 (en) * 2014-05-02 2018-11-20 Qualcomm Incorporated Techniques for serialized execution in a SIMD processing system
GB2540937B (en) * 2015-07-30 2019-04-03 Advanced Risc Mach Ltd Graphics processing systems
US9921838B2 (en) * 2015-10-02 2018-03-20 Mediatek Inc. System and method for managing static divergence in a SIMD computing architecture
US10409610B2 (en) * 2016-01-29 2019-09-10 Advanced Micro Devices, Inc. Method and apparatus for inter-lane thread migration
US10115175B2 (en) * 2016-02-19 2018-10-30 Qualcomm Incorporated Uniform predicates in shaders for graphics processing units
KR20180038793A (ko) * 2016-10-07 2018-04-17 삼성전자주식회사 영상 데이터 처리 방법 및 장치
US10649770B2 (en) 2017-01-31 2020-05-12 Facebook, Inc. κ-selection using parallel processing
US10474468B2 (en) * 2017-02-22 2019-11-12 Advanced Micro Devices, Inc. Indicating instruction scheduling mode for processing wavefront portions
US10310861B2 (en) 2017-04-01 2019-06-04 Intel Corporation Mechanism for scheduling threads on a multiprocessor
US10496448B2 (en) * 2017-04-01 2019-12-03 Intel Corporation De-centralized load-balancing at processors
US10325341B2 (en) 2017-04-21 2019-06-18 Intel Corporation Handling pipeline submissions across many compute units
US10620994B2 (en) 2017-05-30 2020-04-14 Advanced Micro Devices, Inc. Continuation analysis tasks for GPU task scheduling
US10866806B2 (en) * 2017-11-14 2020-12-15 Nvidia Corporation Uniform register file for improved resource utilization
CN111712793B (zh) * 2018-02-14 2023-10-20 华为技术有限公司 线程处理方法和图形处理器
US12099867B2 (en) 2018-05-30 2024-09-24 Advanced Micro Devices, Inc. Multi-kernel wavefront scheduler
WO2020186631A1 (en) * 2019-03-21 2020-09-24 Huawei Technologies Co., Ltd. Compute shader warps without ramp up
US12405790B2 (en) 2019-06-28 2025-09-02 Advanced Micro Devices, Inc. Compute unit sorting for reduced divergence
US20210132985A1 (en) * 2019-10-30 2021-05-06 Advanced Micro Devices, Inc. Shadow latches in a shadow-latch configured register file for thread storage
KR102346601B1 (ko) 2020-02-26 2022-01-03 성균관대학교산학협력단 운영체제 내 쓰기 순서 보장이 필요한 여러 쓰기 입출력의 처리 속도 향상 방법
CN113535251A (zh) 2020-04-13 2021-10-22 华为技术有限公司 一种线程管理方法及装置
US11288765B2 (en) * 2020-04-28 2022-03-29 Sony Interactive Entertainment LLC System and method for efficient multi-GPU execution of kernels by region based dependencies
US11204774B1 (en) * 2020-08-31 2021-12-21 Apple Inc. Thread-group-scoped gate instruction
US11640647B2 (en) * 2021-03-03 2023-05-02 Qualcomm Incorporated Methods and apparatus for intra-wave texture looping
US20230153176A1 (en) * 2021-11-17 2023-05-18 Intel Corporation Forward progress guarantee using single-level synchronization at individual thread granularity
US20250068429A1 (en) * 2023-08-22 2025-02-27 Advanced Micro Devices, Inc. Streaming wave coalescer circuit

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59180668A (ja) * 1983-03-31 1984-10-13 Fujitsu Ltd 条件付命令の実行時命令選択方式
US6212544B1 (en) * 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
JP2004220070A (ja) 2003-01-09 2004-08-05 Japan Science & Technology Agency コンテキスト切り替え方法及び装置、中央演算装置、コンテキスト切り替えプログラム及びそれを記憶したコンピュータ読み取り可能な記憶媒体
US7746347B1 (en) 2004-07-02 2010-06-29 Nvidia Corporation Methods and systems for processing a geometry shader program developed in a high-level shading language
US7639252B2 (en) 2004-08-11 2009-12-29 Ati Technologies Ulc Unified tessellation circuit and method therefor
US7480840B2 (en) 2004-10-12 2009-01-20 International Business Machines Corporation Apparatus, system, and method for facilitating port testing of a multi-port host adapter
US7522167B1 (en) 2004-12-16 2009-04-21 Nvidia Corporation Coherence of displayed images for split-frame rendering in multi-processor graphics system
US8171461B1 (en) 2006-02-24 2012-05-01 Nvidia Coporation Primitive program compilation for flat attributes with provoking vertex independence
US7696993B2 (en) 2007-02-08 2010-04-13 Via Technologies, Inc. Geometry primitive type conversion in a GPU pipeline
US8072460B2 (en) 2007-10-17 2011-12-06 Nvidia Corporation System, method, and computer program product for generating a ray tracing data structure utilizing a parallel processor architecture
US8661226B2 (en) * 2007-11-15 2014-02-25 Nvidia Corporation System, method, and computer program product for performing a scan operation on a sequence of single-bit values using a parallel processor architecture
US20100064291A1 (en) 2008-09-05 2010-03-11 Nvidia Corporation System and Method for Reducing Execution Divergence in Parallel Processing Architectures
US8615646B2 (en) 2009-09-24 2013-12-24 Nvidia Corporation Unanimous branch instructions in a parallel thread processor
US20110219221A1 (en) 2010-03-03 2011-09-08 Kevin Skadron Dynamic warp subdivision for integrated branch and memory latency divergence tolerance
US8732711B2 (en) 2010-09-24 2014-05-20 Nvidia Corporation Two-level scheduler for multi-threaded processing
US8595701B2 (en) 2011-02-04 2013-11-26 Fujitsu Limited Symbolic execution and test generation for GPU programs
US9153193B2 (en) 2011-09-09 2015-10-06 Microsoft Technology Licensing, Llc Primitive rendering using a single primitive type
US9606808B2 (en) * 2012-01-11 2017-03-28 Nvidia Corporation Method and system for resolving thread divergences

Similar Documents

Publication Publication Date Title
JP2016532180A5 (enExample)
KR102253426B1 (ko) Gpu 다이버전스 배리어
CN103336718B (zh) 一种gpu线程调度优化方法
JP2017530444A5 (enExample)
WO2015153121A8 (en) A data processing apparatus and method for executing a stream of instructions out of order with respect to original program order
FI4099168T3 (fi) Laskentaoptimoinnit alhaisen tarkkuuden koneoppimistoimintoja varten
GB2517877A (en) Controlling an order for processing data elements during vector processing
EP2889760A3 (en) SMS4 acceleration processors, methods, systems, and instructions
JP2017517082A5 (enExample)
WO2014150727A3 (en) Method, apparatuses and program product to save and store system memory management unit contexts
CN111414197A (zh) 数据处理系统、编译器、处理器的方法和机器可读介质
EA201390868A1 (ru) Способ и система для вычислительного ускорения обработки сейсмических данных
CN106575431A8 (zh) 用于高度高效的图形处理单元(gpu)执行模型的方法和装置
WO2018052606A3 (en) Apparatus and method for optimized ray tracing
JP2015527681A5 (enExample)
MX2017016197A (es) Ventana de instruccion de procesador desacoplada y memoria intermedia de operando.
EP3614267A3 (en) Recoverable stream processing
EP4418136A3 (en) Systems, apparatuses, and methods for fused multiply add
RU2016127443A (ru) Команда запуска виртуального выполнения для диспетчеризации множественных потоков в компьютере
EP3343361A3 (en) Apparatus and methods to support counted loop exits in a multi-strand loop processor
US20140075160A1 (en) System and method for synchronizing threads in a divergent region of code
EP3007065A3 (en) Parallelization in virtual machine operation
RU2017105354A (ru) Равноправное разделение системных ресурсов в исполнении рабочего процесса
JP2014511526A5 (enExample)
WO2017052811A3 (en) Secure modular exponentiation processors, methods, systems, and instructions