JP2016508635A5 - - Google Patents

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Publication number
JP2016508635A5
JP2016508635A5 JP2015555160A JP2015555160A JP2016508635A5 JP 2016508635 A5 JP2016508635 A5 JP 2016508635A5 JP 2015555160 A JP2015555160 A JP 2015555160A JP 2015555160 A JP2015555160 A JP 2015555160A JP 2016508635 A5 JP2016508635 A5 JP 2016508635A5
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JP
Japan
Prior art keywords
domain
diagonal strip
outputting
primitives
coordinates
Prior art date
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Granted
Application number
JP2015555160A
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English (en)
Japanese (ja)
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JP6400601B2 (ja
JP2016508635A (ja
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Publication date
Priority claimed from US13/754,005 external-priority patent/US9123168B2/en
Application filed filed Critical
Publication of JP2016508635A publication Critical patent/JP2016508635A/ja
Publication of JP2016508635A5 publication Critical patent/JP2016508635A5/ja
Application granted granted Critical
Publication of JP6400601B2 publication Critical patent/JP6400601B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2015555160A 2013-01-30 2013-12-19 テッセレーションのためのドメイン座標の出力順序付け Expired - Fee Related JP6400601B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/754,005 2013-01-30
US13/754,005 US9123168B2 (en) 2013-01-30 2013-01-30 Output ordering of domain coordinates for tessellation
PCT/US2013/076655 WO2014120359A1 (en) 2013-01-30 2013-12-19 Output ordering of domain coordinates for tessellation

Publications (3)

Publication Number Publication Date
JP2016508635A JP2016508635A (ja) 2016-03-22
JP2016508635A5 true JP2016508635A5 (enExample) 2017-01-12
JP6400601B2 JP6400601B2 (ja) 2018-10-03

Family

ID=49998671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015555160A Expired - Fee Related JP6400601B2 (ja) 2013-01-30 2013-12-19 テッセレーションのためのドメイン座標の出力順序付け

Country Status (6)

Country Link
US (1) US9123168B2 (enExample)
EP (1) EP2951784A1 (enExample)
JP (1) JP6400601B2 (enExample)
KR (1) KR20150110675A (enExample)
CN (1) CN104956402B (enExample)
WO (1) WO2014120359A1 (enExample)

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Publication number Priority date Publication date Assignee Title
KR102066533B1 (ko) * 2013-11-19 2020-01-16 삼성전자 주식회사 도메인 쉐이딩 방법과 이를 수행하는 장치들
KR101555426B1 (ko) * 2014-02-07 2015-09-25 고려대학교 산학협력단 지형 렌더링 방법 및 장치
US9842428B2 (en) * 2014-06-27 2017-12-12 Samsung Electronics Co., Ltd. Dynamically optimized deferred rendering pipeline
US20160093102A1 (en) * 2014-09-25 2016-03-31 Peter L. Doyle Efficient tessellation cache
KR20160063081A (ko) * 2014-11-26 2016-06-03 삼성전자주식회사 선택적 테셀레이션 방법 및 장치
GB2533443B (en) 2015-06-05 2018-06-06 Imagination Tech Ltd Tessellation method using recursive sub-division of triangles
GB2533444B (en) 2015-06-05 2017-08-16 Imagination Tech Ltd Tessellation method
GB2539042B (en) 2015-06-05 2019-08-21 Imagination Tech Ltd Tessellation method using displacement factors
GB2542133B (en) * 2015-09-08 2020-05-27 Imagination Tech Ltd Graphics processing method and system for processing sub-primitives
US10685473B2 (en) * 2017-05-31 2020-06-16 Vmware, Inc. Emulation of geometry shaders and stream output using compute shaders
US10621782B1 (en) * 2017-12-06 2020-04-14 Apple Inc. Sub-patch techniques for graphics tessellation
GB2570304B (en) 2018-01-18 2022-06-01 Imagination Tech Ltd Topology preservation in a graphics pipeline
GB2572625B (en) 2018-04-05 2020-06-17 Imagination Tech Ltd Ordering in tessellation operations
GB2572617B (en) 2018-04-05 2021-06-16 Imagination Tech Ltd Blending hardware
US11232532B2 (en) * 2018-05-30 2022-01-25 Sony Interactive Entertainment LLC Multi-server cloud virtual reality (VR) streaming
US11010862B1 (en) * 2019-11-14 2021-05-18 Advanced Micro Devices, Inc. Reduced bandwidth tessellation factors
US11481967B2 (en) * 2020-08-31 2022-10-25 Advanced Micro Devices, Inc. Shader core instruction to invoke depth culling
EP4241230A4 (en) * 2020-11-09 2024-08-28 Qualcomm Incorporated METHOD AND DEVICE FOR GRIDDING CALCULATION WORKLOADS
US12488491B2 (en) * 2022-07-26 2025-12-02 Biosense Webster (Israel) Ltd. Tracking coordinates of electrodes

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7436405B2 (en) * 2004-05-14 2008-10-14 Microsoft Corporation Terrain rendering using nested regular grids
US8237709B2 (en) * 2007-09-06 2012-08-07 Qualcomm Incorporated Method and apparatus for optimizing triangles into triangle strips according to a variety of criteria
US8120607B1 (en) * 2008-05-30 2012-02-21 Nvidia Corporation Boundary transition region stitching for tessellation
US8188999B2 (en) * 2008-06-17 2012-05-29 Qualcomm Incorporated Method and apparatus for organizing object geometry for spatial and memory coherency and optimal rendering
US20100164954A1 (en) * 2008-12-31 2010-07-01 Sathe Rahul P Tessellator Whose Tessellation Time Grows Linearly with the Amount of Tessellation
US20100214294A1 (en) 2009-02-20 2010-08-26 Microsoft Corporation Method for tessellation on graphics hardware
US20100253683A1 (en) 2009-04-01 2010-10-07 Munkberg Carl J Non-uniform tessellation technique
US8884957B2 (en) 2009-09-09 2014-11-11 Advanced Micro Devices, Inc. Tessellation engine and applications thereof
US8537158B2 (en) 2009-12-02 2013-09-17 Microsoft Corporation Parallel triangle tessellation
GB201007348D0 (en) 2010-04-30 2010-06-16 Imagination Tech Ltd Programmable tessellation in a tile based rendering system
US20110310102A1 (en) 2010-06-17 2011-12-22 Via Technologies, Inc. Systems and methods for subdividing and storing vertex data

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