JP2016225359A - Light receiving element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a light receiving element capable of reducing the ratio of dark current to photocurrent.SOLUTION: A light receiving element according to the present invention comprises a substrate, a semiconductor laminate stacked on the substrate, a plurality of p-type semiconductor regions provided in the semiconductor laminate, and one electrode provided on the semiconductor laminate. A plurality of p-type semiconductor regions are provided from an upper surface of the semiconductor laminate toward the substrate. The semiconductor laminate has a light receiving layer. The semiconductor laminate has a plurality of PN junctions at a boundary between the light receiving layer and the plurality of p-type semiconductor regions. The plurality of p-type semiconductor regions are connected to one electrode.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a light receiving element.

  Patent Document 1 discloses a photodiode array element. Patent Document 2 discloses a light receiving element array. This light receiving element array has a configuration for reducing the leakage current between the light receiving elements. Patent Document 3 discloses an InGaAs photodiode array. The InGaAs photodiode array includes a photodiode array having semiconductor mesas.

JP 2002-319696 A JP 2009-277742 A Special table 2014-521216 gazette

  The light receiving element is evaluated by a characteristic related to generation of a photocurrent related to light reception sensitivity and a characteristic related to dark current. A part of the dark current is generated in the depletion layer related to the PN junction of the light receiving element. In this depletion layer, electron-hole pairs are also generated by light absorption. In a planar light-receiving element having a PN junction formed by a p-type semiconductor region provided in a light-receiving layer including an n-type semiconductor and the n-type semiconductor, photocurrent is incident on a depletion layer related to the PN junction. Generated from light absorption. According to the inventor's study, the photocurrent is generated not only from light absorption in the depletion layer but also from absorption of light incident on the outside of the depletion layer. The latter of the photocurrents is generated by light-absorbing electron-hole pairs in the light-receiving layer outside the depletion layer (hereinafter referred to as “extended region”), and specifically reaches the p-type semiconductor region. Corresponds to the Hall component. The range of movement of holes in the extended region is related to the diffusion coefficient of holes in the light receiving layer. According to this finding, the photoelectric flow rate is related to the carrier amount in the depletion layer of the PN junction related to the p-type semiconductor region and the carrier amount from the extended region.

  An object of one aspect of the present invention is to provide a light receiving element capable of collecting a photocurrent to a p-side electrode by effectively using an extended region.

  A light receiving element according to the present invention includes a substrate, a semiconductor stack stacked on the substrate, a plurality of p-type semiconductor regions provided in the semiconductor stack, and one electrode provided on the semiconductor stack. The plurality of p-type semiconductor regions are provided from an upper surface of the semiconductor stack toward the substrate, the semiconductor stack includes a light receiving layer, and the semiconductor stack includes the light receiving layer and the plurality of semiconductor layers. A plurality of PN junctions are provided at a boundary with the p-type semiconductor region, and the plurality of p-type semiconductor regions are connected to the one electrode.

  ADVANTAGE OF THE INVENTION According to this invention, the light receiving element which can collect the photocurrent to the p side electrode effectively using an expansion area | region can be provided.

It is a figure which shows typically the light receiving element which concerns on 1st Embodiment. It is a figure which shows typically the depletion layer and extended area | region which concern on the p-type semiconductor region which comprises the light absorption area | region which concerns on 1st Embodiment. It is a figure which shows typically one Example of the pixel which has three p-type semiconductor regions. It is a figure which shows typically the light receiving element which has a single p-type semiconductor region. It is sectional drawing taken along the VV line shown by the (b) part of FIG. It is the figure which showed the relationship between the photocurrent and dark current of the light receiving element which concern on 1st Embodiment, and the area of a p-type semiconductor region. It is a figure which shows typically the main processes in the method of producing the light receiving element which concerns on 1st Embodiment.

  A light receiving element according to the present invention includes a substrate, a semiconductor stack stacked on the substrate, a plurality of p-type semiconductor regions provided in the semiconductor stack, and one electrode provided on the semiconductor stack. The plurality of p-type semiconductor regions are provided from an upper surface of the semiconductor stack toward the substrate, the semiconductor stack includes a light receiving layer, and the semiconductor stack includes the light receiving layer and the plurality of semiconductor layers. A plurality of PN junctions are provided at a boundary with the p-type semiconductor region, and the plurality of p-type semiconductor regions are connected to the one electrode.

  According to this light receiving element, a plurality of p-type semiconductor regions are provided in the semiconductor stack, and these p-type semiconductor regions are connected to a single electrode. In the semiconductor stack, the plurality of p-type semiconductor regions are spaced apart from each other, and therefore, a plurality of PN junctions related to the p-type semiconductor region are provided in the semiconductor stack. In the light receiving layer outside these PN junctions, one or a plurality of extension regions are defined according to the arrangement of the plurality of p-type semiconductor regions. Holes in the electron-hole pairs generated by light absorption in the extended region flow into any of the p-type semiconductor regions and become a plurality of hole current components. A single electrode generates a single photocurrent from multiple Hall current components.

  As already described, the hole movement range can be estimated from the hole diffusion coefficient in the light receiving layer. Compared to the fact that the size of the p-type semiconductor region can be changed by the device design and the size of the PN junction in the p-type semiconductor region depends on the device design, the hole diffusion length is not changeable by the device design. Independent from. Accordingly, the extension region associated with the plurality of p-type semiconductor regions is appropriately provided for the light receiving element by the arrangement of the p-type semiconductor regions, so that the hole component from the extension region can contribute to the photocurrent. In addition, a depletion layer associated with a plurality of p-type semiconductor regions is appropriately provided for the light receiving element by the arrangement of the p-type semiconductor regions, thereby reducing dark current caused by the depletion layers.

  In the light receiving element, the light receiving layer may have a type II type InGaAs / GaAsSb quantum well structure. Since carriers easily diffuse at the interface of the type II hetero barrier, the amount of carriers diffused from the extended region to the depletion layer increases. According to this light receiving element, since the bias voltage applied to the depletion layer is reduced, the dark current is further reduced.

  A light receiving element according to some embodiments will be described below with reference to the drawings. In the following description, the same reference numerals are given to the same elements in the description of the drawings.

(First embodiment)
FIG. 1 is a diagram schematically illustrating a light receiving element according to the first embodiment. The light receiving element array 2 in FIG. 1 can include an array of one-dimensional or two-dimensional light receiving elements 1. 1A is a plan view showing a part of the light receiving element array 2, and the light receiving element array 2 indicates nine light receiving element arrays in this embodiment. Part (b) of FIG. 1 is a cross-sectional view taken along the line Ib-Ib shown in part (a) of FIG. Cartesian coordinate system S _R are depicted in Figure 1.

  As shown in part (b) of FIG. 1, the light receiving element 1 includes a substrate 10 and a semiconductor stack 20 stacked on the substrate 10. The substrate 10 is, for example, a semiconductor substrate, and specifically can be an n-type InP substrate. The n-type dopant of the substrate 10 includes, for example, Sn. The semiconductor stack 20 has a light receiving layer 21. The light receiving layer 21 is provided on the substrate 10. The light receiving layer 21 includes, for example, an undoped InGaAs layer or InGaAsP layer, a GaAsSb layer, and a GaInNAs layer. The thickness of the light receiving layer 21 is, for example, 3.0 μm.

The semiconductor stack 20 of the light receiving element 1 has a plurality of p-type semiconductor regions in an area of one element section, and the light receiving element 1 can include, for example, three p-type semiconductor regions spaced from each other. . In FIG. 1B, for the sake of easy understanding, three p-type semiconductor regions included in the area of one element section are drawn, and the three p-type semiconductor regions are the first p-type regions. Reference is made to the type semiconductor region 31, the second p-type semiconductor region 32, and the third p-type semiconductor region 33. The p-type dopants of the first, second, and third p-type semiconductor regions 31, 32, and 33 include, for example, Zn. The p-type dopant concentration is, for example, about 5 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ . The number of p-type semiconductor regions of the light receiving element 1 is not limited to three, and may be a number greater than one. The light receiving element 1 includes one p-electrode 24. The p-electrode 24 is connected to the first, second and third p-type semiconductor regions 31, 32 and 33.

The light receiving element 1 includes a first p-type semiconductor region 31, a second p-type semiconductor region 32, and a third p-type semiconductor region 33. The p-type semiconductor region 32 and the third p-type semiconductor region 33 are provided so as to reach the light receiving layer 21 from the upper surface 20 </ b> A of the semiconductor stack 20. As shown in FIG. 1B, the first p-type semiconductor region 31, the second p-type semiconductor region 32, and the third p-type semiconductor region 33 are formed from the upper surface 20A of the semiconductor stack 20 to the substrate. It extends in the direction toward 10. In the orthogonal coordinate system _{S R,} Z axis represents the extending direction of the first, second and third p-type semiconductor regions 31, 32 and 33. In the semiconductor stack 20, the light receiving layer 21, the first p-type semiconductor region 31, the second p-type semiconductor region 32, and the third p-type semiconductor region 33 form a boundary. , The boundary has a plurality of PN junctions. These PN junctions are referred to as a first PN junction 41, a second PN junction 42, and a third PN junction 43, respectively. In the light receiving layer 21, the first PN junction 41, the second PN junction 42, and the third PN junction 43 are respectively a first depletion layer 51, a second depletion layer 52, and a third depletion layer. With layer 53. The first, second and third p-type semiconductor regions 31, 32, 33 have a depth 34H defined from the upper surface 20A of the semiconductor stack 20, and the depth 34H is, for example, 1.5 μm. The first, second, and third p-type semiconductor regions 31, 32, and 33 are roughly constituted by a side surface and a bottom surface.

  As shown in FIG. 1B, the light receiving layer 21 has a first region 40a inside the first PN junction 41 in each element section. Similarly, the light-receiving layer 21 has a second region 40b and a third region 40c, and the second region 40b and the third region 40c are inside the second PN junction 42 and the third PN junction 43, respectively. Located in. The light receiving layer 21 has a fourth region 40d. The fourth region 40d reaches the element section and is located outside the first, second, and third PN junctions 41, 42, 43, and the first, second, and third PN junctions 41, 42, The first, second, and third PN junctions 41, 42, and 43 are partly in contact with the bottom surface as well as the side surface of 43.

The first, second and third regions 40a, 40b and 40c all have p-type conductivity. The fourth region 40d has n-type conductivity. The names of these regions and the minority carrier concentration in each region are summarized as follows.
Name of each area, carrier name, carrier concentration.
First, second and third regions, ^{Hall, 5 × 10 15 cm -3 ~1} × 10 18 cm -3.
Fourth region, ^{electrons, 5 × 10 14 cm -3 ~5} × 10 15 cm -3.
The carrier concentration (hole concentration) of the first, second, and third regions 40a, 40b, and 40c corresponding to the first, second, and third p-type semiconductor regions 31, 32, and 33, respectively, Higher than the carrier concentration (electron concentration) of the fourth region 40d. Therefore, the first, second, and third depletion layers 51, 52, 53 can extend into the light receiving layer 21 in response to application of a bias voltage.

  In the light receiving element 1, the first p-type semiconductor region 31, the second p-type semiconductor region 32, and the third p-type semiconductor region 33 are a first extension region 61, a second extension region 62, respectively. And a third extension region 63, the first extension region 61, the second extension region 62, and the third extension region 63 include a first depletion layer 51, a second depletion layer 52, and It is located around the third depletion layer 53. In FIG. 1B, an extended region and a depletion layer in the light receiving layer 21 are drawn. The first, second, and third extension regions 61, 62, and 63 can generate electron-hole pairs by light absorption, and the holes are formed in the first, second, and third depletion layers 51, 52, and 53. Move towards. Specifically, the holes are generated by light absorption in the first, second, and third extension regions 61, 62, and 63, and diffused to form the first, second, and third p-type semiconductors. It flows into the regions 31, 32 and 33 and becomes the respective hole components. The first p-type semiconductor region 31 receives the first carrier generated in the first depletion layer 51 and the second carrier generated in the first extension region 61. Since the second carrier can move by the diffusion length associated with the lifetime, the first p-type semiconductor region 31 receives carriers from the limited light receiving layer 21 outside the first depletion layer 51. In the present embodiment, the first, second, and third extended regions 61, 62, and 63 include the light absorption region 3 in the light receiving layer 21 together with the first, second, and third depletion layers 51, 52, and 53. Form.

The semiconductor stacked layer 20 further includes a semiconductor layer 22 provided on the light receiving layer 21 as necessary. The semiconductor layer 22 includes, for example, an n-type III-V group compound semiconductor such as InGaAs or InP that can form an ohmic contact when a p-type region is formed. The electron density of the semiconductor layer 22 can be about 2 × 10 ¹⁶ cm ⁻³ , for example. The thickness of the semiconductor layer 22 is, for example, 1.0 μm.

As shown in FIG. 1B, the upper surface 20A of the semiconductor stack 20 is covered with a dielectric film 23 in this embodiment. The dielectric film 23 includes, for example, a Si-based inorganic insulating layer, and more specifically is formed of, for example, a SiN film, a SiO ₂ film, or a SiON film. In this embodiment, a SiN film is used for the dielectric film 23. The thickness of the SiN film is, for example, 300 nm. The dielectric film 23 has a plurality of openings 23N. A p-electrode 24 is provided in the opening 23N. The p electrode 24 includes, for example, Ti / Pt / Au. In this embodiment, one p-electrode 24 is connected to three p-type semiconductor regions, that is, the first, second, and third p-type semiconductor regions 31, 32, and 33 through respective openings 23N. The The diameter 24D of the p-electrode 24 is 2 μm, for example.

In the light receiving element 1, an antireflection film 25 is provided on the back surface 10 </ b> B of the substrate 10. The antireflection film 25 includes, for example, a SiO ₂ film or a SiON film, and the thickness of the antireflection film 25 is, for example, 300 nm. The antireflection film 25 has an opening 25N. An n electrode 26 is provided in the opening 25N, and the n electrode 26 is connected to the substrate 10 through the opening 25N. The n electrode 26 includes, for example, Ti / Pt / Au. The semiconductor stack 20 may have a buffer layer between the substrate 10 and the light receiving layer 21 as necessary. The buffer layer includes, for example, n-type InP. The n-type dopant of the buffer layer is, for example, Si, and the dopant concentration is, for example, 1 × 10 ¹⁷ cm ⁻³ . The thickness of the buffer layer is, for example, 0.5 μm.

  The light receiving element 1 has a back incident type structure in which the entire back surface receives incident light, and in this embodiment, the light absorption region 3 absorbs light. Although the light absorption region 3 has a three-dimensional shape, since the thickness of the light receiving layer 21 is constant, the light absorption in the light absorption region 3 can be simply explained by a two-dimensional plane (XY plane). Hereinafter, the light absorption region 3 will be described with reference to a two-dimensional plane.

  FIG. 2 is a diagram schematically showing a depletion layer and an extension region related to the p-type semiconductor region constituting the light absorption region. FIG. 2 is a cross-sectional view taken along line II-II shown in part (b) of FIG. The first p-type semiconductor region 31 has a circular cross section. Therefore, the outer edge of the first depletion layer 51 also has a circular cross section. With reference to the two-dimensional model shown in FIG. 2, the ratio between the photocurrent component from the first extension region 61 and the photocurrent component from the first depletion layer 51 in the first p-type semiconductor region 31. Estimate.

As shown in FIG. 2, defined by the outer edge of the first extension region 61 using the hole diffusion length “R _D ” and the radius “R _V ” of the circle defining the outer edge of the first depletion layer 51. The radius of the circle is represented as R _D + R _V. The area of the first depletion layer 51 is expressed as π × R _V ² , and the area of the first extension region 61 is determined from the area of the circle defined by the outer edge of the first extension region 61 by the first by subtracting the area of the depletion layer _{51, π × (R D +} R V) are represented as ² -π × _R ^V 2.

It is assumed that the magnitude of the photocurrent is proportional to the area of the light-absorbing region, the light incidence is uniform, and the generation of electron / hole pairs is the first extended region 61 and the first depletion layer 51. Are the same. Then, when expressed as the photocurrent _IV in the first depletion layer 51 and the photocurrent _ID in the first extension region 61, the ratio I _D / I _V is determined by the area of the first depletion layer 51 and the first depletion layer 51. It is represented by a ratio with the area of one extended region 61. That is, the ratio _ID / _IV of the photocurrent _ID to the photocurrent _IV is expressed by the following formula (1).
I _D / I _V = (π × (R _D + R _V ) ² −π × R _V ² ) / (π × R _V ² ) = (π × (R _D + R _V + R _V ) × (R _D + _{R V -R V)) / (} π × R V 2) = (R D 2 + 2R D × R V) / R V 2 = (R D / R V) 2 +2 (R D / R V) = ((R _D / R _V ) +1) ² −1 (1)
The light receiving element 1, the diffusion length R _D, since independent of the size of the p-type semiconductor region and the depletion layer, the equation (1), the radius ratio radius R _V by reducing the first depletion layer 51 R It can be seen that as _{D 1} / R _V is increased, the ratio I _D / I _V increases monotonously. Reducing the radius of the first p-type semiconductor region 31, the radius R _V of the first depletion layer 51 is small. When the ratio _ID / _IV increases, the amount of the hole component from the first extension region 61 to the first p-type semiconductor region 31 increases, and the ratio of the hole component from the first extension region 61 in the photocurrent is increased. Can be increased with respect to the hole component from the first depletion layer 51.

  FIG. 3 is a diagram schematically showing an embodiment of a pixel having three p-type semiconductor regions. 3 is a cross-sectional view taken along line III-III shown in FIG. In the example shown in FIG. 3, a tetrahedral area, for example, a square area is allocated for the light receiving element 1 as one section of the light receiving element array. The length of one side of this area is, for example, 30 μm.

  As shown in FIG. 3, when one structural example of the light absorption region 3 is represented by a two-dimensional plane, the first, second, and third p-type semiconductor regions 31, 32, and 33 are, for example, circular two-dimensional. It is drawn as a shape. The first, second, and third p-type semiconductor regions 31, 32, and 33 have a two-dimensional shape diameter 34D, and the diameter 34D is, for example, 3 μm.

  In the light receiving element 1, in order to avoid a monotonous decrease in the total amount of photocurrent due to simply reducing the size of the first p-type semiconductor region 31, a plurality of p-type semiconductor regions (for example, first, second, and The third p-type semiconductor regions 31, 32, and 33) are provided in one light receiving element 1, and the first, second, and third p-type semiconductor regions 31, 32, and 33 are provided as a single p-electrode 24. Connect to. Since the first, second and third p-type semiconductor regions 31, 32, 33 are spaced apart from each other, depending on the arrangement of the first, second and third p-type semiconductor regions 31, 32, 33 Thus, a plurality of expansion regions (for example, the first, second, and third expansion regions 61, 62, and 63) can be provided to the light receiving element 1 to compensate for the decrease in photocurrent.

  Such a structure of the light receiving element 1 makes it possible to reduce the size of the depletion layer as one pixel in accordance with the reduction of the size of the p-type semiconductor region. Since part of the dark current is generated in the depletion layer, reducing the size of the p-type semiconductor region results in a reduction in the region that generates the dark current. A plurality of p-type semiconductor regions (for example, first, second, and third p-type semiconductor regions 31, 32, and 33) connected to a single p-electrode 24 are provided, and from the viewpoint of dark current, these The p-type semiconductor region (for example, the first, second, and third p-type semiconductor regions 31, 32, and 33) is a depletion layer (for example, the first, second, and third depletion layers) related to the p-type semiconductor region. The layers 51, 52, 53) are preferably arranged so as to overlap. Further, from the viewpoint of photocurrent, the number and arrangement of the p-type semiconductor regions may be extended regions (for example, the first, second, and third p-type semiconductor regions 31, 32, and 33) (for example, The first, second and third expansion regions 61, 62, 63) are preferably determined so as not to overlap.

  More specifically, the image sensor includes individual light receiving elements 1 constituting an array of light receiving elements 1. Therefore, all the light receiving elements 1 have the same size, and the size is, for example, about several tens of micrometers. The photocurrent of one light receiving element 1 is generated from the light incident on the light receiving area. For this reason, a plurality of p-type semiconductor regions (for example, the first, second, and third p-type semiconductor regions 31) are formed so that many portions of the light receiving area serve as an extension region and the dark current of the light receiving element 1 is reduced. , 32, 33).

In order to reduce the dark current and increase the photocurrent, in the example shown in FIG. 3, the distance L1 between the first p-type semiconductor region 31 and the second p-type semiconductor region 32, and the second p-type semiconductor region 32 are used. The distance L2 between the type semiconductor region 32 and the third p-type semiconductor region 33 and the distance L3 between the third p-type semiconductor region 33 and the first p-type semiconductor region 31 may be adjusted. From the viewpoint of dark current, it is preferable that the depletion layers are arranged so as to overlap. At this time, the interval L1 may be L1 = 4 μm to 7 μm. However, when this interval L1 is selected, the photocurrent decreases. On the other hand, from the viewpoint of photocurrent, it is preferable that the extension regions are determined so as not to overlap. The distance L1 at this time can be L1 = 17 μm to 25 μm. However, when this interval L1 is selected, the depletion layer does not overlap, so the dark current also increases. Therefore, the interval L1 is preferably L1 = 7 μm to 12 μm. As a result, it is possible to obtain a balanced characteristic at a level where there is no practical problem with respect to both the dark current and the photocurrent characteristics. According to the inventor's estimate, the diffusion length _RD in this embodiment is, for example, 4 μm.

Hereinafter, based on a specific example, the ratio _ID / _IV of the photocurrent _ID in the extended region to the photocurrent _IV in the depletion layer is calculated. In the example shown in FIG. 3, the intervals L1, L2, and L3 are all 9 μm, for example, and the centers of the circles for the first, second, and third p-type semiconductor regions 31, 32, and 33 are equilateral triangles. It is located at the apex of The first, second, and third depletion layers 51, 52, and 53 are represented as circles that match the shapes of the first, second, and third p-type semiconductor regions 31, 32, and 33, respectively. The first, second, and third depletion layers 51, 52, and 53 each have a diameter 54D. The diameter 54D is a reverse bias voltage (practically used during operation of the light receiving element). Is 1 μm, for example, 8 μm. When the total area of the first, second, and third depletion layers 51, 52, 53 is calculated, this area is 3 × π × (8/2) ² = 151 μm ² .

The first, second, and third expansion regions 61, 62, 63 have, for example, a circular shape, and are defined by the outer edges of the first, second, and third expansion regions 61, 62, 63. Both have a diameter of 64D. The diameter 64D is 16 μm, for example, when the diameter of the depletion layer (8 μm) and the diffusion length into the depletion layer (4 μm × 2 = 8 μm) are combined. Using this diameter 64D, the area of the two-dimensional light absorption region 3 (that is, the region combining the extension region and the depletion layer) is calculated. This area is 3 × when the overlap between the extension regions is not considered. π × (16/2) ² = 603 μm ²

In the example shown in FIG. 3, the extension regions overlap each other, and the overlapped region is subtracted in order to calculate the area of the light absorption region 3. When attention is paid to the overlap between the first extension region 61 and the second extension region 62, the area of the overlap portion (first overlap portion) is 29 μm ² . The area of the second overlap portion between the second extension region 62 and the third extension region 63 and the area of the third overlap portion between the third extension region 63 and the first extension region 61 are the first overlap. It is the same as the area of the part, and both are 29 μm ² . The area of the overlap portion (fourth overlap portion) of the three regions of the first extension region 61, the second extension region 62, and the second extension region 62 is 5 μm ² .

The area of the overlapping portion limited to the two regions of the first extended region 61 and the second extended region 62 is obtained by subtracting the area of the fourth overlapping portion from the area of the first overlapping portion. 5 the area of the overlapped portion) is 29μm ² -5μm ² = 24μm ^2. Similarly, the area of the overlapping portion (sixth overlapping portion) limited to the two regions of the second extension region 62 and the third extension region 63, and the third extension region 63 and the first extension region 61. The area of the overlapping portion (seventh overlapping portion) limited to the two regions is 24 μm ² . In the example shown in FIG. 3, the area of the overlap between the extended regions, that is, the total of the four regions of the fourth overlap portion, the fifth overlap portion, the sixth overlap portion, and the seventh overlap portion is 5 μm ² + 3 × 24 μm ² = 77 μm ² .

From the above, when the area of the light absorption region 3 is calculated in consideration of the overlap between the extension regions, this area is 603 μm ² −77 μm ² = 526 μm ² . Of the area of the light absorption region 3, the total area of the first, second, and third depletion layers 51, 52, 53 is 151 μm ^{2 as} described above, so the first, second, and third total area of the expansion region 61, 62, 63 is subtracted the area of the depletion layer from the area of the light-absorbing region 3 is 526μm ² -151μm ² = 375μm ^2. In the example of the light receiving element 1 shown in FIG. 3, the ratio of the photocurrent _ID in the expansion region to the photocurrent _IV in the depletion layer ( _ID / _IV ) ₁ is calculated as ( _ID / _IV ) ₁ = is a ^{(375μm 2 / 151μm 2) =} 2.5.

  FIG. 4 is a diagram schematically showing a light receiving element having a single p-type semiconductor region. Part (a) of FIG. 4 shows a plan view of the light receiving element array 2Q. Part (b) of FIG. 4 is a cross-sectional view taken along line IVb-IVb shown in part (a) of FIG. In this embodiment, the light receiving element array 2Q includes an array of two-dimensional light receiving elements 1Q. In this embodiment, nine light receiving element arrays are shown.

  For easy understanding, the light receiving element 1Q is provided in a square area of the same size as the light receiving element 1 in FIG. 1 and has a single p-type semiconductor region 30 formed in the semiconductor multilayer structure. The p-type semiconductor region 30 is connected to the p electrode 24.

As shown in part (b) of FIG. 4, the p-type semiconductor region 30 extends from the upper surface 20A of the semiconductor stack 20Q toward the substrate 10Q. In the semiconductor stacked layer 20Q, the p-type semiconductor region 30 forms a junction with the light receiving layer 21Q, and this junction is referred to as a PN junction 40. A depletion layer 50 is formed in the light receiving layer 21 at the PN junction 40. In the light receiving element 1Q, the p-type dopant concentration of the p-type semiconductor region 30 is, for example, about 5 × 10 ¹⁶ cm ⁻³ . For ease of understanding, in the p-type semiconductor region 30, the depth 30H from the upper surface 20A of the semiconductor stack 20Q is substantially the same as the depth 34H.

In the light receiving element 1Q, the light receiving layer 21Q includes an eleventh region 40p and a twelfth region 40q. The eleventh region 40p is located inside the PN junction 40, and the twelfth region 40q is located outside the PN junction 40. The eleventh region 40p has p-type conductivity. The twelfth region 40q has n-type conductivity. The hole concentration in the eleventh region 40p is 5 × 10 ¹⁶ cm ⁻³ , and the electron concentration in the twelfth region 40q is 2 × 10 ¹⁵ cm ⁻³ .

FIG. 5 is a cross-sectional view taken along the line VV shown in FIG. 4B. In FIG. 5, the cross-sectional shape of the p-type semiconductor region 30 is a circle having a diameter of 18 μm, and the diameter 50D of the depletion layer 50 generated by the PN junction 40 is the reverse bias voltage applied during the operation of the light receiving element. Specifically, it is 23 μm at 1 volt, for example. In the light receiving element 1Q, the area of the depletion layer 50 in the light absorption region 3Q is π × (23/2) ² = 415 μm ² .

Also in the light receiving element 1Q, the extended region 60 is formed around the depletion layer 50, and in this embodiment, the diffusion length _RD is 4 μm, for example. In the light receiving element 1Q, when the diameter (23 μm) of the depletion layer 50 is combined with the diffusion length (4 μm × 2 = 8 μm) into the depletion layer 50, the diameter 60D of the expansion region 60 is, for example, 31 μm. When the area of the light absorption region 3Q of the light receiving element 1Q is calculated using the diameter 60D, this area is π × (31/2) ² = 754 μm ² . The area of the extended region 60 is obtained by subtracting the area of the depletion layer 50 and is 754 μm ² −415 μm ² = 339 μm ² . The ratio of the light receiving element _{1Q (I D / I V)} 1Q _is a _{(I D / I V) 1Q} = (339μm 2 / 415μm 2) = 0.82.

The total area (151 μm ² ) of the first, second and third depletion layers 51, 52 and 53 of the light receiving element 1 in FIG. 1 is equal to the area (415 μm ² ) of the depletion layer 50 in the light receiving element 1Q in FIG. Smaller than that. However, as can be seen from the equation (1), in the light receiving element 1 of FIG. 1, the area (375 μm ² ) of the first, second and third extension regions 61, 62, 63 is smaller than that of the light receiving element 1Q of FIG. It becomes larger than the area (339 μm ² ) of the extended region 60. As a result, the ratio (I _D / I _V ) _1Q is 0.82, whereas (I _D / I _V ) ₁ is 2.5. In the light receiving element 1, the decrease in photocurrent due to the small size of the first, second, and third p-type semiconductor regions 31, 32, 33 is caused by the first, second, and third extension regions 61, 62, 63. It is compensated. The light receiving element 1 collects the photocurrent to the p-electrode 24 using the extension regions (for example, the first, second, and third extension regions 61, 62, 63).

As already described, the dark current generated in the light receiving layer gradually increases as the size of the depletion layer in the light absorption region increases. Since the carrier diffusion length _RD is constant regardless of the size of the depletion layer, as the size of the depletion layer per light receiving element decreases, the ratio of the extended region to the light absorption region increases. The rate decreases. Depletion area of cross-section shown in Figure 3 of the light receiving element 1 (151μm ²⁾ is 36% of the depletion layer area of the light receiving element 1Q (415μm ^2). As the depletion layer area is reduced to 36%, the light receiving element 1 in FIG. 1 can reduce the dark current generated in the depletion layer as compared with the light receiving element 1Q in FIG.

  FIG. 6 is a diagram showing the relationship between the photocurrent and dark current of the light receiving element according to the first embodiment and the area of the p-type semiconductor region. For comparison, FIG. 6 also shows the relationship between the photocurrent and dark current of the light receiving element 1Q of FIG. 4 and the area of the p-type semiconductor region. The light absorption regions 3 and 3Q are considered in a two-dimensional plane.

As shown in FIG. 6, in the light receiving element 1 </ ^b > Q of FIG. 4, the photocurrent value gradually increases from the value of 1.0 × 10 ⁻¹⁰ A, where the area of the p-type semiconductor region is about 20 μm ² , The amount of increase in photocurrent gradually decreases. 4 and 5 has a square shape, and the p-type semiconductor region and the extension region have a circular shape. Therefore, the edge of the circular extension region 60 contacts the four sides of the square before contacting the four vertices of the square. In the light receiving element 1Q, the diameter 3D of the light absorption region 3Q is obtained by subtracting the increase (5 μm) due to the depletion layer 50 and the increase (8 μm) due to the expansion region 60. When contacting or intersecting four square sides (length 30 μm) in the light absorption region 3Q, the diameter 30D of the p-type semiconductor region is 30D = 30 μm− (5 μm + 8 μm) = 17 μm, and the area of the p-type semiconductor region Is π × (17/2) ² = 227 μm ² . Therefore, due to the difference in shape between the p-type semiconductor region and the light receiving element, the increase rate of the area of the p-type semiconductor region decreases from the point where the area of the p-type semiconductor region exceeds, for example, about 227 μm ^2. Accordingly, the increase rate of the photocurrent is saturated.

The dark current increases in proportion to the size of the depletion layer 50, and the diameter 50D of the depletion layer 50 is obtained by subtracting the increase due to the diffusion region (8 μm). When contacting or intersecting four square sides (length 30 μm) in the light absorption region 3Q, the diameter 50D of the depletion layer 50 is 50D = 30 μm−8 μm = 22 μm, and the area of the depletion layer 50 is π × (22/2) ² = 380 μm ² . Therefore, only when the depletion layer area exceeds, for example, about 380 μm ² , the increase rate of the depletion layer area decreases, and the increase rate of the dark current is saturated accordingly.

When the area of the p-type semiconductor region on the horizontal axis in FIG. 6 is 20 μm ² , the dark current value, the photocurrent value, and the photocurrent with respect to the dark current in the light receiving element 1 in FIG. 1 and the light receiving element 1Q in FIG. The ratio (dark current / photocurrent) is summarized as follows.
Name of light receiving element, dark current value (A), photocurrent value (A), dark current / photocurrent.
The light receiving element of FIG. 1, 1.8 × 10 ⁻¹² , 3 × 10 ⁻¹⁰ , 6 × 10 ⁻³ .
The light receiving element of FIG. 4, 9 × 10 ⁻¹³ , 1.3 × 10 ⁻¹⁰ , 7 × 10 ⁻³ .
Comparing the dark current / photocurrent in the two light receiving elements, the dark current / photocurrent value of the model corresponding to the light receiving element 1 in FIG. 1 is the dark current / photocurrent of the model corresponding to the light receiving element 1Q in FIG. Compared to the value of. In the model corresponding to the light receiving element 1 in FIG. 1, since the ratio of the depletion layer per one light receiving element is smaller than that in the model corresponding to the light receiving element 1Q in FIG. 4, the dark current generated in the depletion layer can be reduced. Is shown.

  In the light receiving element, in one embodiment, the light receiving layer 21 may have a type II type InGaAs / GaAsSb quantum well structure. Since carriers easily diffuse at the interface of the type II hetero barrier, the amount of carriers diffused from the extended region to the depletion layer increases. Since this light receiving element can reduce the bias voltage applied to the depletion layer, the dark current can be further reduced. The light receiving layer 21 may include an InGaAsP layer, a GaAsSb layer, and a GaInNAs layer in addition to undoped InGaAs and type II type InGaAs / GaAsSb quantum wells.

  FIG. 7 is a diagram schematically showing main steps in the method of manufacturing the light receiving element according to the first embodiment. Hereinafter, a method for producing the light receiving element 1 will be schematically described. In this description, for ease of understanding, reference numerals of components of the light receiving element 1 shown in FIG. 1 are used where possible.

  In the first step, the substrate 10 is prepared. The substrate 10 can be, for example, an n-type InP wafer. As shown in part (a) of FIG. 7, the semiconductor stack 20 is grown on the substrate 10. For this growth, for example, metal organic vapor phase epitaxy (OMVPE) method or molecular beam epitaxy (MBE) method is applied. As shown in part (a) of FIG. 7, the light receiving layer 21 of the semiconductor stack 20 is grown on the main surface of the substrate 10 in the plane orientation (100). The light receiving layer 21 includes an undoped InGaAs layer. A semiconductor layer 22 is grown on the light receiving layer 21. The semiconductor layer 22 includes, for example, n-type InP. In the first step, if necessary, a buffer layer may be grown on the main surface of the substrate 10 before the light receiving layer 21 is grown.

In the second step, a dielectric film 23 is grown on the semiconductor layer 22 as shown in part (b) of FIG. The dielectric film 23 includes, for example, a Si-based inorganic insulating layer, and more specifically includes, for example, a SiN film, a SiO ₂ film, and a SiON film. In this embodiment, a SiN film is used as the dielectric film 23, and this SiN film is formed by, for example, a plasma CVD method. The thickness of the SiN film is, for example, 500 nm. Next, an opening 23N for selective diffusion is formed in the dielectric film 23 by using, for example, a photolithography method and an etching method. The number of openings 23N can be, for example, three per element section, and can have a circular shape. The shape of the opening 23N is not limited to a circle, and can be, for example, a square or a rectangle. When the opening 23N has a circular shape, the diameter 23D is, for example, 3 μm. Through these steps, a semiconductor substrate product is produced.

  In the third step, a p-type semiconductor region is formed as shown in part (c) of FIG. The p-type semiconductor region is formed by, for example, a vapor phase diffusion method using red phosphorus, arsenic, and zinc. In the vapor phase diffusion method, a semiconductor substrate product is enclosed in a quartz tube and placed under vacuum. Next, Zn is diffused by a heat treatment at 500 ° C. for 30 minutes to form a p-type semiconductor region. The p-type semiconductor region extends from the upper surface 20 </ b> A of the semiconductor stack 20 toward the substrate 10 and reaches the light receiving layer 21. The depth 30H of the p-type semiconductor region can be, for example, 1.5 μm from the upper surface 20A of the semiconductor stack 20.

In the fourth step, as shown in FIG. 7D, the electrodes and the antireflection film are formed. A p-electrode 24 connected to the p-type semiconductor region is formed. Next, the back surface 10B of the substrate 10 is polished, and the antireflection film 25 and the n electrode 26 are formed. Specifically, these steps will be described. The p-electrode 24 is formed by a photolithography technique and a lift-off process using vapor deposition. A resist mask for the p-electrode 24 is formed on the dielectric film 23 of the semiconductor substrate product, and then a metal film for the p-electrode 24 is deposited on the entire surface of the semiconductor substrate product in a vacuum evaporation furnace. The Thereafter, the p-electrode 24 is formed by lift-off using a resist mask. While the back surface 10B of the substrate 10 is mirror-polished, an antireflection film 25 and an n-electrode 26 are formed. The thickness of the substrate 10 after polishing is, for example, 350 μm. The antireflection film 25 includes, for example, a SiO ₂ film or a SiON film, and the thickness of the antireflection film 25 is, for example, 300 nm. The antireflection film 25 is provided with an opening 25N for each chip, and an n-electrode 26 is formed in the opening 25N by a lift-off process. The material of the p electrode 24 and the n electrode 26 can be, for example, Ti / Pt / Au. Through these steps, a substrate product for the light receiving element 1 is produced. The substrate product is divided by dicing and / or cleaving to produce a light receiving element array 2 including the light receiving elements 1.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

  According to the present embodiment, it is possible to provide a light receiving element that can collect the photocurrent to the p-side electrode by effectively using the extension region.

DESCRIPTION OF SYMBOLS 1 ... Light receiving element, 10 ... Board | substrate, 20 ... Semiconductor laminated layer, 21 ... Light receiving layer, 24 ... P electrode, 31 ... 1st p-type semiconductor region, 32 ... 2nd p-type semiconductor region, 33 ... 3rd p Type semiconductor region, 41 ... first PN junction, 42 ... second PN junction, 43 ... third PN junction.

Claims (2)

A substrate,
A semiconductor stack stacked on the substrate;
A plurality of p-type semiconductor regions provided in the semiconductor stack;
One electrode provided on the semiconductor stack;
With
The plurality of p-type semiconductor regions are provided from the upper surface of the semiconductor stack toward the substrate,
The semiconductor stack has a light receiving layer,
The semiconductor stack has a plurality of PN junctions at the boundary between the light receiving layer and the plurality of p-type semiconductor regions,
A light receiving element in which the plurality of p-type semiconductor regions are connected to the one electrode.   The light receiving element according to claim 1, wherein the light receiving layer has a type II InGaAs / GaAsSb quantum well structure.

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