JP2016213917A - Semiconductor module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor module capable of properly avoiding interference of noise at respective power terminals of a U-phase coil, a V-phase coil and a V-phase coil of a three-phase motor and achieving further downsizing of a module substrate.SOLUTION: A semiconductor module comprises: semiconductor elements each of which has electrodes on each of a top face and on an undersurface; leads which join to the electrode on the top face and some of which has one end having a second substrate joint surface which extends to a virtual plane including a first substrate joint surface corresponding to a joint surface between the electrodes on the undersurface of the semiconductor element and a module substrate; leads 61G-63G, 71G-73G, 81G-83G, 63S, 73S and 83S corresponding to a motor control input part in which the first and second substrate joint surfaces of an intermediate module where the leads are joined to the top face of the semiconductor element are joined to a module substrate 50, for controlling an operation of an arm circuit, and an arm circuit output part corresponding to an output of the arm circuit are provided at a distance from the module substrate without being connected to the module substrate.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor module in which a semiconductor element is mounted on a module substrate.

  In recent years, for example, in the case of a vehicle, it is required to reduce the size and weight of parts in order to improve fuel consumption and reduce costs. Since semiconductor elements used for driving electric motors or the like generate a relatively large amount of heat, they are generally mounted on a small module substrate with good heat dissipation. Such a semiconductor element is mounted on a module substrate and configured as a semiconductor module.

  For example, in Patent Document 1, a plurality of semiconductor elements constituting three inverter circuits that supply power to each of a U-phase coil, a V-phase coil, and a W-phase coil of a three-phase motor, and power are supplied to the inverter circuit A semiconductor module is disclosed in which a plurality of semiconductor elements constituting a power relay to be mounted are mounted on one module substrate. One side of the module board is provided with a plurality of wide power terminals, which are input / output terminals through which a large current flows, and the other side of the module board is an input / output through which a small current for controlling each semiconductor element flows. A plurality of narrow control terminals which are terminals are provided. The module board is input to two inverter input terminals that supply power to each inverter circuit, two inverter ground terminals for grounding each inverter circuit, and a power supply relay that controls power supplied to each inverter circuit. One power input terminal, one U-phase winding terminal that outputs power to the U-phase coil, one V-phase winding terminal that outputs power to the V-phase coil, and power to the W-phase coil Eight power terminals including one W-phase winding terminal are provided.

JP 2011-250491 A

  The power to be supplied to each of the U-phase coil, V-phase coil, and W-phase coil of the three-phase motor is a large current and may be repeatedly turned on and off in a very short time. Multiple noises are likely to occur. Therefore, if the power terminal to the U-phase coil, the power terminal to the V-phase coil, and the power terminal to the W-phase coil are arranged close to each other on the module substrate, there is a possibility that noise from the terminals mutually interferes. Therefore, it is not preferable.

  As a method for avoiding the interference of noise, a method of increasing the interval between the power terminals and a method of changing the layer for each power terminal by using a module substrate as a multilayer substrate structure are conceivable. However, the method of increasing the interval between the power terminals is not preferable because the size of the module substrate increases and the semiconductor module increases in size. Even if the interval between the power terminals is increased, there is no meaning unless the interval between the wiring elements (wiring patterns formed on the module substrate) from the semiconductor elements mounted on the module substrate to the power terminals is increased. This is not preferable because the size of the substrate is further increased. Also, the method of making the module substrate a multilayer substrate structure is not preferable because the heat dissipation is reduced and the cost is increased.

  Therefore, in the semiconductor module described in Patent Document 1, a U-phase winding terminal that outputs power to the U-phase coil, a V-phase winding terminal that outputs power to the V-phase coil, and a W that outputs power to the W-phase coil. Each of the phase winding terminals is arranged so as to be sandwiched between an inverter input terminal (power supply terminal) and an inverter ground terminal (earth terminal). In the semiconductor module described in Patent Document 1, an inverter ground terminal is disposed between the U-phase winding terminal and the V-phase winding terminal, and between the V-phase winding terminal and the W-phase winding terminal. Is provided with an inverter input terminal. In the semiconductor module described in Patent Document 1, noise interference from the U-phase winding terminal, the V-phase winding terminal, and the W-phase winding terminal is suppressed by the inverter input terminal or the inverter ground terminal sandwiched therebetween. The number of inverter input terminals and inverter ground terminals can be increased. Therefore, the size of the module substrate is increased by the increased number of terminals, which is not preferable.

  The present invention was devised in view of such points, and can appropriately avoid noise interference of each power terminal that is an output to the U-phase coil, V-phase coil, and W-phase coil of the three-phase motor. A further object is to provide a semiconductor module capable of further reducing the size of the module substrate.

  In order to solve the above problems, the semiconductor module according to the present invention takes the following means. A first aspect of the present invention is a semiconductor module in which a semiconductor element is mounted on a module substrate, wherein three arm circuits for driving a three-phase motor are constituted by the semiconductor element. Each has an upper surface and a lower surface, and has an electrode on each of the upper surface and the lower surface. Each of the leads on the upper surface of each of the semiconductor elements is joined to each lead formed of a conductor and associated with the electrode, and one end of a part of the leads is formed on the lower surface of the semiconductor element. It has the 2nd board | substrate joint surface extended to the virtual plane containing the 1st board | substrate joint surface equivalent to the joint surface of an electrode and the said module substrate. Each of the semiconductor elements is configured as an intermediate module in which the leads are bonded to an upper surface, and the first substrate bonding surface and the second substrate bonding surface of each of the intermediate modules are connected to the module substrate. The leads corresponding to the motor control input unit that is bonded and controls the operation of the arm circuit and the arm circuit output unit corresponding to the output of the arm circuit are connected to the module substrate without being connected to the module substrate. The module substrate is disposed apart from the module substrate.

  Next, a second invention of the present invention is the semiconductor module according to the first invention, wherein three motor relays configured by the semiconductor elements are connected to outputs of the three arm circuits. And the lead corresponding to the output part of the motor relay serving as the arm circuit output part and the motor relay control input part for controlling the operation of the motor relay, without being connected to the module substrate. The module substrate is disposed apart from the module substrate.

  Next, a third invention of the present invention is the semiconductor module according to the first invention or the second invention, wherein the intermediate module has one arm circuit when the motor relay is not included. In the case of having the motor relay, it is constituted by one arm circuit and one motor relay. The wiring pattern formed on the module substrate includes a first internal wiring pattern which is a wiring pattern used for connecting the semiconductor elements in the intermediate module, and a power-related wiring from any of the semiconductor elements. The power supply that is a wiring pattern for power supplied to each of the arm circuits except for a second internal wiring pattern that is a wiring pattern used for a predetermined electronic component connected to a pattern or a GND wiring pattern Only the related wiring pattern and the GND wiring pattern which is a wiring pattern for grounding the arm circuit are formed.

  Next, a fourth invention of the present invention is the semiconductor module according to any one of the first to third inventions, wherein the semiconductor element outputs power supplied to each of the arm circuits. The intermediate module includes one arm circuit when the motor relay is not included, and one arm circuit and one when the motor relay is included. A first intermediate module including the two motor relays, and a second intermediate module including the power relay, wherein each of the first intermediate module and the second intermediate module includes the first substrate. The module substrate is covered with a molding material such that the bonding surface and the second substrate bonding surface are exposed and the leads protrude, and the module substrate includes three first intermediate modules. And Yuru, and one of said second intermediate module, are bonded.

  According to the first invention, the lead (corresponding to the power terminal) corresponding to the arm circuit output corresponding to the output to the U-phase coil, V-phase coil and W-phase coil of the three-phase motor is connected to the module substrate. Without being spaced apart from the module substrate. That is, the leads serving as power terminals for the U-phase coil, the V-phase coil, and the W-phase coil are not provided on the module substrate, but are projected from the intermediate module. Therefore, since the interval between adjacent intermediate modules is the interval between the leads serving as power terminals to the U-phase coil, V-phase coil, and W-phase coil, a sufficient interval can be secured and noise interference can be ensured. Can be avoided appropriately. In addition, it is not necessary to provide each of the leads serving as power terminals for the U-phase coil, V-phase coil, and W-phase coil on the module substrate, and the number of power terminals arranged on the module substrate can be reduced. Can be further reduced in size. Also, it is not necessary to provide a control terminal (motor control input unit) for controlling the semiconductor element on the module substrate, and the number of control terminals arranged on the module substrate can be reduced, so that the size of the module substrate is further reduced. can do.

  According to the second invention, by providing a motor relay at the output part of the arm circuit, a semiconductor module that can control the three-phase motor more safely can be configured. Also, a lead (corresponding to a power terminal) corresponding to the output part of the motor relay and a lead (corresponding to the control terminal) corresponding to the motor relay control input part are arranged apart from the module substrate. Therefore, since the number of power terminals arranged on the module substrate and the number of control terminals arranged on the module substrate can be reduced, the size of the module substrate can be further reduced.

  According to the third aspect of the present invention, only the power supply related wiring pattern and the GND wiring pattern are formed on the module substrate except for the first internal wiring pattern and the second internal wiring pattern. Therefore, it is not necessary to make the module substrate multilayer, and it is possible to realize a small and low-cost semiconductor module having good heat dissipation (low thermal resistance). In addition, since there are few types of wiring patterns, the degree of freedom of wiring is high. For example, if a layout in which a power-related wiring pattern and a GND wiring pattern are arranged in parallel, a noise canceling effect can be expected more.

  According to the fourth aspect of the present invention, the module substrate is mounted with the semiconductor elements constituting the three arm circuits for driving the three-phase motor, or the three arm circuits and motor relays, and the power supply relay. It is possible to realize a semiconductor module.

It is an example of the electronic circuit implement | achieved by a semiconductor module. It is a perspective view explaining the example of the external appearance of a semiconductor element. It is a whole perspective view of the semiconductor module which mounted the intermediate module covered with the mold material on the module board. It is the figure which looked at the semiconductor module shown in FIG. 3 from IV direction. It is the figure which looked at the semiconductor module shown in FIG. 3 from the V direction.

  Hereinafter, embodiments of the present invention will be described in order with reference to the drawings.

● [Example of electronic circuit to be realized (Fig. 1)]
In recent years, an electronic circuit using a MOSFET has been used as a drive circuit for an electric motor that requires a relatively large current. For example, a drive circuit for each phase of a three-phase motor having a U-phase coil, a V-phase coil, and a W-phase coil. There is an electronic circuit shown in FIG. The electronic circuit includes a U phase circuit 10 that outputs power to the U phase coil, a V phase circuit 20 that outputs power to the V phase coil, a W phase circuit 30 that outputs power to the W phase coil, and a U phase circuit. 10, a power relay circuit 40 (corresponding to a power relay) that supplies power to the V phase circuit 20 and the W phase circuit 30. Moreover, Tr11-13, Tr21-23, Tr31-33, Tr41, Tr42 which are the semiconductor elements used for each circuit are n channel MOSFETs, respectively, of gate (G), source (S), and drain (D). Each electrode is provided.

  The U-phase circuit 10 includes an arm circuit (inverter circuit) configured by the semiconductor element Tr11 and the semiconductor element Tr12, and a motor relay configured by the semiconductor element Tr13 that permits or blocks output from the arm circuit. It is configured. The drain D11 of the semiconductor element Tr11 is connected to the relay output power supply Vrout via the power supply Vu +, and the source S11 of the semiconductor element Tr11 is connected to the drain D12 of the semiconductor element Tr12 and the drain D13 of the semiconductor element Tr13. An input Vuin1 that is a control signal from a control means (a control device such as a computer that controls a three-phase motor) (not shown) is input to the gate G11 of the semiconductor element Tr11.

  The drain D12 of the semiconductor element Tr12 is connected to the source S11 of the semiconductor element Tr11 and the drain D13 of the semiconductor element Tr13, and the source S12 of the semiconductor element Tr12 is connected to the ground GND via the ground Vu−. An input Vuin2 that is a control signal from a control unit (not shown) is input to the gate G12 of the semiconductor element Tr12.

  The drain D13 of the semiconductor element Tr13 is connected to the source S11 of the semiconductor element Tr11 and the drain D12 of the semiconductor element Tr12, and the source S13 of the semiconductor element Tr13 is connected to the U-phase coil as the U-phase output Vuout. An input Vuin3 that is a control signal from a control unit (not shown) is input to the gate G13 of the semiconductor element Tr13. An output Vum (monitoring output) is output from the drain D13 of the semiconductor element Tr13 to the control means.

  The V-phase circuit 20 includes an arm circuit (inverter circuit) configured by the semiconductor element Tr21 and the semiconductor element Tr22, and a motor relay configured by the semiconductor element Tr23 that permits or blocks output from the arm circuit. It is configured. Note that the connection of the semiconductor elements Tr21, Tr22, Tr23 and the like is the same as the connection of the semiconductor elements Tr11, Tr12, Tr13 described above, and a description thereof will be omitted.

  The W-phase circuit 30 includes an arm circuit (inverter circuit) configured by the semiconductor element Tr31 and the semiconductor element Tr32, and a motor relay configured by the semiconductor element Tr33 that permits or blocks output from the arm circuit. It is configured. Note that the connection of the semiconductor elements Tr31, Tr32, Tr33 and the like is the same as the connection of the semiconductor elements Tr11, Tr12, Tr13, and the description thereof will be omitted.

  The power supply relay circuit 40 is composed of at least one semiconductor element. In the present embodiment, an example where the power relay circuit 40 is composed of two semiconductor elements Tr41 and Tr42 will be described. The drain D41 of the semiconductor element Tr41 is connected to a power supply Vdd (a battery in the case of a vehicle), and the source S41 of the semiconductor element Tr41 is connected to the source S42 of the semiconductor element Tr42. An input Vrin1 that is a control signal from a control unit (not shown) is input to the gate G41 of the semiconductor element Tr41.

  From the drain D42 of the semiconductor element Tr42, a relay output power supply Vrout that is a power supply for the U-phase circuit 10, the V-phase circuit 20, and the W-phase circuit 30 is output. The source S42 of the semiconductor element Tr42 is connected to the source S41 of the semiconductor element Tr41. An input Vrin2 that is a control signal from a control unit (not shown) is input to the gate G42 of the semiconductor element Tr42. Further, an output Vrm (monitoring output) is output from the sources S41 and S42 of the semiconductor elements Tr41 and Tr42 to the control means. Note that a capacitor C1 is connected between the relay output power supply Vrout and GND (ground), but the capacitor C1 is connected to the outside of the semiconductor module without being mounted on the semiconductor module. Is shown. The input Vuin1 to input Vuin3, input Vvin1 to input Vvin3, and input Vwin1 to input Vwin3 correspond to motor control input units that control the operations of the U-phase circuit 10, V-phase circuit 20, and W-phase circuit 30 that are arm circuits. To do. Further, the U-phase output Vuout, the V-phase output Vvout, and the W-phase output Vwout correspond to an arm circuit output unit corresponding to the output of the arm circuit. When the semiconductor elements Tr13, Tr23, and Tr33 are omitted, the source of the semiconductor element Tr11, the source of the semiconductor element Tr21, and the source of the semiconductor element Tr31 correspond to an arm circuit output unit corresponding to the output of the arm circuit. .

[External appearance of semiconductor element (FIG. 2) and wiring patterns of semiconductor module 1 and module substrate 50 (FIGS. 3 to 5)]
The semiconductor elements Tr11 to Tr13, Tr21 to Tr23, Tr31 to Tr33, Tr41, and Tr42 described in the present embodiment are all n-channel MOSFETs and have the same shape. Therefore, the external appearance of the semiconductor element will be described by taking the semiconductor element Tr11 as an example. The semiconductor element Tr11 has a substantially rectangular plate shape with a side of several [mm], and as shown in FIG. 2, a source S11 (source electrode) and a gate G11 (gate electrode) are formed on the surface. Is formed. A drain D11 (drain electrode) is formed on the entire back surface of the semiconductor element Tr11. The source S11 and the drain D11 through which a relatively large current flows have a large area, and the gate G11 through which almost no current flows has a very small area.

  The semiconductor elements Tr11, Tr12, Tr13 constituting the U-phase circuit 10 in FIG. 1 constitute an intermediate module covered with a molding material such as resin, and the semiconductor elements Tr21, Tr22, Tr23 constituting the V-phase circuit 20 are The semiconductor elements Tr31, Tr32, and Tr33 constituting the intermediate module covered with the mold material and constituting the W-phase circuit 30 constitute the intermediate module covered with the mold material. The semiconductor elements Tr41 and Tr42 constituting the power relay circuit 40 in FIG. 1 constitute an intermediate module covered with a molding material. These intermediate modules are further resin-molded as a whole (see FIG. 3).

  The module substrate 50 has a power supply related wiring pattern, a GND wiring pattern, a first internal wiring pattern, and a second internal wiring pattern formed on the surface of a substantially rectangular base substrate. That is, the wiring patterns formed on the module substrate 50 are formed with only the power-related wiring pattern and the GND wiring pattern except for the first internal wiring pattern and the second internal wiring pattern.

  Power terminals T1, T2, and T3 are provided on one side of the base substrate. On the surface of the module substrate 50, mounting regions for mounting the semiconductor elements Tr11, Tr12, Tr13 are prepared, mounting regions for mounting the semiconductor elements Tr21, Tr22, Tr23 are prepared, and the semiconductor elements Tr31, Tr32, Tr33 are mounted. A mounting area is prepared, and a mounting area for mounting the semiconductor elements Tr41 and Tr42 is prepared.

  In the power supply related wiring pattern, power is supplied to the power supply related wiring pattern to which the power terminal T1 is connected and the relay output power supply Vrout shown in FIG. 1, which is the U phase circuit 10, the V phase circuit 20, and the W phase circuit 30. And power supply related wiring patterns. The power terminal T1 is a terminal connected to the power supply Vdd in FIG. 1, and the power supply related wiring pattern is a wiring pattern for the power supply Vdd input to the power supply relay circuit 40 in FIG. A power terminal T3 is connected to the power supply related wiring pattern.

  The GND wiring pattern is a wiring pattern to which the power terminal T2 is connected. The power terminal T2 is a terminal connected to GND (ground) in FIG.

  The first internal wiring patterns 53u, 53v, 53w are wiring patterns used for connecting semiconductor elements in each intermediate module.

  The second internal wiring pattern (not shown) is a wiring pattern used for a predetermined electronic component connected from one of the semiconductor elements to the power supply related wiring pattern or the GND wiring pattern. For example, in the electronic circuit shown in FIG. 1, between ground Vu− and GND, between ground Vv− and GND, between ground Vw− and GND, or between relay output power supply Vrout and power supply Vu +. , A shunt resistor (predetermined electronic component) for current detection is provided at each position between the relay output power source Vrout and the power source Vv + and between the relay output power source Vrout and the power source Vw +. A second internal wiring pattern may be provided as a wiring pattern. In this case, the second internal wiring pattern for the shunt resistor has a routing length of almost zero and becomes a wiring pattern of only the land.

  As described above, the wiring patterns formed on the module substrate 50 are only the power-related wiring pattern and the GND wiring pattern except for the first internal wiring pattern and the second internal wiring pattern. Yes. That is, the module substrate 50 is not provided with the power terminals of the U-phase output Vuout, the V-phase output Vvout, and the W-phase output Vwout in FIG. Further, on the module board 50, the control terminals of input Vuin1 to Vuin3, output Vum, input Vvin1 to Vvin3, output Vvm, input Vwin1 to Vwin3, output Vwm, input Vrin1, Vrin2, and output Vrm in FIG. There is no wiring pattern for terminals.

● [Semiconductor module manufacturing method]
The intermediate module composed of the semiconductor elements Tr11 to Tr13 has a heat spreader bonded to the lower surface of each of the semiconductor elements Tr11 to Tr13, and leads corresponding to the electrodes on the upper surface of the semiconductor elements Tr11 to Tr13. And the semiconductor element to which the lead is bonded is covered with a molding material. The first substrate bonding surface which is the lower surface of each heat spreader and is bonded to the module substrate by solder or the like, and the second substrate bonding surface which is the lower surface of some leads and is bonded to the module substrate by solder or the like is a mold. Exposed from the material. The first substrate bonding surface is a surface corresponding to the bonding surface between the electrode on the lower surface of the semiconductor element (in this case, the drain electrode) and the module substrate. When the heat spreader is not bonded, the lower surface of the semiconductor element is bonded to the first substrate. When the heat spreader is bonded, the lower surface of the heat spreader corresponds to the first substrate bonding surface. The second substrate bonding surface is a lower surface of a part of the leads extending to a virtual plane including the first substrate bonding surface (that is, the surface of the module substrate). In the example of FIG. 3, the lower surfaces of the leads 62S, 72S, and 82S that are bonded to the module substrate 50 correspond to the second substrate bonding surface.

  The heat spreader is a member made of a conductive material such as copper and formed in a plate shape with a material having good heat dissipation. The upper surface of the heat spreader has an area covering the drain electrode, which is the lower surface of the corresponding semiconductor element, and the entire drain electrode, which is the electrode on the lower surface of the semiconductor element, is joined by solder or the like to dissipate heat from the semiconductor element. To encourage. The lower surface of the heat spreader serves as a first substrate bonding surface bonded to the module substrate. The drain of the lower surface of each semiconductor element is joined to the upper surface of the heat spreader.

  The lead frame has leads connected to the source and gate, which are the electrodes of the semiconductor elements Tr11 to Tr13, and the leads are formed of a conductor such as copper. The lead frame is connected to the lead 61G joined to the gate G11 of the semiconductor element Tr11, the lead 61S joined to the source S11 of the semiconductor element Tr11, the lead 62G joined to the gate G12 of the semiconductor element Tr12, and the source S12 of the semiconductor element Tr12. The lead 62S is joined, the lead 63G is joined to the gate G13 of the semiconductor element Tr13, and the lead 63S is joined to the source S13 of the semiconductor element Tr13. Each lead is positioned relative to each other by a frame and a runner (not shown).

  One end of the lead 61G is joined (or connected by a bonding wire) to the gate G11 of the semiconductor element Tr11. The other end of the lead 61G becomes a control terminal (input Vuin1).

  One end of the lead 62G is joined (or connected by a bonding wire) to the gate G12 of the semiconductor element Tr12. The other end of the lead 62G serves as a control terminal (input Vuin2).

  One end of the lead 63G is joined (or connected by a bonding wire) to the gate G13 of the semiconductor element Tr13. The other end of the lead 63G is a control terminal (input Vuin3). One end of the lead 63S is joined to the source S13 of the semiconductor element Tr13. The other end of the lead 63S serves as a power terminal (U-phase output Vuout).

● [Appearance of semiconductor module (Figs. 3-5)]
3 to 5, power terminals T1 (Vr +), T2 (GND), T3 (Vrout), power terminals 63S (U-phase output Vuout), 73S (V-phase output Vvout), 83S ( In the W-phase output Vwout), only three power terminals T1 (Vr +), T2 (GND), and T3 (Vrout) are provided on the module substrate 50. Leads 63S, 73S, and 83S that are output portions of the semiconductor elements Tr13, Tr23, and Tr33 that are motor relays are arranged at appropriate intervals. The leads 63S, 73S, 83S are arranged so as to be separated from the module substrate 50 in the air without being connected to the module substrate 50. Therefore, wiring patterns for the leads 63S, 73S, and 83S that are power terminals are not formed on the module substrate 50. Thereby, it is possible to appropriately avoid mutual noise interference in the leads 63S, 73S, and 83S that are the power terminals that are outputs to the U-phase coil, the V-phase coil, and the W-phase coil of the three-phase motor. Moreover, since there are only three power terminals provided on the module substrate 50, the size of the module substrate can be further reduced. Thereby, the width LW shown in FIG. 4 can be further shortened. In addition, the wiring pattern formed on the module substrate 50 is only the power-related wiring pattern and the GND wiring pattern except for the intermediate module wiring pattern, so that the degree of freedom in wiring is high, and the power-related wiring pattern and the GND wiring pattern are combined. Layout in parallel is easy, and the effect of noise cancellation by this parallel layout can be expected.

  Also, the leads 61G, 62G, 63G, 61S, 71G, 72G, 73G, 71S, 81G, 82G, 83G, 81S, 94G, 95G, and 94S, which are control terminals, are not provided on the module substrate 50. Therefore, on the module substrate 50, wiring patterns for leads 61G, 62G, 63G, 61S, 71G, 72G, 73G, 71S, 81G, 82G, 83G, 81S, 94G, 95G, 94S, which are control terminals, are formed. Not. Thereby, since the control terminals provided on the module substrate 50 are reduced, the size of the module substrate can be further reduced. Thus, since the number of power terminals provided on the module substrate and the number of control terminals can be reduced, an increase in the size of the module substrate by arranging a large number of terminals as in Patent Document 1, The size of the module substrate can be further reduced. On the module substrate 50, wiring patterns for leads 63S, 73S, 83S as power terminals and leads 61G, 62G, 63G, 61S, 71G, 72G, 73G, 71S, 81G, 82G, 83G, 81S as control terminals are provided. , 94G, 95G, and 94S need not be provided, and therefore the width LW and height LH shown in FIG. 4 can be further shortened.

  The configuration, structure, appearance, shape, manufacturing method, and the like of the semiconductor module 1 of the present invention can be variously changed, added, and deleted without changing the gist of the present invention. For example, in the description of the present embodiment, an n-channel MOSFET has been described as an example of a semiconductor element, but a p-channel MOSFET may be used.

  In addition, the electronic circuit realized by the semiconductor module 1 is not limited to the electronic circuit illustrated in the example of FIG. 1, and various electronic circuits can be applied to the semiconductor module described in this embodiment. .

  In the description of the present embodiment, an example has been described in which the intermediate module is covered with a molding material, thereby avoiding the destruction of the joint portion with the lead bonded to the semiconductor element and the integration of the intermediate module. The molding material may be omitted, and the junction between the semiconductor element and each lead and the adjacent semiconductor element may be fixed (integrated) with an adhesive or the like.

  In the description of the present embodiment, an example in which a heat spreader is bonded to the lower surface of each semiconductor element and the lower surface of the heat spreader is the first substrate bonding surface has been described. However, the heat spreader is omitted and the electrodes ( In this case, the drain electrode) may be the first substrate bonding surface. The first substrate bonding surface is a surface corresponding to the bonding surface between the electrode on the lower surface of the semiconductor element and the module substrate.

  The semiconductor module 1 described in the present embodiment has been described as an example having one power supply relay (intermediate module), but may have at least one power supply relay, or the power supply relay is omitted from the semiconductor module. A power relay may be provided outside the semiconductor module. Further, the semiconductor elements Tr13, Tr23, Tr33 which are motor relays may be omitted.

  Each intermediate module composed of the semiconductor elements Tr11 to Tr13, Tr21 to Tr23, Tr31 to Tr33 corresponds to a first intermediate module including one arm circuit and one motor relay. In addition, you may comprise the 1st intermediate module which abbreviate | omitted the motor relay (semiconductor element Tr13, Tr23, Tr33) from said each 1st intermediate module. The intermediate module composed of the semiconductor elements Tr41 and Tr42 corresponds to a second intermediate module including a power relay.

DESCRIPTION OF SYMBOLS 1 Semiconductor module 10 U phase circuit 20 V phase circuit 30 W phase circuit 40 Power supply relay circuit 50 Module board | substrate 53u, 53v, 53w 1st internal wiring pattern 61G, 62G, 63G Lead (control terminal)
61S, 62S, 63S Lead (Power terminal)
T1, T2, T3 Power terminals Tr11 to Tr13 Semiconductor element Tr21 to Tr23 Semiconductor element Tr31 to Tr33 Semiconductor element Tr41, Tr42 Semiconductor element

Claims (4)

A semiconductor module in which a semiconductor element is mounted on a module substrate,
Three arm circuits for driving a three-phase motor are composed of the semiconductor elements,
Each of the semiconductor elements has an upper surface and a lower surface, and has an electrode on each of the upper surface and the lower surface,
Respective leads formed of a conductor and associated with the electrodes are joined to the electrodes on the upper surfaces of the respective semiconductor elements,
Some of the leads have a second substrate bonding surface whose one end extends to a virtual plane including a first substrate bonding surface corresponding to a bonding surface between the electrode on the lower surface of the semiconductor element and the module substrate. And
Each of the semiconductor elements is configured as an intermediate module in which the leads are bonded to the upper surface,
The first substrate bonding surface and the second substrate bonding surface of each of the intermediate modules are bonded to the module substrate;
The leads corresponding to the motor control input unit for controlling the operation of the arm circuit and the arm circuit output unit corresponding to the output of the arm circuit are separated from the module substrate without being connected to the module substrate. Arranged,
Semiconductor module. The semiconductor module according to claim 1,
Having three motor relays connected to respective outputs of the three arm circuits and composed of the semiconductor elements;
The leads corresponding to the output part of the motor relay serving as the arm circuit output part and the motor relay control input part for controlling the operation of the motor relay are connected to the module board without being connected to the module board. Spaced apart,
Semiconductor module. The semiconductor module according to claim 1 or 2,
The intermediate module is composed of one arm circuit when the motor relay is not provided, and one arm circuit and one motor relay when the motor relay is provided. And
The wiring pattern formed on the module substrate is
A first internal wiring pattern which is a wiring pattern used for connecting the semiconductor elements in the intermediate module, and a predetermined electronic component connected from any of the semiconductor elements to a power supply related wiring pattern or a GND wiring pattern Except for the second internal wiring pattern which is the wiring pattern used for
Only the power-related wiring pattern, which is a wiring pattern for power supplied to each arm circuit, and the GND wiring pattern, which is a wiring pattern for grounding the arm circuit, are formed.
Semiconductor module. The semiconductor module according to any one of claims 1 to 3,
A power relay composed of the semiconductor element that outputs power supplied to each of the arm circuits;
The intermediate module is
A first intermediate module including one arm circuit if the motor relay is not included, and one arm circuit and one motor relay if the motor relay is included;
A second intermediate module including the power relay,
Each of the first intermediate module and the second intermediate module is covered with a molding material such that the first substrate bonding surface and the second substrate bonding surface are exposed and the leads protrude. And
Three first intermediate modules and one second intermediate module are bonded to the module substrate.
Semiconductor module.

Images