JP2016174090A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing a threshold voltage from being unstable due to impurity ions introduced in a body region.SOLUTION: A semiconductor device includes: a P-type first body region 22 provided at a surface side of an N-type well 13; a P-type second body region 18 located at the N-type well and provided under the first body region; a P-type third body region 19 located at the surface side of the N-type well and adjacent to the first body region; a gate insulating film 23 and a gate electrode 16 located on the N-type well and on the first body region and the third body region; and a source diffusion layer 24 and a drain diffusion layer 25 located at the N-type well. An impurity concentration of the first body region is equal to or less than that of the second body region.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

A P-type body impurity region of a conventional N-channel LDMOS (Lateral Diffused MOS) is formed by one ion implantation. Since this ion implantation does not punch through between the source diffusion layer (N ⁺ ) and the drain diffusion layer, it is necessary to select a sufficiently deep implantation condition as compared with the source diffusion layer, and at the same time, the threshold Vth of DMOS is adjusted. There is a need to.

In order to obtain a threshold voltage (for example, Vth = 1V) necessary for a switching device in a general NLDMOS, it is necessary to have a sufficiently high channel concentration (for example, 2 × 10 ¹⁷ cm ⁻³ ). When deep and deep implantation is performed by one ion implantation using the resist pattern as a mask, impurities hardly remain on the surface side with respect to the opening region of the resist pattern, so that the surface concentration is difficult to stabilize. In addition, the threshold voltage may become unstable due to impurity ions penetrating through the edge of the resist pattern. A technique related to the conventional NLDMOS is disclosed in Patent Document 1.

JP 2006-32493 A

  Some embodiments of the present invention relate to a semiconductor device or a manufacturing method thereof in which threshold voltage is prevented from becoming unstable due to impurity ions introduced into a body region.

  In one embodiment of the present invention, a first body region located on a surface side of a semiconductor layer, a second body region located in the semiconductor layer and below the first body region, and the semiconductor A third body region located on the surface side of the layer and adjacent to the first body region; and a gate insulating film located on the semiconductor layer and on the first body region and the third body region And a gate electrode located on the gate insulating film, and a source diffusion layer and a drain diffusion layer located in the semiconductor layer, and the impurity concentration of the first body region is the same as that of the second body region. A semiconductor device having an impurity concentration or less.

  According to the above aspect of the present invention, the third body region and the first body region are positioned on the surface layer side of the semiconductor layer, and the impurity concentration of the first body region is less than or equal to the impurity concentration of the second body region. To do. Therefore, the impurity concentration peak value of the third body region in the channel region under the gate electrode can be made lower than the impurity concentration or impurity concentration peak value of the first body region. Thereby, it is possible to suppress the threshold voltage from becoming unstable due to impurity ions introduced into the body region.

  The semiconductor layer includes various semiconductor substrates and epitaxial layers, and also includes wells or impurity diffusion layers formed in the semiconductor substrate or epitaxial layers.

  One embodiment of the present invention is the above-described embodiment of the present invention, wherein the surface side of the first body region and the third body region is a channel region, and the third body region in the channel region is The semiconductor device is characterized in that the impurity concentration or the impurity concentration peak value is lower than that of the first body region. Thereby, it is possible to suppress the threshold voltage from becoming unstable due to impurity ions introduced into the body region.

One embodiment of the present invention includes a step (a) of forming a resist pattern on a semiconductor layer, and implanting a first impurity ion into the semiconductor layer using the resist pattern as a mask, whereby a second pattern is formed in the semiconductor layer. (B) forming a body region and forming a third body region below the end of the resist pattern and on the surface layer side of the semiconductor layer; and using the resist pattern as a mask, A step (c) of forming a first body region on a surface layer side of the semiconductor layer by implantation, a step (d) of removing the resist pattern, the first body region on the semiconductor layer, and Forming a gate insulating film on the third body region (e); forming a gate electrode on the gate insulating film (f);
Forming a source diffusion layer and a drain diffusion layer located in the semiconductor layer, wherein the second body region formed in the step (b) is located below the first body region. The third body region formed in the step (b) is adjacent to the first body region, and the impurity concentration of the first body region is lower than the impurity concentration of the second body region. This is a method for manufacturing a semiconductor device.

  According to one embodiment of the present invention, the first impurity ions and the second impurity ions are implanted in a self-aligned manner using the resist pattern as a mask, that is, two different ion implantations are performed. A body region and a first body region are formed in the semiconductor layer. The impurity concentration of the first body region is not more than the impurity concentration of the second body region. Therefore, the impurity concentration peak value of the third body region in the channel region under the gate electrode can be made lower than the impurity concentration or impurity concentration peak value of the first body region. Thereby, it is possible to suppress the threshold voltage from becoming unstable due to impurity ions introduced into the body region.

  Another embodiment of the present invention is the above-described embodiment of the present invention, wherein the direction in which the first impurity ions are implanted in the step (b) is a direction inclined with respect to a direction perpendicular to the surface of the semiconductor layer. In the method of manufacturing a semiconductor device, the direction of implanting the second impurity ions in the step (c) is a direction closer to the vertical direction than the direction of implanting the first impurity ions. is there.

  Another embodiment of the present invention is the method for manufacturing a semiconductor device according to the above embodiment of the present invention, wherein an end portion of the resist pattern formed in the step (a) has a tapered shape.

  Another embodiment of the present invention is the above-described embodiment of the present invention, wherein the ion implantation in the step (b) has both an acceleration voltage and a dose larger than those in the ion implantation in the step (c). A method for manufacturing a semiconductor device. Thereby, the impurity concentration of the first body region can be made lower than the impurity concentration of the second body region.

4A to 4C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A and 4B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. (A), (B) is sectional drawing for demonstrating the manufacturing method of the semiconductor device by a comparative example.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

[Embodiment 1]
1 and 2 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. This semiconductor device is an N-channel LDMOS.

  As shown in FIG. 1A, an epitaxial layer is formed on a P-type silicon substrate 11. In this embodiment, a P-type epitaxial layer is formed, but an N-type epitaxial layer may be formed. Next, N-type impurity ions are introduced into the P-type epitaxial layer, and heat treatment is performed to form an N-type well (also referred to as a semiconductor layer) 13 in the P-type epitaxial layer.

Next, as shown in FIG. 1B, a field insulating film 14 as an offset insulating film is formed on the N-type well 13. The field insulating film 14 is made of SiO ₂ formed by the LOCOS method and has a thickness of, for example, 400 nm. Next, a SiO ₂ film 12 that allows impurity ions to pass therethrough is formed. The thickness of the SiO ₂ film 12 is 30 nm, for example.

Thereafter, as shown in FIG. 1C, a photoresist film is applied on the entire surface including the field insulating film 14, exposed and developed, so that a resist pattern 15 is formed on the field insulating film 14 and the SiO ₂ film 12. Form. The resist pattern 15 is formed so as to cover a part of the gate electrode 16 formed in a later step.

  Next, P-type impurity ions 17 are implanted into the N-type well 13 using the resist pattern 15 as a mask. Thus, a P-type second body region 18 is formed in the N-type well 13, and a P-type third body region 19 is formed below the end of the resist pattern 15 and on the surface layer side of the N-type well 13. Since the P-type impurity ions 17 are implanted at a high acceleration voltage and a high dose, the second body region 18 is formed deep in the N-type well 13. However, since the direction in which the P-type impurity ions 17 are implanted is a direction inclined with respect to the direction perpendicular to the surface of the N-type well 13, the third body region 19 is located below the end of the resist pattern 15 and in the N-type well 13 It is formed on the surface layer side. However, even if the P-type impurity ions 17 are not implanted obliquely as shown in FIG. 1C but in the direction perpendicular to the surface of the N-type well 13, the surface layer of the N-type well 13 is formed below the end of the resist pattern 15. A third body region 19 is formed on the side.

  Next, as shown in FIG. 2A, by implanting P-type impurity ions 21 into the N-type well 13 using the resist pattern 15 as a mask, a P-type first body is formed on the surface layer side of the N-type well 13. Region 22 is formed. The direction in which the P-type impurity ions 21 are implanted is closer to the vertical direction than the direction in which the P-type impurity ions 17 are implanted. Since the P-type impurity ions 21 are implanted at a lower acceleration voltage and a lower dose than the P-type impurity ions 17, the first body region 22 is formed on the surface layer side of the N-type well 13. The second body region 18 is located below the first body region 22, and the third body region 19 is adjacent to the first body region 22.

The implantation conditions of the P-type impurity ions 17 in FIG. 1C and the implantation conditions of the P-type impurity ions 21 in FIG. 2A are such that the impurity concentration of the first body region 22 is the impurity concentration of the second body region 18. The conditions are as follows. For example, the implantation condition of P-type impurity ions 17 is 2 × 10 ¹³ cm ⁻³ at an acceleration voltage of 350 KeV, the impurity ions are boron, and the implantation condition of P-type impurity ions 21 is 2 × 10 at an acceleration voltage of 60 KeV. The dose is ¹² cm ⁻³ and impurity ions are boron. Thus, by implanting the P-type impurity ions 17 at a higher acceleration voltage and a higher dose than the P-type impurity ions 21, the impurity concentration of the first body region 22 is less than or equal to the impurity concentration of the second body region 18. It becomes. In that case, the surface side of the first body region 22 and the third body region 19 is a channel region, and the third body region 19 in this channel region has an impurity concentration or impurity concentration peak value higher than that of the first body region 21. Lower.

  The punch-through is controlled by the impurity concentration of the second body region 18 formed by the implantation of the P-type impurity ions 17. Further, the threshold is determined depending on the impurity concentration on the surface layer side of the first body region 22 formed by implantation of the P-type impurity ions 21 and on the surface layer side of the third body region 19 formed by implantation of the P-type impurity ions 17. The voltage is determined.

  Thereafter, as shown in FIG. 2B, the resist pattern 15 is removed. Next, a gate insulating film 23 is formed by thermal oxidation on the surface of the N-type well 13 where the field insulating film 14 is not formed and on the first body region 22 and the third body region 19. Next, a polysilicon film is formed on the entire surface including the field insulating film 14 and the gate insulating film 23, and the polysilicon film is processed to form the gate electrode 17 on the field insulating film 14 and the gate insulating film 23. .

Next, as shown in FIG. 2C, an N ⁺ -type drain region diffusion layer 25 is formed in the N-type well 13 in a self-aligned manner with respect to the field insulating film 14, and an N-type drain region 25 is formed in the first body region 22. ^{The +} type source region diffusion layer 24 is formed in a self-aligned manner with respect to the gate electrode 16.

  The impurity concentration of the X ″ -X ′ ″ line shown in FIG. 2C (that is, the impurity concentration of the channel region under the gate electrode 16) is shown in the lower graph of FIG. The vertical axis of this graph indicates the impurity concentration, and the horizontal axis indicates the position of the channel region. As shown in this graph, the B line in the graph indicates the surface layer side (channel region) of the first body region 22, and the surface layer side (channel region) of the third body region 19 indicates the A line in the graph. Shows. Thus, the third body region 19 in the channel region has a lower impurity concentration or impurity concentration peak value than the first body region 21.

  According to the present embodiment, the third body region is formed by implanting the P-type impurity ions 17 and 21 in a self-aligning manner using the resist pattern 15 as a mask, that is, by performing ion implantation twice at different depths. 19 and the first body region 21 are formed in the N-type well 13. Then, as shown in the graph of FIG. 2C, the impurity concentration peak value A of the third body region 19 in the channel region (in the horizontal plane) is greater than the impurity concentration or impurity concentration peak value B of the first body region 21. make low. As a result, the threshold voltage can be prevented from becoming unstable due to the impurity ions introduced into the body region, and the threshold voltage can be stabilized.

  FIG. 4 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to a comparative example. The same parts as those in FIGS. 1 to 2 are denoted by the same reference numerals, and only different parts will be described.

  As shown in FIG. 4A, P-type impurity ions 17b are implanted once into the N-type well 13 using the resist pattern 15 as a mask. As a result, P-type first to third body regions 22 a, 18 a, 19 a are formed in the N-type well 13. A second body region 18 a is formed under the first body region 22 a, and a third body region 19 is formed under the edge of the resist pattern 15 and on the surface layer side of the N-type well 13. The third body region 19 is adjacent to the first body region 22a.

  In this comparative example, the threshold voltage is controlled on the surface layer side of the first body region 22a formed by one implantation of the P-type impurity ions 17b of FIG. 4A, and the second body region 18a is punched. Controls slew prevention. In order to control both the threshold voltage and the punch-through by one ion implantation in this way, the acceleration voltage at the time of implantation of the P-type impurity ions 17b in FIG. 4A is changed to the P-type impurity in FIG. The acceleration voltage is set lower than the acceleration voltage at the time of implantation of ions 17 and higher than the acceleration voltage at the time of implantation of P-type impurity ions 21 in FIG. The acceleration voltage at the time of implantation of the P-type impurity ions 17b in FIG. 4A is, for example, 140 KeV, and the impurity ions are boron.

  The impurity concentration of the XX ′ line shown in FIG. 4B (that is, the impurity concentration of the channel region under the gate electrode 16) is shown in the lower graph of FIG. The vertical axis of this graph indicates the impurity concentration, and the horizontal axis indicates the position of the channel region. As shown in this graph, the surface B side (channel region) of the first body region 22a is indicated by a line B in the graph, and the surface layer side (channel region) of the third body region 19 is indicated by the line A in the graph. Shows.

  When the first body region 22a and the second body region 18a are formed by one ion implantation as described above, the P-type impurity ions 17b are masked halfway along the edge of the resist pattern 15. As a result, a third body region 19 a is formed below the end of the resist pattern 15 and on the surface layer side of the N-type well 13. As a result, the impurity concentration peak value A on the surface layer side (channel region) of the third body region 19a becomes higher than the impurity concentration B on the surface layer side (channel region) of the first body region 22a. Therefore, in the semiconductor device according to the comparative example shown in FIG. 4B, the threshold voltage becomes unstable. That is, an impurity concentration peak value A having an unstable concentration appears outside the opening region B of the resist pattern 15 (resist pattern 15 formation region), and the threshold voltage is determined by the impurity concentration peak value A.

  On the other hand, in the semiconductor device shown in FIG. 2C, the impurity concentration peak value A of the third body region 19 in the channel region is changed to the impurity concentration or impurity concentration peak value B of the first body region 21 as described above. Can be lower. Therefore, in the semiconductor device illustrated in FIG. 2C, the threshold voltage can be prevented from becoming unstable due to the impurity ions introduced into the body region, compared to the semiconductor device illustrated in FIG. The threshold voltage can be stabilized.

  In this embodiment, the N-channel LDMOS has been described. However, the present invention is not limited to the N-channel, and the P-channel LDMOS can also be implemented by reversing the conductivity type.

  In the present embodiment, after the first to third body regions 22 and 18.19 are formed in the N-type well 13, the gate insulating film 23 and the gate electrode 16 are formed. However, the present invention is not limited to this, and the first to third body regions 22 and 18.19 are formed in the N-type well 13 after the gate insulating film 23 and the gate electrode 16 are formed on the N-type well 13. May be.

[Embodiment 2]
FIG. 3 is a cross-sectional view for describing the method for manufacturing a semiconductor device according to one embodiment of the present invention. The same portions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and only different portions will be described.

As shown in FIG. 3A, a resist pattern 15 a is formed on the field insulating film 14 and the SiO ₂ film 12. The end portion of the resist pattern 15 has a tapered shape.

  Next, P-type impurity ions 17a are implanted into the N-type well 13 using the resist pattern 15a as a mask. As a result, a P-type second body region 18 is formed in the N-type well 13, and a P-type third body region 19 is formed below the end of the resist pattern 15 a and on the surface layer side of the N-type well 13. Since the P-type impurity ions 17 are implanted at a high acceleration voltage and a high dose, the second body region 18 is formed deep in the N-type well 13. However, since the end portion of the resist pattern 15 a is tapered, the third body region 19 is formed below the end portion of the resist pattern 15 a and on the surface layer side of the N-type well 13. However, even if the end portion of the resist pattern 15a is not tapered as shown in FIG. 3A, the third body region 19 is formed below the end portion of the resist pattern 15a and on the surface layer side of the N-type well 13.

  Next, as shown in FIG. 3B, a P-type first body is formed on the surface layer side of the N-type well 13 by implanting P-type impurity ions 21a into the N-type well 13 using the resist pattern 15a as a mask. Region 22 is formed. Since the P-type impurity ions 21a are implanted at a lower acceleration voltage and a lower dose than the P-type impurity ions 17a, the first body region 22 is formed on the surface layer side of the N-type well 13. The second body region 18 is located below the first body region 22, and the third body region 19 is adjacent to the first body region 22.

The implantation conditions of the P-type impurity ions 17a in FIG. 3A and the implantation conditions of the P-type impurity ions 21a in FIG. 3B are such that the impurity concentration of the first body region 22 is the impurity concentration of the second body region 18. The conditions are as follows. For example, the implantation condition of the P-type impurity ions 17a is 2 × 10 ¹³ cm ⁻³ at an acceleration voltage of 350 KeV, the impurity ions are boron, and the implantation condition of the P-type impurity ions 21a is 2 × 10 at an acceleration voltage of 60 KeV. The dose is ¹² cm ⁻³ and impurity ions are boron. Thus, by implanting the P-type impurity ions 17a at a higher acceleration voltage and a higher dose than the P-type impurity ions 21a, the impurity concentration of the first body region 22 is less than or equal to the impurity concentration of the second body region 18. It becomes. In that case, the surface side of the first body region 22 and the third body region 19 is a channel region, and the third body region 19 in this channel region has an impurity concentration or impurity concentration peak value higher than that of the first body region 21. Lower.

  Punch-through is controlled by the impurity concentration of the second body region 18 formed by implantation of the P-type impurity ions 17a. Further, the threshold value depends on the impurity concentration on the surface layer side of the first body region 22 formed by implantation of the P-type impurity ions 21a and on the surface layer side of the third body region 19 formed by implantation of the P-type impurity ions 17a. The voltage is determined.

Also in the present embodiment, the same effect as in the first embodiment can be obtained.
Even if the end portion of the resist pattern 15a has a tapered shape, the threshold voltage of the transistor is not affected by the impurity concentration on the surface side of the third body region 19, so that the device characteristic variation can be reduced.

In the present invention, when a specific B (hereinafter referred to as “B”) is formed above (or below) a specific A (hereinafter referred to as “A”) (when B is formed), Or, it is not limited to the case where B is directly formed (below). It includes the case where B is formed (otherwise B) is formed on the upper side (or the lower side) of A through other things as long as the effects of the present invention are not inhibited.
Further, the structure expressed by the expression above (or below) is not necessarily limited to one direction. For example, when B is formed above (or below) A (B is formed), the semiconductor device When used upside down, it includes the case where B is formed below (or above) A (B is formed).

  Moreover, you may implement combining said Embodiment 1 and Embodiment 2 suitably.

11 ... P-type silicon substrate, 12 ... SiO ₂ film, 13 ... N-type well, 14 ... field insulating film, 15, 15a ... resist pattern, 16 ... gate electrode, 17, 17a, 17b ... P-type impurity ions, 18, 18a ... P-type second body region, 19, 19a ... P-type third body region, 21, 21a ... P-type impurity ions, 22, 22a ... P-type first body region, 23 ... Gate insulation Film, 24... N ⁺ type source region diffusion layer, 25... N ⁺ type drain region diffusion layer.

Claims (6)

A first body region located on the surface side of the semiconductor layer;
A second body region located in the semiconductor layer and below the first body region;
A third body region located on the surface side of the semiconductor layer and adjacent to the first body region;
A gate insulating film located on the semiconductor layer and on the first body region and the third body region;
A gate electrode located on the gate insulating film;
A source diffusion layer and a drain diffusion layer located in the semiconductor layer;
Including
The semiconductor device according to claim 1, wherein an impurity concentration of the first body region is equal to or less than an impurity concentration of the second body region. In claim 1,
The surface side of the first body region and the third body region is a channel region, and the third body region in the channel region has an impurity concentration or an impurity concentration peak value lower than that of the first body region. A featured semiconductor device. Forming a resist pattern on the semiconductor layer (a);
By implanting first impurity ions into the semiconductor layer using the resist pattern as a mask, a second body region is formed in the semiconductor layer, and a third body region is formed below the edge of the resist pattern and on the surface layer side of the semiconductor layer. Forming a body region of (b),
(C) forming a first body region on the surface side of the semiconductor layer by implanting second impurity ions into the semiconductor layer using the resist pattern as a mask;
Removing the resist pattern (d);
Forming a gate insulating film on the semiconductor layer and on the first body region and the third body region (e);
Forming a gate electrode on the gate insulating film (f);
Forming a source diffusion layer and a drain diffusion layer located in the semiconductor layer (g);
Including
The second body region formed in the step (b) is located under the first body region;
The third body region formed in the step (b) is adjacent to the first body region;
A method of manufacturing a semiconductor device, wherein an impurity concentration of the first body region is equal to or less than an impurity concentration of the second body region. In claim 3,
A direction in which the first impurity ions are implanted in the step (b) is a direction inclined with respect to a direction perpendicular to the surface of the semiconductor layer;
The method of manufacturing a semiconductor device, wherein a direction in which the second impurity ions are implanted in the step (c) is closer to the vertical direction than a direction in which the first impurity ions are implanted. In claim 3,
An end portion of the resist pattern formed in the step (a) has a taper shape. In any one of Claims 3 thru | or 5,
The method of manufacturing a semiconductor device, wherein the ion implantation in the step (b) has a larger acceleration voltage and dose than the ion implantation in the step (c).

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