JP2016171275A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which achieves a gentle current waveform at the time of reverse recovery operation of a high-speed diode, and has a structure having a shallower P-type layer excellent in uniformity of an impurity concentration.SOLUTION: In a semiconductor device, amorphous silicon added with a P-type impurity is deposited on an N-type silicon substrate 3 by a vacuum deposition method, a plasma CVD method and the like, and a P-type layer 2 of an anode layer shallower than by a thermal diffusion method by crystallizing the amorphous silicon by annealing thereby to uniformize a concentration in the P-type layer 2.SELECTED DRAWING: Figure 1

Description

The present invention relates to a diode having soft switching characteristics in a current waveform during reverse recovery operation.

As a technique for increasing the speed of the switching diode used for high-frequency rectification and further softening the switching waveform, a technique of reducing the depth of the P-type anode diffusion layer is employed.

Japanese Patent Application Laid-Open No. 7-235623 Sansha Electric Manufacturing Co., Ltd.

However, when the diffusion layer is formed by the conventional thermal diffusion technique, it is difficult to form a sufficiently shallow P-type anode diffusion layer. Further, the thermal diffusion technique has a problem that the uniformity of the impurity concentration of the formed P-type anode diffusion layer is low and a stable breakdown voltage cannot be obtained.

The present invention relates to a semiconductor device having a structure having a P-type layer which solves the above problems and is shallower than the prior art and has excellent uniformity of impurity concentration.

In order to solve the above-described problems, the present invention has the following configurations.
The semiconductor device of the present invention is formed of an anode layer formed by crystallizing amorphous silicon to which a P-type impurity is added.

According to the present invention, since a shallow P-type layer can be formed as compared with a P-type anode layer formed by thermal diffusion, the switching waveform of the diode can be made softer than before. Further, since impurities are added during the growth of amorphous silicon, the impurity concentration can be made uniform as compared with the P layer formed by thermal diffusion, so that a uniform electric field can be applied to the PN junction and a stable breakdown voltage can be obtained. it can.

It is sectional drawing of the diode chip which concerns on Example 1 of this invention.

  The structure of the diode according to Example 1 will be described. As shown in FIG. 1, in the diode of the present invention, a thin P-type layer obtained by annealing amorphous silicon and depositing it is deposited on an N-type semiconductor layer. Amorphous silicon can be grown by adding a P-type impurity such as boron by a technique such as vacuum deposition or plasma CVD. The growth temperature is preferably in the range of 200 ° C. to 350 ° C. in order to reduce the stress of the film. Amorphous silicon is crystallized by laser annealing or the like, and the annealing temperature is, for example, 700 ° C. to 1200 ° C., preferably 700 ° C. to 900 ° C. so as not to generate stress between the N-type silicon substrate and the P-type interlayer. It is preferable to carry out at temperature. The concentration of the P-type layer is preferably 1E12 atom / cm3 or more and 1E20 atom / cm3 or less, and is 1E15 atom / cm3 or more and 1E19 atom / cm3 in order to reduce the stress at the PN junction interface and obtain good electrical characteristics. preferable. In addition, it is desirable that the impurity concentration distribution in the P-type layer be 5% or less in order to obtain a stable breakdown voltage.

1. Anode electrode 2. P-type layer (crystallize amorphous silicon)
3. N-type semiconductor substrate 4. Cathode electrode

Claims (3)

A PN junction semiconductor device having a structure in which a P-type semiconductor layer crystallized from amorphous silicon is continuously deposited on an N-type semiconductor substrate.
2. The semiconductor device according to claim 1, wherein the concentration of the P-type semiconductor layer is 1E15 atom / cm 3 or more and 1E19 atom / cm 3 or less.
The semiconductor device according to claim 2, wherein a concentration distribution of the P-type semiconductor layer is 5% or less.

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