JP2016171179A - Solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of shortening a time for driving each pixel.SOLUTION: According to one embodiment, provided is a solid-state imaging device comprising a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a plurality of pixels. On the second semiconductor chip, the first semiconductor chip is laminated. The second semiconductor chip has an AD conversion circuit, a control circuit, a repeater wire, wiring, and a plurality of repeaters. The repeater wire extends from the control circuit. The wiring connects the repeater wire with the plurality of pixels three-dimensionally. The plurality of repeaters are arranged on the repeater wire so as to correspond to the plurality of pixels.SELECTED DRAWING: Figure 6

Description

  Embodiments generally relate to solid state imaging devices.

  In a solid-state imaging device having a plurality of pixels, a control circuit and a plurality of pixels are connected by wiring, and each pixel is driven by a signal supplied from the control circuit. At this time, it is desired to shorten the time for driving each pixel.

JP 2010-225927 A

  An object of one embodiment is to provide a solid-state imaging device capable of shortening the time for driving each pixel.

  According to one embodiment, a solid-state imaging device having a first semiconductor chip and a second semiconductor chip is provided. The first semiconductor chip has a plurality of pixels. The first semiconductor chip is stacked on the second semiconductor chip. The second semiconductor chip includes an AD conversion circuit, a control circuit, a repeater line, a wiring, and a plurality of repeaters. The repeater line extends from the control circuit. The wiring connects the repeater line to a plurality of pixels three-dimensionally. The plurality of repeaters are arranged corresponding to the plurality of pixels on the repeater line.

1 is a cross-sectional view illustrating a configuration of an imaging system to which a solid-state imaging device according to a first embodiment is applied. 1 is a block diagram illustrating a configuration of an imaging system to which a solid-state imaging device according to a first embodiment is applied. 1 is a circuit diagram showing a configuration of a solid-state imaging apparatus according to a first embodiment. FIG. 3 is a circuit diagram illustrating a configuration of a pixel in the first embodiment. FIG. 3 is an exploded perspective view illustrating a stacked configuration of the solid-state imaging device according to the first embodiment. FIG. 2 is a circuit diagram illustrating a stacked configuration of the solid-state imaging device according to the first embodiment. FIG. 2 is a circuit diagram showing a connection configuration between a repeater and a pixel in the first embodiment. FIG. 6 is a circuit diagram illustrating a stacked configuration of a solid-state imaging device according to a modification of the first embodiment. FIG. 6 is a circuit diagram showing a stacked configuration of a solid-state imaging device according to another modification of the first embodiment. FIG. 6 is a circuit diagram showing a stacked configuration of a solid-state imaging device according to another modification of the first embodiment. FIG. 6 is a circuit diagram showing a stacked configuration of a solid-state imaging device according to another modification of the first embodiment. FIG. 6 is a circuit diagram illustrating a stacked configuration of a solid-state imaging device according to a second embodiment. The circuit diagram which shows the laminated structure of the solid-state imaging device in the modification of 2nd Embodiment.

  Exemplary embodiments of a solid-state imaging device will be described below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
A solid-state imaging device according to the first embodiment will be described. The solid-state imaging device is applied to the imaging system shown in FIGS. 1 and 2, for example. 1 and 2 are diagrams illustrating a schematic configuration of an imaging system. In FIG. 1, OP indicates an optical axis.

  The imaging system 81 may be, for example, a digital camera, a digital video camera, or the like, or a camera module applied to an electronic device (for example, a mobile terminal with a camera). As shown in FIG. 2, the imaging system 81 includes an imaging unit 82 and a post-processing unit 83. The imaging unit 82 is, for example, a camera module. The imaging unit 82 includes an imaging optical system 84 and a solid-state imaging device 100. The post-processing unit 83 includes an ISP (Image Signal Processor) 86, a storage unit 87, and a display unit 88.

  The imaging optical system 84 includes a photographing lens 47, a half mirror 49, a mechanical shutter 46, a lens 44, a prism 45, and a finder 48. The photographing lens 47 includes photographing lenses 47a and 47b, a diaphragm (not shown), and a lens driving mechanism 47c. The aperture is disposed between the photographic lens 47a and the photographic lens 47b, and adjusts the amount of light guided to the photographic lens 47b. In FIG. 1, the case where the photographing lens 47 includes two photographing lenses 47a and 47b is exemplarily shown, but the photographing lens 47 may include a large number of photographing lenses.

  The solid-state imaging device 100 is disposed on the planned imaging plane of the photographic lens 47. For example, the photographing lens 47 refracts incident light and guides it to the imaging surface of the solid-state imaging device 100 via the half mirror 49 and the mechanical shutter 46 to form an image of the subject on the imaging surface of the solid-state imaging device 100. The solid-state imaging device 100 generates an image signal corresponding to the subject image.

  As shown in FIG. 3, the solid-state imaging device 100 includes an image sensor 90 and a signal processing circuit 91. FIG. 3 is a diagram illustrating a circuit configuration of the solid-state imaging device 100. The image sensor 90 may be, for example, a CMOS image sensor or a CCD image sensor. The image sensor 90 includes a pixel array PA, a row decoder 93, a timing control unit 95, a CDS + ADC 97, and a line memory 98.

  In the pixel array PA, a plurality of pixels P are arranged in, for example, the row direction and the column direction. The row decoder 93 controls the pixel array PA, for example, in units of rows in accordance with a control signal from the timing control unit 95.

  As shown in FIG. 4, each pixel P includes, for example, a photoelectric conversion unit 3, a transfer unit 8, a charge / voltage conversion unit 4, a reset unit 7, an amplification unit 5, and a selection unit 6. FIG. 4 is a diagram illustrating a configuration of each pixel P. In FIG. 4, the pixel P (n, m) in the nth row and the mth column is exemplarily shown, but the same applies to other pixels.

  The photoelectric conversion unit 3 performs photoelectric conversion, and generates and accumulates charges corresponding to the received light. The photoelectric conversion unit 3 includes, for example, a photodiode PD.

  The transfer unit 8 transfers the charge of the photoelectric conversion unit 3 to the charge-voltage conversion unit 4 in the active state, and does not transfer the charge of the photoelectric conversion unit 3 to the charge-voltage conversion unit 4 in the inactive state. The transfer unit 8 transfers the charge of the photoelectric conversion unit 3 to the charge-voltage conversion unit 4 when it receives the active level control signal φREADn from the row decoder 93 via the drive line DL (n) -3. The transfer unit 8 does not transfer the charge of the photoelectric conversion unit 3 to the charge voltage conversion unit 4 when receiving the non-active level control signal φREADn from the row decoder 93 via the drive line DL (n) -3. The transfer unit 8 includes, for example, a transfer transistor Td that functions as a transfer gate, and is turned on when an active level control signal φREADn is received at the gate, whereby the charge of the photoelectric conversion unit 3 is changed to the charge-voltage conversion unit 4. The charge of the photoelectric conversion unit 3 is not transferred to the charge-voltage conversion unit 4 by turning off when receiving a non-active level control signal φREADn at its gate.

  The charge-voltage converter 4 converts the transferred charge into a voltage using the parasitic capacitance. The charge-voltage conversion unit 4 includes, for example, a floating junction FJ.

  The photoelectric conversion unit 3 starts to accumulate charges after the transfer of the charges by the transfer unit 8 is completed, and accumulates charges until the transfer unit 8 transfers the charges to the charge-voltage conversion unit 4 next time. That is, the photoelectric conversion unit 3 performs the charge accumulation operation in the charge accumulation period from the completion timing of the transfer operation by the transfer unit 8 to the start timing of the next transfer operation by the transfer unit 8.

  The reset unit 7 resets the potential of the charge voltage conversion unit 4 to a predetermined potential (for example, VDDreset) when receiving an active level control signal φRESET_FJn from the row decoder 93 via the drive line DL (n) -2. . The reset unit 7 includes, for example, a reset transistor Tc, and is turned on when receiving an active level control signal φRESET_FJn at its gate, whereby the potential of the charge-voltage conversion unit 4 is set to a predetermined potential (for example, VDDreset). Reset.

  The amplifying unit 5 outputs a signal based on the voltage of the charge voltage converting unit 4 to the signal line SL when the pixel P (n, m) is in a selected state. The amplifying unit 5 includes, for example, an amplifier transistor Tb, and performs a source follower operation together with the load current source CS connected via the signal line SL when the pixel P (n, m) is in a selected state. Thus, a signal corresponding to the voltage of the charge-voltage converter 4 is output to the signal line SL. The load current source CS has a load transistor TLM and a bias generation circuit 9.

  When receiving the active level control signal φADRESn from the row decoder 93 via the drive line DL (n) −1, the selection unit 6 sets the pixel P (n, m) to the selected state, and the drive line DL from the row decoder 93. When the non-active level control signal φADRESn is received via (n) −1, the pixel P (n, m) is brought into a non-selected state. The selection unit 6 includes, for example, a selection transistor Ta, and is turned on when the gate receives an active level control signal φADRESn, thereby bringing the pixel P (n, m) into a selected state and making the gate inactive. When the level control signal φADRESn is received, the pixel P (n, m) is brought into a non-selected state by turning off. The drain of the selection transistor Ta is connected to the power supply potential VDDsf. The power supply potential VDDsf and the power supply potential VDDreset can be short-circuited.

  4 illustrates a configuration in which the selection transistor Ta is connected to the power supply potential VDDsf side and the amplifier transistor Tb is connected to the signal line SL side. However, the amplifier transistor Tb is connected to the power supply potential VDDsf side and the selection transistor Ta is It may be configured to be connected to the signal line SL side.

  Further, the pixel P may have a configuration in which the selection unit 6 is omitted. In that case, the drive line DL (n) -1 may be omitted, and the reset unit 7 may perform an operation for bringing the pixel P into a selected state / non-selected state. For example, the reset unit 7 selects the pixel P by resetting the potential of the charge-voltage conversion unit 4 to a first potential (for example, VDD level), and sets the potential of the charge-voltage conversion unit 4 to the second potential ( The pixel P may be brought into a non-selected state by resetting to a potential at which the amplifying unit 5 (amplifier transistor Tb) is turned off, for example, a GND level.

  A plurality of drive lines DL (n) extend to each pixel P. In the following, for the sake of simplicity of explanation, it is assumed that one drive line DL (n) extends to each pixel P. . Further, although a plurality of control signals are supplied to each pixel P, it is assumed that one control signal is supplied to each pixel P for simplification of description.

  Returning to FIG. 3, the image signal generated in each pixel P is read to the CDS + ADC 97 side by the timing control unit 95 and the row decoder 93, converted to image data through the CDS + ADC 97, and the signal processing circuit via the line memory 98. 91 is output. The signal processing circuit 91 performs signal processing. These signal processed image data are output to the ISP 86.

  As shown in FIGS. 3 and 4, the row decoder 93 is arranged around the pixel array PA, and each drive line DL extends from the row decoder 93 to each pixel in the corresponding row in the row direction. The row decoder 93 sequentially selects a row to be driven among a plurality of rows in the pixel array PA as a first row, a second row,..., And selects in the pixel array PA via the drive line DL of the selected row. Control is performed by supplying a control signal to a plurality of pixels included in a row.

  For example, if the pixel array PA includes a large number of pixels in order to satisfy the demand for increasing the number of pixels, the drive line DL becomes long and the resistance value of the drive line DL tends to increase. Further, since the number of pixels connected to the drive line DL is increased, the capacitance value of the drive line DL is likely to increase. Therefore, there is a possibility that the pixel drive time when the row decoder 93 drives the pixel via the drive line DL becomes long.

  If the pixel drive time is prolonged, there is a possibility that the required frame rate of the image signal output from the solid-state imaging device 100 cannot be satisfied. If the frame rate cannot satisfy the required speed, when the image obtained from the image signal is a moving image, it is difficult to secure the number of frames within a predetermined time, and it is difficult to obtain a smooth moving image. Alternatively, when the image obtained from the image signal is a still image, the release time lag increases, and it may be difficult to capture a photo opportunity.

  At this time, in order to ensure pixel characteristics, it is difficult to reduce the resistance value / capacitance value of the drive line DL. Consider a case where a repeater for driving a control signal is inserted at a position between the row decoder 93 and the pixel array PA on the drive line DL. In this case, since the inserted repeater drives the pixel from one end side of the drive line DL with respect to a plurality of pixels connected to the drive line DL, it is greatly affected by delay due to the capacitance. For this reason, it is considered difficult to shorten the pixel driving time.

  Further, in the pixel array PA, it is difficult to add repeaters at positions between the pixels on the drive line DL in order to ensure pixel characteristics (pixel arrangement pitch).

  Therefore, in the first embodiment, by stacking chips using substrate bonding, electrode junctions can be arranged below the pixel region, and a plurality of pixels are arranged at positions corresponding to a plurality of pixels in the repeater line of the lower chip. By inserting a repeater and supplying the driven control signal from the lower chip to the upper chip, the delay of the control signal is reduced.

  Specifically, as shown in FIGS. 5 and 6, the solid-state imaging device 100 includes a semiconductor chip CH1 and a semiconductor chip CH2. FIG. 5 is an exploded perspective view showing a stacked configuration of the solid-state imaging device 100. FIG. 6 is a circuit diagram illustrating a stacked configuration of the solid-state imaging device 100.

  The semiconductor chip CH1 is stacked on the semiconductor chip CH2. The semiconductor chip CH1 and the semiconductor chip CH2 are bonded by substrate bonding. The semiconductor chip CH1 and the semiconductor chip CH2 are bonded to each other on the surface side, and the electrodes EL can be bonded (for example, Cu—Cu bonding). Each of the semiconductor chip CH1 and the semiconductor chip CH2 has a multilayer wiring structure formed on the surface side, and has an electrode EL whose surface is exposed on the uppermost wiring layer.

  Of the components in the solid-state imaging device 100 shown in FIG. 3, the pixel array PA is arranged on the semiconductor chip CH1. For example, the semiconductor chip CH1 includes a plurality of pixels P (1,1) to P (4,4), a plurality of drive lines DL (1) to DL (4), and a plurality of wirings WR (1,1) to WR ( 4, 4), and a plurality of signal lines (not shown). The plurality of pixels P (1,1) to P (4,4) are arranged in the row direction and the column direction, and constitute, for example, 4 rows and 4 columns. 5 and 6 exemplify a case where the number of pixels in the pixel array PA is 4 rows and 4 columns, but the number of pixels is not limited to this. Although not shown, each of the pixels P (1, 1) to P (4, 4) has a back-illuminated pixel configuration.

  The plurality of drive lines DL (1) to DL (4) correspond to a plurality of rows of pixels. Each drive line DL (1) to DL (4) extends in the row direction and is connected to each pixel in the corresponding row. For example, the drive line DL (1) corresponds to the pixels P (1,1) to P (1,4) in the first row, and the pixels P (1,1) to P (1,4) in the first row. )It is connected to the.

  Each of the plurality of wirings WR (1, 1) to WR (4, 4) three-dimensionally connects the drive lines DL (1) to DL (4) to the semiconductor chip CH2 side. For example, the wirings WR (1,1) to WR (1,4) are electrodes provided with nodes DN (1,1) to DN (1,4) on the drive line DL (1) below, respectively. Connect to EL.

  Of the configuration in the solid-state imaging device 100 shown in FIG. 3, other than the pixel array PA is arranged on the semiconductor chip CH2. For example, the semiconductor chip CH2 includes an ADC 97, a logic circuit 99, a row decoder (control circuit) 93, a plurality of repeater lines RL (1) to RL (4), and a plurality of wirings LWR (1, 1) to LWR (4, 4). ), And a plurality of repeaters RP (1,1) to RP (4,4). In the semiconductor chip CH2, the row decoder 93 is arranged near the end. Near the arrangement area of the row decoder 93, ADC arrangement areas 11 to 14 and logic circuit arrangement areas 15 to 18 are provided. For example, the ADC 97 is divided and arranged in the ADC arrangement regions 11 to 14. Logic circuits 99 are divided and arranged in the logic circuit arrangement regions 15 to 18. The logic circuit 99 includes a signal processing circuit 91 and the like (see FIG. 3).

  The plurality of repeater lines RL (1) to RL (4) correspond to the plurality of drive lines DL (1) to DL (4). Each repeater line RL (1) to RL (4) extends along a corresponding drive line DL. For example, the repeater lines RL (1) and RL (2) extend from the row decoder 93 in the row direction and pass through the logic circuit arrangement regions 15 to 18. The repeater lines RL (1) and RL (2) pass through the logic circuit arrangement regions 15 to 18 but are not connected to the logic circuit 99. For example, the repeater lines RL (3), RL (4) extend from the row decoder 93 in the row direction and pass through the ADC arrangement regions 11-14. The repeater lines RL (3) and RL (4) pass through the ADC placement areas 11 to 14 but are not connected to the ADC 97.

  Each of the plurality of wirings LWR (1, 1) to LWR (4, 4) three-dimensionally connects the repeater lines RL (1) to RL (4) to the semiconductor chip CH1 side. For example, the wirings LWR (1, 1) to LWR (1, 4) are respectively electrodes provided with nodes RN (1, 1) to RN (1, 4) on the repeater line RL (1) above them. Connect to EL.

  For example, node RN (1, 1) → wiring LWR (1,1) → electrode EL of semiconductor chip CH2 → electrode EL of semiconductor chip CH1 → wiring WR (1,1) → node DN (1,1) → pixel P (1, 1). Node RN (1, 4) → wiring LWR (1,4) → electrode EL of semiconductor chip CH2 → electrode EL of semiconductor chip CH1 → wiring WR (1,4) → node DN (1,4) → pixel P (1 , 4). That is, each of the plurality of wirings LWR (1, 1) to LWR (4, 4) connects the repeater lines RL (1) to RL (4) to the plurality of pixels three-dimensionally.

  The plurality of repeaters RP (1,1) to RP (4,4) correspond to the plurality of repeater lines RL (1) to RL (4). The plurality of repeaters RP (1,1) to RP (1,4) are arranged on the repeater line RL (1) corresponding to the plurality of pixels P (1,1) to P (1,4). . The plurality of repeaters RP (1,1) to RP (1,4) can drive the pixels P (1,1) to P (1,4) in the same row in the pixel array PA.

  For example, as shown in FIG. 7, the repeater RP (1,1) has an input terminal connected to the row decoder 93 via a repeater line RL (1). FIG. 7 is a circuit diagram showing a connection configuration between a repeater and a pixel. The repeater RP (1,1) has an output terminal connected to the pixel P (1,1) via the repeater line RL (1) and the wirings LWR (1,1) and WR (1,1). It is connected to the input terminal of the next-stage repeater RP (1, 2) via the repeater line RL (1). Thus, the repeater RP (1,1) can drive the control signal to the next-stage repeater RP (1,2) while driving the control signal to the pixel P (1,1).

  The repeater RP (1, 2) has an input terminal connected to the repeater RP (1, 1) via the repeater line RL (1). The repeater RP (1,2) has an output terminal connected to the pixel P (1,2) via the repeater line RL (1) and the wirings LWR (1,2), WR (1,2). It is connected to the input terminal of the next-stage repeater RP (1, 3) via the repeater line RL (1). Thus, the repeater RP (1,2) can drive the control signal to the next-stage repeater RP (1,3) while driving the control signal to the pixel P (1,2).

  The repeater RP (1,3) has an input terminal connected to the repeater RP (1,2) via the repeater line RL (1). The repeater RP (1,3) has an output terminal connected to the pixel P (1,3) via the repeater line RL (1) and the wirings LWR (1,3), WR (1,3). It is connected to the input terminal of the next-stage repeater RP (1, 4) via the repeater line RL (1). Thus, the repeater RP (1,3) can drive the control signal to the next-stage repeater RP (1,4) while driving the control signal to the pixel P (1,3).

  The repeater RP (1, 4) has an input terminal connected to the repeater RP (1, 3) via the repeater line RL (1). The output terminal of the repeater RP (1, 4) is connected to the pixel P (1, 4) via the repeater line RL (1) and the wirings LWR (1, 4), WR (1, 4). Thereby, repeater RP (1, 4) can drive a control signal to pixel P (1, 4).

  Similarly, the plurality of repeaters RP (4,1) to RP (4,4) are arranged on the repeater line RL (4) corresponding to the plurality of pixels P (4,1) to P (4,4). Has been. The plurality of repeaters RP (4,1) to RP (4,4) can drive the pixels P (4,1) to P (4,4) in the same row in the pixel array PA.

  As described above, in the first embodiment, in the solid-state imaging device 100, by stacking chips using substrate bonding, electrode junctions can be arranged below the pixel region, and a plurality of lower chip repeater lines are arranged. A plurality of repeaters are inserted at positions corresponding to the pixels, and a driven control signal is supplied from the lower chip to the upper chip. Thereby, since the control signal can be driven in the middle of the path of the control signal from the row decoder 93 to the pixel, the delay of the control signal can be easily reduced as compared with the case where the control signal is driven from one end side of the drive line DL. The pixel driving time can be easily shortened. As a result, the frame rate can be increased, and the required frame rate can be satisfied.

  In the first embodiment, in the solid-state imaging device 100, for example, the repeaters RP (1,1) to RP (1,3) are control signals to the pixels P (1,1) to P (1,3). , The control signals to the next-stage repeaters RP (1,2) to RP (1,4) can be driven. As a result, the drive capability of each of the repeaters RP (1,1) to RP (1,3) can be reduced compared to the case where the control signal is driven from one end side of the drive line DL, and the delay of the control signal can be easily reduced. it can. Further, since pixels farther from the row decoder 93 are repeatedly driven, the difference in waveform distortion of the control signal between the pixels P (1,1) closer to the row decoder 93 and the far pixels P (1,4) can be reduced. . Further, since the control signal is transmitted by the common repeater line RL (1) to the pixel P (1,1) close to the row decoder 93 and the far pixel P (1,4), the repeater line RL (1) The wiring density can be suppressed, and the repeater line RL (1) can be easily thickened so that the wiring resistance of the repeater line RL (1) is not applied.

  Note that a repeater RP corresponding to each pixel is arranged on each repeater line RL, but a repeater RP corresponding to each of a plurality of pixels may be arranged.

  The drive lines DL in each row in the semiconductor chip CH1 may be divided for each repeater RP. For example, in the drive line DL (1) in the first row shown in FIG. 6, the broken line portion shown in FIG. 8 is cut, and as shown in FIG. The driving lines DL (1) _1 to DL (1) _4 may be divided. FIG. 8 is a circuit diagram illustrating a stacked configuration of a solid-state imaging device 100i according to a modification of the first embodiment. The drive lines in other rows may be configured similarly. Thereby, for example, since the number of pixels P connected to the drive line DL connected to each repeater RP can be reduced to one, the capacitance value of the drive line DL can be effectively reduced in the solid-state imaging device 100i. The delay of the control signal can be easily reduced.

  Alternatively, the row decoder in the semiconductor chip CH2 may drive the control signal on both sides of the repeater line. For example, as shown in FIG. 9, a row decoder 93 'may be connected to the opposite side of the row decoder 93 in each repeater line RL (1) to RL (4). FIG. 9 is a circuit diagram illustrating a stacked configuration of a solid-state imaging device 100j according to a modification of the first embodiment. For example, the row decoder 93 includes repeaters RP (1, 1), RP (1, 2), wiring LWR (1, 1), LWR (1, 2), WR (1, 1), WR (1, 2). The pixels P (1,1) and P (1,2) can be driven via the vias. For example, the row decoder 93 ′ includes repeaters RP (1, 4), RP (1, 3), wirings LWR (1, 4), LWR (1, 3), WR (1, 4), WR (1, 3). ), The pixels P (1, 4) and P (1, 3) can be driven. As described above, since the pixels in each row can be driven from both sides of the drive line, in the solid-state imaging device 100j, the drive capability of the control signal can be increased and the delay of the control signal can be further reduced.

  Alternatively, in the configuration shown in FIG. 9, the repeater lines RL in each row in the semiconductor chip CH2 may be divided for each of the row decoders 93 and 93 '. For example, in the repeater line RL (1) in the first row shown in FIG. 9, the broken line portion shown in FIG. 10 is cut, and as shown in FIG. It may be divided into repeater lines RL (1) _1 and RL (1) _2. FIG. 10 is a circuit diagram illustrating a stacked configuration of a solid-state imaging device 100k according to a modification of the first embodiment. The drive lines in other rows may be configured similarly. Thereby, for example, the number of repeaters RP connected to the repeater lines RL connected to the row decoders 93 and 93 ′ can be reduced by half, so that the capacitance value of the repeater lines RL can be effectively reduced in the solid-state imaging device 100k. The delay of the control signal can be easily reduced.

  Alternatively, in the configuration shown in FIG. 10, the drive lines DL in each row in the semiconductor chip CH1 may be divided for each repeater RP. For example, in the drive line DL (1) in the first row shown in FIG. 10, the broken line portion shown in FIG. 11 is cut and the drive line DL (1) in the first row has a plurality of drive lines DL (1) as shown in FIG. The driving lines DL (1) _1 to DL (1) _4 may be divided. FIG. 11 is a circuit diagram illustrating a stacked configuration of a solid-state imaging device 100p according to a modification of the first embodiment. The drive lines in other rows may be configured similarly. Thereby, for example, since the number of pixels P connected to the drive line DL connected to each repeater RP can be reduced to one, the capacitance value of the drive line DL can be effectively reduced in the solid-state imaging device 100p. The delay of the control signal can be easily reduced.

(Second Embodiment)
Next, a solid-state imaging device 200 according to the second embodiment will be described. Below, it demonstrates centering on a different part from 1st Embodiment.

  In the first embodiment, the control signal output from the row decoder 93 and driven by the repeater RP is supplied to the pixel P via the wirings LWR and WR, and the pixel P is driven.

  However, if the operating voltage of the row decoder 93 and the repeater RP is lowered for the purpose of reducing the power consumption, the level of the control signal supplied to the pixel P may not be sufficient as required. Can occur. For example, if the active level of the control signal φREADn remains relatively low, when the transfer unit 8 is turned on and charges of the photoelectric conversion unit 3 are transferred to the charge-voltage conversion unit 4, some charges are transferred. There is a possibility that an afterimage resulting from remaining in the photoelectric conversion unit 3 without being generated.

  Therefore, in the second embodiment, the control signal output from the row decoder 93 and driven by the repeater RP is converted into a desired voltage amplitude (desired level) before being supplied to the pixel P.

  Specifically, as shown in FIG. 12, the semiconductor chip CH202 further includes a plurality of level shifters LS (1,1) to LS (4,4). FIG. 12 is a circuit diagram illustrating a stacked configuration of the solid-state imaging device 200. The plurality of level shifters LS (1,1) to LS (1,4) are connected to the plurality of pixels P (1,1) to P (1,4) on the wirings LWR (1,1) to LWR (1,4). It is arranged corresponding to. The plurality of level shifters LS (1,1) to LS (1,4) can drive the pixels P (1,1) to P (1,4) in the same row in the pixel array PA.

  For example, the level shifter LS (1, 1) is disposed on the wiring LWR (1, 1). When the amplitude of the control signal output from the row decoder 93 and driven by the repeater RP (1,1) is V1, the level shifter LS (1,1) converts the amplitude of the control signal from V1 to V2 (> V1). To do. The level shifter LS (1, 1) supplies the control signal whose amplitude is converted to V2 to the pixel P (1, 1) via the wirings LWR (1, 1) and WR (1, 1). Thereby, the pixel P (1, 1) can be operated with a control signal of a desired level.

  The level shifter LS (1, 4) is disposed on the wiring LWR (1, 4). When the amplitude of the control signal output from the row decoder 93 and driven by each of the repeaters RP (1,1) to RP (1,4) is V1, the level shifter LS (1,4) determines the amplitude of the control signal. Conversion from V1 to V2 (> V1). The level shifter LS (1, 4) supplies the control signal whose amplitude is converted to V2 to the pixel P (1, 4) via the wirings LWR (1, 4) and WR (1, 4). Thereby, the pixel P (1, 4) can be operated with a control signal of a desired level.

  As described above, in the second embodiment, in the solid-state imaging device 200, the control signal output from the row decoder 93 and driven by the repeater RP is supplied to the pixel P with a desired voltage amplitude (desired by the level shifter LS). Level). As a result, when the operating voltage of the row decoder 93 and the repeater RP is lowered to reduce power consumption, the pixel P can be operated with a control signal of a desired level, and the characteristics of the pixel P are improved. Can be made.

  The level shifter may be arranged on each repeater line RL instead of being arranged on each wiring LWR. For example, as shown in FIG. 13, in the solid-state imaging device 200 ', the semiconductor chip CH202' may include a plurality of level shifters LS '(1) to LS' (4). FIG. 13 is a circuit diagram illustrating a stacked configuration of the solid-state imaging device. The level shifters LS ′ (1) to LS ′ (4) are arranged between the row decoder 93 and the plurality of repeaters PR on the repeater lines RL (1) to RL (4).

  For example, the level shifter LS ′ (1) is disposed between the row decoder 93 and the plurality of repeaters PR (1, 1) to RP (1, 4) on the repeater line RL (1). When the amplitude of the control signal output from the row decoder 93 is V1, the level shifter LS ′ (1) converts the amplitude of the control signal from V1 to V2 (> V1). The level shifter LS ′ (1) receives the control signal whose amplitude is converted to V2 through the repeater line RL (1), the repeater PR (1,1), and the wiring LWR (1,1), WR (1,1). To P (1,1). Thereby, the pixel P (1, 1) can be operated with a control signal of a desired level.

  Thus, when the level shifter LS ′ is arranged between the row decoder 93 and the plurality of repeaters PR on each repeater line RL instead of being arranged on each wiring LWR, the number of level shifters LS ′ to be prepared is reduced. Thus, the cost of the solid-state imaging device 200 ′ can be reduced.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  81 imaging system, 100 solid-state imaging device.

Claims (5)

A first semiconductor chip having a plurality of pixels;
The first semiconductor chip is stacked, an AD conversion circuit, a control circuit, a repeater line extending from the control circuit, a wiring for connecting the repeater line to the plurality of pixels three-dimensionally, and the repeater line A second semiconductor chip having a plurality of repeaters arranged corresponding to the plurality of pixels;
A solid-state imaging device comprising: The plurality of pixels includes a first pixel and a second pixel,
The plurality of repeaters are:
A first repeater having an input terminal connected to the control circuit via the repeater line and an output terminal connected to the first pixel via the repeater line and the wiring;
A second repeater having an input terminal connected to the output terminal of the first repeater via the repeater line and an output terminal connected to the second pixel via the repeater line and the wiring;
The solid-state imaging device according to claim 1, comprising: The plurality of pixels are arranged at least in the row direction,
The repeater line extends in a row direction,
The solid-state imaging device according to claim 1, wherein the wiring three-dimensionally connects the repeater line to a plurality of pixels in the same row. 4. The solid-state imaging device according to claim 1, wherein the second semiconductor chip further includes a plurality of level shifters arranged on the wiring corresponding to the plurality of pixels. 5. . 4. The solid state according to claim 1, wherein the second semiconductor chip further includes a level shifter disposed between the control circuit and the plurality of repeaters on the repeater line. 5. Imaging device.

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