JP2016163288A - Analog/digital conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D conversion device capable of continuing A/D conversion processing even if an abnormality occurs in a part of a component to be converted into a digital signal when converting an analog signal into a digital signal and generating the digital signal.SOLUTION: An A/D conversion device comprises: a voltage superposition part 11 for outputting an analog signal by superposing a predetermined voltage on a conversion target analog signal 1; A/D converters 3a-3h to which the analog signal is inputted and which are disposed in parallel; a digital signal combination part 12 for combining digital signals that are converted by the A/D converters 3a-3h; an output signal measurement part 4 for measuring the digital signals of the A/D converters 3a-3h; and a fault discrimination part 13 that uses the digital signals measured by the output signal measurement part 4 to individually discriminates faults in the A/D converters 3a-3h.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an analog / digital conversion apparatus that converts an analog signal into a high-resolution digital signal.

  In recent years, with higher performance of electronic control devices, sensors mounted on the electronic control devices are also required to have high accuracy. For example, the voltage sensor converts an analog voltage value into a digital value by an A / D converter, and the converted digital value is represented by an N-bit value and is used as a reference value for failure detection or power control. The accuracy of the digital value after conversion is determined by N which is the resolution of the A / D converter. Therefore, an A / D conversion device for obtaining high resolution is required.

For this reason, for example, in the analog-digital converter of Patent Document 1, 2 ^m resistors connected in series to an AD converter for converting an analog input voltage into a digital signal of upper m bits and lower n bits, the ^m comparators, of ^the 2 ⁿ connected in series resistance, ^the 2 ⁿ comparators, and comprises an amplifier. The upper bit is determined by comparing the input voltage with a reference voltage obtained by dividing the first predetermined voltage by 2 ^m resistors, and the difference voltage between the input voltage and the voltage represented by the upper bit is amplified. It is disclosed that the lower bit is determined by comparing the obtained voltage with a reference voltage obtained by dividing the second predetermined voltage by ²ⁿ resistors. This realizes a high-speed AD converter that requires a small number of parts for generating the reference voltage and does not require a highly accurate comparator.

Japanese Patent Laid-Open No. 10-285032

  However, the conventional A / D converter of Patent Document 1 has a problem that A / D conversion processing cannot be continued if any of the comparators constituting the A / D converter becomes unusable due to a failure or the like. there were.

  The present invention has been made to solve the above problems, and when an analog signal is converted into a digital signal and generated, even if an abnormality occurs in a part of the component that converts into a digital signal, An object of the present invention is to provide an analog / digital conversion device capable of continuing the A / D conversion process.

  In order to solve the above-described problems, an analog / digital conversion apparatus according to the present invention includes N A / D converters that are connected in parallel and convert an analog signal into a digital signal, and the N A / D converters. A failure determination unit that individually determines whether or not there is a failure in the converter, and n * (minimum resolution analog signal / (N−M)) (where M is the number of failures, n = 0, 1, .., NM-1) are sequentially superposed individually and output to NM A / D converters that are not determined to be faulty, and the N A / Ds. A digital signal synthesis unit that synthesizes digital signals output from the NM A / D converters that are not determined to be faulty among the converters.

  According to the analog / digital conversion apparatus of the present invention, an analog signal in which a predetermined voltage is individually superimposed on an analog signal to be converted is input to a plurality of A / D converters arranged in parallel, and the digital signal After being converted to, by synthesizing these digital signals, it is possible to obtain a high resolution according to the number of A / D converters, and when any A / D converter has an abnormality However, there is an effect that the A / D conversion process can be continued with a resolution suitable for the number of remaining A / D conversions.

1 is a schematic configuration diagram of an analog / digital conversion device according to a first embodiment. 3 is a flowchart illustrating a processing process of a voltage superimposing unit in the first embodiment. 6 is a diagram illustrating an example of a processing result of a voltage superimposing unit in Embodiment 1. FIG. 3 is a flowchart showing processing steps of a digital signal synthesis unit in the first embodiment. 6 is a diagram illustrating an example of a processing result of a digital signal synthesis unit according to Embodiment 1. FIG. 6 is a diagram illustrating an example of a processing result of the analog / digital conversion device in Embodiment 1. FIG. 3 is a flowchart illustrating an overall processing process of a failure determination unit according to the first embodiment. 3 is a flowchart showing a detachment digital signal detection processing step of a failure determination unit in the first embodiment. 6 is a diagram illustrating an example of a result of an outlier digital signal detection process performed by a failure determination unit according to Embodiment 1. FIG. 3 is a flowchart illustrating an under-digital signal detection processing step of a failure determination unit in the first embodiment. 6 is a diagram illustrating an example of an under-digital signal detection processing result of a failure determination unit according to Embodiment 1. FIG.

  Details of an analog / digital conversion device (hereinafter referred to as an A / D conversion device) according to an embodiment of the present invention will be described below with reference to FIGS.

Embodiment 1 FIG.
FIG. 1 is a schematic configuration diagram of the A / D conversion device according to the first embodiment, FIG. 2 is a flowchart showing processing steps of the voltage superimposing unit, and FIG. 3 is an example of processing results of the voltage superimposing unit. 4 is a flowchart showing the processing steps of the digital signal synthesis unit, FIG. 5 is a diagram showing an example of the processing result of the digital signal synthesis unit, and FIG. It is a figure which shows the example of the process result of D conversion apparatus. Further, FIG. 7 is a flowchart showing the entire processing steps of the failure determination unit, FIG. 8 is a flowchart showing the failure digital signal detection processing step of the failure determination unit, and FIG. FIG. 10 is a flowchart illustrating an example of an under-digital signal detection processing step of the failure determination unit, and FIG. 11 illustrates an example of an under-digital signal detection process result of the failure determination unit. FIG.

First, the configuration of the A / D conversion device according to the first embodiment will be described with reference to FIG. The A / D converter includes a voltage superimposing unit 11 that outputs an analog signal in which a predetermined voltage is superimposed on a conversion target analog signal 1, and an A / D converter arranged in parallel to which the output analog signal is input. 3a to 3h, a digital signal synthesizer 12 that synthesizes the digital signals converted by the A / D converters 3a to 3h, and an A / D converter 3a to 3h that is connected between the digital signal synthesizer 12 and A A / D converters 3a to 3h using the output signal measuring unit 4 that measures the digital signals of the D / D converters 3a to 3h and the digital signals measured by the digital signal sensors 4a to 4h of the output signal measuring unit 4 And a failure determination unit 13 for individually determining the failure. Here, an example in which eight A / D converters are arranged in parallel is shown.

  Next, the flow of processing steps of the voltage superimposing unit 11 and the digital signal synthesizing unit 12 in the first embodiment will be described with reference to the flowcharts of FIGS.

  First, the voltage superimposing unit 11 will be described with reference to the flowchart of FIG. In the process of the voltage superimposing unit 11, the initial value of the number of normal A / D converters N and the initial value of the counter C used for calculation are set in the process of step S1101. Both the number of normal A / D converters N and the counter C used for calculation are set to “0” as initial values.

  Next, in the process of step S1102, the process is repeatedly performed from the A / D converter 3a to the A / D converter 3h in the processes of steps S1103 and S1104 described below. Here, x used in the description of the processes in steps S1103 and S1104 represents a to h, and indicates that the process corresponds to the A / D converter 3h to the A / D converter 3h.

  In step S1103, it is determined whether or not the state of the A / D converter 3x is “normal”. If it is determined that the state of the A / D converter 3x is “normal”, 1 is added to the number N of normal A / D converters in the next step S1104. If it is determined that the state of the A / D converter 3x is not “normal”, the process of step S1104 is skipped, and this process is not performed.

  The number of normal A / D converters N indicating the number of A / D converters in which the state is “normal” among the A / D converters 3 a to 3 h by the processing of steps S 1102 to S 1104 described above. Is calculated.

  Next, in the process of step S1105, the process is repeatedly performed from the A / D converter 3a to the A / D converter 3h in the processes of steps S1106 to S1109 described below. X used in the description of the processing in steps S1106 to S1109 represents a to h, and indicates that the processing is from the A / D converter 3a to the A / D converter 3h.

First, in step S1106, it is determined whether or not the state of the A / D converter 3x is “normal”. If it is determined that the state of the A / D converter 3x is “normal”, the analog signal Vin_x calculated by using the following expression (1) in the process of the next step S1107 is A / D It is input to the D converter 3x. The analog signal Vin_x is calculated using the conversion target analog signal 1, the minimum resolution analog signal 2, the number of normal A / D converters N, and the counter C. Next, 1 is added to the counter C in the process of step S1108.

Vin_x = analog signal to be converted + (minimum resolution analog signal × (C / N))
... (1)

Here, the minimum resolution analog signal 2 indicates the magnitude of the analog signal corresponding to the digital signal “1” output from the A / D converter 3x. For example, in the case of the A / D converter 3x that converts an input voltage of 0 to 5V into a 12-bit digital value, the minimum resolution analog signal 2 is 5V / 2 ¹² ≈0.0012207V.

  If it is determined in step S1106 that the state of the A / D converter 3x is not “normal”, the analog signal Vin_x = 0 is input to the A / D converter 3x in the next step S1109. Is done.

  Through the processes in steps S1105 to S1109 described above, an analog signal in which the predetermined voltage represented by the expression (1) is superimposed on the conversion target analog signal 1 is input from the A / D converter 3a to the A / D converter 3h. . That is, the voltage superimposing unit 11 adds n * (minimum resolution analog signal / (N−M)) (where n = 0) to the conversion target analog signal 1 when M is the number of A / D converter failures. , 1,..., NM-1) are sequentially superimposed on each other and output to an A / D converter that has not been determined to be faulty.

  FIG. 3 shows an example in which an analog signal is input to the A / D converters connected in parallel by the voltage superimposing unit 11. Here, a case where the states of the A / D converter 3c and the A / D converter 3g in the A / D converter 3a to the A / D converter 3h are determined to be “failure” will be described as an example. To do. In this case, the number of A / D converters in which the state is “normal” is 6 (N = 6), and the analog signal input to the A / D converter in which the state is “normal” Are inputted so as to be equal within “minimum resolution analog signal / 6”.

  Next, the digital signal synthesis unit 12 will be described with reference to the flowchart of FIG. In the processing of the digital signal synthesis unit 12, the initial value of the normal A / D converter number N and the initial value of the digital signal total value Dsum are set in the processing of step S1201. “0” is set as an initial value for the number of normal A / D converters N and the digital signal total value Dsum.

  Next, in the process of step S1202, the process is repeatedly performed from the A / D converter 3a to the A / D converter 3h in the processes of steps S1203 to S1205 described below. X used in the description of the processes in steps S1203 to S1205 represents a to h, and indicates that the process is performed from the A / D converter 3a to the A / D converter 3h.

  First, in step S1203, it is determined whether the state of the A / D converter 3x is “normal”. If it is determined that the state of the A / D converter 3x is “normal”, 1 is added to the number N of normal A / D converters in the process of step S1204. In step S1205, the digital signal from the A / D converter 3x is added to the digital signal total value Dsum.

  Through the processes in steps S1203 to S1205 described above, the number N of normal A / D converters representing the number of A / D converters in the “normal” state and the digital signal total value Dsum are calculated.

Next, in the process of step S1206, an analog signal Dave calculated using the following equation (2) is output. The analog signal Dave is calculated using the number of normal A / D converters N and the digital signal total value Dsum.

Dave = Dsum / N (2)

  As a result of the processing in steps S1201 to S1206, the digital signal synthesizer 12 outputs the signals from a plurality of A / D converters that are not determined to be faulty among the A / D converters 3a to 3h. Digital signals are combined and output as a combined digital signal 10.

FIG. 5 shows an example in which the digital signal output from the A / D converters connected in parallel by the digital signal combining unit 12 is combined. Among the A / D converter 3a to A / D converter 3h, the states of the A / D converter 3c and the A / D converter 3g are “failure”, and the A / D converter 3a, A / D When the digital signal output from the converter 3b, the A / D converter 3d and the A / D converter 3e is X, and the digital signal output from the A / D converter 3f and the A / D converter 3h is X + 1 Will be described as an example. Since the output of the digital signal when the analog signal is “0” depends on the specifications of the A / D converter, it is an indefinite value in this example. In this case, the number of A / D converters whose state is “normal” is 6 (N = 6), and the combined digital signal 10 output from the digital signal combining unit 12 is X + (2/6). .

  According to the above processing, among the plurality of A / D converters that perform A / D conversion, the voltage is superimposed so that the analog signal difference input to the non-failed A / D converter is equalized. Thus, a high-resolution digital signal can be obtained for a single A / D converter.

  FIG. 6 shows an example in which three types of conversion target analog signals Vin_A, Vin_B, and Vin_C are converted into the composite digital signal 10 according to the first embodiment. A case where all the states of the A / D converter 3a to the A / D converter 3h are “normal” will be described as an example. Since the conversion target analog signals Vin_A, Vin_B, and Vin_C are analog signals whose digital signals are equal to or greater than X and less than X + 1, when there is one A / D converter, the digital signals are all X. On the other hand, in the case of the conversion according to the first embodiment, the digital signal output from the A / D converter 3a to the A / D converter 3h by the voltage superimposing unit 11 is X or X + 1. As a result, the synthesized digital signal 10 output from the digital signal synthesizer 12 can obtain a signal having a resolution that is eight times the resolution of the A / D converter.

  In the first embodiment, the combined digital signal 10 output from the digital signal combining unit 12 is an average value, but the digital signal total value and the number of normal A / D converters are output simultaneously. Also good.

As a result, the A / D converter has a configuration in which a plurality of A / D converters are connected in parallel, so that the resolution of the A / D converter is Y bits and the number of A / D converters is N. In this case, a digital signal having a resolution corresponding to (Y + log ₂ N) bits can be obtained. Further, when M A / D converters fail, it is equivalent to (Y + log ₂ (N−M)) bits by using (NM) A / D converters that are not failed. A digital signal with the resolution to be obtained can be obtained.

  Next, the flow of the entire processing steps of the failure determination unit 13 will be described using the flowchart of FIG. In the process of the failure determination unit 13, first, an outlier digital signal detection process is performed in the process of step S 1300, and a digital signal outside the predetermined range is output as compared with the digital signals of other A / D converters. A / D converter is detected. Furthermore, in the process of the next step S1350, an under-digital signal detection process is performed, and an A / D converter that outputs a smaller digital signal compared to the digital signals of other A / D converters is detected.

  Details of the outlier digital signal detection processing performed in the processing of step S1300 will be described with reference to the flowchart of FIG. First, in the process of step S1301, the digital signals Da to Dh of the A / D converter whose state is “normal” among the A / D converters 3a to 3h are converted into the digital signal sensors 4a to 4h. Is detected.

  Next, in the process of step S1302, among the digital signals Da to Dh, the maximum value digital signal Dmax and the minimum value digital signal Dmin are respectively calculated.

  Next, in the process of step S1303, a process for determining the difference between the maximum value digital signal Dmax and the minimum value digital signal Dmin is performed. When the difference is 2 or more, processing in steps S1304 to S1311 described later is performed, and when the difference is less than 2, the outlier digital signal detection processing is ended.

A case will be described in which the difference between the maximum value digital signal Dmax and the minimum value digital signal Dmin is 2 or more in the process of step S1303 described above. First, in step S1304, among the digital signals Da to Dh, the number of digital signals Smax equal to or greater than the maximum value digital signal Dmax-1 and the number of digital signals Smin equal to or less than the minimum value digital signal Dmin + 1 are calculated.

  Next, in step S1305, a comparison determination process is performed to determine whether the number of digital signals Smax and the number of digital signals Smin are equal. When the digital signal number Smax and the digital signal number Smin are not equal, the process proceeds to step S1306 or step S1309. When the number of digital signals Smax is smaller than the number of digital signals Smin, processing in steps S1306 to S1308 described later is performed. When the digital signal number Smax is larger than the digital signal number Smin, processing in steps S1309 to S1311 described later is performed. If it is determined in step S1305 that the number of digital signals Smax and the number of digital signals Smin are equal, the outlier digital signal detection processing is terminated.

  First, the case where the number of digital signals Smax is smaller than the number of digital signals Smin in the process of step S1305 will be described. In step S1306, steps S1307 and S1308 described below are repeatedly performed from the A / D converter 3a to the A / D converter 3h. X used in the description of the processes in steps S1307 and S1308 represents a to h, and indicates that the process is from the A / D converter 3a to the A / D converter 3h.

  Subsequently, in step S1307, it is determined whether or not the state of the A / D converter 3x is “normal” and the digital signal Dx is equal to the maximum digital signal Dmax. When the state of the A / D converter 3x is “normal” and the digital signal Dx and the maximum value digital signal Dmax are equal, in the next step S1308, the state of the A / D converter 3x is “ "Failure". If it is determined in step S1307 that the state of the A / D converter 3x is not “normal” or if the digital signal Dx is not equal to the maximum digital signal Dmax, the process in step S1308 is not performed.

  Next, the case where the number of digital signals Smax is larger than the number of digital signals Smin in the process of step S1305 described above will be described. In step S1309, steps S1310 and S1311 described below are repeatedly performed from the A / D converter 3a to the A / D converter 3h. X used in the description of the processes in steps S1310 and S1311 represents a to h, and indicates that the process is performed from the A / D converter 3a to the A / D converter 3h.

  Subsequently, in the process of step S1310, it is determined whether or not the state of the A / D converter 3x is “normal” and the digital signal Dx is equal to the digital signal Dmin having the minimum value. When the state of the A / D converter 3x is “normal” and the digital signal Dx is equal to the minimum digital signal Dmin, the state of the A / D converter 3x is “in step S1311”. It is determined that it is a “failure”. If the state of the A / D converter 3x is not “normal” or the digital signal Dx is not equal to the minimum digital signal Dmin in the process of step S1310, the process of step S1311 is not performed.

  The state of the A / D converter that outputs the digital signal out of the predetermined range compared with the digital signals of other A / D converters by the out-of-process digital signal detection processing of steps S1301 to S1311 is as follows. , “Failure” is determined.

  FIG. 9 shows an example in which a failure is detected by the outlier digital signal detection processing in steps S1301 to S1311. In FIG. 9, a case where the A / D converter 3e has already been determined to be “failure” will be described as an example. In FIG. 9A, the maximum value digital signal Dmax is the digital signal Df, the minimum value digital signal Dmin is the digital signals Da, Db, and Dc, and the number of digital signals Smax is smaller than the number of digital signals Smin. The digital signal Df is off and is a digital signal, indicating that the state of the A / D converter 3f is “failure”. In FIG. 9B, the digital signal Dmax having the maximum value is the digital signals Dd, Df, Dg and Dh, the digital signal Dmin having the minimum value is the digital signal Dc, and the digital signal number Smax is larger than the digital signal number Smin. This indicates that the digital signal Dc is off and is a digital signal, and the state of the A / D converter 3c is “failure”.

  Details of the under-digital signal detection process performed in step S1350 described above will be described with reference to the flowchart of FIG. First, in the process of step S1351, the determination state of under-digital signal detection is set to the initial value “unconfirmed”.

  Next, in the process of step S1352, the digital signals Da to Dh of the A / D converter whose state is “normal” among the A / D converters 3a to 3h are converted into the digital signal sensors 4a to 4h. Detected by 4h.

  Next, in step S1353, the processes in steps S1354 to S1362 described below are repeated from the A / D converter 3a to the A / D converter 3h. X used in the description of the processing of steps S1354 to S1362 represents a to h, and indicates that the processing is from the A / D converter 3a to the A / D converter 3h. Also, x-1 indicates the previous alphanumeric character. For example, in the state where the digital signals Da, Db, Dd are detected and x is b, x-1 indicates a and x is d. In the case of x-1, x-1 represents b.

First, in the process of step S1354, it is determined whether or not the digital signal Dx is equal to the digital signal Dx-1. If the digital signal Dx is equal to the digital signal Dx−1, it is further determined in the process of step S1355 whether or not the determination state is “indeterminate”. If the determination state is “unconfirmed”, the determination state is set to “lower limit determination” and the lower limit value Dlow in the detection of an under-digital signal is set to Dx in the next step S1356. If the determination state is not “indeterminate”, it is further determined in step S1357 whether the determination state is “lower limit determined” and the digital signal Dx is equal to the lower limit Dlow + 1. When the determination state is “determined lower limit value” and the digital signal D _x is equal to the lower limit value Dlow + 1, the determination state is determined as “determined upper limit value” in the processing of the next step S1358, and the upper limit in under-digital signal detection. Let the value Dhigh be Dx. If the determination state is other than “determined lower limit value” or the digital signal Dx is not equal to the lower limit value Dlow + 1, the process of step S1358 is not performed.

  If the digital signal Dx is not equal to the digital signal Dx−1 in the determination of the process in step S1354, it is further determined in step S1359 whether the digital signal Dx is smaller than the digital signal Dx−1. The If the digital signal Dx is smaller than the digital signal Dx−1, it is further determined in step S1360 whether or not the determination state is “lower limit determined” and the digital signal Dx is smaller than the lower limit Dlow. . When the determination state is “determined lower limit value” and the digital signal Dx is smaller than the lower limit value Dlow, the state of the A / D converter 3x is set to “failure” in the next step S1361. If the determination state is other than “determined lower limit value”, or if the digital signal Dx is greater than or equal to the lower limit value Dlow, then in step S1362, the determination state is “determined upper limit value” and the digital signal Dx is the upper limit value. It is determined whether the value is less than Dhigh. When the determination state is “fixed upper limit value” and the digital signal Dx is smaller than the upper limit value Dhigh, the state of the A / D converter 3x is set to “failure” in the next step S1361. If the determination state is other than “fixed upper limit value” or the digital signal Dx is equal to or higher than the upper limit value Dhigh, the process of step S 1361 is not performed.

  As a result of the under-digital signal detection processing in steps S1351 to S1362 described above, the A / D converter that outputs a digital signal smaller than the digital signals of other A / D converters is regarded as “failure”.

  FIG. 11 shows an example in which a failure is detected by the under-digital signal detection process of steps S1351 to S1362. In FIG. 11, a case where the A / D converter 3e has already been determined to be “failure” will be described as an example. In FIG. 11A, since the lower limit value Dlow is determined in the determination of the digital signal Db and the digital signal Dc is smaller than the lower limit value Dlow in the determination of the digital signal Dc, the digital signal Dc is an under-digital signal. It shows that the state of the A / D converter 3c is “failure”. In FIG. 11B, since the upper limit value Dhigh is determined in the determination of the digital signal Dd and the digital signal Df is smaller than the upper limit value Dhigh in the determination of the digital signal Df, the digital signal Df is an under-digital signal. This indicates that the state of the / D converter 3f is “failure”.

  According to the above processing, a faulty A / D converter is determined by digital signal output among a plurality of A / D converters that perform A / D conversion, and a faulty A / D converter is not detected. By superimposing the voltage so that the difference between the analog signals input to is equal, a high-resolution digital signal can be obtained for a single A / D converter.

  As described above, according to the A / D conversion device according to the first embodiment, a plurality of A / D conversions in which analog signals in which predetermined voltages are individually superimposed on analog signals to be converted are arranged in parallel are performed. After being input to the converter and converted into digital signals, these digital signals can be combined to obtain a high resolution according to the number of A / D converters, and to any A / D converter Even when an abnormality occurs, an abnormal A / D converter can be accurately extracted by detecting and comparing digital signal outputs of a plurality of A / D converters, and the remaining normal A / D conversions. There is an effect that the A / D conversion process can be continued with a resolution suitable for the number of A / D.

  Note that the present invention is not limited to the above-described embodiment, and the embodiment can be appropriately modified and omitted within the scope of the invention.

  Moreover, in the figure, the same code | symbol shows the same or an equivalent part.

  1 conversion target analog signal, 2 minimum resolution analog signal, 3a to 3h A / D converter, 4 output signal measuring unit, 4a to 4h digital signal sensor, 10 synthesized digital signal, 11 voltage superimposing unit, 12 digital signal synthesizing unit, 13 Failure judgment part

Claims (2)

N A / D converters connected in parallel and converting an analog signal into a digital signal;
A failure determination unit for individually determining the presence or absence of a failure in the N A / D converters;
N * (minimum resolution analog signal / (N−M)) (where M is the number of failures, n = 0, 1,..., N−M−1) sequentially and individually for the analog signal to be converted A voltage superimposing unit that outputs to NM A / D converters that are not determined to be faulty by superimposing;
A digital signal synthesizing unit that synthesizes digital signals output from the NM A / D converters that are not determined to be faulty among the N A / D converters;
An analog / digital conversion device characterized by comprising: An output signal measuring unit for individually measuring digital signals output from the N A / D converters;
2. The failure determination unit determines whether or not the N A / D converters have a failure by comparing the digital signals measured by the output signal measurement unit with each other. The analog / digital conversion device described.

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