JP2016162977A - Wiring board and manufacturing method of the same - Google Patents

Wiring board and manufacturing method of the same Download PDF

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Publication number
JP2016162977A
JP2016162977A JP2015042917A JP2015042917A JP2016162977A JP 2016162977 A JP2016162977 A JP 2016162977A JP 2015042917 A JP2015042917 A JP 2015042917A JP 2015042917 A JP2015042917 A JP 2015042917A JP 2016162977 A JP2016162977 A JP 2016162977A
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Prior art keywords
wiring
layer
wiring board
insulating layer
connection
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山本 健一
Kenichi Yamamoto
健一 山本
千亜紀 朝倉
Chiaki Asakura
千亜紀 朝倉
隆浩 熊沢
Takahiro Kumazawa
隆浩 熊沢
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Eastern Co Ltd
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Eastern Co Ltd
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Priority to JP2015042917A priority Critical patent/JP2016162977A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which achieves excellent component mountability in a recessed part.SOLUTION: A wiring board (10) includes: wiring layers (16) which are laminated; an insulation layer (18-4) having a surface (17) and a surface (19) on which a wiring layer (16-4) and a wiring layer (16-5) of the wiring layers (16) are respectively provided; a cavity (24) which is recessed from a surface (17) side to a middle part of the insulation layer (18-4); and a connection part (22-4) which is electrically connected with the wiring layer (16-5) and is provided at the insulation layer (18-4) so as to be exposed on a bottom surface of the cavity (24). The connection part (22-4) has: an exposed surface (26) exposed on the bottom surface of the cavity (24); a connection surface (28) which contacts with the wiring layer (16-5); and a side surface (30) which contacts with the insulation layer (18-4). The side surface (30) inclines.SELECTED DRAWING: Figure 2

Description

本発明は、配線基板およびその製造方法に適用して有効な技術に関する。   The present invention relates to a technique effective when applied to a wiring board and a manufacturing method thereof.

特開2004−342641号公報(以下、「特許文献1」という。)には、キャビティの底面で露出するスルーホールを接続部として、キャビティ内でコンデンサを接続する技術が記載されている。   Japanese Patent Laying-Open No. 2004-326441 (hereinafter referred to as “Patent Document 1”) describes a technique for connecting a capacitor in a cavity using a through hole exposed on the bottom surface of the cavity as a connecting portion.

特開2004−342641号公報Japanese Patent Laid-Open No. 2004-326441

配線基板とこれに搭載される電子部品(例えば、半導体チップや、チップコンデンサなどの受動部品)とを備える電子製品の小型化(薄型化含む)や高機能化に伴い、配線基板にも工夫が求められている。例えば、配線基板自体の薄型化や、配線パターン(配線層)の微細化・高密度化が挙げられる。また、電子部品の搭載位置に関しては、基板平面上に限らず、電子部品を搭載(収容)させるための凹部(キャビティ;Cavity)を形成することで、基板内部に搭載する工夫もなされている。電子部品搭載用凹部を有する配線基板としては、例えば、特許文献1に記載の技術のように、ザグリ加工による電子部品搭載用凹部を形成し、このときに削られて短くなったスルーホールを電子部品との接続部として用いるものがある。   As electronic products including wiring boards and electronic components (for example, passive components such as semiconductor chips and chip capacitors) mounted on them are miniaturized (including thinning) and highly functional, wiring boards are also devised. It has been demanded. For example, the wiring board itself can be made thinner, and the wiring pattern (wiring layer) can be made finer and denser. Further, regarding the mounting position of the electronic component, not only on the substrate plane, but also a device for mounting inside the substrate is formed by forming a recess (cavity) for mounting (accommodating) the electronic component. As a wiring board having a recess for mounting an electronic component, for example, as in the technique described in Patent Document 1, a recess for mounting an electronic component is formed by counterbore processing. Some of them are used as connection parts with parts.

しかしながら、配線基板の薄型化に対応させた場合、特許文献1に記載の技術では、スルーホールの長さ(基板厚み方向の距離)が単に短くなり、配線基板の層間絶縁層との密着性が低下し、電子部品と接合されてスルーホールにストレスが掛かる条件によっては不具合(例えば、剥離など)が生じてしてしまうおそれがある。また、特許文献1に記載の技術では、スルーホールの端面が露出して電子部品と接続(接合)されるが、その露出面(接続面)の大きさや形状(円形状)がスルーホール自身に起因して制約されてしまい、微細化や、種々の形状(例えば、長方形状などの矩形状)には対応することができない。また、特許文献1に記載の技術では、電子部品搭載用凹部を形成する際に、スルーホールへの加工ストレスによりその内壁面の銅薄膜が剥離してしまうなどの不具合が生ずるおそれがある。   However, when dealing with the thinning of the wiring board, in the technique described in Patent Document 1, the length of the through hole (distance in the board thickness direction) is simply shortened, and the adhesion with the interlayer insulating layer of the wiring board is reduced. Depending on the conditions under which the through hole is stressed by being bonded to the electronic component, there is a possibility that a malfunction (for example, peeling) may occur. In the technique described in Patent Document 1, the end face of the through hole is exposed and connected (joined) to the electronic component, but the size and shape (circular shape) of the exposed face (connecting face) are in the through hole itself. Therefore, it is restricted and cannot cope with miniaturization and various shapes (for example, a rectangular shape such as a rectangular shape). Moreover, in the technique described in Patent Document 1, there is a risk that when forming the concave part for mounting an electronic component, a copper thin film on the inner wall surface is peeled off due to processing stress on the through hole.

本発明の目的は、凹部での部品搭載性に優れた配線基板を提供することにある。本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The objective of this invention is providing the wiring board excellent in the component mounting property in a recessed part. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。   Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

本発明の一解決手段に係る配線基板は、積層される複数の配線層と、前記複数の配線層の第1および第2配線層がそれぞれ設けられる第1および第2面を有する絶縁層と、前記第1面側から前記絶縁層の中途まで窪む凹部と、前記第2配線層と電気的に接続し、前記凹部の底面で露出するように前記絶縁層に設けられる接続部とを備え、前記接続部は、前記凹部の底面で露出する露出面と、前記第2配線層と接する接続面と、前記露出面および前記接続面と交差し、前記絶縁層に接する側面とを有し、該側面が傾斜していることを特徴とする。   A wiring board according to one solution of the present invention includes a plurality of wiring layers to be stacked, an insulating layer having first and second surfaces on which the first and second wiring layers of the plurality of wiring layers are respectively provided; A concave portion that is recessed from the first surface side to the middle of the insulating layer, and a connection portion that is electrically connected to the second wiring layer and is provided on the insulating layer so as to be exposed at the bottom surface of the concave portion, The connection portion has an exposed surface exposed at a bottom surface of the recess, a connection surface in contact with the second wiring layer, and a side surface that intersects the exposed surface and the connection surface and contacts the insulating layer, The side surface is inclined.

これによれば、絶縁層中の接続部の側面が傾斜していることで、傾斜していないものに比べて絶縁層との接触面積が大きくなるため接続部の密着性を向上させることができる。このため、例えば、基板が薄型化した場合であっても接続部が抜け取れてしまうことを防止することができる。すなわち、凹部に電子部品を搭載しても、接続部との接続信頼性が確保される部品搭載性に優れた配線基板を提供することができる。   According to this, since the side surface of the connection part in the insulating layer is inclined, the contact area with the insulating layer is larger than that of the non-inclined one, so that the adhesion of the connection part can be improved. . For this reason, for example, even when the substrate is thinned, it is possible to prevent the connection portion from being removed. That is, even if an electronic component is mounted in the recess, it is possible to provide a wiring board excellent in component mounting property that ensures connection reliability with the connection portion.

また、前記一実施形態に係る配線基板は、前記接続部が、前記第1面側から前記第2面側へ末広がる形状であることがより好ましい。これによれば、接続部が末広がる形状となることで、接続部を凹部の底面からより抜け取れ難くすることができる。   In the wiring board according to the embodiment, it is more preferable that the connection portion has a shape that spreads from the first surface side to the second surface side. According to this, since the connection portion has a shape that widens at the end, the connection portion can be more difficult to be removed from the bottom surface of the recess.

また、前記一実施形態に係る配線基板は、前記接続部が、前記第1面側から前記第2面側へ尻窄まる形状であることがより好ましい。このように、接続部を尻窄まる形状とすれば、所望の大きさの接続面を確保しつつ露出面(接続面)を大きくすることができるので、部品との接続信頼性をより確保することができる。   In the wiring board according to the embodiment, it is more preferable that the connection portion has a shape that is narrowed from the first surface side to the second surface side. In this way, if the connecting portion has a shape that narrows the bottom, the exposed surface (connecting surface) can be enlarged while securing a connecting surface of a desired size, so that the connection reliability with the component is further ensured. be able to.

また、前記一実施形態に係る配線基板は、前記接続部が、前記第1配線層と前記第2配線層とを電気的に接続して、前記第1配線層と前記第2配線層との間の前記絶縁層に設けられ、前記接続部の第1面側端部は、該第1面側端部の一部が前記第1配線層に接したまま前記凹部によって該第1面側端部の他部が削られて前記露出面が設けられていることがより好ましい。これによれば、接続部が第1配線層と第2配線層とに挟まれたままであるので、基板を薄型化した場合であっても接続部が抜け取れてしまうことを防止することができる。   In the wiring board according to the embodiment, the connection portion electrically connects the first wiring layer and the second wiring layer, and the first wiring layer and the second wiring layer are connected to each other. The first surface side end of the connecting portion is provided between the first surface side end by the recess while a part of the first surface side end portion is in contact with the first wiring layer. More preferably, the exposed surface is provided by shaving the other part of the part. According to this, since the connection portion remains sandwiched between the first wiring layer and the second wiring layer, it is possible to prevent the connection portion from coming off even when the substrate is thinned. .

また、前記一実施形態に係る配線基板は、前記露出面が、前記凹部の底面中央部から底面外周部の方向が長手となる長方形状であることがより好ましく、さらに、前記接続部が、前記凹部の底面縁部に沿って複数設けられていることがより好ましい。これによれば、例えば、凹部の底面中央部に電子部品を搭載し、この電子部品から接続部へのワイヤボンディングが容易となる。   In the wiring board according to the embodiment, it is more preferable that the exposed surface has a rectangular shape in which the direction from the center of the bottom surface of the recess to the outer periphery of the bottom surface is a longitudinal direction. It is more preferable that a plurality are provided along the bottom edge of the recess. According to this, for example, an electronic component is mounted on the center of the bottom surface of the recess, and wire bonding from the electronic component to the connection portion is facilitated.

また、前記一実施形態に係る配線基板は、前記凹部を露出して前記第1配線層を覆うように基板表面に設けられる表面層を備え、前記表面層が、前記凹部の開口よりも拡大して開口された拡大開口部を有することがより好ましい。これによれば、例えば、凹部に搭載された電子部品を樹脂封止する際に凹部の開口と拡大開口部の開口との段付き部によって樹脂止めさせることができる。   The wiring board according to the embodiment includes a surface layer provided on a substrate surface so as to expose the recess and cover the first wiring layer, and the surface layer is larger than an opening of the recess. It is more preferable to have an enlarged opening that is open. According to this, for example, when resin-sealing an electronic component mounted in the recess, the resin can be stopped by the stepped portion between the opening of the recess and the opening of the enlarged opening.

また、前記一実施形態に係る配線基板は、前記凹部の底面で前記絶縁層を貫通する貫通部を備えることがより好ましい。これによれば、例えば、基板に放熱板を設け、貫通部を介して電子部品の放熱性を高めることができる。   The wiring board according to the embodiment more preferably includes a through portion that penetrates the insulating layer at the bottom surface of the recess. According to this, for example, a heat radiating plate can be provided on the substrate, and the heat radiating property of the electronic component can be enhanced through the through portion.

また、前記一実施形態に係る配線基板は、前記絶縁層を第1絶縁層と、前記凹部を第1凹部と、前記接続部を第1接続部とし、前記複数の配線層の第3および第4配線層がそれぞれ設けられる第3および第4面を有する第2絶縁層と、前記第3面側から前記第2絶縁層の中途まで窪む第2凹部と、前記第4配線層と電気的に接続し、前記第2凹部の底面で露出するように前記第2絶縁層に設けられる第2接続部とを備え、前記第1、第2、第3、および第4配線層がこの順で積層され、前記第2接続部が、前記第2凹部の底面で露出する露出面と、前記第3配線層と接する接続面と、前記露出面および前記接続面と交差し、前記第2絶縁層に接する側面とを有し、前記第2接続部の側面が傾斜し、前記第1接続部が前記第1面側から前記第2面側へ末広がる形状であるときに、前記第2接続部が前記第3面側から前記第4面側へ尻窄まる形状であり、前記第1接続部が前記第1面側から前記第2面側へ尻窄まる形状であるときに、前記第2接続部が前記第3面側から前記第4面側へ末広がる形状であることがより好ましい。さらに、前記第1凹部が、基板厚みの一方向に開口し、前記第2凹部が、前記一方向の反対方向に開口していることがより好ましい。これによれば、搭載される複数の電子部品に対応させて、電子部品との接続信頼性をより確保したり、接続部をより抜け取れ難くしたりすることができる。   In the wiring substrate according to the embodiment, the insulating layer is a first insulating layer, the concave portion is a first concave portion, the connecting portion is a first connecting portion, and the third and third wiring layers are formed. A second insulating layer having third and fourth surfaces provided with four wiring layers, a second recess recessed from the third surface side to the middle of the second insulating layer, and the fourth wiring layer electrically And a second connection portion provided in the second insulating layer so as to be exposed at the bottom surface of the second recess, wherein the first, second, third, and fourth wiring layers are in this order. The second insulating layer is stacked, and the second connecting portion intersects the exposed surface exposed at the bottom surface of the second recess, the connecting surface in contact with the third wiring layer, the exposed surface and the connecting surface, and the second insulating layer. A side surface of the second connection portion is inclined, and the first connection portion is inclined from the first surface side to the second side. The second connecting portion has a shape that narrows from the third surface side to the fourth surface side, and the first connecting portion extends from the first surface side to the second surface. It is more preferable that the second connecting portion has a shape that spreads from the third surface side to the fourth surface side when the shape is narrowed to the surface side. Furthermore, it is more preferable that the first recess is opened in one direction of the substrate thickness, and the second recess is opened in a direction opposite to the one direction. According to this, it is possible to further ensure the connection reliability with the electronic component or to make it difficult to remove the connection portion in correspondence with the plurality of electronic components to be mounted.

本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、次のとおりである。本発明の一解決手段によれば、凹部での部品搭載性に優れた配線基板を提供することができる。   Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows. According to one solution of the present invention, it is possible to provide a wiring board that is excellent in component mounting properties in a recess.

本発明の一実施形態に係る配線基板の模式的平面図である。1 is a schematic plan view of a wiring board according to an embodiment of the present invention. 図1に示すII−II線に対応する配線基板の模式的断面図である。It is typical sectional drawing of the wiring board corresponding to the II-II line shown in FIG. 図1に示す配線基板に電子部品が搭載された状態の模式的断面図である。FIG. 2 is a schematic cross-sectional view showing a state where electronic components are mounted on the wiring board shown in FIG. 1. 図1に示す配線基板に電子部品が搭載された状態の模式的断面図である。FIG. 2 is a schematic cross-sectional view showing a state where electronic components are mounted on the wiring board shown in FIG. 1. 図1に示す配線基板に電子部品が搭載された状態の模式的断面図である。FIG. 2 is a schematic cross-sectional view showing a state where electronic components are mounted on the wiring board shown in FIG. 1. 本発明の一実施形態に係る製造過程の配線基板の模式的断面図である。It is a typical sectional view of a wiring board of a manufacture process concerning one embodiment of the present invention. 図6に続く製造過程の配線基板の模式的断面図である。FIG. 7 is a schematic cross-sectional view of a wiring board in a manufacturing process subsequent to FIG. 6. 図7に続く製造過程の配線基板の模式的断面図である。FIG. 8 is a schematic cross-sectional view of a wiring board in a manufacturing process subsequent to FIG. 7. 図8に続く製造過程の配線基板の模式的断面図である。FIG. 9 is a schematic cross-sectional view of a wiring board in a manufacturing process subsequent to FIG. 8. 図9に続く製造過程の配線基板の模式的断面図である。FIG. 10 is a schematic cross-sectional view of the wiring board in the manufacturing process subsequent to FIG. 9. 図10に続く製造過程の配線基板の模式的断面図である。FIG. 11 is a schematic cross-sectional view of a wiring board in a manufacturing process subsequent to FIG. 10. 図11に続く製造過程の配線基板の模式的断面図である。FIG. 12 is a schematic cross-sectional view of the wiring board in the manufacturing process subsequent to FIG. 11. 図12に続く製造過程の配線基板の模式的断面図である。FIG. 13 is a schematic cross-sectional view of a wiring board in a manufacturing process subsequent to FIG. 12. 本発明者らが検討した配線基板の模式的断面図である。It is typical sectional drawing of the wiring board which the present inventors examined. 本発明の他の実施形態に係る配線基板の模式的断面図である。It is a typical sectional view of a wiring board concerning other embodiments of the present invention. 本発明の他の実施形態に係る製造過程の配線基板の模式的断面図である。It is typical sectional drawing of the wiring board of the manufacture process which concerns on other embodiment of this invention. 図16に続く製造過程の配線基板の模式的断面図である。FIG. 17 is a schematic cross-sectional view of a wiring board in a manufacturing process subsequent to FIG. 16. 図17に続く製造過程の配線基板の模式的断面図である。FIG. 18 is a schematic cross-sectional view of a wiring board in a manufacturing process subsequent to FIG. 17. 図18に続く製造過程の配線基板の模式的断面図である。FIG. 19 is a schematic cross-sectional view of the wiring board in the manufacturing process subsequent to FIG. 18. 図19に続く製造過程の配線基板の模式的断面図である。FIG. 20 is a schematic cross-sectional view of the wiring board in the manufacturing process subsequent to FIG. 19. 図20に続く製造過程の配線基板の模式的断面図である。FIG. 21 is a schematic cross-sectional view of the wiring board in the manufacturing process subsequent to FIG. 20. 本発明の他の実施形態に係る配線基板の模式的断面図である。It is a typical sectional view of a wiring board concerning other embodiments of the present invention. 本発明の他の実施形態に係る配線基板の模式的断面図である。It is a typical sectional view of a wiring board concerning other embodiments of the present invention. 本発明の他の実施形態に係る配線基板の模式的断面図である。It is a typical sectional view of a wiring board concerning other embodiments of the present invention. 本発明の他の実施形態に係る配線基板の模式的断面図である。It is a typical sectional view of a wiring board concerning other embodiments of the present invention. 本発明の他の実施形態に係る配線基板の模式的断面図である。It is a typical sectional view of a wiring board concerning other embodiments of the present invention.

以下の本発明における実施形態では、必要な場合に複数のセクションなどに分けて説明するが、原則、それらはお互いに無関係ではなく、一方は他方の一部または全部の変形例、詳細などの関係にある。このため、全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。また、構成要素の数(個数、数値、量、範囲などを含む)については、特に明示した場合や原理的に明らかに特定の数に限定される場合などを除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良い。また、構成要素などの形状に言及するときは、特に明示した場合および原理的に明らかにそうではないと考えられる場合などを除き、実質的にその形状などに近似または類似するものなどを含むものとする。   In the following embodiments of the present invention, the description will be divided into a plurality of sections when necessary. However, in principle, they are not irrelevant to each other, and one of them is related to some or all of the other modifications, details, etc. It is in. For this reason, the same code | symbol is attached | subjected to the member which has the same function in all the figures, and the repeated description is abbreviate | omitted. In addition, the number of components (including the number, numerical value, quantity, range, etc.) is limited to that specific number unless otherwise specified or in principle limited to a specific number in principle. It may be more than a specific number or less. In addition, when referring to the shape of a component, etc., it shall include substantially the same or similar to the shape, etc., unless explicitly stated or in principle otherwise considered otherwise .

(実施形態1)
本発明の実施形態1に係る配線基板10の構造について図1〜5を参照して説明する。図1は、配線基板10の模式的平面図である。図2は、図1に示すII−II線に対応する配線基板10の模式的断面図である。図3〜図5は、配線基板10に電子部品12、13が搭載された状態(電子製品14)の模式的断面図である。
(Embodiment 1)
The structure of the wiring board 10 according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic plan view of the wiring board 10. FIG. 2 is a schematic cross-sectional view of the wiring board 10 corresponding to the II-II line shown in FIG. 3 to 5 are schematic cross-sectional views of the state in which the electronic components 12 and 13 are mounted on the wiring board 10 (electronic product 14).

配線基板10は、積層される複数の配線層16を備える多層配線基板(図2では、6層の多層配線基板)である。また、配線基板10は、各配線層16間に設けられる複数の絶縁層18(層間絶縁層)と、複数の配線層16を覆うように基板表面(主面およびこれとは反対側の裏面)に設けられる複数の表面層20と、絶縁層18に設けられ、配線層16と電気的に接続される複数の接続部22とを備える。なお、基板上面を主面、基板下面を裏面として説明するが、使用状態によっては基板上下が逆になるため、基板下面が主面、基板上面が裏面であってもよい。   The wiring board 10 is a multilayer wiring board (in FIG. 2, a six-layer multilayer wiring board) including a plurality of wiring layers 16 to be stacked. In addition, the wiring substrate 10 includes a plurality of insulating layers 18 (interlayer insulating layers) provided between the wiring layers 16 and a substrate surface (a main surface and a back surface opposite to the main surface) so as to cover the plurality of wiring layers 16. And a plurality of connection portions 22 provided on the insulating layer 18 and electrically connected to the wiring layer 16. The upper surface of the substrate will be described as the main surface and the lower surface of the substrate will be described as the back surface. However, depending on the state of use, the upper and lower surfaces of the substrate may be reversed.

本実施形態では、図2などに示すように、2層の表面層20を区別するために、上面(主面)側の表面層20U、下面(裏面)側の表面層20Lとして符号を付している。また、6層の配線層16を上面側から順に配線層16−1、16−2、16−3、16−4、16−5、16−6と符号を付し、5層の絶縁層18を上面側から順に絶縁層18−1、18−2、18−3、18−4、18−5として符号を付している。また、絶縁層18−1、18−2、18−3、18−4、18−5のそれぞれに設けられる5層の接続部22を接続部22−1、22−2、22−3、22−4、22−5として符号を付している。   In the present embodiment, as shown in FIG. 2 and the like, in order to distinguish the two surface layers 20, reference numerals are assigned as the surface layer 20U on the upper surface (main surface) side and the surface layer 20L on the lower surface (back surface) side. ing. Further, the six wiring layers 16 are sequentially denoted by the wiring layers 16-1, 16-2, 16-3, 16-4, 16-5, 16-6 from the upper surface side, and five insulating layers 18 are provided. Are numbered as insulating layers 18-1, 18-2, 18-3, 18-4, and 18-5 in order from the upper surface side. In addition, the five layers of connection portions 22 provided in each of the insulating layers 18-1, 18-2, 18-3, 18-4, and 18-5 are connected to the connection portions 22-1, 22-2, 22-3, and 22 respectively. Reference numerals -4 and 22-5 are assigned.

また、配線基板10は、上面側(表面層20U側)から窪む電子部品搭載用のキャビティ24(凹部)を備える。本実施形態では、キャビティ24は、配線層16−4が設けられる上面側の面17および配線層16−5が設けられる下面側の面19を有する絶縁層18−4の中途まで窪んでおり、絶縁層18−4にキャビティ24の底面(底部)が設けられる。このキャビティ24の底面では配線層16−5と電気的に接続される接続部22−4が露出することとなる。   In addition, the wiring board 10 includes a cavity 24 (recessed portion) for mounting electronic components that is recessed from the upper surface side (surface layer 20U side). In the present embodiment, the cavity 24 is recessed to the middle of the insulating layer 18-4 having the upper surface 17 on which the wiring layer 16-4 is provided and the lower surface 19 on which the wiring layer 16-5 is provided. The bottom surface (bottom portion) of the cavity 24 is provided in the insulating layer 18-4. At the bottom surface of the cavity 24, the connection portion 22-4 that is electrically connected to the wiring layer 16-5 is exposed.

接続部22−4は、キャビティ24の底面で露出する露出面26と、配線層16−5と接する接続面28と、露出面26および接続面28と交差し、絶縁層18−4に接する側面30とを有し、側面30が傾斜している。ここで、図3〜図5に示すように、キャビティ24の底面で露出する接続部22−4の露出面26は、電子部品12、13と電気的に接続される接続面(接続パッドP1、P2)となる。電子部品12と電子部品13とは例えば接着材によって積み重ねられた状態でキャビティ24に収容されて配線基板10に搭載される。電子部品12は、接続バンプ32を介して配線基板10の接続部22−4(図1に示す円形状の接続パッドP1)と電気的に接続(フリップチップ接続)される。また、電子部品13は、ボンディングワイヤ34を介して配線基板10の接続部22−4(図1に示す矩形状の接続パッドP2)と電気的に接続(ワイヤボンディング接続)される。   The connecting portion 22-4 has an exposed surface 26 exposed at the bottom surface of the cavity 24, a connecting surface 28 that contacts the wiring layer 16-5, a side surface that intersects the exposed surface 26 and the connecting surface 28, and contacts the insulating layer 18-4. 30 and the side surface 30 is inclined. Here, as shown in FIGS. 3 to 5, the exposed surface 26 of the connection portion 22-4 exposed at the bottom surface of the cavity 24 is a connection surface (connection pad P <b> 1, P2). The electronic component 12 and the electronic component 13 are accommodated in the cavity 24 in a state where they are stacked with an adhesive, for example, and mounted on the wiring board 10. The electronic component 12 is electrically connected (flip-chip connection) to the connection portion 22-4 (circular connection pad P1 shown in FIG. 1) of the wiring substrate 10 via the connection bumps 32. Further, the electronic component 13 is electrically connected (wire bonding connection) to the connection portion 22-4 (rectangular connection pad P2 shown in FIG. 1) of the wiring board 10 through the bonding wire 34.

このような配線基板10では、絶縁層18−4中の接続部22−4の側面30が傾斜していることで、傾斜していないもの(基板厚み方向に側面が真っ直ぐなもの)に比べ絶縁層18−4との接触面積が大きくなるため接続部22−4の密着性を向上させることができる。このため、例えば、配線基板10が薄型化した場合であっても接続部22−4が抜け取れてしまうことを防止することができる。すなわち、キャビティ24に電子部品12、13を搭載しても、接続部22−4との接続信頼性が確保される部品搭載性に優れた配線基板10を提供することができる。   In such a wiring board 10, the side surface 30 of the connecting portion 22-4 in the insulating layer 18-4 is inclined, so that it is insulated as compared with the case where the side surface 30 is not inclined (the side surface is straight in the substrate thickness direction). Since the contact area with the layer 18-4 becomes large, the adhesion of the connecting portion 22-4 can be improved. For this reason, for example, even when the wiring board 10 is thinned, it is possible to prevent the connecting portion 22-4 from being removed. That is, even when the electronic components 12 and 13 are mounted in the cavity 24, it is possible to provide the wiring board 10 excellent in component mounting property that ensures connection reliability with the connection portion 22-4.

本実施形態では、側面30が傾斜している接続部22−4は、図2に示すように、絶縁層18−4の面17側から面19側へ末広がる形状である。このため、接続部22−4の露出面26の面積より接続面28の面積が大きくなっている。接続部22−4が末広がる形状となることで、接続部22−4をキャビティ24の底面からより抜け取れ難くすることができる。   In the present embodiment, the connecting portion 22-4 whose side surface 30 is inclined has a shape that spreads from the surface 17 side to the surface 19 side of the insulating layer 18-4 as shown in FIG. For this reason, the area of the connection surface 28 is larger than the area of the exposed surface 26 of the connection part 22-4. Since the connecting portion 22-4 has a shape that widens at the end, the connecting portion 22-4 can be more difficult to be removed from the bottom surface of the cavity 24.

ここで、フリップチップ接続用の接続パッドP1となる接続部22−4は、後述するスルーホール(接続部22−3)から構成することもできる(後述)が、スルーホール形成の際にはドリルを用いた孔開けがなされるので、スルーホールではパッド面積が比較的大きくなってしまう。例えば、図2に示すように、接続部22−4の径φaより接続部22−3(スルーホール)の径φbが大きくなってしまう。電子部品12の微細化に対応させるには接続パッドP1を微細化させる必要があるため、ドリルではなく、例えば、微細化に対応可能なレーザを用いて接続部22−4(接続パッドP1のものが円錐台形状の貫通部、接続パッドP2のものが板状であって四角錐台形状の貫通部)を形成することが好ましい。   Here, the connection part 22-4 which becomes the connection pad P1 for flip chip connection can also be configured from a through hole (connection part 22-3) which will be described later (described later). Therefore, the pad area is relatively large in the through hole. For example, as shown in FIG. 2, the diameter φb of the connection portion 22-3 (through hole) is larger than the diameter φa of the connection portion 22-4. Since it is necessary to miniaturize the connection pad P1 in order to cope with the miniaturization of the electronic component 12, the connection portion 22-4 (the one of the connection pad P1) is used, for example, using a laser capable of miniaturization instead of a drill. It is preferable to form a truncated cone-shaped penetrating portion and a connection pad P2 having a plate shape and a truncated pyramid-shaped penetrating portion.

また、本実施形態では、接続部22−4の面17側端部(図2中、上端部)では、面17側端部の一部が配線層16−4に接したままキャビティ24によって他部が削られて露出面26(接続パッドP2)が設けられる。これによれば、接続パッドP2を構成する接続部22−4は、配線層16−4と配線層16−5とに挟まれたままであるので、配線基板10を薄型化した場合であっても抜け取れ防止されることとなる。   Further, in the present embodiment, at the end portion on the surface 17 side (the upper end portion in FIG. 2) of the connection portion 22-4, the other end portion on the surface 17 side is in contact with the wiring layer 16-4 by the cavity 24. The exposed portion 26 (connection pad P2) is provided by cutting the portion. According to this, since the connection portion 22-4 constituting the connection pad P2 remains sandwiched between the wiring layer 16-4 and the wiring layer 16-5, even when the wiring board 10 is thinned. It will be prevented from coming off.

また、本実施形態では、接続パッドP2となる接続部22−4の露出面26が、図1に示すように、キャビティ24の底面中央部から底面外周部の方向が長手となる長方形状である。すなわち、接続パッドP2となる接続部22−4は、接続パッドP1となる接続部22−4の円錐台形状に対して、板状(四角錐台形状)に形成されている。この板状の接続部22−4は、絶縁層18−4に差し込まれるように設けられて絶縁層18−4との密着性が向上されているため、例えば、配線基板10が薄型化した場合であっても接続部22−4が抜け取れてしまうことを防止することができる。   Further, in the present embodiment, the exposed surface 26 of the connection portion 22-4 that becomes the connection pad P2 has a rectangular shape in which the direction from the center of the bottom surface of the cavity 24 to the outer periphery of the bottom surface is long as shown in FIG. . In other words, the connection portion 22-4 that becomes the connection pad P2 is formed in a plate shape (square pyramid shape) with respect to the truncated cone shape of the connection portion 22-4 that becomes the connection pad P1. The plate-like connecting portion 22-4 is provided so as to be inserted into the insulating layer 18-4 and has improved adhesion with the insulating layer 18-4. For example, when the wiring board 10 is thinned Even so, it is possible to prevent the connecting portion 22-4 from being removed.

また、この接続パッドP2となる接続部22−4が、キャビティ24の底面縁部に沿うように長手側で交差して複数設けられる。本実施形態では、キャビティ24の底面中央部に電子部品13を搭載して配線基板10の接続パッドP2と電気的に接続する際に、電子部品13が搭載される底面中央部から底面外周部へボンディングワイヤ34を引き延ばすことになる。このため、その引き延ばす方向が長手となる長方形状の接続パッドP2(接続部22−4)を設けることで、電子部品13から接続パッドP2(接続部22−4)へのワイヤボンディングが容易となる。   Further, a plurality of connection portions 22-4 serving as the connection pads P <b> 2 are provided so as to intersect on the longitudinal side along the bottom edge of the cavity 24. In the present embodiment, when the electronic component 13 is mounted on the central portion of the bottom surface of the cavity 24 and electrically connected to the connection pad P2 of the wiring board 10, the central portion of the bottom surface on which the electronic component 13 is mounted is changed to the outer peripheral portion of the bottom surface. The bonding wire 34 is stretched. For this reason, wire bonding from the electronic component 13 to the connection pad P2 (connection part 22-4) becomes easy by providing the rectangular connection pad P2 (connection part 22-4) whose extending direction is long. .

また、本実施形態では、キャビティ24を露出して配線層16を覆うように基板表面に設けられる表面層20Uが、キャビティ24の開口よりも拡大して開口された拡大開口部36を有する。この拡大開口部36を設けることで、キャビティ24の開口縁と拡大開口部36の開口縁とで段付き部38が形成される。このため、例えば、ディスペンサを用いたポッテイングによって、キャビティ24に搭載された電子部品12、13を樹脂封止する場合には、図4に示すように、段付き部38によって封止樹脂40を樹脂止めさせることができる。また、成形金型を用いた樹脂成形をする場合には、図5に示すように、キャビティ24および段付き部38にまで封止樹脂40が入り込むので配線基板10と封止樹脂40との密着性を向上させることができる。   In the present embodiment, the surface layer 20 </ b> U provided on the substrate surface so as to expose the cavity 24 and cover the wiring layer 16 has an enlarged opening 36 that is opened larger than the opening of the cavity 24. By providing the enlarged opening 36, a stepped portion 38 is formed by the opening edge of the cavity 24 and the opening edge of the enlarged opening 36. Therefore, for example, when the electronic parts 12 and 13 mounted in the cavity 24 are resin-sealed by potting using a dispenser, the sealing resin 40 is resinated by the stepped portion 38 as shown in FIG. It can be stopped. In the case of resin molding using a molding die, as shown in FIG. 5, the sealing resin 40 enters the cavity 24 and the stepped portion 38, so that the wiring substrate 10 and the sealing resin 40 are in close contact with each other. Can be improved.

次に、本発明の実施形態1に係る配線基板10の製造方法について図2、図6〜図13を参照して説明する。図6〜図13は、配線基板10(図2参照)の製造過程の模式的断面図である。   Next, a method for manufacturing the wiring substrate 10 according to the first embodiment of the present invention will be described with reference to FIGS. 2 and 6 to 13. 6 to 13 are schematic cross-sectional views of the manufacturing process of the wiring board 10 (see FIG. 2).

まず、図6に示すように、絶縁層18−3と、その両面に設けられた配線層16−3、16−4を有するコア材42を準備する。絶縁層18−3は、例えば、ガラス繊維布を内包する絶縁性樹脂(例えば、エポキシ系樹脂)から構成される。また、配線層16−3、16−4は、例えば、銅箔から構成される。   First, as shown in FIG. 6, a core material 42 having an insulating layer 18-3 and wiring layers 16-3 and 16-4 provided on both surfaces thereof is prepared. The insulating layer 18-3 is made of, for example, an insulating resin (for example, an epoxy resin) that encloses a glass fiber cloth. Moreover, the wiring layers 16-3 and 16-4 are made of, for example, copper foil.

続いて、コア材42に貫通孔44(図6では、破線で示す。)を形成した後、図7に示すように、貫通孔44に接続部22−3を形成し、また、パターニングされた配線層16−3、16−4を形成する。このパターニングによって配線層16−3では回路形成が行われる。接続部22−3は、例えば、スルーホールから構成される。スルーホールの形成には、まず、ドリルを用いて貫通孔44を形成し、その内壁面にめっき(例えば、銅めっき)によってめっき膜を形成する。次いで、貫通孔44を絶縁性材料46(例えば、絶縁性樹脂)で埋め込み、貫通孔44の両端を覆うように必要に応じて蓋めっき(例えば、銅めっき)することで接続部22−3(スルーホール)が形成される。次いで、例えば、サブトラクティブ法によって配線層16−3、16−4をパターニングして回路形成を行う。なお、貫通孔44は、レーザ加工で形成してもよい。また、絶縁性材料46の代わりに導電性材料(例えば、銅めっき)を用いて貫通孔44を埋め込んでもよい。   Subsequently, after forming a through hole 44 (indicated by a broken line in FIG. 6) in the core material 42, as shown in FIG. 7, a connection portion 22-3 is formed in the through hole 44 and patterned. Wiring layers 16-3 and 16-4 are formed. By this patterning, a circuit is formed in the wiring layer 16-3. The connection part 22-3 is composed of, for example, a through hole. In forming the through hole, first, a through hole 44 is formed using a drill, and a plating film is formed on the inner wall surface by plating (for example, copper plating). Next, the through hole 44 is filled with an insulating material 46 (for example, insulating resin), and cover plating (for example, copper plating) is performed as necessary so as to cover both ends of the through hole 44, thereby connecting portions 22-3 ( Through hole) is formed. Next, for example, the wiring layers 16-3 and 16-4 are patterned by a subtractive method to form a circuit. The through hole 44 may be formed by laser processing. Further, the through hole 44 may be embedded using a conductive material (for example, copper plating) instead of the insulating material 46.

続いて、図8に示すように、配線層16−2が設けられた絶縁層18−2を絶縁層18−3の上面に積層させ、配線層16−5が設けられた絶縁層18−4を絶縁層18−3の下面に積層させる。例えば、絶縁層18−3を絶縁層18−2、18−4で挟むようにして熱圧着することで、これらが積層される。これにより、配線層16−3が絶縁層18−2によって覆われ、また、配線層16−4が絶縁層18−4によって覆われる。絶縁層18−2、18−4は、例えば、絶縁性樹脂(例えば、エポキシ系樹脂)から構成される。また、配線層16−2、16−5は、例えば、銅箔から構成される。   Then, as shown in FIG. 8, the insulating layer 18-2 provided with the wiring layer 16-2 is laminated on the upper surface of the insulating layer 18-3, and the insulating layer 18-4 provided with the wiring layer 16-5 is provided. Is laminated on the lower surface of the insulating layer 18-3. For example, these layers are laminated by thermocompression bonding such that the insulating layer 18-3 is sandwiched between the insulating layers 18-2 and 18-4. Thereby, the wiring layer 16-3 is covered with the insulating layer 18-2, and the wiring layer 16-4 is covered with the insulating layer 18-4. The insulating layers 18-2 and 18-4 are made of, for example, an insulating resin (for example, an epoxy resin). The wiring layers 16-2 and 16-5 are made of, for example, copper foil.

続いて、図9に示すように、絶縁層18−2の上面側から配線層16−3に達し、内壁面が傾斜する貫通部48を絶縁層18−2に形成する。また、絶縁層18−4の下面側から配線層16−4に達し、内壁面が傾斜する貫通部50、52を絶縁層18−4に形成する。貫通部48、50、52の加工方法は、特に限定するものではないが、本実施形態では、加工形状の自由度が高いレーザ加工を用いている。また、コンフォーマルマスクを用いることで、加工精度も確保することができる。このため、開口された配線層16−2、16−5をコンフォーマルマスクとしてレーザ(例えば、炭酸ガスレーザ)を照射し、絶縁層18−2に貫通部48を形成し、絶縁層18−4に貫通部50、52を形成する。   Subsequently, as illustrated in FIG. 9, a penetrating portion 48 that reaches the wiring layer 16-3 from the upper surface side of the insulating layer 18-2 and has an inclined inner wall surface is formed in the insulating layer 18-2. In addition, penetrating portions 50 and 52 are formed in the insulating layer 18-4 that reach the wiring layer 16-4 from the lower surface side of the insulating layer 18-4 and in which the inner wall surface is inclined. The processing method of the penetrating portions 48, 50, and 52 is not particularly limited, but in this embodiment, laser processing with a high degree of freedom in the processing shape is used. Further, by using a conformal mask, processing accuracy can be ensured. Therefore, a laser (for example, carbon dioxide laser) is irradiated using the opened wiring layers 16-2 and 16-5 as a conformal mask to form a through-hole 48 in the insulating layer 18-2, and the insulating layer 18-4 The through portions 50 and 52 are formed.

レーザ加工によれば、レーザ入射側で開口が若干広く、尻窄まるように開口が狭くなって貫通部48、50、52が形成される。これにより、貫通部48、50、52の内壁面が傾斜するように形成される。そして、貫通部50は、円錐台形状の貫通孔に形成され、貫通部52は、四角錐台形状の貫通溝に形成されるように所望の形状となる。なお、貫通部50、52は、後の工程で導電性部材が埋め込まれた後、ザグリ加工によって、それぞれフリップチップ接続用の接続パッドP1、ワイヤボンディング接続用の接続パッドP2を構成することとなる(図2参照)。   According to the laser processing, the opening is slightly wide on the laser incident side, and the opening is narrowed so that the bottom is narrowed, so that the through portions 48, 50, and 52 are formed. Thereby, it forms so that the inner wall face of the penetration parts 48, 50, and 52 may incline. The penetrating part 50 is formed in a truncated cone-shaped through hole, and the penetrating part 52 has a desired shape so as to be formed in a quadrangular pyramid-shaped penetrating groove. The through-holes 50 and 52 constitute a connection pad P1 for flip chip connection and a connection pad P2 for wire bonding connection by counterbore processing after a conductive member is embedded in a later step. (See FIG. 2).

続いて、図10に示すように、貫通部48に導電性材料を埋め込んで配線層16−3と電気的に接続される接続部22−2(Filled Via)を形成し、接続部22−2と電気的に接続されるように、絶縁層18−2の上面にパターニングされた配線層16−2を形成する。このパターニングによって配線層16−2では回路形成が行われる。また、貫通部50、52に導電性材料を埋め込んで配線層16−4と電気的に接続される接続部22−4(Filled Via)を形成し、接続部22−4と電気的に接続されるように、絶縁層18−4の下面にパターニングされた配線層16−5を形成する。このパターニングによって配線層16−5では回路形成が行われる。配線層16−2、16−5のパターニング方法は、特に限定するものではないが、本実施形態では、サブトラクティブ法を用いている。   Subsequently, as illustrated in FIG. 10, a conductive material is embedded in the through portion 48 to form a connection portion 22-2 (Filled Via) that is electrically connected to the wiring layer 16-3, and the connection portion 22-2 is formed. Then, a patterned wiring layer 16-2 is formed on the upper surface of the insulating layer 18-2. By this patterning, a circuit is formed in the wiring layer 16-2. Further, a conductive material is embedded in the through portions 50 and 52 to form a connection portion 22-4 (Filled Via) that is electrically connected to the wiring layer 16-4, and is electrically connected to the connection portion 22-4. Thus, a patterned wiring layer 16-5 is formed on the lower surface of the insulating layer 18-4. By this patterning, a circuit is formed in the wiring layer 16-5. The patterning method of the wiring layers 16-2 and 16-5 is not particularly limited, but in this embodiment, a subtractive method is used.

貫通部48、50、52に埋め込まれる導電性材料としては、例えば、銅めっきを用いることができる。銅めっきの場合、いわゆるビアフィルめっきのように、必要に応じて前処理として貫通部48、50、52の内壁面に対してデスミア処理を行った後、無電解銅めっき、電解銅めっきをこの順で行い、接続部22−2、22−4を形成する。この接続部22−2、22−4は、内壁面に無電解銅めっき膜が形成された貫通部48、50、52に対して電解銅めっきが埋め込まれて形成される。   As the conductive material embedded in the through portions 48, 50, and 52, for example, copper plating can be used. In the case of copper plating, after the desmear treatment is performed on the inner wall surfaces of the through portions 48, 50, 52 as necessary as in the case of so-called via fill plating, electroless copper plating and electrolytic copper plating are performed in this order. Then, the connecting portions 22-2 and 22-4 are formed. The connection portions 22-2 and 22-4 are formed by embedding electrolytic copper plating in the through portions 48, 50 and 52 in which an electroless copper plating film is formed on the inner wall surface.

続いて、図11に示すように、配線層16−1が設けられた絶縁層18−1を絶縁層18−2の上面に積層させ、配線層16−6が設けられた絶縁層18−5を絶縁層18−4の下面に積層させる。例えば、絶縁層18−2、18−3、18−4を絶縁層18−1、18−5で挟むようにして熱圧着することで、これらが積層される。これにより、配線層16−2が絶縁層18−1によって覆われ、また、配線層16−5が絶縁層18−5によって覆われる。絶縁層18−1、18−5は、例えば、絶縁性樹脂(例えば、エポキシ系樹脂)から構成される。また、配線層16−1、16−6は、例えば、銅箔から構成される。   Subsequently, as shown in FIG. 11, the insulating layer 18-1 provided with the wiring layer 16-1 is laminated on the upper surface of the insulating layer 18-2, and the insulating layer 18-5 provided with the wiring layer 16-6. Is laminated on the lower surface of the insulating layer 18-4. For example, the insulating layers 18-2, 18-3, and 18-4 are laminated by being thermocompression bonded so as to be sandwiched between the insulating layers 18-1 and 18-5. As a result, the wiring layer 16-2 is covered with the insulating layer 18-1, and the wiring layer 16-5 is covered with the insulating layer 18-5. The insulating layers 18-1 and 18-5 are made of, for example, an insulating resin (for example, an epoxy resin). Moreover, the wiring layers 16-1 and 16-6 are made of, for example, copper foil.

続いて、図12に示すように、配線層16−2と電気的に接続される接続部22−1(Filled Via)を形成し、接続部22−1と電気的に接続されるように、絶縁層18−1の上面にパターニングされた配線層16−1を形成する。また、配線層16−5と電気的に接続される接続部22−5(Filled Via)を形成し、接続部22−5と電気的に接続されるように、絶縁層18−5の下面にパターニングされた配線層16−6を形成する。このパターニングによって配線層16−1、16−6では回路形成が行われる。なお、これらは、例えば、図9および図10を参照して説明した工程と同様の工程にて形成される。   Subsequently, as illustrated in FIG. 12, a connection portion 22-1 (Filled Via) electrically connected to the wiring layer 16-2 is formed, and the connection portion 22-1 is electrically connected. A patterned wiring layer 16-1 is formed on the upper surface of the insulating layer 18-1. Further, a connection portion 22-5 (Filled Via) electrically connected to the wiring layer 16-5 is formed, and is formed on the lower surface of the insulating layer 18-5 so as to be electrically connected to the connection portion 22-5. A patterned wiring layer 16-6 is formed. Circuit formation is performed in the wiring layers 16-1 and 16-6 by this patterning. In addition, these are formed in the process similar to the process demonstrated with reference to FIG. 9 and FIG. 10, for example.

続いて、図13に示すように、基板表面(主面)となる表面層20Uを絶縁層18−1の上面に積層し、キャビティ24(図2参照)の開口よりも拡大して開口された拡大開口部36を有するようにパターニングされた表面層20Uを形成する。これにより、配線層16−1が表面層20Uによって覆われ、拡大開口部36からは絶縁層18−1が露出する。また、基板表面(裏面)となる表面層20Lを絶縁層18−5に積層する。これにより、配線層16−6が表面層20Lによって覆われる。表面層20U、20Lは、例えば、ソルダレジストから構成される。   Subsequently, as shown in FIG. 13, a surface layer 20 </ b> U serving as a substrate surface (main surface) was laminated on the upper surface of the insulating layer 18-1, and was opened larger than the opening of the cavity 24 (see FIG. 2). The surface layer 20U patterned so as to have the enlarged opening 36 is formed. As a result, the wiring layer 16-1 is covered with the surface layer 20 U, and the insulating layer 18-1 is exposed from the enlarged opening 36. Further, a surface layer 20L to be a substrate surface (back surface) is laminated on the insulating layer 18-5. Thereby, the wiring layer 16-6 is covered with the surface layer 20L. The surface layers 20U and 20L are made of, for example, a solder resist.

続いて、図2に示すように、表面層20U側から絶縁層18−1、18−2、18−3を貫通し、絶縁層18−4の中途(すなわち、4層目の配線層16−4と5層目の配線層16−5の間)まで窪むキャビティ24(凹部)を形成する。これにより、キャビティ24の底面で露出する露出面26と、配線層16−5と接する接続面28と、露出面26および接続面28と交差し、絶縁層18−4に接する側面30とを有する接続部22−4が複数形成される。複数の接続部22−4のうち、貫通部50に形成されたものがフリップチップ接続用の接続パッドP1を構成し、貫通部52に形成されたものがワイヤボンディング接続用の接続パッドP2を構成する。また、接続パッドP2を構成する接続部22−4では、キャビティ24を形成することによって、接続部22−4の絶縁層18−4の面17側端部の一部を配線層16−4に接したまま、他部を削って露出面26が形成される。その後、接続パッドP1、P2の酸化防止などの一般的な表面処理を行い、配線基板10が略完成する。また、必要に応じて出荷サイズに分割し、洗浄や検査工程を経て出荷となる。   Subsequently, as shown in FIG. 2, the insulating layer 18-1, 18-2, 18-3 is penetrated from the surface layer 20U side, and the middle of the insulating layer 18-4 (that is, the fourth wiring layer 16-). A cavity 24 (concave portion) that is recessed to the fourth and fifth wiring layers 16-5) is formed. Thus, the exposed surface 26 exposed at the bottom surface of the cavity 24, the connection surface 28 in contact with the wiring layer 16-5, and the side surface 30 intersecting the exposed surface 26 and the connection surface 28 and in contact with the insulating layer 18-4 are provided. A plurality of connection portions 22-4 are formed. Among the plurality of connection portions 22-4, the one formed in the through portion 50 constitutes a connection pad P1 for flip chip connection, and the one formed in the through portion 52 constitutes a connection pad P2 for wire bonding connection. To do. Further, in the connection portion 22-4 constituting the connection pad P2, by forming the cavity 24, a part of the end portion on the surface 17 side of the insulating layer 18-4 of the connection portion 22-4 becomes the wiring layer 16-4. The exposed surface 26 is formed by scraping the other part while in contact. Thereafter, general surface treatment such as oxidation prevention of the connection pads P1 and P2 is performed, and the wiring board 10 is substantially completed. Further, it is divided into shipping sizes as necessary, and is shipped through a cleaning and inspection process.

本実施形態では、キャビティ24の加工方法としては、ザグリ加工(切削加工)を用いている。例えば、拡大開口部36がない表面層20Uと共にキャビティ24を形成することができるが、ザグリ加工を用いると、表面層20Uでの開口周りに削り屑が残ってしまう場合がある。そこで、本実施形態では、キャビティ24の開口よりも拡大して開口する拡大開口部36を有する表面層20Uを形成した後、その拡大開口部36内でザグリ加工によってキャビティ24を形成し、削り屑が発生するのを防止している。なお、表面層20Uを形成する前にキャビティ24を形成し、その後、拡大開口部36を有する表面層20Uを形成してもよい。   In this embodiment, a counterboring process (cutting process) is used as a processing method of the cavity 24. For example, the cavity 24 can be formed together with the surface layer 20U without the enlarged opening 36, but if counterbore processing is used, shavings may remain around the opening in the surface layer 20U. Therefore, in the present embodiment, after forming the surface layer 20U having the enlarged opening 36 that opens larger than the opening of the cavity 24, the cavity 24 is formed by counterbore processing in the enlarged opening 36, and the shavings are formed. Is prevented from occurring. The cavity 24 may be formed before the surface layer 20U is formed, and then the surface layer 20U having the enlarged opening 36 may be formed.

また、本実施形態では、接続パッドP1、P2を構成する接続部22−4は、配線層16−4が設けられる上面側の面17から配線層16−5が設けられる下面側の面19へ末広がる形状となって側面30が傾斜したものとなる。これは、接続部22−4がレーザ加工によって所望形状に形成された貫通部50、52に導電性部材が埋め込まれたものから構成され、絶縁層18−4の中途まで行われるザグリ加工によって、接続部22−4の一部(貫通部50、52の開口が狭い側)が削り出されるからである。   In the present embodiment, the connection portion 22-4 constituting the connection pads P1 and P2 extends from the upper surface 17 where the wiring layer 16-4 is provided to the lower surface 19 where the wiring layer 16-5 is provided. It becomes the shape which spreads at the end, and the side surface 30 becomes inclined. This is composed of a conductive member embedded in the through portions 50 and 52 in which the connecting portion 22-4 is formed in a desired shape by laser processing, and by the counterboring process performed halfway through the insulating layer 18-4, This is because part of the connecting portion 22-4 (the side where the openings of the through portions 50 and 52 are narrow) is cut out.

ここで、図2に示す配線基板10と、図14に示す配線基板500との相違について説明する。図14は、本発明者らが検討した配線基板500の模式的断面図である。これらは、キャビティ24の底面に設けられる接続パッドP1、P2が、配線基板10では接続部22−4であるのに対して、配線基板500では配線層16−4である点で相違する。接続パッドP1、P2は、前述したように、キャビティ24を形成することで形成(露出)されるものである。   Here, the difference between the wiring board 10 shown in FIG. 2 and the wiring board 500 shown in FIG. 14 will be described. FIG. 14 is a schematic cross-sectional view of a wiring board 500 examined by the present inventors. These are different in that the connection pads P1 and P2 provided on the bottom surface of the cavity 24 are the connection portion 22-4 in the wiring substrate 10 and the wiring layer 16-4 in the wiring substrate 500. The connection pads P1 and P2 are formed (exposed) by forming the cavity 24 as described above.

配線基板500において配線層16−4がザグリ加工で削り出されて接続パッドP1、P2が形成される場合、ザグリ加工の深さ精度(機械的精度)、配線層16−4の加工ストレス(ダメージ)が問題となる。特に、微細化された配線層16−4の場合、その厚みも薄くなるため、キャビティ24の形成には非常に高い加工精度が要求され、また、高精度に加工するには基板厚さバラツキを抑える必要もある。しかしながら、ザグリ加工の精度(ここでは、配線層16−4の厚みから残したい厚みを引いた厚みが許容できる精度)では配線層16−4を均一に削り出すことが困難となる。また、その接続パッドP1、P2も極めて薄くなる(図14中の箇所A)ため、加工ストレスにより剥離してしまうなどの不具合が生じるおそれがある。加工ストレス耐性を向上させるためには、配線層16−4の幅(キャビティ24の底面視の幅)を太くすることも考えられるが、微細化に対応することができなくなってしまう。   In the wiring substrate 500, when the wiring layer 16-4 is cut out by counterboring to form the connection pads P1 and P2, the depth accuracy (mechanical accuracy) of the counterboring processing, the processing stress (damage to the wiring layer 16-4) ) Is a problem. In particular, in the case of the miniaturized wiring layer 16-4, the thickness thereof is also reduced. Therefore, very high processing accuracy is required for the formation of the cavity 24, and the substrate thickness variation is required for processing with high accuracy. There is also a need to suppress. However, it is difficult to evenly cut the wiring layer 16-4 with the accuracy of counterbore processing (here, the accuracy in which the thickness obtained by subtracting the desired thickness from the thickness of the wiring layer 16-4 is acceptable). In addition, since the connection pads P1 and P2 are also extremely thin (location A in FIG. 14), there is a possibility that problems such as peeling due to processing stress may occur. In order to improve the processing stress resistance, it is conceivable to increase the width of the wiring layer 16-4 (the width of the cavity 24 as viewed from the bottom), but it becomes impossible to cope with miniaturization.

そこで、配線基板10ではキャビティ24を形成する際、ザグリ加工を用いた場合であっても、絶縁層18−4の厚み方向に接続部22−4を形成しておくことで、接続パッドP1、P2を構成する接続部22−4の一部を削り出すための許容できる加工精度を大幅に緩和することができる。また、接続部22−4の側面30を傾斜させて形成し、絶縁層18−4との接触面積を大きくしているため、加工ストレスに対して接続部22−4が剥がれにくい構造となっている。また、ワイヤボンディング接続用の接続パッドP2を構成する接続部22−4は、配線層16−4と配線層16−5との間に挟まれた状態であるので、加工ストレスにも優れた構造となっている。   Therefore, even when the counterbore process is used when forming the cavity 24 in the wiring substrate 10, the connection pad P1, the connection portion 22-4 is formed in the thickness direction of the insulating layer 18-4. The allowable machining accuracy for cutting out a part of the connecting portion 22-4 constituting the P2 can be remarkably reduced. Further, the side surface 30 of the connection portion 22-4 is formed to be inclined and the contact area with the insulating layer 18-4 is increased, so that the connection portion 22-4 does not easily peel off due to processing stress. Yes. Further, since the connection portion 22-4 constituting the connection pad P2 for wire bonding connection is sandwiched between the wiring layer 16-4 and the wiring layer 16-5, the structure is excellent in processing stress. It has become.

このような配線基板10の製造技術では、ザグリ加工に耐えうる配線構造となったことにより、例えば、配線基板500のものよりも微細な配線パターンを形成することができる。また、配線基板10の製造技術では、ザグリ加工の加工精度や基板厚さバラツキを許容できる配線構造となったことにより、製造歩留まり(加工歩留まり)を向上させることができる。また、必要に応じて、キャビティ24の大きさも拡大させても、これらの作用効果を得ることができる。   With such a manufacturing technique of the wiring board 10, a wiring pattern that can withstand the counterboring process can be formed, and, for example, a wiring pattern finer than that of the wiring board 500 can be formed. Moreover, in the manufacturing technique of the wiring board 10, since the wiring structure can accept the machining accuracy of the counterboring process and the board thickness variation, the manufacturing yield (processing yield) can be improved. Moreover, even if the size of the cavity 24 is enlarged as necessary, these effects can be obtained.

(実施形態2)
本発明の実施形態2に係る配線基板10Aについて図15〜図21を参照して説明する。図15は、配線基板10Aの模式的平面図である。図16〜図21は、配線基板10Aの製造過程の模式的断面図である。前記実施形態1に対して本実施形態では、接続パッドP1、P2を構成する露出面26を有する接続部22−2が、露出面26側からその反対面側へ尻窄まる形状である点で相違する(図15参照)。以下では、相違点を中心にして説明する。
(Embodiment 2)
A wiring board 10A according to Embodiment 2 of the present invention will be described with reference to FIGS. FIG. 15 is a schematic plan view of the wiring board 10A. 16 to 21 are schematic cross-sectional views of the manufacturing process of the wiring board 10A. In contrast to the first embodiment, in the present embodiment, the connection portion 22-2 having the exposed surface 26 that constitutes the connection pads P1 and P2 has a shape that narrows from the exposed surface 26 side to the opposite surface side. They are different (see FIG. 15). Below, it demonstrates centering around difference.

配線基板10Aは、積層される複数の配線層16を備える多層配線基板(図15では、6層の多層配線基板)である。この配線基板10Aは、上面側(表面層20U側)から窪む電子部品搭載用のキャビティ24(凹部)を備える。本実施形態では、キャビティ24は、配線層16−2が設けられる上面側の面54および配線層16−3が設けられる下面側の面56を有する絶縁層18−2の中途まで窪んでおり、絶縁層18−2にキャビティ24の底面(底部)が設けられる。このキャビティ24の底面では配線層16−3と電気的に接続される接続部22−2が露出することとなる。   The wiring board 10A is a multilayer wiring board (in FIG. 15, a six-layer multilayer wiring board) including a plurality of wiring layers 16 to be stacked. This wiring board 10A includes an electronic component mounting cavity 24 (recessed portion) that is recessed from the upper surface side (surface layer 20U side). In the present embodiment, the cavity 24 is recessed to the middle of the insulating layer 18-2 having the upper surface 54 on which the wiring layer 16-2 is provided and the lower surface 56 on which the wiring layer 16-3 is provided. The bottom surface (bottom part) of the cavity 24 is provided in the insulating layer 18-2. At the bottom surface of the cavity 24, the connection portion 22-2 that is electrically connected to the wiring layer 16-3 is exposed.

接続部22−2は、キャビティ24の底面で露出する露出面26と、配線層16−3と接する接続面28と、露出面26および接続面28と交差し、絶縁層18−2に接する側面30とを有し、側面30が傾斜している。ここで、キャビティ24の底面で露出する接続部22−2の露出面26は、例えば、図3に示したような電子部品12、13と電気的に接続される接続面(接続パッドP1、P2)となる。なお、本実施形態でも、図1に示したように、フリップチップ接続用の接続パッドP1は円形状、ワイヤボンディング接続用の接続パッドP2は矩形状となる。   The connection portion 22-2 includes an exposed surface 26 exposed at the bottom surface of the cavity 24, a connection surface 28 in contact with the wiring layer 16-3, and a side surface that intersects the exposed surface 26 and the connection surface 28 and contacts the insulating layer 18-2. 30 and the side surface 30 is inclined. Here, the exposed surface 26 of the connection portion 22-2 exposed at the bottom surface of the cavity 24 is, for example, a connection surface (connection pads P1, P2) electrically connected to the electronic components 12, 13 as shown in FIG. ) Also in this embodiment, as shown in FIG. 1, the flip-chip connection pad P1 has a circular shape, and the wire bonding connection pad P2 has a rectangular shape.

このような配線基板10Aでは、絶縁層18−2中の接続部22−2の側面30が傾斜していることで、傾斜していないもの(基板厚み方向に側面が真っ直ぐなもの)に比べ絶縁層18−2との接触面積が大きくなるため接続部22−2の密着性を向上させることができる。このため、例えば、配線基板10Aが薄型化した場合であっても接続部22−2が抜け取れてしまうことを防止することができる。すなわち、キャビティ24に電子部品12、13を搭載しても、接続部22−2との接続信頼性が確保される部品搭載性に優れた配線基板10Aを提供することができる。   In such a wiring board 10A, the side surface 30 of the connecting portion 22-2 in the insulating layer 18-2 is inclined, so that it is insulated as compared with the case where the side surface 30 is not inclined (the side surface is straight in the substrate thickness direction). Since the contact area with the layer 18-2 becomes large, the adhesiveness of the connection part 22-2 can be improved. For this reason, for example, even when the wiring board 10A is thinned, it is possible to prevent the connection portion 22-2 from being removed. That is, even when the electronic components 12 and 13 are mounted in the cavity 24, it is possible to provide the wiring board 10A excellent in component mounting property that ensures connection reliability with the connection portion 22-2.

本実施形態では、側面30が傾斜している接続部22−2は、図15に示すように、絶縁層18−2の面54側から面56側へ尻窄まる形状である。このため、接続部22−2の露出面26の面積より接続面28の面積が小さくなっている。接続部22−2が尻窄まる形状となることで、所望の大きさの露出面28を確保しつつ露出面26(接続パッドP1、P2となる接続面)を大きくすることができるので、特に、フリップチップ接続されるような電子部品12との接続信頼性をより確保することができる。   In the present embodiment, as shown in FIG. 15, the connecting portion 22-2 in which the side surface 30 is inclined has a shape that is narrowed from the surface 54 side to the surface 56 side of the insulating layer 18-2. For this reason, the area of the connection surface 28 is smaller than the area of the exposed surface 26 of the connection part 22-2. Since the connecting portion 22-2 has a narrowed shape, the exposed surface 26 (the connecting surface to be the connection pads P1 and P2) can be enlarged while securing the exposed surface 28 of a desired size. Further, connection reliability with the electronic component 12 that is flip-chip connected can be further ensured.

次に、本発明の実施形態2に係る配線基板10Aの製造方法について説明する。まず、コア材42(図6参照)を準備した後、図16に示すように、コア材42に形成された貫通孔44に接続部22−3を形成し、また、パターニングされた配線層16−3、16−4を形成する。続いて、図17に示すように、配線層16−2が設けられた絶縁層18−2を絶縁層18−3の上面に積層させ、配線層16−5が設けられた絶縁層18−4を絶縁層18−3の下面に積層させる。   Next, a manufacturing method of the wiring board 10A according to the second embodiment of the present invention will be described. First, after preparing the core material 42 (see FIG. 6), as shown in FIG. 16, the connecting portion 22-3 is formed in the through hole 44 formed in the core material 42, and the patterned wiring layer 16 is also formed. -3, 16-4. Subsequently, as shown in FIG. 17, the insulating layer 18-2 provided with the wiring layer 16-2 is laminated on the upper surface of the insulating layer 18-3, and the insulating layer 18-4 provided with the wiring layer 16-5 is provided. Is laminated on the lower surface of the insulating layer 18-3.

続いて、図18に示すように、絶縁層18−2の上面側から配線層16−3に達し、内壁面が傾斜する貫通部50、52を絶縁層18−2に形成する。また、絶縁層18−4の下面側から配線層16−4に達し、内壁面が傾斜する貫通部48を絶縁層18−4に形成する。貫通部48、50、52の形成には、加工形状の自由度が高いレーザ加工を用いている。レーザ加工によれば、レーザ入射側で開口が若干広く、尻窄まるように開口が狭くなって貫通部48、50、52が形成される。これにより、貫通部48、50、52の内壁面が傾斜するように形成される。そして、本実施形態でも、貫通部50は、円錐台形状の貫通孔に形成され、貫通部52は、四角錐台形状の貫通溝に形成される。   Subsequently, as shown in FIG. 18, through portions 50 and 52 that reach the wiring layer 16-3 from the upper surface side of the insulating layer 18-2 and have an inclined inner wall surface are formed in the insulating layer 18-2. In addition, a penetrating portion 48 that reaches the wiring layer 16-4 from the lower surface side of the insulating layer 18-4 and has an inclined inner wall surface is formed in the insulating layer 18-4. For the formation of the through portions 48, 50, and 52, laser processing with a high degree of freedom in processing shape is used. According to the laser processing, the opening is slightly wide on the laser incident side, and the opening is narrowed so that the bottom is narrowed, so that the through portions 48, 50, and 52 are formed. Thereby, it forms so that the inner wall face of the penetration parts 48, 50, and 52 may incline. Also in the present embodiment, the penetrating portion 50 is formed in a truncated cone-shaped through hole, and the penetrating portion 52 is formed in a quadrangular frustum-shaped through groove.

続いて、図19に示すように、貫通部50、52に導電性材料を埋め込んで配線層16−3と電気的に接続される接続部22−2(Filled Via)を形成し、接続部22−2と電気的に接続されるように、絶縁層18−2の上面にパターニングされた配線層16−2を形成する。また、貫通部48に導電性材料を埋め込んで配線層16−4と電気的に接続される接続部22−4(Filled Via)を形成し、接続部22−4と電気的に接続されるように、絶縁層18−4の下面にパターニングされた配線層16−5を形成する。   Subsequently, as illustrated in FIG. 19, a conductive material is embedded in the through portions 50 and 52 to form a connection portion 22-2 (Filled Via) electrically connected to the wiring layer 16-3. -2 is formed on the upper surface of the insulating layer 18-2 so as to be electrically connected to -2. In addition, a conductive material is embedded in the through portion 48 to form a connection portion 22-4 (Filled Via) that is electrically connected to the wiring layer 16-4, and is electrically connected to the connection portion 22-4. Then, a patterned wiring layer 16-5 is formed on the lower surface of the insulating layer 18-4.

続いて、図20に示すように、配線層16−1が設けられた絶縁層18−1を絶縁層18−2の上面に積層させ、配線層16−6が設けられた絶縁層18−5を絶縁層18−4の下面に積層させる。続いて、図21に示すように、配線層16−2と電気的に接続される接続部22−1を形成し、接続部22−1と電気的に接続されるように、絶縁層18−1の上面にパターニングされた配線層16−1を形成する。また、配線層16−5と電気的に接続される接続部22−5を形成し、接続部22−5と電気的に接続されるように、絶縁層18−5の下面にパターニングされた配線層16−6を形成する。次いで、基板表面(主面)となる表面層20Uを絶縁層18−1の上面に積層し、キャビティ24の開口よりも拡大して開口された拡大開口部36を有するようにパターニングされた表面層20Uを形成する(図15参照)。   Subsequently, as shown in FIG. 20, the insulating layer 18-1 provided with the wiring layer 16-1 is laminated on the upper surface of the insulating layer 18-2, and the insulating layer 18-5 provided with the wiring layer 16-6. Is laminated on the lower surface of the insulating layer 18-4. Subsequently, as illustrated in FIG. 21, a connection portion 22-1 that is electrically connected to the wiring layer 16-2 is formed, and the insulating layer 18-is electrically connected to the connection portion 22-1. A patterned wiring layer 16-1 is formed on the upper surface of 1. Further, a wiring portion 22-5 electrically connected to the wiring layer 16-5 is formed, and the wiring patterned on the lower surface of the insulating layer 18-5 so as to be electrically connected to the connection portion 22-5. Layer 16-6 is formed. Next, a surface layer 20U to be the substrate surface (main surface) is laminated on the upper surface of the insulating layer 18-1, and is patterned to have an enlarged opening 36 that is opened larger than the opening of the cavity 24. 20U is formed (see FIG. 15).

続いて、図15に示すように、表面層20U側から絶縁層18−1を貫通し、絶縁層18−2の中途(すなわち、2層目の配線層16−2と3層目の配線層16−3の間)まで窪むキャビティ24(凹部)を形成する。これにより、キャビティ24の底面で露出する露出面26と、配線層16−3と接する接続面28と、露出面26および接続面28と交差し、絶縁層18−2に接する側面30とを有する接続部22−2が複数形成される。複数の接続部22−2のうち、貫通部50に形成されたものがフリップチップ接続用の接続パッドP1を構成し、貫通部52に形成されたものがワイヤボンディング接続用の接続パッドP2を構成する。その後、接続パッドP1、P2の酸化防止などの一般的な表面処理を行い、配線基板10Aが略完成する。   Subsequently, as shown in FIG. 15, the insulating layer 18-1 is penetrated from the surface layer 20 U side, and the middle of the insulating layer 18-2 (that is, the second wiring layer 16-2 and the third wiring layer). Cavity 24 (concave portion) that is recessed to 16-3) is formed. Thus, the exposed surface 26 exposed at the bottom surface of the cavity 24, the connection surface 28 in contact with the wiring layer 16-3, and the side surface 30 intersecting the exposed surface 26 and the connection surface 28 and in contact with the insulating layer 18-2 are provided. A plurality of connection portions 22-2 are formed. Among the plurality of connection portions 22-2, the one formed in the through portion 50 constitutes a connection pad P1 for flip chip connection, and the one formed in the through portion 52 constitutes a connection pad P2 for wire bonding connection. To do. Thereafter, general surface treatment such as oxidation prevention of the connection pads P1 and P2 is performed, and the wiring board 10A is substantially completed.

このような配線基板10Aの製造技術では、配線基板10と同様の作用効果を得ることができる。すなわち、ザグリ加工に耐えうる配線構造となったことにより、微細な配線パターンを形成することができる。また、ザグリ加工の加工精度や基板厚さバラツキを許容できる配線構造となったことにより、製造歩留まり(加工歩留まり)を向上させることができる。   With such a manufacturing technique of the wiring board 10A, the same effects as the wiring board 10 can be obtained. That is, a fine wiring pattern can be formed because the wiring structure can withstand counterboring. Further, the manufacturing yield (processing yield) can be improved by providing a wiring structure that can accept the machining accuracy of the counterboring process and the substrate thickness variation.

(実施形態3)
本発明の実施形態3に係る配線基板10Bについて図22、図23を参照して説明する。図22および図23は、配線基板10Bの模式的断面図である。前記実施形態1のキャビティ24に対して本実施形態では、キャビティ24が浅い凹部24Aおよび深い凹部24Bを有して2段に構成されている点で相違する。以下では、相違点を中心にして説明する。
(Embodiment 3)
A wiring board 10B according to Embodiment 3 of the present invention will be described with reference to FIGS. 22 and 23 are schematic cross-sectional views of the wiring board 10B. This embodiment is different from the cavity 24 of the first embodiment in that the cavity 24 has a shallow recess 24A and a deep recess 24B and is configured in two stages. Below, it demonstrates centering around difference.

図22、図23に示すように、配線基板10Bは、積層される複数の配線層16を備える多層配線基板(6層の多層配線基板)である。この配線基板10Bは、上面側(表面層20U側)から窪む電子部品搭載用のキャビティ24(凹部)を備える。キャビティ24は、浅い凹部24Aと、この底面(底部)に位置する深い凹部24Bとを有する。これら浅い凹部24Aおよび深い凹部24Bもザグリ加工によって形成することができる。   As shown in FIGS. 22 and 23, the wiring board 10B is a multilayer wiring board (six layers of multilayer wiring board) including a plurality of wiring layers 16 to be stacked. The wiring board 10B includes a cavity 24 (concave portion) for mounting electronic components that is recessed from the upper surface side (surface layer 20U side). The cavity 24 has a shallow recess 24A and a deep recess 24B located on the bottom surface (bottom). These shallow recesses 24A and deep recesses 24B can also be formed by counterboring.

本実施形態では、浅い凹部24Aは、配線層16−2が設けられる上面側の面54および配線層16−3が設けられる下面側の面56を有する絶縁層18−2の中途まで窪んでおり、絶縁層18−2に浅い凹部24Aの底面(底部)が設けられる。この浅い凹部24Aの底面では配線層16−3と電気的に接続される接続部22−2が露出することとなる。また、深い凹部24Bは、配線層16−4が設けられる上面側の面17および配線層16−5が設けられる下面側の面19を有する絶縁層18−4の中途まで窪んでおり、絶縁層18−4に深い凹部24Bの底面(底部)が設けられる。そして、図23に示す配線基板10Bの深い凹部24Bの底面では配線層16−5と電気的に接続される接続部22−4が露出することとなる。   In the present embodiment, the shallow recess 24A is recessed to the middle of the insulating layer 18-2 having the upper surface 54 on which the wiring layer 16-2 is provided and the lower surface 56 on which the wiring layer 16-3 is provided. The bottom surface (bottom portion) of the shallow recess 24A is provided in the insulating layer 18-2. At the bottom surface of the shallow concave portion 24A, the connection portion 22-2 that is electrically connected to the wiring layer 16-3 is exposed. The deep recess 24B is recessed to the middle of the insulating layer 18-4 having the upper surface 17 on which the wiring layer 16-4 is provided and the lower surface 19 on which the wiring layer 16-5 is provided. The bottom face (bottom part) of the deep recessed part 24B is provided in 18-4. Then, the connection portion 22-4 that is electrically connected to the wiring layer 16-5 is exposed on the bottom surface of the deep recess 24B of the wiring substrate 10B shown in FIG.

図22に示す配線基板10Bでは、浅い凹部24Aの底面で露出する接続部22−2の露出面26が、ワイヤボンディング接続用の接続パッドP2として矩形状となる。このように、図22に示す配線基板10Bは、深い凹部24Bに1つの電子部品を搭載し、その電子部品が浅い凹部24Aの接続パッドP2と電気的に接続される構造である。   In the wiring substrate 10B shown in FIG. 22, the exposed surface 26 of the connection portion 22-2 exposed at the bottom surface of the shallow recess 24A has a rectangular shape as a connection pad P2 for wire bonding connection. As described above, the wiring board 10B shown in FIG. 22 has a structure in which one electronic component is mounted in the deep recess 24B and the electronic component is electrically connected to the connection pad P2 of the shallow recess 24A.

また、図23に示す配線基板10Bでは、浅い凹部24Aの底面で露出する接続部22−2の露出面26が、フリップチップ接続用の接続パッドP1として円形状となる。また、深い凹部24Bの底面で露出する接続部22−4の露出面26が、フリップチップ接続用の接続パッドP1として円形状となる。このように、図23に示す配線基板10Bは、例えば、浅い凹部24Aと深い凹部24Bのそれぞれに電子部品を搭載し、各電子部品が接続パッドP1と電気的に接続される構造である。   Further, in the wiring substrate 10B shown in FIG. 23, the exposed surface 26 of the connection portion 22-2 exposed at the bottom surface of the shallow recess 24A has a circular shape as a connection pad P1 for flip chip connection. Further, the exposed surface 26 of the connection portion 22-4 exposed at the bottom surface of the deep recess 24B has a circular shape as a connection pad P1 for flip chip connection. As described above, the wiring substrate 10B shown in FIG. 23 has a structure in which, for example, electronic components are mounted in each of the shallow concave portion 24A and the deep concave portion 24B, and each electronic component is electrically connected to the connection pad P1.

また、図23に示す配線基板10Bでは、接続部22−2が面54側(基板上面側)から面56側(基板下面側)へ尻窄まる形状であり、接続部22−4が面17側(基板上面側)から面19側(基板下面側)へ末広がる形状となっている。これによれば、例えば、浅い凹部24Aでは薄い電子部品が搭載され、深い凹部24Bでは深い電子部品が搭載されるなど、搭載される複数の電子部品に対応させて、接続部22−2を用いて電子部品との接続信頼性をより確保したり、接続部22−4をより抜け取れ難くしたりすることができる。なお、配線基板10Bでは、キャビティ24が2段の凹部で構成される場合について説明したが、これに限らず、3段以上の複数の凹部で構成される場合であってもよい。   Further, in the wiring board 10B shown in FIG. 23, the connecting portion 22-2 has a shape that is narrowed from the surface 54 side (the substrate upper surface side) to the surface 56 side (the substrate lower surface side), and the connecting portion 22-4 is the surface 17. The shape widens from the side (substrate upper surface side) to the surface 19 side (substrate lower surface side). According to this, for example, a thin electronic component is mounted in the shallow concave portion 24A, and a deep electronic component is mounted in the deep concave portion 24B, so that the connection portion 22-2 is used corresponding to a plurality of electronic components to be mounted. Thus, it is possible to further secure the connection reliability with the electronic component or to make it difficult to remove the connection portion 22-4. In the wiring board 10B, the case where the cavity 24 is configured by two-stage recesses has been described. However, the configuration is not limited to this, and the case may be configured by a plurality of recesses of three or more stages.

(実施形態4)
本発明の実施形態4に係る配線基板10Cについて図24を参照して説明する。図24は、配線基板10Cの模式的断面図である。前記実施形態1のキャビティ24に対して本実施形態では、キャビティ24の底面で絶縁層18−4、18−5を貫通する貫通部58を備える点で相違する。以下では、相違点を中心にして説明する。
(Embodiment 4)
A wiring board 10C according to Embodiment 4 of the present invention will be described with reference to FIG. FIG. 24 is a schematic cross-sectional view of the wiring board 10C. This embodiment is different from the cavity 24 of the first embodiment in that a through portion 58 that penetrates the insulating layers 18-4 and 18-5 is provided on the bottom surface of the cavity 24. Below, it demonstrates centering around difference.

図24に示すように、配線基板10Cは、積層される複数の配線層16を備える多層配線基板(6層の多層配線基板)である。この配線基板10Cは、上面側(表面層20U側)から窪む電子部品搭載用のキャビティ24(凹部)を備える。そして、このキャビティ24は、例えば、ザグリ加工後のドリル加工によって、キャビティ24の底面(底部)に形成された貫通部58を備える。このような配線基板10Cでは、例えば、基板下面となる表面層20Lに放熱板を貼り、貫通部58に電子部品を搭載することで、放熱性を高めることができる。また、配線基板10Bでは、貫通部58の開口周りのキャビティ24に形成されたワイヤボンディング接続用の接続パッドP2と電子部品を電気的に接続することができる。   As shown in FIG. 24, the wiring board 10C is a multilayer wiring board (six layers of multilayer wiring board) including a plurality of wiring layers 16 to be stacked. This wiring board 10C includes a cavity 24 (recessed portion) for mounting electronic components that is recessed from the upper surface side (surface layer 20U side). And this cavity 24 is provided with the penetration part 58 formed in the bottom face (bottom part) of the cavity 24, for example by the drilling after a counterbore process. In such a wiring substrate 10 </ b> C, for example, a heat dissipation plate can be attached to the surface layer 20 </ b> L serving as the lower surface of the substrate, and an electronic component can be mounted on the through portion 58, thereby improving heat dissipation. Further, in the wiring substrate 10B, the electronic component can be electrically connected to the connection pad P2 for wire bonding connection formed in the cavity 24 around the opening of the through portion 58.

(実施形態5)
本発明の実施形態5に係る配線基板10Dについて図25を参照して説明する。図25は、配線基板10Dの模式的断面図である。前記実施形態1の1つのキャビティ24に対して本実施形態では、基板上下面からそれぞれ窪む2つのキャビティ24を備える点で相違する。以下では、相違点を中心にして説明する。
(Embodiment 5)
A wiring board 10D according to Embodiment 5 of the present invention will be described with reference to FIG. FIG. 25 is a schematic cross-sectional view of the wiring board 10D. This embodiment is different from the first embodiment in that two cavities 24 that are recessed from the upper and lower surfaces of the substrate are provided. Below, it demonstrates centering around difference.

図25に示すように、配線基板10Dは、積層される複数の配線層16を備える多層配線基板(6層の多層配線基板)である。この配線基板10Dは、上面側(表面層20U側)から窪む電子部品搭載用のキャビティ24(凹部)と、下面側(表面層20L側)から窪む電子部品搭載用のキャビティ24(凹部)とを備え、基板厚みの一方向および反対方向にそれぞれ開口している。これによれば、使用状況に応じて、複数の電子部品を搭載することができる。   As shown in FIG. 25, the wiring board 10D is a multilayer wiring board (six layers of multilayer wiring board) including a plurality of wiring layers 16 to be stacked. The wiring board 10D includes an electronic component mounting cavity 24 (recessed portion) recessed from the upper surface side (surface layer 20U side) and an electronic component mounting cavity 24 (recessed portion) recessed from the lower surface side (surface layer 20L side). Are opened in one direction and the opposite direction of the substrate thickness. According to this, a plurality of electronic components can be mounted according to the usage situation.

(実施形態6)
本発明の実施形態6に係る配線基板10Eについて図26を参照して説明する。図26は、配線基板10Eの模式的断面図である。前記実施形態1の6層の配線基板10に対して本実施形態では、2層の配線基板10Eである点で相違する。以下では、相違点を中心にして説明する。
(Embodiment 6)
A wiring board 10E according to Embodiment 6 of the present invention will be described with reference to FIG. FIG. 26 is a schematic cross-sectional view of the wiring board 10E. This embodiment is different from the six-layer wiring board 10 of the first embodiment in that it is a two-layer wiring board 10E. Below, it demonstrates centering around difference.

図26に示すように、配線基板10Eは、積層される複数の配線層16を備える多層配線基板(2層の多層配線基板)である。この配線基板10Eは、上面側(表面層20U側)から窪む電子部品搭載用のキャビティ24(凹部)を備える。このような、2層の配線基板10Eであっても、また、3層以上の配線基板であっても、配線基板10と同様の作用効果を得ることができる。   As shown in FIG. 26, the wiring board 10E is a multilayer wiring board (two-layer multilayer wiring board) including a plurality of wiring layers 16 to be stacked. This wiring board 10E includes a cavity 24 (concave portion) for mounting electronic components that is recessed from the upper surface side (surface layer 20U side). Even if it is such a two-layer wiring board 10E or a three-layer or more wiring board, the same effect as the wiring board 10 can be obtained.

以上、本発明を実施形態に基づき具体的に説明したが、本発明は前記実施形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。すなわち、前記実施形態に係る配線基板は、本発明に係る配線基板の一部であり、各実施形態を組み合わせた構造などにおいても、本発明の有効性に変わりはない。   Although the present invention has been specifically described above based on the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. That is, the wiring board according to the embodiment is a part of the wiring board according to the present invention, and the effectiveness of the present invention is not changed even in a structure in which the embodiments are combined.

10 配線基板; 12、13 電子部品; 14 電子製品;
16 配線層; 17 面; 18 絶縁層;
19 面; 20 表面層; 22 接続部;
24 キャビティ(凹部); 26 露出面; 28 接続面;
30 側面; 32 接続バンプ;
34 ボンディングワイヤ; 36 拡大開口部; 38 段付き部;
40 封止樹脂; 42 コア材; 44 貫通孔;
46 絶縁性材料; 48、50、52 貫通部; 54、56 面;
58 貫通部; 500 配線基板;
P1、P2 接続パッド。
10 Wiring board; 12, 13 Electronic component; 14 Electronic product;
16 wiring layers; 17 surfaces; 18 insulating layers;
19 surfaces; 20 surface layers; 22 connecting parts;
24 cavity (recess); 26 exposed surface; 28 connecting surface;
30 side surfaces; 32 connection bumps;
34 Bonding wire; 36 Enlarged opening; 38 Stepped portion;
40 sealing resin; 42 core material; 44 through hole;
46 insulating material; 48, 50, 52 through; 54, 56 surfaces;
58 penetration part; 500 wiring board;
P1, P2 connection pads.

Claims (17)

積層される複数の配線層と、
前記複数の配線層の第1および第2配線層がそれぞれ設けられる第1および第2面を有する絶縁層と、
前記第1面側から前記絶縁層の中途まで窪む凹部と、
前記第2配線層と電気的に接続し、前記凹部の底面で露出するように前記絶縁層に設けられる接続部と
を備え、
前記接続部は、前記凹部の底面で露出する露出面と、前記第2配線層と接する接続面と、前記露出面および前記接続面と交差し、前記絶縁層に接する側面とを有し、該側面が傾斜していることを特徴とする配線基板。
A plurality of laminated wiring layers;
An insulating layer having first and second surfaces on which the first and second wiring layers of the plurality of wiring layers are respectively provided;
A recess recessed from the first surface side to the middle of the insulating layer;
A connection portion provided in the insulating layer so as to be electrically connected to the second wiring layer and exposed at the bottom surface of the recess;
The connection portion has an exposed surface exposed at a bottom surface of the recess, a connection surface in contact with the second wiring layer, and a side surface that intersects the exposed surface and the connection surface and contacts the insulating layer, A wiring board characterized in that a side surface is inclined.
請求項1記載の配線基板において、
前記接続部が、前記第1面側から前記第2面側へ末広がる形状である。
The wiring board according to claim 1,
The connecting portion has a shape that spreads from the first surface side to the second surface side.
請求項1記載の配線基板において、
前記接続部が、前記第1面側から前記第2面側へ尻窄まる形状である。
The wiring board according to claim 1,
The connecting portion has a shape that narrows from the first surface side to the second surface side.
請求項1〜3のいずれか一項に記載の配線基板において、
前記接続部が、前記第1配線層と前記第2配線層とを電気的に接続して、前記第1配線層と前記第2配線層との間の前記絶縁層に設けられ、
前記接続部の第1面側端部は、該第1面側端部の一部が前記第1配線層に接したまま前記凹部によって該第1面側端部の他部が削られて前記露出面が設けられている。
In the wiring board as described in any one of Claims 1-3,
The connecting portion is provided in the insulating layer between the first wiring layer and the second wiring layer by electrically connecting the first wiring layer and the second wiring layer;
The first surface side end portion of the connection portion has the other portion of the first surface side end portion scraped off by the recess while a part of the first surface side end portion is in contact with the first wiring layer. An exposed surface is provided.
請求項1〜4のいずれか一項に記載の配線基板において、
前記露出面が、前記凹部の底面中央部から底面外周部の方向が長手となる長方形状である。
In the wiring board as described in any one of Claims 1-4,
The exposed surface has a rectangular shape in which the direction from the center of the bottom surface of the concave portion to the outer peripheral portion of the bottom surface is a longitudinal direction.
請求項5記載の配線基板において、
前記接続部が、前記凹部の底面縁部に沿って複数設けられている。
The wiring board according to claim 5,
A plurality of the connection portions are provided along the bottom edge of the recess.
請求項1〜6のいずれか一項に記載の配線基板において、
前記凹部を露出して前記第1配線層を覆うように基板表面に設けられる表面層を備え、
前記表面層が、前記凹部の開口よりも拡大して開口された拡大開口部を有する。
In the wiring board as described in any one of Claims 1-6,
A surface layer provided on the surface of the substrate so as to expose the recess and cover the first wiring layer;
The surface layer has an enlarged opening that is larger than the opening of the recess.
請求項1〜7のいずれか一項に記載の配線基板において、
前記凹部の底面で前記絶縁層を貫通する貫通部を備える。
In the wiring board as described in any one of Claims 1-7,
A through portion penetrating the insulating layer is provided at the bottom surface of the concave portion.
請求項1〜8記載の配線基板において、
前記絶縁層を第1絶縁層と、前記凹部を第1凹部と、前記接続部を第1接続部とし、
前記複数の配線層の第3および第4配線層がそれぞれ設けられる第3および第4面を有する第2絶縁層と、
前記第3面側から前記第2絶縁層の中途まで窪む第2凹部と、
前記第4配線層と電気的に接続し、前記第2凹部の底面で露出するように前記第2絶縁層に設けられる第2接続部と
を備え、
前記第1、第2、第3、および第4配線層がこの順で積層され、
前記第2接続部が、前記第2凹部の底面で露出する露出面と、前記第3配線層と接する接続面と、前記露出面および前記接続面と交差し、前記第2絶縁層に接する側面とを有し、
前記第2接続部の側面が傾斜し、
前記第1接続部が前記第1面側から前記第2面側へ末広がる形状であるときに、前記第2接続部が前記第3面側から前記第4面側へ尻窄まる形状であり、
前記第1接続部が前記第1面側から前記第2面側へ尻窄まる形状であるときに、前記第2接続部が前記第3面側から前記第4面側へ末広がる形状である。
In the wiring board according to claim 1,
The insulating layer is a first insulating layer, the concave portion is a first concave portion, and the connecting portion is a first connecting portion,
A second insulating layer having third and fourth surfaces provided with third and fourth wiring layers of the plurality of wiring layers, respectively;
A second recess recessed from the third surface side to the middle of the second insulating layer;
A second connection portion provided in the second insulating layer so as to be electrically connected to the fourth wiring layer and exposed at a bottom surface of the second recess;
The first, second, third, and fourth wiring layers are stacked in this order,
The second connection portion is an exposed surface exposed at the bottom surface of the second recess, a connection surface in contact with the third wiring layer, a side surface that intersects the exposed surface and the connection surface, and is in contact with the second insulating layer. And
A side surface of the second connecting portion is inclined;
When the first connection portion has a shape that widens from the first surface side to the second surface side, the second connection portion has a shape that narrows from the third surface side to the fourth surface side. ,
When the first connection portion has a shape that narrows from the first surface side to the second surface side, the second connection portion has a shape that spreads from the third surface side to the fourth surface side. .
請求項9記載の配線基板において、
前記第1凹部が、基板厚みの一方向に開口し、
前記第2凹部が、前記一方向の反対方向に開口している。
The wiring board according to claim 9, wherein
The first recess opens in one direction of the substrate thickness;
The second recess opens in a direction opposite to the one direction.
積層される複数の配線層と、前記複数の配線層の第1および第2配線層がそれぞれ設けられる第1および第2面を有する絶縁層とを備える配線基板の製造方法であって、
(a)前記第2面側から前記第1配線層に達し、内壁面が傾斜する貫通部を前記絶縁層に形成する工程と、
(b)前記貫通部に導電性材料を埋め込んで前記第1配線層と電気的に接続される接続部を形成する工程と、
(c)前記接続部と電気的に接続されるように前記第2面に前記第2配線層を形成する工程と、
(d)前記第1面側から前記絶縁層の中途まで窪む凹部を形成することによって、前記凹部の底面で露出する露出面と、前記第2配線層と接する接続面と、前記露出面および前記接続面と交差し、前記絶縁層に接する側面とを有し、前記第1面側から前記第2面側へ末広がる形状となって前記側面が傾斜している前記接続部を形成する工程と
を含むことを特徴とする配線基板の製造方法。
A method of manufacturing a wiring board comprising: a plurality of wiring layers to be laminated; and an insulating layer having first and second surfaces on which first and second wiring layers of the plurality of wiring layers are respectively provided.
(A) a step of forming, in the insulating layer, a penetrating portion that reaches the first wiring layer from the second surface side and whose inner wall surface is inclined;
(B) embedding a conductive material in the penetrating portion to form a connecting portion electrically connected to the first wiring layer;
(C) forming the second wiring layer on the second surface so as to be electrically connected to the connection portion;
(D) By forming a recess that is recessed from the first surface side to the middle of the insulating layer, an exposed surface that is exposed at the bottom surface of the recess, a connection surface that is in contact with the second wiring layer, the exposed surface, and A step of forming the connection portion having a side surface that intersects the connection surface and contacts the insulating layer, and has a shape that widens from the first surface side to the second surface side; A method for manufacturing a wiring board, comprising:
積層される複数の配線層と、前記複数の配線層の第1および第2配線層がそれぞれ設けられる第1および第2面を有する絶縁層とを備える配線基板の製造方法であって、
(a)前記第1面側から前記第2配線層に達し、内壁面が傾斜する貫通部を前記絶縁層に形成する工程と、
(b)前記貫通部に導電性材料を埋め込んで前記第2配線層と電気的に接続される接続部を形成する工程と、
(c)前記接続部と電気的に接続されるように前記第1面に前記第1配線層を形成する工程と、
(d)前記第1面側から前記絶縁層の中途まで窪む凹部を形成することによって、前記凹部の底面で露出する露出面と、前記第2配線層と接する接続面と、前記露出面および前記接続面と交差し、前記絶縁層に接する側面とを有し、前記第1面側から前記第2面側へ尻窄まる形状となって前記側面が傾斜している前記接続部を形成する工程と
を含むことを特徴とする配線基板の製造方法。
A method of manufacturing a wiring board comprising: a plurality of wiring layers to be laminated; and an insulating layer having first and second surfaces on which first and second wiring layers of the plurality of wiring layers are respectively provided.
(A) a step of forming, in the insulating layer, a penetrating portion that reaches the second wiring layer from the first surface side and whose inner wall surface is inclined;
(B) embedding a conductive material in the penetrating portion to form a connecting portion that is electrically connected to the second wiring layer;
(C) forming the first wiring layer on the first surface so as to be electrically connected to the connection portion;
(D) By forming a recess that is recessed from the first surface side to the middle of the insulating layer, an exposed surface that is exposed at the bottom surface of the recess, a connection surface that is in contact with the second wiring layer, the exposed surface, and The connecting portion has a side surface that intersects with the connection surface and contacts the insulating layer, and has a shape that is narrowed from the first surface side to the second surface side, and the side surface is inclined. A method for manufacturing a wiring board comprising the steps of:
請求項11または12記載の配線基板の製造方法において、
前記(d)工程では、前記凹部を形成することによって、前記接続部の第1面側端部の一部を前記第1配線層に接したまま、該第1面側端部の他部を削って前記露出面を形成する。
In the manufacturing method of the wiring board of Claim 11 or 12,
In the step (d), by forming the recess, a part of the first surface side end of the connection portion is kept in contact with the first wiring layer, and the other portion of the first surface side end is changed. The exposed surface is formed by shaving.
請求項11〜13のいずれか一項に記載の配線基板の製造方法において、
前記(d)工程の前に、前記凹部の開口よりも拡大して開口された拡大開口部を有し、前記第1配線層を覆うように基板表面に設けられる表面層を形成する。
In the manufacturing method of the wiring board as described in any one of Claims 11-13,
Before the step (d), a surface layer having an enlarged opening that is larger than the opening of the recess and provided on the substrate surface so as to cover the first wiring layer is formed.
請求項11〜14のいずれか一項に記載の配線基板の製造方法において、
前記(d)工程後、前記凹部の底面で前記絶縁層を貫通する貫通部を形成する。
In the manufacturing method of the wiring board as described in any one of Claims 11-14,
After the step (d), a penetrating portion that penetrates the insulating layer is formed on the bottom surface of the concave portion.
請求項11〜15のいずれか一項に記載の配線基板の製造方法において、
前記(d)工程では、ザグリ加工によって前記凹部を形成する。
In the manufacturing method of the wiring board as described in any one of Claims 11-15,
In the step (d), the recess is formed by counterboring.
請求項11〜16のいずれか一項に記載の配線基板の製造方法において、
前記(a)工程では、レーザ加工によって前記貫通部を形成する。
In the manufacturing method of the wiring board as described in any one of Claims 11-16,
In the step (a), the through portion is formed by laser processing.
JP2015042917A 2015-03-04 2015-03-04 Wiring board and manufacturing method of the same Pending JP2016162977A (en)

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JP2016201424A (en) * 2015-04-08 2016-12-01 イビデン株式会社 Printed wiring board and method for manufacturing the same
JP2019096796A (en) * 2017-11-27 2019-06-20 日本特殊陶業株式会社 Manufacturing method of wiring board
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Publication number Priority date Publication date Assignee Title
JP2016201424A (en) * 2015-04-08 2016-12-01 イビデン株式会社 Printed wiring board and method for manufacturing the same
JP2019096796A (en) * 2017-11-27 2019-06-20 日本特殊陶業株式会社 Manufacturing method of wiring board
US11406013B2 (en) * 2018-05-28 2022-08-02 Murata Manufacturing Co., Ltd. Resin multilayer substrate and electronic device
JP7379511B2 (en) 2019-09-25 2023-11-14 京セラ株式会社 Printed wiring board and method for manufacturing printed wiring board
CN114096059A (en) * 2020-08-25 2022-02-25 宏恒胜电子科技(淮安)有限公司 Circuit board and manufacturing method thereof
CN114096059B (en) * 2020-08-25 2023-10-10 宏恒胜电子科技(淮安)有限公司 Circuit board and manufacturing method thereof
CN114258193A (en) * 2020-09-23 2022-03-29 庆鼎精密电子(淮安)有限公司 Manufacturing method of circuit board connecting structure and circuit board connecting structure
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