JP2016158378A - Switching power supply circuit and switching loss suppression method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a switching loss in a switching power supply circuit.SOLUTION: A switching power supply circuit 1 includes two switch elements 3, 4, a control circuit 5 and a charging circuit 6. The switch elements 3, 4 are connected in series. The control circuit 5 controls the switching operation of the switch elements 3, 4, when one of the switch elements 3, 4 becomes an OFF state, to switch another to an ON state. Based on the control operation of the control circuit 5, the charging circuit 6 accelerates the charging of the parasitic capacitance 7 (or parasitic capacitance 8) of the switch element 3 (or switch element 4) having been controlled to switch from the ON state to the OFF state.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a technology related to a switching power supply circuit including two switch elements connected in series.

  Patent Document 1 discloses an example of a half-bridge type switching power supply circuit. The half-bridge type switching power supply circuit includes two switch elements connected in series. When one of these switch elements is turned off, the switching operation is controlled so that the other is turned on. The switch element is connected to a transformer and supplies energy generated in the transformer by such a switching operation to the output side.

  Patent Document 2 discloses a switching power supply circuit that can operate with high efficiency with respect to a wide range of loads from a light load to a rated load and a heavy load and that is excellent in output response. Patent Document 3 discloses a technique for improving the power efficiency of a circuit that drives a piezoelectric element.

JP-A-9-201054 International Publication No. 2011/111483 JP 2008-283830 A

  In a switching power supply circuit as disclosed in Patent Document 1, the switching operation of the switch element is increased in frequency, so that circuit components such as coils and capacitors constituting the circuit are miniaturized.

  However, on the other hand, the problem of the following switching loss has been increased by increasing the switching operation of the switch element. That is, in Patent Document 1, the switch element is a semiconductor switch element and has parasitic capacitance. When the switch element is switched from the on state to the off state, the parasitic capacitance of the switch element starts to be charged, and thereby the voltage of the switch element starts to rise. Further, when the switch element is switched to the OFF state, the energization current of the switch element is decreased. Due to this state (that is, a state in which a voltage is applied to the switch element and a current is applied), power loss (switching loss) occurs. When the frequency is increased, the number of times the switch element is turned off increases, so that power loss (switching loss) increases.

  The present invention has been devised to solve the above problems. That is, a main object of the present invention is to provide a technique for suppressing a switching loss of a switching power supply circuit.

In order to achieve the above object, the switching power supply circuit of the present invention comprises:
Two switch elements connected in series;
A control circuit for controlling the switching operation of the switch element such that when one of the switch elements is turned off, the other is turned on;
And a charging circuit that promotes charging of the parasitic capacitance of the switch element that is controlled to be switched from the on state to the off state based on the control operation of the control circuit.

Further, the switching loss suppressing method of the present invention is
When one of the two switch elements connected in series is turned off, the control operation of the control circuit that controls the switching operation of the switch element is detected so that the other is turned on.
When it is detected that one of the switch elements is controlled to be switched from the on state to the off state, charging of the parasitic capacitance of the switch element is promoted.

  According to the present invention, it is possible to suppress the switching loss of the switching power supply circuit.

1 is a block diagram schematically illustrating a circuit configuration of a switching power supply circuit according to a first embodiment of the present invention. It is a figure explaining the circuit operation example of the switching power supply circuit of 1st Embodiment, and its effect. It is a circuit diagram showing the circuit structure of the switching power supply circuit of 2nd Embodiment which concerns on this invention. It is a time chart showing the circuit operation example of the switching power supply circuit of 2nd Embodiment. It is a figure explaining the operation example of a charging circuit. Furthermore, it is a figure explaining the operation example of a charging circuit. It is a figure explaining the effect by the switching power supply circuit of 2nd Embodiment. It is a figure explaining other embodiment.

  Embodiments according to the present invention will be described below with reference to the drawings.

<First Embodiment>
FIG. 1 is a circuit diagram showing a simplified circuit configuration of the switching power supply circuit according to the first embodiment of the present invention. The switching power supply circuit 1 according to the first embodiment includes two switch elements 3, 4, a control circuit 5, and a charging circuit 6.

  The switch elements 3 and 4 are connected in series. Each of these switch elements 3 and 4 is, for example, a semiconductor switch element and has parasitic capacitances (internal capacitances) 7 and 8, respectively.

  The control circuit 5 has a function of controlling the switching operation of the switch elements 3 and 4 so that when one of the switch elements 3 and 4 is turned off, the other is turned on.

  The charging circuit 6 is a circuit that promotes charging of the parasitic capacitance 7 (or the parasitic capacitance 8) of the switch element 3 (or the switch element 4) that is controlled to be switched from the on state to the off state based on the control operation of the control circuit 5. It has a configuration.

  The switching power supply circuit 1 according to the first embodiment includes a charging circuit 6 and charges the parasitic capacitance 7 and the parasitic capacitance 8 of the switch elements 3 and 4 that are controlled to be switched from the on state to the off state by the charging circuit 6. Can promote. Thereby, the said switching power supply circuit 1 can acquire the effect that the switching loss at the time of the switch elements 3 and 4 switching from an ON state to an OFF state can be suppressed.

  This effect will be described with reference to FIG. FIG. 2 is a waveform diagram of signals, voltages, and the like representing the circuit operation of the switching power supply circuit 1. The signal S3 shown in FIG. 2 is an example of a signal that the control circuit 5 supplies to the switch element 3 for switching control of the switch element 3. The signal S4 is an example of a signal that the control circuit 5 supplies to the switch element 4 for switching control of the switch element 4.

  Here, it is assumed that the charging circuit 6 is not provided. In this case, when the switching elements 3 and 4 are subjected to switching control by the signals S3 and S4, for example, a voltage as represented by the solid line waveform V2 in FIG. A current as represented by I2 is energized.

  That is, when the switching element 3 is controlled to be switched from the on state to the off state, charging of the parasitic capacitance 7 of the switching element 3 is started, and the voltage V2 starts to be generated in the switching element 3. On the other hand, the current I2 supplied to the switch element 3 gradually decreases. When the switching element 3 is switched to the OFF state by such voltage V2 and current I2, switching loss (power loss) as represented by the hatching region M in FIG. 2 occurs.

  On the other hand, in the first embodiment, the switching power supply circuit 1 includes the charging circuit 6, and when the switching elements 3 and 4 are controlled to be turned off, the charging circuit 6 causes the switching elements 3 and 4 to become parasitic. Charging the capacities 7 and 8 can be promoted. As the charging circuit 6 accelerates the charging of the parasitic capacitances 7 and 8, for example, a voltage represented by the solid line waveform V1 in FIG. That is, when the switching element 3 is controlled to be turned off, the voltage V1 of the switching element 3 rises abruptly, and accordingly, the energization current I1 of the switching element 3 is represented by the dotted waveform I1 in FIG. Decreases rapidly. Thereby, the voltage V1 is generated in the switch element 3 and the current I1 is prevented from being energized, and the switching loss is reduced (region M due to the voltage V2 and the current I2 in FIG. 2). Is almost gone). The same applies to the switch element 4, and when the switch element 4 is controlled to be switched to the OFF state, a voltage is generated in the switch element 4 and a state in which a current is energized is suppressed, and the switching loss is suppressed. Is reduced. Therefore, the switching power supply circuit 1 of the first embodiment can suppress the switching loss.

Second Embodiment
The second embodiment according to the present invention will be described below.

  FIG. 3 is a circuit diagram illustrating a main circuit configuration of the switching power supply circuit according to the second embodiment. The switching power supply circuit 20 of the second embodiment is a half-bridge type switching power supply circuit. The switching power supply circuit 20 includes a transformer 21, an input circuit 22, an output circuit 23, a control circuit 24, and a charging circuit 25.

An input circuit 22 is connected to the primary side of the transformer 21, and an output circuit 23 is connected to the secondary side of the transformer 21. The input circuit 22 has two switch elements Q1 and Q2. These switch elements Q1 and Q2 are FETs (Field Effect Transistors). Thereby, the switch elements Q1 and Q2 respectively have parasitic capacitances (internal capacitances) C _Q1 and C _Q2 and parasitic diodes (internal diodes) D _Q1 and D _Q2 due to the internal structure.

  The switch elements Q1 and Q2 are connected in series so that the source side of the switch element Q1 and the drain side of the switch element Q2 are connected. An input capacitor C1 is connected in parallel to the series connection circuit of the switch elements Q1 and Q2. Further, a series connection circuit of capacitors C2 and C3 is connected in parallel to the series connection circuit of the switch elements Q1 and Q2. The connection part of the switch elements Q1, Q2 is connected to one end side of the primary coil of the transformer 21 via the inductance L1. The other end side of the primary coil of the transformer 21 is connected to the connection part of the capacitors C2 and C3.

  The output circuit 23 connected to the secondary coil of the transformer 21 rectifies and smoothes the energy output from the secondary coil of the transformer 21 and outputs the rectified and smoothed voltage from the output unit OUT to a load (not shown). It has a function to do. In the second embodiment, the circuit configuration of the output circuit 23 is not limited as long as such a function can be realized, and an appropriate circuit configuration may be adopted. Here, the description of the circuit configuration of the output circuit 23 is omitted.

  The charging circuit 25 has a switch element Q3. This switch element Q3 is also an FET element like the switch elements Q1 and Q2, and the cathode side of the diodes D1 and D2 is connected to the drain side of the switch element Q3. The cathode side of the diode D3 is connected to the anode side of the diode D1, and the cathode side of the diode D4 is connected to the anode side of the diode D2. The anode sides of the diodes D3 and D4 are connected to the source side of the switch element Q3. The connection part of the diodes D2 and D4 is connected to one end side of the primary coil of the transformer 21, and the connection part of the diodes D1 and D3 is connected to the other end side of the primary coil of the transformer 21.

  The control circuit 24 is connected to the gate side of the switch elements Q1, Q2, Q3, and has a circuit configuration for controlling the switching operation of the switch elements Q1, Q2, Q3. FIG. 4 is a time chart showing the circuit operation of the switching power supply circuit 20. A waveform Q1 shown in FIG. 4 represents an example of a signal waveform applied from the control circuit 24 to the gate of the switch element Q1. A waveform Q2 represents an example of a signal waveform applied from the control circuit 24 to the gate of the switch element Q2. A waveform Q3 represents an example of a signal waveform applied from the control circuit 24 to the gate of the switch element Q3.

  For example, the control circuit 24 controls the switch elements Q1 and Q2 so as to perform a switching operation as described below. That is, as shown in the waveforms Q1 and Q2 in FIG. 4, when one of the switch elements Q1 and Q2 is in the off state, the other is in the on state. Further, the switch elements Q1, Q2 are switched from the off state to the on state with a preset period. Further, the switch elements Q1 and Q2 are configured so that the output voltage Vout is stabilized at the set voltage Vs according to the difference between the output voltage Vout supplied from the output circuit 23 to the load and a predetermined set voltage Vs. The length of the on-state period (on period) varies.

  Further, as represented by a waveform Q3 in FIG. 4, the control circuit 24 switches the switching elements Q1 and Q2 so that the switching elements Q1 and Q2 are switched from the off state to the on state at the timing when the switching elements Q1 and Q2 are switched from the on state to the off state, respectively. Q3 is subjected to switching control. Furthermore, in the second embodiment, the control circuit 24 performs switching control of the switch element Q3 so that the switch elements Q1 and Q2 are switched from the on state to the off state at the timing when the switch elements Q1 and Q2 are switched to the on state.

  There are various circuit configurations for switching control of the switching elements Q1, Q2, and Q3 as described above. Here, the control circuit 24 may adopt any circuit configuration, and the description thereof will be given below. Omitted.

  The switching power supply circuit 20 of the second embodiment is configured as described above. Next, circuit operations of the input circuit 22 and the charging circuit 25 in the switching power supply circuit 20 will be described with reference to FIGS.

For example, when the switch element Q1 is on and the switch element Q2 is off, when the switch element Q1 is switched to the off state (time t1 in FIG. 4), both the switch elements Q1 and Q2 are off. It becomes. Further, the switch element Q1 is switched to the off state, and the switch element Q3 is switched to the on state. At this time, the parasitic capacitance C _Q1 of the switching element Q1 is a state where no charge is accumulated, the parasitic capacitance C _Q2 of the switching element Q2 is a state of charge charge is accumulated.

By switching the switching elements Q1, Q3 as mentioned above, the input circuit 22 to the charging circuit 25, a current I _M, as represented in FIG. 5 is energized. That is, the current I _M is energized with a path back from the input capacitor C1 to the parasitic capacitance C _Q1 → inductance L1 → the diode D2 → switching element Q3 → the diode D3 → the input through a capacitor C3 capacitor C1 of the switching element Q1. By energization of the current I _M, the charge in the parasitic capacitance C _Q1 of the switching element Q1 will be accumulated, the parasitic capacitance C _Q1 is charged.

A waveform V _Q1 shown in FIG. 4 represents the drain-source voltage V _Q1 of the switch element Q1. By charging the parasitic capacitance C _Q1 of the switch element Q1 as described above, the drain-source voltage V _Q1 of the switch element Q1 rises like a waveform V _Q1 in the period from time t1 to time t2 in FIG. Along with this, the current _IQ1 that flows between the drain and source represented by the waveform _IQ1 in FIG. 4 decreases.

Further, while the current I _M is energized from the capacitor C3 to the input capacitor C1, a part I _m of the current I _M is shunted, and the current I _m passes through the parasitic diode D _Q2 of the switch element Q2 to the inductance L1. It is energized by the flowing path. By energization of the current I _m, the charge of the parasitic capacitance C _Q2 of the switching element Q2 discharges. As a result, the drain-source voltage V _Q2 of the switch element Q2 decreases as represented by the waveform V _Q2 in FIG. Note that a waveform _IQ2 in FIG. 4 represents the waveform of the current _IQ2 that flows between the drain and the source.

Thereafter, the switching element Q2 from the control circuit 24, the signal Q2 of the switching element Q2 in the ON state is applied (time t3), slightly current to energize the parasitic diode D _Q2 of the switching element Q2. When the drain-source voltage V _Q2 of the switch element Q2 is zero volts, the switch element Q2 is turned on. Thus, the switch element Q2 is switched to the on state, and the switch element Q3 is switched from the on state to the off state.

Thereafter, when the switch element Q2 is switched from the on state to the off state (time t4), both the switch elements Q1 and Q2 are turned off. Further, the switch element Q2 is switched to the off state, and the switch element Q3 is switched to the on state. At this time, the parasitic capacitance C _Q1 of the switching element Q1 is a state of charge electric charges are accumulated, the parasitic capacitance C _Q2 of the switching element Q2 is a state where no charge is stored.

By switching the switching elements Q2, Q3 as mentioned above, the input circuit 22 to the charging circuit 25, a current I _N, as represented in FIG. 6 is energized. That is, the current I _N is energized with a path back from the input capacitor C1 to the capacitor C2 → the diode D1 → switching element Q3 → the diode D4 → inductance L1 → switching element Q2 input capacitor C1 through the parasitic capacitance C _Q2 for. This by energization current I _N, the charge in the parasitic capacitance C _Q2 of the switching element Q2 will be accumulated, the parasitic capacitance C _Q2 is charged. As a result, the drain-source voltage V _Q2 of the switch element Q2 increases as represented by the waveform V _Q2 in the period from time t4 to time t5 in FIG. Along with this, the current IQ2 _flowing between the drain and the source represented by the waveform _IQ2 in FIG. 4 decreases.

Further, in the course of current _{I N} is energized inductance L1 in the parasitic capacitance C _Q2 of the switching element Q2, flow part _{I n} of the current _{I N} min, the current _{I n} is the parasitic diode D _Q1 of the switching element Q1 It is energized through a path through to the capacitor C2. By energization of the current I _n, the charge of the parasitic capacitance C _Q1 of the switching element Q1 is discharged. As a result, the drain-source voltage V _Q1 of the switch element Q1 decreases as shown in the period from time t4 to time t5 in FIG.

Thereafter, the switching element Q1 from the control circuit 24, the signal Q1 to the switching element Q1 in the ON state is applied (time t6), slightly current to energize the parasitic diode D _Q1 of the switching element Q1. When the drain-source voltage V _Q1 of the switch element Q1 is zero volts, the switch element Q1 is turned on. Thus, the switch element Q1 is switched to the on state, and the switch element Q3 can be switched from the on state to the off state.

The switching power supply circuit 20 of the second embodiment includes a charging circuit 25 for charging the parasitic capacitances C _Q1 and C _Q2 of the switch elements Q1 and Q2 that are controlled to be switched from the on state to the off state by the charging circuit 25. Can promote. That is, FIG. 7 shows a waveform example of the drain-source voltage V _Q1 corresponding to the charging voltage of the parasitic capacitance C _Q1 of the switch element _Q1 and the current I _Q1 energized between the drain and source. FIG. 7 also shows, as a comparative example, waveform examples of the drain-source voltage V _q1 of the switch element Q1 and the current I _q1 energized between the drain and source when the charging circuit 25 is not provided. Has been. As can be seen from the comparison of the waveforms V _Q1 and V _q1 in FIG. 7, when the switch element Q1 is switched from the on state to the off state (time t1), the charging circuit 25 causes the parasitic capacitance C _{Q1 of the} switch element Q1 to be switched. Is charged more rapidly than when the charging circuit 25 is not provided. As a result, when the switch element Q1 is switched from the on-state to the off-state, the conduction current _IQ1 between the drain and source of the switch element Q1 rapidly decreases. As a result, when the switching element Q1 is switched from the on state to the off state, the switching power supply circuit 20 generates a state in which the voltage V _Q1 is applied to the switching element Q1 and the current I _Q1 is energized. (See region P in FIG. 7). For this reason, the switching power supply circuit 20 of the second embodiment can suppress the switching loss due to the voltage V _q1 and the current I _q1 as represented by the hatching region M in FIG. 7 to be very small.

  The same applies to the case where the switch element Q2 is switched from the on state to the off state, and the switching power supply circuit 20 can suppress the switching loss in the switch element Q2 very small.

  Therefore, the switching power supply circuit 20 can suppress the switching loss of the switch elements Q1 and Q2, and can improve the circuit efficiency. Moreover, since the circuit configuration of the charging circuit 25 is simple, the switching power supply circuit 20 can obtain the effect that the switching loss as described above can be suppressed while suppressing a significant increase in the number of components. Furthermore, even if the charging circuit 25 is provided, the switching power supply circuit 20 realizes zero volt switching of the switching elements Q1 and Q2.

<Other embodiments>
In addition, this invention is not limited to 1st or 2nd embodiment, Various embodiment can be taken. For example, in the second embodiment, the charging circuit 25 includes a switch element Q3 and diodes D1 to D4. Instead, the charging circuit 25 may be configured by switching elements Q4 and Q5 as shown in FIG.

  In the charging circuit 25 shown in FIG. 8, the switch elements Q4 and Q5 are FET elements. The source side of the switch element Q4 is connected to one end side of the primary coil of the transformer 21, and the source side of the switch element Q5 is connected to the other end side of the primary coil of the transformer 21. Further, the drain sides of the switch elements Q4 and Q5 are connected to each other. The gates of the switch elements Q4 and Q5 are connected to the control circuit 24, respectively, and the switching operation of the switch elements Q4 and Q5 is controlled by the control circuit 24. For example, the control circuit 24 controls the switch elements Q4 and Q5 to turn on at the same timing as the switch element Q3 of the charging circuit 25 in the second embodiment is turned on. Further, the control circuit 24 controls the switch elements Q4 and Q5 so that the switch elements Q4 and Q5 are turned off at the same timing as the switch element Q3 of the charging circuit 25 in the second embodiment is turned off.

  Adopting the charging circuit 25 in FIG. 8 can reduce the number of elements constituting the charging circuit 25. Moreover, since it comprises not a diode but FET element, the charging circuit 25 can make conduction | electrical_connection loss smaller than the charging circuit 25 in 2nd Embodiment.

1,20 switching power supply circuit 3,4, Q1, Q2, Q3, Q4, Q5 switching element 5,24 control circuit 6,25 charging circuit 7,8, C _Q1 , C _Q2 parasitic capacitance

Claims (5)

Two switch elements connected in series;
A control circuit for controlling the switching operation of the switch element such that when one of the switch elements is turned off, the other is turned on;
A switching power supply circuit comprising: a charging circuit that promotes charging of a parasitic capacitance of the switch element that is controlled to be switched from an on state to an off state based on a control operation of the control circuit. A transformer,
Each of the switch elements is provided on the primary coil side of the transformer,
The charging circuit energizes a current through a path that passes through the charging circuit, the parasitic capacitance of the switch element that is controlled to be switched from an on state to an off state, and an input capacitor provided on the primary coil side of the transformer. 2. The switching power supply circuit according to claim 1, wherein charging of the parasitic capacitance of the switch element controlled to be switched to an off state is promoted using energy stored in the input capacitor.   When one of the two switching elements is controlled to be switched from an on state to an off state, the charging circuit includes a parasitic capacitance of the one switching element that is controlled to be switched to the off state, the input capacitor, By energizing a current through a path passing through the charging circuit and using the energy stored in the input capacitor, the charging of the parasitic capacitance of the one switching element controlled to be switched off is promoted and the other 3. The switching according to claim 2, wherein a current is passed through a parasitic diode of the other switch element to discharge a parasitic capacitance of the other switch element in a period until the switch element is switched from an off state to an on state. Power supply circuit.   The charging circuit is configured to include a switching element, and the switching of the switching element by the control circuit switches between conduction and non-conduction of the current path through the charging circuit. The switching power supply circuit according to claim 3. When one of the two switch elements connected in series is turned off, the control operation of the control circuit that controls the switching operation of the switch element is detected so that the other is turned on.
A switching loss suppression method for promoting charging of a parasitic capacitance of a switch element when it is detected that one of the switch elements is controlled to be switched from an on state to an off state.

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