JP2016144365A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2016144365A
JP2016144365A JP2015020368A JP2015020368A JP2016144365A JP 2016144365 A JP2016144365 A JP 2016144365A JP 2015020368 A JP2015020368 A JP 2015020368A JP 2015020368 A JP2015020368 A JP 2015020368A JP 2016144365 A JP2016144365 A JP 2016144365A
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conductive portion
electrically connected
conductive
terminal
semiconductor device
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JP6352200B2 (en
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悦宏 神山
Netsuhiro Kamiyama
悦宏 神山
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Shindengen Electric Manufacturing Co Ltd
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Shindengen Electric Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a small wiring resistance, thereby having high efficiency.SOLUTION: A semiconductor device 100 for converting DC power into AC power is provided that comprises: a conductive part 1 electrically connected to a power terminal VDD and extending to a first direction; a conductive part 2 electrically connected to a ground terminal GND and extending to the first direction; a plurality of conductive parts 3 disposed between the conductive part 1 and the conductive part 2 and arrayed in the first direction; a plurality of high side switches 11, 12, 13, mounted on the conductive part 1 along the first direction, each having one end electrically connected to the conductive part 1; and a plurality of low side switches 14, 15, 16 each mounted on each of the conductive parts 3 and having one end electrically connected to the other end of each high side switch, and the other end electrically connected to the conductive part 2.SELECTED DRAWING: Figure 1

Description

本発明は、半導体装置、より詳しくは、直流電力を交流電力に変換する半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device that converts DC power into AC power.

従来、半導体装置の一つとして、直流電源から入力した直流電力を交流電力に変換して出力するインバータ装置が知られている。このインバータ装置は、例えば、直流電圧を３相の交流電圧に変換し、３相モータを駆動するために用いられる。このような半導体装置に対しては、近年、ますます小型化および高効率化が求められている。   2. Description of the Related Art Conventionally, as one of semiconductor devices, an inverter device that converts DC power input from a DC power source into AC power and outputs it is known. This inverter device is used, for example, to convert a DC voltage into a three-phase AC voltage and drive a three-phase motor. In recent years, such semiconductor devices are increasingly required to be smaller and more efficient.

特許文献１には、制御用端子と、電源端子およびグランド端子とを離間させることで、損失やノイズの低減を図った半導体装置（パワーモジュール）が記載されている。   Patent Document 1 describes a semiconductor device (power module) in which loss and noise are reduced by separating a control terminal from a power supply terminal and a ground terminal.

特開２０１４−７２３１６号公報JP 2014-72316 A

しかしながら、特許文献１に記載の半導体装置では、電源端子に電気的に接続された電源ブロックと、グランドに接続されるグランドブロックとが隣接して配置されているため、電流経路が長くなって配線抵抗が大きくなり、その結果、効率が低下するという問題がある。そこで、本発明は、配線抵抗が小さく、高効率な半導体装置を提供することを目的とする。   However, in the semiconductor device described in Patent Document 1, since the power supply block electrically connected to the power supply terminal and the ground block connected to the ground are disposed adjacent to each other, the current path becomes long and the wiring is performed. There is a problem that the resistance increases and as a result, the efficiency decreases. Therefore, an object of the present invention is to provide a highly efficient semiconductor device with low wiring resistance.

本発明の一態様に係る半導体装置は、
直流電力を交流電力に変換する半導体装置であって、
電源端子に電気的に接続され、第１の方向に延在する第１の導電部と、
グランド端子に電気的に接続され、前記第１の方向に延在する第２の導電部と、
前記第１の導電部と前記第２の導電部との間に配置され、前記第１の方向に並ぶ複数の第３の導電部と、
前記第１の方向に沿って前記第１の導電部上に実装され、一端が前記第１の導電部に電気的に接続された複数のハイサイドスイッチと、
前記第３の導電部の各々の上に実装され、前記ハイサイドスイッチの他端に一端が電気的に接続され且つ前記第２の導電部に他端が電気的に接続された複数のローサイドスイッチと、
を備えることを特徴とする。
また、前記半導体装置において、
前記複数の第３の導電部との間に前記第１の導電部が位置するように前記第１の方向に沿って配列され、前記ハイサイドスイッチまたは前記ローサイドスイッチを制御するための複数の制御端子と、
前記複数の第３の導電部との間に前記第２の導電部が位置するように前記第１の方向に沿って配列され、前記ハイサイドスイッチの前記他端および前記ローサイドスイッチの前記一端に電気的に接続された複数の出力端子と、
をさらに備えてもよい。 A semiconductor device according to one embodiment of the present invention includes:
A semiconductor device that converts DC power into AC power,
A first conductive portion electrically connected to the power supply terminal and extending in the first direction;
A second conductive portion electrically connected to a ground terminal and extending in the first direction;
A plurality of third conductive portions arranged between the first conductive portion and the second conductive portion and arranged in the first direction;
A plurality of high-side switches mounted on the first conductive portion along the first direction and having one end electrically connected to the first conductive portion;
A plurality of low-side switches mounted on each of the third conductive portions, one end of which is electrically connected to the other end of the high-side switch and the other end of which is electrically connected to the second conductive portion. When,
It is characterized by providing.
In the semiconductor device,
Plural controls for controlling the high-side switch or the low-side switch, arranged along the first direction so that the first conductive portion is located between the plurality of third conductive portions. A terminal,
Arranged along the first direction so that the second conductive portion is positioned between the plurality of third conductive portions, and the other end of the high-side switch and the one end of the low-side switch A plurality of electrically connected output terminals;
May be further provided.

また、前記半導体装置において、
前記電源端子および前記グランド端子は、前記複数の出力端子と並んで設けられているようにしてもよい。 In the semiconductor device,
The power supply terminal and the ground terminal may be provided side by side with the plurality of output terminals.

また、前記半導体装置において、
前記第２の導電部と前記第３の導電部との間に配置され、前記第１の方向に並ぶ複数の第４の導電部と、
前記第４の導電部の各々の上に実装され、一端が前記第３の導電部を介して前記ハイサイドスイッチの前記他端および前記ローサイドスイッチの前記一端に電気的に接続され、他端が前記出力端子に電気的に接続された複数の出力制御スイッチと、
をさらに備え、
前記出力制御スイッチの制御端子は、前記制御端子と並んで設けられていてもよい。 In the semiconductor device,
A plurality of fourth conductive portions arranged between the second conductive portion and the third conductive portion and arranged in the first direction;
Mounted on each of the fourth conductive portions, one end is electrically connected to the other end of the high-side switch and the one end of the low-side switch via the third conductive portion, and the other end is A plurality of output control switches electrically connected to the output terminal;
Further comprising
The control terminal of the output control switch may be provided along with the control terminal.

また、前記半導体装置において、
前記第２の導電部と前記第３の導電部との間に前記第４の導電部と隣り合うように配置され、前記ローサイドスイッチの前記他端と前記第２の導電部とを電気的に接続する複数の第５の導電部をさらに備えてもよい。 In the semiconductor device,
The second conductive portion is disposed between the second conductive portion and the third conductive portion so as to be adjacent to the fourth conductive portion, and electrically connects the other end of the low-side switch and the second conductive portion. A plurality of fifth conductive parts to be connected may be further provided.

また、前記半導体装置において、
一端が前記第５の導電部に接続され、他端が前記第２の導電部に接続されたシャント抵抗と、
前記シャント抵抗の前記一端に電気的に接続された第１の電流検出端子と、
前記シャント抵抗の前記他端に電気的に接続された第２の電流検出端子と、をさらに備え、
前記第１および第２の電流検出端子は、前記ハイサイドスイッチまたは前記ローサイドスイッチの制御端子と、前記出力制御スイッチの制御端子との間に設けられていてもよい。 In the semiconductor device,
A shunt resistor having one end connected to the fifth conductive portion and the other end connected to the second conductive portion;
A first current detection terminal electrically connected to the one end of the shunt resistor;
A second current detection terminal electrically connected to the other end of the shunt resistor,
The first and second current detection terminals may be provided between a control terminal of the high side switch or the low side switch and a control terminal of the output control switch.

また、前記半導体装置において、
隣接する前記第３の導電部間、および隣接する前記第５の導体部と前記第４の導体部間を延在するように設けられ、前記シャント抵抗の前記一端と前記第１の電流検出端子とを電気的に接続する第１の接続配線と、
前記第１の接続配線に並んで延在するように設けられ、前記シャント抵抗の前記他端と前記第２の電流検出端子とを電気的に接続する第２の接続配線と、
をさらに備えてもよい。 In the semiconductor device,
The one end of the shunt resistor and the first current detection terminal are provided so as to extend between the adjacent third conductive portions and between the adjacent fifth conductor portion and the fourth conductor portion. A first connection wiring for electrically connecting
A second connection wiring provided so as to extend alongside the first connection wiring and electrically connecting the other end of the shunt resistor and the second current detection terminal;
May be further provided.

本発明に係る半導体装置では、電源端子に電気的に接続され、複数のハイサイドスイッチが実装され、第１の方向に延在する第１の導電部と、グランド端子に電気的に接続され、第１の方向に延在する第２の導電部と、第１の導電部と第２の導電部との間に配置され、複数のローサイドスイッチが実装された複数の第３の導電部とを備えている。これにより、配線抵抗が小さく、高効率な半導体装置を提供することができる。   In the semiconductor device according to the present invention, the plurality of high-side switches are electrically connected to the power supply terminal, and are electrically connected to the first conductive portion extending in the first direction and the ground terminal, A second conductive portion extending in the first direction, and a plurality of third conductive portions disposed between the first conductive portion and the second conductive portion and mounted with a plurality of low-side switches. I have. Thereby, a highly efficient semiconductor device with low wiring resistance can be provided.

本発明の実施形態に係る半導体装置１００の平面図である。1 is a plan view of a semiconductor device 100 according to an embodiment of the present invention. 本発明の実施形態に係る半導体装置１００の回路図である。1 is a circuit diagram of a semiconductor device 100 according to an embodiment of the present invention.

以下、図面を参照しつつ本発明の実施形態に係る半導体装置について説明する。   A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

本発明の実施形態に係る半導体装置１００は、図１および図２に示すように、直流電源（図示せず）から入力した直流電力を３相の交流電力に変換して出力する半導体装置（インバータ装置）である。この半導体装置１００は、セラミック基板等の絶縁基板１０と、三相フルブリッジ回路を構成するハイサイドスイッチ１１，１２，１３およびローサイドスイッチ１４，１５，１６等の電子部品とが封止樹脂５０により封止されたものとして構成されている。   As shown in FIGS. 1 and 2, a semiconductor device 100 according to an embodiment of the present invention converts a DC power input from a DC power supply (not shown) into a three-phase AC power and outputs the semiconductor device (inverter). Device). In this semiconductor device 100, an insulating substrate 10 such as a ceramic substrate and electronic components such as high-side switches 11, 12, 13 and low-side switches 14, 15, 16 constituting a three-phase full bridge circuit are formed by a sealing resin 50. It is comprised as what was sealed.

より詳しくは、半導体装置１００は、図１に示すように、絶縁基板１０と、導電部１（第１の導電部）と、導電部２（第２の導電部）と、複数の導電部３（第３の導電部）と、複数の導電部４（第４の導電部）と、複数の導電部５（第５の導電部）と、導電部６（第６の導電部）と、ハイサイドスイッチ１１，１２，１３と、ローサイドスイッチ１４，１５，１６と、出力制御スイッチ１７，１８，１９と、制御端子２１〜２９と、シャント抵抗３０ａ，３０ｂ，３０ｃと、電流検出端子３１〜３６と、接続配線４１，４２と、封止樹脂５０と、モニタ端子５１〜５３と、電源端子ＶＤＤと、グランド端子ＧＮＤと、出力端子ＯＵＴ１〜３と、を備えている。以下、半導体装置１００の各構成要素について詳しく説明する。   More specifically, as shown in FIG. 1, the semiconductor device 100 includes an insulating substrate 10, a conductive portion 1 (first conductive portion), a conductive portion 2 (second conductive portion), and a plurality of conductive portions 3. (Third conductive portion), a plurality of conductive portions 4 (fourth conductive portion), a plurality of conductive portions 5 (fifth conductive portion), a conductive portion 6 (sixth conductive portion), and a high Side switches 11, 12, 13, low-side switches 14, 15, 16, output control switches 17, 18, 19, control terminals 21-29, shunt resistors 30a, 30b, 30c, and current detection terminals 31-36 Connection wires 41 and 42, sealing resin 50, monitor terminals 51 to 53, a power supply terminal VDD, a ground terminal GND, and output terminals OUT1 to OUT3. Hereinafter, each component of the semiconductor device 100 will be described in detail.

ハイサイドスイッチ１１，１２，１３の下面、上面および側面には、ドレイン電極、ソース電極およびゲート電極１１ａ，１２ａ，１３ａがそれぞれ設けられている。同様に、ローサイドスイッチ１４，１５，１６の下面、上面および側面には、ドレイン電極、ソース電極およびゲート電極１４ａ，１５ａ，１６ａがそれぞれ設けられている。出力制御スイッチ１７，１８，１９の下面、上面および側面には、ドレイン電極、ソース電極およびゲート電極１７ａ，１８ａ，１９ａがそれぞれ設けられている。   A drain electrode, a source electrode, and gate electrodes 11a, 12a, and 13a are provided on the lower surface, upper surface, and side surfaces of the high-side switches 11, 12, and 13, respectively. Similarly, a drain electrode, a source electrode, and gate electrodes 14a, 15a, and 16a are provided on the lower surface, the upper surface, and the side surfaces of the low-side switches 14, 15, and 16, respectively. Drain electrodes, source electrodes, and gate electrodes 17a, 18a, and 19a are provided on the lower surface, upper surface, and side surfaces of the output control switches 17, 18, and 19, respectively.

なお、ハイサイドスイッチ１１〜１３、ローサイドスイッチ１４〜１６、出力制御スイッチ１７，１８，１９は、例えばパワーＭＯＳＦＥＴであるが、ＩＧＢＴ等の他の半導体スイッチング素子であってもよい。   The high side switches 11 to 13, the low side switches 14 to 16, and the output control switches 17, 18, and 19 are, for example, power MOSFETs, but may be other semiconductor switching elements such as IGBTs.

導電部１〜６は、絶縁基板１０上に設けられた導電パターンである。この導電部１〜６は、銅、アルミ等の金属層からなる。図１に示すように、導電部１は、電源端子ＶＤＤに電気的に接続され、第１の方向（図１において横方向）に延在している。より詳しくは、導電部１は、導電部６を介して電源端子ＶＤＤに電気的に接続されている。導電部６は、第１の方向に直交する第２の方向（図１において縦方向）に延在している。   The conductive portions 1 to 6 are conductive patterns provided on the insulating substrate 10. The conductive portions 1 to 6 are made of a metal layer such as copper or aluminum. As shown in FIG. 1, the conductive portion 1 is electrically connected to the power supply terminal VDD and extends in the first direction (lateral direction in FIG. 1). More specifically, the conductive portion 1 is electrically connected to the power supply terminal VDD via the conductive portion 6. The conductive portion 6 extends in a second direction (vertical direction in FIG. 1) orthogonal to the first direction.

導電部１上には、図１に示すように、ハイサイドスイッチ１１，１２，１３が第１の方向に沿って配置されている。ハイサイドスイッチ１１，１２，１３は、一端（ドレイン電極）が導電部１に電気的に接続されるように導電部１上に実装されている。   As shown in FIG. 1, high-side switches 11, 12, and 13 are disposed on the conductive portion 1 along the first direction. The high-side switches 11, 12, and 13 are mounted on the conductive portion 1 so that one end (drain electrode) is electrically connected to the conductive portion 1.

ハイサイドスイッチ１１，１２，１３の他端（ソース電極）は、導線７０により導電部３に電気的に接続されている。また、ハイサイドスイッチ１１，１２，１３のゲート電極１１ａ，１２ａ，１３ａは、導線７０により制御端子２１〜２３にそれぞれ電気的に接続されている。   The other ends (source electrodes) of the high side switches 11, 12, and 13 are electrically connected to the conductive portion 3 by a conductive wire 70. The gate electrodes 11 a, 12 a, and 13 a of the high-side switches 11, 12, and 13 are electrically connected to the control terminals 21 to 23 by conducting wires 70, respectively.

導電部２は、図１に示すように、グランド端子ＧＮＤに電気的に接続され、第１の方向（図１において横方向）に延在している。この導電部２は、導電部１に対して、第１の方向に直交する第２の方向に配置されている。   As shown in FIG. 1, the conductive portion 2 is electrically connected to the ground terminal GND, and extends in the first direction (lateral direction in FIG. 1). The conductive portion 2 is disposed in a second direction orthogonal to the first direction with respect to the conductive portion 1.

このように、導電部１と導電部２は略平行に離間して設けられており、導電部１と導電部２との間には導電部３〜５が配置されている。図１に示すように、導電部３の各々は、第１の方向に並んでいる。また、導電部４の各々は、導電部２と導電部３との間に配置され、第１の方向に並んでいる。導電部５の各々は、導電部２と導電部３との間に導電部４と隣り合うように設けられている。   As described above, the conductive portion 1 and the conductive portion 2 are provided so as to be separated from each other substantially in parallel, and the conductive portions 3 to 5 are disposed between the conductive portion 1 and the conductive portion 2. As shown in FIG. 1, each of the conductive portions 3 is aligned in the first direction. In addition, each of the conductive parts 4 is disposed between the conductive part 2 and the conductive part 3 and is arranged in the first direction. Each of the conductive parts 5 is provided between the conductive part 2 and the conductive part 3 so as to be adjacent to the conductive part 4.

導電部３の各々には、ローサイドスイッチ１４，１５，１６がそれぞれ配置されている。ローサイドスイッチ１４，１５，１６は、一端（ドレイン電極）が導電部３に電気的に接続されるように導電部３上に実装されている。これにより、ローサイドスイッチ１４，１５，１６のドレイン電極は、ハイサイドスイッチ１１，１２，１３のソース電極に電気的に接続される。   Low-side switches 14, 15, and 16 are disposed in each of the conductive portions 3. The low-side switches 14, 15, and 16 are mounted on the conductive portion 3 so that one end (drain electrode) is electrically connected to the conductive portion 3. As a result, the drain electrodes of the low-side switches 14, 15, 16 are electrically connected to the source electrodes of the high-side switches 11, 12, 13.

ローサイドスイッチ１４，１５，１６の他端（ソース電極）は、導線７０により導電部５に電気的に接続されている。導電部５はシャント抵抗３０ａ，３０ｂ，３０ｃにより導電部２に電気的に接続されているため、ローサイドスイッチ１４，１５，１６のソース電極は導電部２に電気的に接続される。シャント抵抗３０ａ，３０ｂ，３０ｃは、一端が導電部５に接続され、他端が導電部２に接続されている。ローサイドスイッチ１４，１５，１６のゲート電極１４ａ，１５ａ，１６ａは、導線７０により制御端子２４〜２６にそれぞれ電気的に接続されている。   The other ends (source electrodes) of the low-side switches 14, 15, 16 are electrically connected to the conductive portion 5 by a conductive wire 70. Since the conductive portion 5 is electrically connected to the conductive portion 2 by the shunt resistors 30a, 30b, and 30c, the source electrodes of the low-side switches 14, 15, and 16 are electrically connected to the conductive portion 2. The shunt resistors 30 a, 30 b, and 30 c have one end connected to the conductive portion 5 and the other end connected to the conductive portion 2. The gate electrodes 14 a, 15 a, 16 a of the low side switches 14, 15, 16 are electrically connected to the control terminals 24 to 26 by conducting wires 70, respectively.

導電部４の各々には、出力制御スイッチ１７，１８，１９がそれぞれ配置されている。出力制御スイッチ１７，１８，１９は、半導体装置１００の出力（交流電力の出力）を制御するためのスイッチである。出力制御スイッチ１７，１８，１９の一端（ソース電極）は導線７０により導電部３に電気的に接続されている。これにより、出力制御スイッチ１７，１８，１９のソース電極は、導電部３を介してハイサイドスイッチ１１，１２，１３のソース電極と、ローサイドスイッチ１４，１５，１６のドレイン電極とに電気的に接続される。   Output control switches 17, 18, and 19 are disposed in each of the conductive portions 4. The output control switches 17, 18, and 19 are switches for controlling the output (output of AC power) of the semiconductor device 100. One end (source electrode) of the output control switches 17, 18, 19 is electrically connected to the conductive portion 3 by a conductive wire 70. As a result, the source electrodes of the output control switches 17, 18, 19 are electrically connected to the source electrodes of the high-side switches 11, 12, 13 and the drain electrodes of the low-side switches 14, 15, 16 via the conductive part 3. Connected.

出力制御スイッチ１７，１８，１９は、他端（ドレイン電極）が導電部４に電気的に接続されるように導電部４上に実装されている。導電部４の各々には、図１に示すように、出力端子ＯＵＴ１〜３がそれぞれ接続されている。よって、出力制御スイッチ１７，１８，１９のドレイン電極は、出力端子ＯＵＴ１〜３にそれぞれ電気的に接続される。   The output control switches 17, 18, and 19 are mounted on the conductive portion 4 so that the other end (drain electrode) is electrically connected to the conductive portion 4. As shown in FIG. 1, output terminals OUT <b> 1 to OUT <b> 3 are connected to each of the conductive parts 4. Therefore, the drain electrodes of the output control switches 17, 18, and 19 are electrically connected to the output terminals OUT1 to OUT3, respectively.

出力制御スイッチ１７，１８，１９のゲート電極１７ａ，１８ａ，１９ａは、図１に示すように、制御端子２７〜２９にそれぞれ導線７０により電気的に接続されている。   As shown in FIG. 1, the gate electrodes 17a, 18a, 19a of the output control switches 17, 18, 19 are electrically connected to the control terminals 27-29 by conducting wires 70, respectively.

導電部５は、前述のように、ローサイドスイッチ１４，１５，１６のソース電極と導電部２とを電気的に接続する。   As described above, the conductive part 5 electrically connects the source electrodes of the low-side switches 14, 15, 16 and the conductive part 2.

図１に示すように、絶縁基板１０上には、上記の導電部１〜６に加えて、接続配線４１，４２が設けられている。接続配線４１は、シャント抵抗３０ａの一端と電流検出端子３１（第１の電流検出端子）とを電気的に接続する。接続配線４２は、シャント抵抗３０ａの他端と電流検出端子３２（第２の電流検出端子）とを電気的に接続する。接続配線４２（第２の接続配線）は、接続配線４１に並んで延在するように設けられている。接続配線４１，４２（第１の接続配線）は、図１に示すように、隣接する導電部３間、および隣接する導体部５と導体部４間を第２の方向（図１において縦方向）に延在するように設けられている。これにより、絶縁基板１０の面積の増加を可及的に抑制しつつ、シャント抵抗と電流検出端子とを電気的に接続することができる。   As shown in FIG. 1, connection wirings 41 and 42 are provided on the insulating substrate 10 in addition to the conductive portions 1 to 6. The connection wiring 41 electrically connects one end of the shunt resistor 30a and the current detection terminal 31 (first current detection terminal). The connection wiring 42 electrically connects the other end of the shunt resistor 30a and the current detection terminal 32 (second current detection terminal). The connection wiring 42 (second connection wiring) is provided so as to extend alongside the connection wiring 41. As shown in FIG. 1, the connection wires 41 and 42 (first connection wires) are arranged between the adjacent conductive portions 3 and between the adjacent conductor portions 5 and 4 in the second direction (vertical direction in FIG. 1). ) To extend. Accordingly, the shunt resistor and the current detection terminal can be electrically connected while suppressing an increase in the area of the insulating substrate 10 as much as possible.

コンデンサ６０は、図１および図２に示すように、一端が電源端子ＶＤＤに電気的に接続され、他端がグランド端子ＧＮＤに電気的に接続されている。   As shown in FIGS. 1 and 2, the capacitor 60 has one end electrically connected to the power supply terminal VDD and the other end electrically connected to the ground terminal GND.

次に、半導体装置１００の各種端子について説明する。図１に示すように、制御端子２１〜２９、電流検出端子３１〜３６およびモニタ端子５１〜５３は、絶縁基板１０の一端側に第１の方向（図１では横方向）に並んで配置されている。   Next, various terminals of the semiconductor device 100 will be described. As shown in FIG. 1, the control terminals 21 to 29, the current detection terminals 31 to 36, and the monitor terminals 51 to 53 are arranged side by side in a first direction (lateral direction in FIG. 1) on one end side of the insulating substrate 10. ing.

制御端子２１〜２３は、ハイサイドスイッチ１１〜１３をオン／オフ制御するための端子であり、制御端子２４〜２６は、ローサイドスイッチ１４〜１６をオン／オフ制御するための端子である。制御端子２１〜２６と制御端子２７〜２９とは並んで設けられている。   The control terminals 21 to 23 are terminals for on / off control of the high side switches 11 to 13, and the control terminals 24 to 26 are terminals for on / off control of the low side switches 14 to 16. The control terminals 21 to 26 and the control terminals 27 to 29 are provided side by side.

制御端子２７〜２９は、出力制御スイッチ１７〜１９をオン／オフ制御するための端子である。この制御端子２７〜２９は、導電部１を挟んで複数の導電部３の反対側に設けられている。即ち、制御端子２７〜２９は、それら制御端子２７〜２９と複数の導電部３との間に導電部１が位置するように第１の方向に沿って配列されている。   The control terminals 27 to 29 are terminals for performing on / off control of the output control switches 17 to 19. The control terminals 27 to 29 are provided on the opposite side of the plurality of conductive parts 3 with the conductive part 1 interposed therebetween. That is, the control terminals 27 to 29 are arranged along the first direction so that the conductive portion 1 is located between the control terminals 27 to 29 and the plurality of conductive portions 3.

電流検出端子３１〜３６は、各相のスイッチを流れる電流を検出するための端子である。図１に示すように、電流検出端子３１は、接続配線４１を介してシャント抵抗３０ａの一端に電気的に接続されている。また、電流検出端子３２は、接続配線４２を介してシャント抵抗３０ａの他端に電気的に接続されている。電流検出端子３１，３２は、ハイサイドスイッチ１１の制御端子２１（ローサイドスイッチ１４の制御端子２４）と、出力制御スイッチ１８の制御端子２８との間に設けられている。同様に、電流検出端子３３，３４は、ハイサイドスイッチ１２の制御端子２２（ローサイドスイッチ１５の制御端子２５）と、出力制御スイッチ１９の制御端子２９との間に設けられている。   The current detection terminals 31 to 36 are terminals for detecting a current flowing through each phase switch. As shown in FIG. 1, the current detection terminal 31 is electrically connected to one end of the shunt resistor 30 a via the connection wiring 41. Further, the current detection terminal 32 is electrically connected to the other end of the shunt resistor 30a through the connection wiring 42. The current detection terminals 31 and 32 are provided between the control terminal 21 of the high side switch 11 (control terminal 24 of the low side switch 14) and the control terminal 28 of the output control switch 18. Similarly, the current detection terminals 33 and 34 are provided between the control terminal 22 of the high side switch 12 (control terminal 25 of the low side switch 15) and the control terminal 29 of the output control switch 19.

電流検出端子３１と電流検出端子３２を用いて、ハイサイドスイッチ１１およびローサイドスイッチ１４を流れる電流値を検出する。具体的には、電流検出端子３１の電圧と電流検出端子３２の電圧を測定し、その差の電圧値をシャント抵抗３０ａの抵抗値で割ることにより、ハイサイドスイッチ１１およびローサイドスイッチ１４を流れる電流値が求められる。同様に、電流検出端子３３，３４の電圧を用いてハイサイドスイッチ１２およびローサイドスイッチ１５を流れる電流値が求められ、電流検出端子３５，３６の電圧を用いてハイサイドスイッチ１３およびローサイドスイッチ１６を流れる電流値が求められる。   The current detection terminal 31 and the current detection terminal 32 are used to detect the current value flowing through the high side switch 11 and the low side switch 14. Specifically, the current flowing through the high-side switch 11 and the low-side switch 14 is measured by measuring the voltage at the current detection terminal 31 and the voltage at the current detection terminal 32 and dividing the voltage value of the difference by the resistance value of the shunt resistor 30a. A value is determined. Similarly, the current values flowing through the high-side switch 12 and the low-side switch 15 are obtained using the voltages at the current detection terminals 33 and 34, and the high-side switch 13 and the low-side switch 16 are switched using the voltages at the current detection terminals 35 and 36. The flowing current value is obtained.

モニタ端子５１〜５３は、各相の出力電圧をモニタするための端子である。図１および図２に示すように、モニタ端子５１は出力制御スイッチ１７のソース電極に接続され、モニタ端子５２は出力制御スイッチ１８のソース電極に接続され、モニタ端子５３は出力制御スイッチ１９のソース電極に接続されている。   The monitor terminals 51 to 53 are terminals for monitoring the output voltage of each phase. As shown in FIGS. 1 and 2, the monitor terminal 51 is connected to the source electrode of the output control switch 17, the monitor terminal 52 is connected to the source electrode of the output control switch 18, and the monitor terminal 53 is the source of the output control switch 19. Connected to the electrode.

電源端子ＶＤＤ、グランド端子ＧＮＤおよび出力端子ＯＵＴ１〜３は、図１に示すように、絶縁基板１０の他端側に第１の方向に並んで配置されている。   The power supply terminal VDD, the ground terminal GND, and the output terminals OUT1 to OUT3 are arranged side by side in the first direction on the other end side of the insulating substrate 10, as shown in FIG.

上記のように、絶縁基板１０の一端側に、制御端子２１〜２９、電流検出端子３１〜３６およびモニタ端子５１〜５３が第１の方向に並んで配置され、絶縁基板１０の他端側に、電源端子ＶＤＤ、グランド端子ＧＮＤおよび出力端子ＯＵＴ１〜３が第１の方向に並んで配置されている。このように、本実施形態では、小さいが本数の多い制御端子等と、大きいが本数の少ない出力端子等とを、絶縁基板１０の一端側および他端側にそれぞれ配置している。これにより、半導体装置１００の小型化を図ることができる。   As described above, the control terminals 21 to 29, the current detection terminals 31 to 36, and the monitor terminals 51 to 53 are arranged side by side in the first direction on one end side of the insulating substrate 10, and on the other end side of the insulating substrate 10. The power terminal VDD, the ground terminal GND, and the output terminals OUT1 to OUT3 are arranged side by side in the first direction. As described above, in the present embodiment, a small but large number of control terminals and the like, and a large but small number of output terminals and the like are arranged on one end side and the other end side of the insulating substrate 10, respectively. As a result, the semiconductor device 100 can be reduced in size.

電源端子およびグランド端子が１本の端子で構成され且つ一方向に配列されているため、半導体装置の小型化を図ることができる。   Since the power supply terminal and the ground terminal are configured by one terminal and arranged in one direction, the semiconductor device can be reduced in size.

電源端子ＶＤＤは直流電源に接続するための端子であり、グランド端子ＧＮＤは接地用の端子である。出力端子ＯＵＴ１〜３は、三相交流を出力するための端子である。出力端子ＯＵＴ１は、図２に示すように、出力制御スイッチ１７を介して、ハイサイドスイッチ１１のソース電極およびローサイドスイッチ１４のドレイン電極に電気的に接続されている。同様に、出力端子ＯＵＴ２は、出力制御スイッチ１８を介して、ハイサイドスイッチ１２のソース電極およびローサイドスイッチ１５のドレイン電極に電気的に接続されている。出力端子ＯＵＴ３は、出力制御スイッチ１９を介して、ハイサイドスイッチ１３のソース電極およびローサイドスイッチ１６のドレイン電極に電気的に接続されている。   The power supply terminal VDD is a terminal for connecting to a DC power supply, and the ground terminal GND is a grounding terminal. The output terminals OUT1 to OUT3 are terminals for outputting a three-phase alternating current. As shown in FIG. 2, the output terminal OUT <b> 1 is electrically connected to the source electrode of the high side switch 11 and the drain electrode of the low side switch 14 via the output control switch 17. Similarly, the output terminal OUT <b> 2 is electrically connected to the source electrode of the high side switch 12 and the drain electrode of the low side switch 15 via the output control switch 18. The output terminal OUT3 is electrically connected to the source electrode of the high side switch 13 and the drain electrode of the low side switch 16 via the output control switch 19.

図１に示すように、電源端子ＶＤＤおよびグランド端子ＧＮＤは、出力端子ＯＵＴ１〜３と並んで設けられている。電源端子ＶＤＤ、グランド端子ＧＮＤおよび出力端子ＯＵＴ１〜３は、導電部２を挟んで導電部３の反対側に第１の方向に沿って設けられている。即ち、電源端子ＶＤＤ、グランド端子ＧＮＤおよび出力端子ＯＵＴ１〜３は、これらの端子ＶＤＤ，ＧＮＤ，ＯＵＴ１〜３と複数の導電部３との間に導電部２が位置するように第１の方向に沿って配列されている。   As shown in FIG. 1, the power supply terminal VDD and the ground terminal GND are provided along with the output terminals OUT1 to OUT3. The power supply terminal VDD, the ground terminal GND, and the output terminals OUT1 to OUT3 are provided along the first direction on the opposite side of the conductive portion 3 with the conductive portion 2 interposed therebetween. That is, the power supply terminal VDD, the ground terminal GND, and the output terminals OUT1 to OUT3 are arranged in the first direction so that the conductive part 2 is positioned between the terminals VDD, GND, OUT1 to 3 and the plurality of conductive parts 3. Are arranged along.

上記のように、本実施形態に係る半導体装置１００では、電源端子ＶＤＤに電気的に接続され、第１の方向に延在する導電部１と、グランド端子ＧＮＤに電気的に接続され、第１の方向に延在する導電部２と、導電部１と導電部２との間に配置された複数の導電部３とを備えている。即ち、電源端子ＶＤＤに接続された導電部１と、グランド端子ＧＮＤに接続された導電部２とは導電部３を挟んで離間して配置されている。また、導電部１にハイサイドスイッチ１１〜１３が実装され、導電部３にローサイドスイッチ１４〜１６が実装されている。これにより、導電部１および導電部２の第１の方向の長さや、ハイサイドスイッチ１１〜１３とローサイドスイッチ１４〜１６間の配線長を短くすることができる。よって、本実施形態によれば、配線抵抗が小さく、高効率な半導体装置を提供することができる。   As described above, in the semiconductor device 100 according to the present embodiment, the first conductive portion 1 that is electrically connected to the power supply terminal VDD, extends in the first direction, and is electrically connected to the ground terminal GND. And a plurality of conductive parts 3 disposed between the conductive part 1 and the conductive part 2. In other words, the conductive portion 1 connected to the power supply terminal VDD and the conductive portion 2 connected to the ground terminal GND are spaced apart with the conductive portion 3 interposed therebetween. In addition, high-side switches 11 to 13 are mounted on the conductive portion 1, and low-side switches 14 to 16 are mounted on the conductive portion 3. Thereby, the length in the 1st direction of the electroconductive part 1 and the electroconductive part 2, and the wiring length between the high side switches 11-13 and the low side switches 14-16 can be shortened. Therefore, according to the present embodiment, a highly efficient semiconductor device with low wiring resistance can be provided.

上記の記載に基づいて、当業者であれば、本発明の追加の効果や種々の変形を想到できるかもしれないが、本発明の態様は、上述した個々の実施形態に限定されるものではない。異なる実施形態にわたる構成要素を適宜組み合わせてもよい。特許請求の範囲に規定された内容及びその均等物から導き出される本発明の概念的な思想と趣旨を逸脱しない範囲で種々の追加、変更及び部分的削除が可能である。   Based on the above description, those skilled in the art may be able to conceive additional effects and various modifications of the present invention, but the aspects of the present invention are not limited to the individual embodiments described above. . You may combine suitably the component covering different embodiment. Various additions, modifications, and partial deletions can be made without departing from the concept and spirit of the present invention derived from the contents defined in the claims and equivalents thereof.

１〜６ 導電部
１０ 絶縁基板
１１，１２，１３ ハイサイドスイッチ
１１ａ，１２ａ，１３ａ ゲート電極
１４，１５，１６ ローサイドスイッチ
１４ａ，１５ａ，１６ａ ゲート電極
１７，１８，１９ 出力制御スイッチ
１７ａ，１８ａ，１９ａ ゲート電極
２１〜２９ 制御端子
３０ａ，３０ｂ，３０ｃ シャント抵抗
３１〜３６ 電流検出端子
４１，４２ 接続配線
５０ 封止樹脂
５１，５２，５３ モニタ端子
６０ コンデンサ
７０ 導線
１００ 半導体装置
ＶＤＤ 電源端子
ＧＮＤ グランド端子
ＯＵＴ１〜３ 出力端子 1-6 Conductive part 10 Insulating substrate 11, 12, 13 High side switches 11a, 12a, 13a Gate electrodes 14, 15, 16 Low side switches 14a, 15a, 16a Gate electrodes 17, 18, 19 Output control switches 17a, 18a, 19a Gate electrodes 21-29 Control terminals 30a, 30b, 30c Shunt resistors 31-36 Current detection terminals 41, 42 Connection wiring 50 Sealing resin 51, 52, 53 Monitor terminal 60 Capacitor 70 Conductor 100 Semiconductor device VDD Power supply terminal GND Ground terminal OUT1 ~ 3 Output terminal

Claims (7)

直流電力を交流電力に変換する半導体装置であって、
電源端子に電気的に接続され、第１の方向に延在する第１の導電部と、
グランド端子に電気的に接続され、前記第１の方向に延在する第２の導電部と、
前記第１の導電部と前記第２の導電部との間に配置され、前記第１の方向に並ぶ複数の第３の導電部と、
前記第１の方向に沿って前記第１の導電部上に実装され、一端が前記第１の導電部に電気的に接続された複数のハイサイドスイッチと、
前記第３の導電部の各々の上に実装され、前記ハイサイドスイッチの他端に一端が電気的に接続され且つ前記第２の導電部に他端が電気的に接続された複数のローサイドスイッチと、
を備えることを特徴とする半導体装置。 A semiconductor device that converts DC power into AC power,
A first conductive portion electrically connected to the power supply terminal and extending in the first direction;
A second conductive portion electrically connected to a ground terminal and extending in the first direction;
A plurality of third conductive portions arranged between the first conductive portion and the second conductive portion and arranged in the first direction;
A plurality of high-side switches mounted on the first conductive portion along the first direction and having one end electrically connected to the first conductive portion;
A plurality of low-side switches mounted on each of the third conductive portions, one end of which is electrically connected to the other end of the high-side switch and the other end of which is electrically connected to the second conductive portion. When,
A semiconductor device comprising: 前記複数の第３の導電部との間に前記第１の導電部が位置するように前記第１の方向に沿って配列され、前記ハイサイドスイッチまたは前記ローサイドスイッチを制御するための複数の制御端子と、
前記複数の第３の導電部との間に前記第２の導電部が位置するように前記第１の方向に沿って配列され、前記ハイサイドスイッチの前記他端および前記ローサイドスイッチの前記一端に電気的に接続された複数の出力端子と、
をさらに備えることを特徴とする請求項１に記載の半導体装置。 Plural controls for controlling the high-side switch or the low-side switch, arranged along the first direction so that the first conductive portion is located between the plurality of third conductive portions. A terminal,
Arranged along the first direction so that the second conductive portion is positioned between the plurality of third conductive portions, and the other end of the high-side switch and the one end of the low-side switch A plurality of electrically connected output terminals;
The semiconductor device according to claim 1, further comprising: 前記電源端子および前記グランド端子は、前記複数の出力端子と並んで設けられていることを特徴とする請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein the power supply terminal and the ground terminal are provided side by side with the plurality of output terminals. 前記第２の導電部と前記第３の導電部との間に配置され、前記第１の方向に並ぶ複数の第４の導電部と、
前記第４の導電部の各々の上に実装され、一端が前記第３の導電部を介して前記ハイサイドスイッチの前記他端および前記ローサイドスイッチの前記一端に電気的に接続され、他端が前記出力端子に電気的に接続された複数の出力制御スイッチと、
をさらに備え、
前記出力制御スイッチの制御端子は、前記制御端子と並んで設けられていることを特徴とする請求項２に記載の半導体装置。 A plurality of fourth conductive portions arranged between the second conductive portion and the third conductive portion and arranged in the first direction;
Mounted on each of the fourth conductive portions, one end is electrically connected to the other end of the high-side switch and the one end of the low-side switch via the third conductive portion, and the other end is A plurality of output control switches electrically connected to the output terminal;
Further comprising
The semiconductor device according to claim 2, wherein a control terminal of the output control switch is provided side by side with the control terminal. 前記第２の導電部と前記第３の導電部との間に前記第４の導電部と隣り合うように配置され、前記ローサイドスイッチの前記他端と前記第２の導電部とを電気的に接続する複数の第５の導電部をさらに備えることを特徴とする請求項４に記載の半導体装置。   The second conductive portion is disposed between the second conductive portion and the third conductive portion so as to be adjacent to the fourth conductive portion, and electrically connects the other end of the low-side switch and the second conductive portion. The semiconductor device according to claim 4, further comprising a plurality of fifth conductive parts to be connected. 一端が前記第５の導電部に接続され、他端が前記第２の導電部に接続されたシャント抵抗と、
前記シャント抵抗の前記一端に電気的に接続された第１の電流検出端子と、
前記シャント抵抗の前記他端に電気的に接続された第２の電流検出端子と、
をさらに備え、
前記第１および第２の電流検出端子は、前記ハイサイドスイッチまたは前記ローサイドスイッチの制御端子と、前記出力制御スイッチの制御端子との間に設けられていることを特徴とする請求項５に記載の半導体装置。 A shunt resistor having one end connected to the fifth conductive portion and the other end connected to the second conductive portion;
A first current detection terminal electrically connected to the one end of the shunt resistor;
A second current detection terminal electrically connected to the other end of the shunt resistor;
Further comprising
6. The first and second current detection terminals are provided between a control terminal of the high-side switch or the low-side switch and a control terminal of the output control switch. Semiconductor device. 隣接する前記第３の導電部間、および隣接する前記第５の導体部と前記第４の導体部間を延在するように設けられ、前記シャント抵抗の前記一端と前記第１の電流検出端子とを電気的に接続する第１の接続配線と、
前記第１の接続配線に並んで延在するように設けられ、前記シャント抵抗の前記他端と前記第２の電流検出端子とを電気的に接続する第２の接続配線と、
をさらに備えることを特徴とする請求項６に記載の半導体装置。 The one end of the shunt resistor and the first current detection terminal are provided so as to extend between the adjacent third conductive portions and between the adjacent fifth conductor portion and the fourth conductor portion. A first connection wiring for electrically connecting
A second connection wiring provided so as to extend alongside the first connection wiring and electrically connecting the other end of the shunt resistor and the second current detection terminal;
The semiconductor device according to claim 6, further comprising:
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