JP2016139780A - Substrate for light-emitting element and light-emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate for a light-emitting element capable of manufacturing a light-emitting element excellent in light-emitting efficiency with high yield compared with prior art and a light-emitting element.SOLUTION: The substrate for a light-emitting element includes a pattern constituted of a projection and a recess. The pattern includes the recess whose bottom has a minimum length of 30 nm or more and less than 300 nm, and includes the projection such that an inclination angle Θ1 of a side wall having an origin at the bottom of the recess adjacent to the projection is 63° or larger and 86° or less.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a light-emitting element substrate and a light-emitting element that can be used for a light-emitting element such as an LED.

With the background of environmental energy problems, LEDs (Light Emitting Diodes) are attracting attention. Factors that determine the external quantum efficiency EQE indicating the light emission efficiency of the LED include an electron injection efficiency EIE, an internal quantum efficiency IQE, and a light extraction efficiency LEE. In particular, there are many reports that the internal quantum efficiency IQE and the light extraction efficiency LEE can be improved by providing a pattern on the surface of the LED substrate. PSS (Patterned Sapphire Substrate) has already been widely distributed and widely used as an LED substrate. PSS is a substrate made of single crystal sapphire and having a plurality of convex portions on the order of micrometers on the main surface. It has been reported that the light extraction efficiency LEE is improved by using this PSS substrate (see Patent Document 1). However, the efficiency is not sufficient for spreading the LED throughout the world, and further efficiency improvement is required. For example, Patent Document 2 describes an example in which the size of the PSS is in the nanometer order.

JP 2012-160502 A International Publication No. 2014/058069 Pamphlet

  By the way, in order to manufacture LED, it is necessary to go through the CVD (Chemical Vapor Deposition) process with respect to the board | substrate for LED, and the efficiency of LED is greatly influenced also by this CVD process. In particular, by using an LED substrate having a convex portion of the order of nanometers, it is possible to reduce the manufacturing cost and manufacturing time of the LED substrate, and of course, increase the time of the CVD process, which is a heavy process in the LED manufacturing process. It can be shortened. From such a viewpoint, attention has been focused on the technology related to the LED substrate having the convex portion of the nanometer order.

  However, when an LED substrate having a nanometer-order convex portion is used, a plurality of voids are formed at the interface between the convex portion and the layer on which the CVD film is formed. There was a problem of becoming smaller.

  Therefore, the present invention has been made in view of such points, and in particular, to provide a light emitting element substrate and a light emitting element capable of manufacturing a light emitting element having excellent light emission efficiency with a high yield as compared with the prior art. Objective.

  The present invention is a light-emitting element substrate having a pattern composed of a convex portion and a concave portion, wherein the pattern has the concave portion whose shortest length C of the concave portion bottom is 30 nm or more and less than 300 nm, and It has the said convex part with which inclination | tilt angle (theta) 1 of the side wall from the said recessed part bottom part adjacent to a convex part satisfy | fills 63 degrees or more and 86 degrees or less.

  In the present invention, it is more preferable that the inclination angle Θ1 is not less than 63 ° and not more than 79 °.

  In this invention, it is preferable to have the said convex part with which inclination | tilt angle (theta) 2 of the side wall in the position of 40% of the height of the said convex part satisfy | fills 63 to 86 degrees.

  Alternatively, the present invention is a light-emitting element substrate having a pattern composed of a convex part and a concave part, and the pattern has the concave part whose shortest length C of the concave part bottom is 30 nm or more and less than 300 nm, It has the said convex part with which inclination-angle (theta) 2 of the side wall in the position of 40% of the height of the said convex part satisfy | fills 63 degrees or more and 86 degrees or less.

  In the present invention, it is more preferable that the inclination angle Θ2 is 63 ° or more and 79 ° or less.

  In addition, the light-emitting element according to the present invention includes at least a first conductivity type layer, a light-emitting layer, and a second conductivity-type layer on the patterned side of the light-emitting element substrate according to any one of the above. And

  By using the substrate for a light emitting device of the present invention, voids generated in the CVD film formation layer can be suppressed first. Thereby, the light emitting element with high luminous efficiency and excellent long-term reliability can be manufactured. Furthermore, the process window in the CVD process can be widened. That is, the yield of LEDs can be improved, and at the same time, the yield of LEDs with better luminous efficiency can be improved.

It is sectional drawing which shows a part of substrate for light emitting elements of embodiment in this invention. It is the expanded sectional view which expanded and showed one convex part of the board | substrate for light emitting elements shown in FIG. It is a top view which shows some light emitting element substrates of embodiment in this invention, and is explanatory drawing for demonstrating the definition of a recessed part bottom part especially. It is a top view which shows a part of substrate for light emitting elements of embodiment in this invention, and is explanatory drawing for demonstrating the definition of a table top especially. It is a top view which shows a part of substrate for light emitting elements of embodiment in this invention, and is explanatory drawing for demonstrating the definition of a convex part bottom part especially. It is a graph which shows the relationship between the shortest length C of a recessed part bottom, and inclination | tilt angle (theta). It is a graph which shows the relationship between the shortest length C of a recessed part bottom part, and inclination | tilt angle (theta) 1. It is a graph which shows the relationship between the shortest length C of a recessed part bottom, and inclination | tilt angle (theta) 2.

  Hereinafter, an embodiment of the present invention (hereinafter abbreviated as “embodiment”) will be described in detail. In addition, this invention is not limited to the following embodiment, It can implement by changing variously within the range of the meaning.

  The LED substrate in the present embodiment includes a pattern including a convex portion and a concave portion, and the pattern includes the following requirement 1 and requirement 2. Hereinafter, the LED substrate having requirements 1 and 2 is referred to as an LED substrate 1.

(Requirement 1)
The shortest length C of the bottom of the recess has a recess that is 30 nm or more and less than 300 nm.

(Requirement 2)
The side wall has an angle of inclination Θ <b> 1 that starts from the bottom of the concave portion adjacent to the convex portion and satisfies a convex portion that is 63 ° to 86 °.

  The LED substrate 1 in the present embodiment is configured to satisfy both the above requirements 1 and 2 simultaneously.

  As shown in FIG. 1, the inclination angle Θ <b> 1 is the inclination angle Θ of the side wall of the convex portion starting from the bottom of the concave portion adjacent to the convex portion.

  Here, the connection point between the concave portion and the convex portion side surface may be discontinuous or may be continuous. From this, the inclination angle Θ1 is defined as an angle measured according to the following procedure.

(1) The cross section of the pattern of the light emitting element substrate is observed with a scanning electron microscope. At this time, the observation is performed at a magnification at which 5 or more and 8 or less convex portions of the pattern exist in one observation image.
(2) Draw an average line CC at the bottom of all the recesses included in the observed image.
(3) With respect to an arbitrary convex portion, a tangent line 1 is drawn with respect to the side surface at a position of 5% of the height of the convex portion. Note that the position of 5% of the height of the convex portion is a position at a height × 0.05 in the direction of the apex of the convex portion with reference to the average line CC at the bottom of the concave portion. This corresponds to the position of 0.05H shown in FIG.
(4) The angle formed between the average line CC and the tangent line 1 is the inclination angle Θ1. However, the inclination angle Θ1 is an angle located on the inner side of the convex portion, and can take a range of more than 0 ° and not more than 90 °. Since two tangents 1 can be drawn with respect to the side surface of the convex portion, two inclination angles Θ1 are obtained for one observed convex portion. Therefore, these arithmetic average values are set to the inclination angle Θ1 with respect to an arbitrary convex portion.

  Describing in detail with reference to FIG. 2, as shown in FIG. 2, the height that is the shortest distance from the top of the convex portion to the average line CC at the bottom of the concave portion is defined as H. A position at a height of 0.05 × H from the average line CC at the bottom of the concave portion is a position that is 5% of the height of the convex portion. Then, a parallel line a parallel to the average line CC is drawn at a height position of 5% (indicated as X% in FIG. 2), and intersection points b and c where the parallel line a and the side surface intersect are obtained. Then, a tangent is obtained at each of the intersections b and c, and an arithmetic average of the inclination angle Θ1 (denoted as Θ in FIG. 2) obtained from each tangent is obtained. However, FIG. 2 is for explaining how to obtain the parallel line a and the intersection points b and c, and the parallel line a and the intersection points b and c do not indicate the height position of 0.05H.

  It is not necessary that all the convex portions have an inclination angle Θ1 that satisfies 63 ° or more and 86 ° or less, and one or more arbitrarily selected convex portions may have an inclination angle Θ1 that satisfies 63 ° or more and 86 ° or less. . It is preferable that 80% or more of the plurality of convex portions appearing when observed with a scanning electron microscope has an inclination angle Θ1 that satisfies 63 ° or more and 86 ° or less.

  Next, the shortest length C of the bottom of the concave portion indicates the shortest distance between the contour of the bottom of the convex portion and the contour of the bottom of the convex portion closest to the convex portion. Here, the shortest length C of the bottom of the recess is defined according to the following procedure.

(1) The surface of the LED substrate pattern is observed with a scanning electron microscope. At this time, observation is performed at a magnification at which there are 10 or more and 20 or less pattern convex portions in one observation image.
(2) As shown in FIG. 3, an arbitrary convex portion A is selected, and a point A is set on the contour of the convex portion. Note that the point A is a point that can freely traverse the contour line of the convex portion A.
(3) As shown in FIG. 3, the convex part B closest to the convex part A is selected.
(4) A point B is set on the contour of the convex portion B. Note that the point B is a point that can freely move on the contour line of the convex portion B.
(5) Regarding the line segment AB connecting the point A and the point B, the length of the shortest line segment AB when the point A and the point B are moved on the contour of the bottom of the convex part is a concave part. The shortest length C at the bottom.

  It is not necessary that the shortest length C of all the bottom portions of the recesses is 30 nm or more and less than 300 nm, and the shortest length C of one or more recess bottom portions selected arbitrarily may be 30 nm or more and less than 300 nm. In addition, it is preferable that 80% or more of the shortest length C of the bottom of the concave portion that appears when observed with a scanning electron microscope is 30 nm or more and less than 300 nm.

  Or the board | substrate for LED in this Embodiment comprises the pattern comprised by a convex part and a recessed part, and a pattern is provided with said requirement 1 and following requirement 3. FIG. Hereinafter, the LED substrate having requirements 1 and 3 is referred to as an LED substrate 2.

(Requirement 3)
The side wall has a convex portion satisfying an inclination angle Θ2 of 63 ° to 86 ° at a position of 40% of the height of the convex portion.

  The LED substrate 2 in the present embodiment is configured to satisfy both the requirements 1 and 3 simultaneously.

  As described above, the inclination angle Θ <b> 2 is the inclination angle Θ of the side wall at the position of 40% of the height of the protrusion. Here, the inclination angle Θ2 is defined as an angle measured according to the following procedure.

(1) The cross section of the pattern of the LED substrate is observed with a scanning electron microscope. At this time, the observation is performed at a magnification at which there are 5 or more and 8 or less convex portions of the pattern in one observation image.
(2) As shown in FIG. 1, an average line CC is drawn at the bottom of all the recesses included in the observation image.
(3) With respect to an arbitrary convex portion, the tangent line 2 is drawn on the side surface at a position of 40% of the height of the convex portion. In addition, the position of 40% of the height of the convex portion is a position at a height of 0.4 in the direction of the apex of the convex portion with reference to the average line CC at the bottom of the concave portion.
(4) The angle formed between the average line CC and the tangent line 2 is the inclination angle Θ2. However, the inclination angle Θ <b> 2 is an angle located on the inner side of the convex portion, and can take a range of more than 0 ° and not more than 90 °. Since two tangent lines 2 can be drawn with respect to the side surface of the convex portion, two inclination angles Θ2 are obtained for one observed convex portion. Therefore, these arithmetic average values are set to the inclination angle Θ2 with respect to an arbitrary convex portion.

  Also for the inclination angle Θ2, the inclination angle Θ2 is calculated by obtaining the parallel line a at the height position of 0.4H, the height position of 0, 4H, and the intersections b and c from FIG.

  It is not necessary that all the convex portions have an inclination angle Θ2 that satisfies 63 ° to 86 °, and one or more arbitrarily selected convex portions may have an inclination angle Θ2 that satisfies 63 ° to 86 °. . It is preferable that 80% or more of the plurality of convex portions appearing when observed with a scanning electron microscope has an inclination angle Θ2 that satisfies 63 ° or more and 86 ° or less.

  According to the configuration of the LED substrate in the present embodiment, there are two major effects when performing CVD film formation on the pattern surface of the LED substrate. That is, first, it is possible to suppress the generation of voids at the interface between the layer formed by CVD and the pattern. Thereby, LED with high luminous efficiency and excellent long-term reliability can be manufactured. Second, the process window in the CVD process can be enlarged. For example, there is an LED substrate A that can be formed under conditions A (1050 ° C. ± 10 ° C.) as a CVD film formation temperature, while there is an LED substrate B that can be formed under conditions B (1050 ° C. ± 1 ° C.). And In this case, it can be said that the process window in the CVD process of the LED substrate A is wide. As described above, the effect of widening the process window means that the margin for the film formation conditions for the CVD film formation is widened. Even if set to T ° C., it actually has a temperature of T ° C. ± Y ° C. If this T ° C. ± Y ° C. deviates from the temperature at which film formation is possible, a film formation failure will occur. In the above, the temperature is representative, but the window is formed by many parameters such as the pressure of the CVD process, the gas flow rate ratio, and the gas flow rate. By expanding the process window, it can be said that, for example, the yield in units such as months or years is improved. That is, the yield of LEDs can be improved, and at the same time, the yield of LEDs with better luminous efficiency can be improved. The reason why these effects are manifested is to satisfy the requirements 1 and 2 or the requirements 1 and 3 simultaneously. First, when the requirement 1 is satisfied, a layer can be grown starting from the bottom of the concave portion of the pattern in the nucleation to nucleation stages of the CVD process. And by satisfy | filling the requirement 2 or the requirement 3, it can inhibit that a layer grows from the side part of a convex part. That is, by satisfying the requirement 1 and the requirement 2 or the requirement 1 and the requirement 3 at the same time, the CVD film formation starting from the bottom of the concave portion of the pattern becomes possible. Therefore, the process window for CVD film formation is widened. As a result, the above two effects can be achieved. In addition, although the board | substrate 1 for LED and the board | substrate 2 for LED both show the outstanding effect, a more effect can be exhibited by using properly by the detailed shape of a pattern, the conditions of a CVD process, etc. The proper use will be described later.

  Moreover, it is preferable that the board | substrate for LED in this Embodiment satisfy | fills all the above-mentioned requirements 1, above-mentioned requirements 2, and above-mentioned requirements 3 all simultaneously. Hereinafter, the LED substrate having requirements 1, 2 and 3 is referred to as an LED substrate 3.

  According to this configuration, the effects described above are more remarkably exhibited. That is, the efficiency of the LED is higher and the long-term reliability is also longer. And the yield which concerns on LED manufacture improves more based on the process window of a CVD process being expanded more. Furthermore, it is possible to improve the yield of the LED having higher luminous efficiency. As described above, both the yield of the LED substrate and the yield of the CVD process can be improved at the same time, and a more efficient LED can be manufactured.

  In the present embodiment, it is preferable that the inclination angle Θ1 of requirement 2 and / or the inclination angle Θ2 of requirement 3 is not less than 63 ° and not more than 86 °. In the present embodiment, it is more preferable that the inclination angle Θ1 of requirement 2 and / or the inclination angle Θ2 of requirement 3 is 63 ° or more and 79 ° or less. In the present embodiment, it is most desirable that the inclination angle Θ1 of requirement 2 and / or the inclination angle Θ2 of requirement 3 is not less than 63 ° and not more than 75 °. As described above, by defining the numerical range of the inclination angle Θ1 and / or the inclination angle Θ2, the effect described above can be more remarkably exhibited.

  In addition, the LED of the present embodiment has a configuration in which at least the first conductive type layer, the light emitting layer, and the second conductive type layer are provided on the pattern side of the LED substrate described above. With this configuration, a high-yield and high-efficiency LED can be manufactured.

  The LED substrate of the present embodiment includes a pattern composed of convex portions and concave portions on at least one surface of the substrate. This pattern may be provided on the entire surface of the substrate or only on a part thereof. Moreover, you may have a part which does not have a pattern partially.

  The pattern may be a convex shape independent of a concave portion having a plurality of convex portions or a concave shape independent of a convex portion having a plurality of concave portions, but from the viewpoint of the effect according to the present embodiment. It is preferably an independent convex type.

  In the present embodiment, an LED can be manufactured by performing CVD film formation on the pattern side of the LED substrate. For example, gallium nitride (GaN) is formed. Details of the CVD film formation will be described later. Here, the quality of the layer formed by the CVD process greatly affects the performance and yield of the LED. That is, it is necessary to improve the CVD film quality and to increase the process window of the CVD process. By using the LED substrate of the present embodiment, these effects can be achieved. Problems caused by performing CVD film formation on an LED substrate having a pattern are as follows.

-Void generated at the interface between the pattern and the CVD layer A hindrance to the CVD film formation due to the pattern of the LED substrate occurs, and a void is formed at the interface between the pattern and the CVD layer. This void is generated with a thermodynamic probability. That is, voids are generated irregularly and at a certain frequency near the concave portion of the pattern. The generation of voids reduces the crystallinity of the CVD layer and reduces the efficiency of the LED. This is because when a void is generated, a CVD film-forming layer that grows from the bottom of the recess is inhibited from growing. Moreover, the LED efficiency reduction is based on the internal quantum efficiency IQE reduction. Furthermore, since there is a void at the interface between the LED substrate and the CVD layer, it is estimated that the long-term reliability of the LED is lowered. This is based on the fact that there is a void in the vicinity of the growth start of the layer of CVD film formation, and this lowers the crystal quality. Long term reliability refers to the number of years that can be used and the duration of continuous lighting.

-Narrowing of CVD deposition process window In CVD deposition on the pattern of the LED substrate, the CVD component may remain on the side wall of the pattern due to thermal diffusion on the pattern surface of the CVD component. In this case, the CVD layer growth starts from the side wall portion. That is, the layer formed by the CVD process includes a plurality of crystal axis components. In order to avoid such a phenomenon, it is necessary to strictly control the temperature, temperature distribution, CVD component distribution, time, and the like in the CVD process. However, even a slight difference in conditions such as simultaneous film formation on LED substrates in different lots may deviate from the CVD film formation process window and cause the phenomenon described above. This is a narrowing of the CVD film forming process window. Therefore, the yield of LED manufacturing decreases.

  The essence of the solution to the two problems caused by performing the CVD film formation described above is to control the film formation start point of the layer formed in the CVD process. That is, in order to suppress the void, it is considered that the film formation starting from the bottom of the recess is realized, and at the same time, the film formation starting from the side wall is suppressed, thereby expanding the CVD film forming process window. I can do it. Here, considering the fact that the above-mentioned problems have been solved by these methods, an LED having a high yield and a high internal quantum efficiency IQE can be manufactured. Therefore, a design that further improves the light extraction efficiency LEE is essential. You can say that. In view of the above, it can be considered that it is necessary to control the inclination angle Θ of the side surface of the convex portion and the shortest length C of the bottom portion of the concave portion.

  FIG. 6 is a graph showing the relationship between the shortest length C of the recess bottom and the inclination angle Θ. In FIG. 6, the hatched area is a numerical range for defining the LED substrate of the present embodiment. The case where the inclination angle Θ on the vertical axis is defined as the inclination angle Θ1 is the LED substrate 1 described above, and the case where the inclination angle Θ2 is defined as the inclination angle Θ2 is the LED substrate 2. The LED substrate 3 is an LED substrate that satisfies both the numerical range defined for the LED substrate 1 and the numerical range defined for the LED substrate 2.

  First, when paying attention to the inclination angle Θ which is the vertical axis, in the region where Θ is 0 ° or more and less than 63 ° and more than 86 °, the layer growth of the CVD film starting from the side surface portion of the convex portion tends to occur. is there. That is, the growth starting from the bottom of the recess is inhibited, and the growth of a layer having a plurality of crystal axes is promoted. As voids are generated, the process window for CVD deposition is narrowed. On the other hand, when the inclination angle Θ is in the range of 63 ° to 86 °, the growth starting point of the layer formed by the CVD process is defined as the crystal plane. Growth from the convex side surface portion is suppressed. Thereby, the growth starting from the bottom of the recess can be realized. Even if the inclination angle Θ is in the range of 10 ° or more and 40 ° or less, the effect of enlarging the process window in the CVD process can be desired. This could be calculated from the mismatch of the lattice constant between the pattern surface and the CVD layer. On the other hand, the fact that the inclination angle Θ is in the range of 63 ° to 86 ° is determined from the experiment (Example 1) in addition to the calculation of the lattice constant mismatching.

  Next, when paying attention to the shortest length C of the bottom of the recess, which is the horizontal axis, in the region of 0 nm or more and less than 30 nm, the supply capability of the source gas in the CVD process to the bottom of the recess of the pattern is lowered. That is, in the nucleation to nucleation growth stage, the uniformity of the nuclei collected at the bottom of the pattern recess is reduced. Then, the growth of the nucleus from the location is inhibited. That is, growth starting from the bottom of the recess becomes difficult. In the region where the minimum length C of the bottom of the recess is more than 300 nm, growth starting from the bottom of the recess can be realized. However, it is considered that dislocations are generated by collision (association) between the growing CVD layers within the surface of the bottom of the recess. That is, the crystal quality may be lowered. Furthermore, since the light traveling direction is not optimized and the absorption of the LED in the conductive type layer and the active layer is increased, the light extraction efficiency LEE is lowered. On the other hand, in the region of 30 nm or more and 300 nm or less, when attention is paid to the layer formed by the CVD process, the nucleus of the layer can be easily attached to the bottom of the recess. That is, it is possible to grow a layer of CVD film starting from the bottom of the recess, and it is possible to suppress the void and enlarge the process window. In addition, since it is possible to realize a light traveling path that minimizes absorption of the conductive type layer and the active layer of the LED, the light extraction efficiency LEE is also improved at the same time.

  As described above, by satisfying the numerical range of the hatched area shown in FIG. 6, it is possible to realize the layer growth of the CVD film starting from the bottom of the recess. This increases the unity of crystal axes of the layer formed by CVD. That is, since it is possible to balance the growth in the height direction of the convex portion of the pattern and the growth in the radial direction of the convex portion, voids are reduced. Furthermore, resistance to fluctuations in the conditions of the CVD process increases. By these, the following effects will be produced. First, based on the suppression of the void, the light emission efficiency of the LED is improved, and at the same time, the long-term reliability is improved. And the process window in a CVD process is expanded. And since there also exists an improvement effect of light extraction efficiency LEE, the yield with respect to LED with higher efficiency improves.

  Based on the above consideration, the LED substrate of the present embodiment is configured to satisfy the requirement 1 in which the shortest length C of the bottom of the recess is 30 nm or more and less than 300 nm. The LED substrate 1 is configured to satisfy the requirement 2 in which the inclination angle Θ1 shown in FIG. In addition, the LED substrate 2 is configured to satisfy the requirement 3 at the same time as the requirement 1 in which the inclination angle Θ2 shown in FIG. Further, the LED substrate 3 is configured to satisfy the requirements 1, 2 and 3 simultaneously. The LED substrate 1 and the LED substrate 2 can be selectively used depending on the shape and arrangement of patterns provided on the LED substrate, conditions of the CVD process, and the like.

  Regarding the LED substrate 1, the process window for the initial process of the CVD process, for example, the seed layer forming process is particularly large. Therefore, the process window of the entire CVD process becomes large. More specifically, in the LED substrate 1, the rising angle of the side surface portion of the convex portion with respect to the concave bottom portion is defined. That is, the crystal plane on which the seed layer can be grown is defined. Therefore, a seed layer is formed preferentially at the bottom of the recess. Using this seed layer as a starting point, CVD film growth can be realized. Since this is a layer growth starting from the bottom of the recess in the expression described above, the effect described above can be exhibited.

  Regarding the LED substrate 2, the process window for the flattening step for flattening the pattern is particularly large in the initial step of the CVD step. Therefore, the process window of the entire CVD process becomes large. More specifically, in the LED substrate 2, the angle of the side surface portion at a position of 40% of the height of the convex portion is defined. That is, in the process of growing nuclei generated by CVD film formation and flattening the pattern, it is possible to define the crystal plane of the CVD film formation layer with respect to the side surface portion of the convex portion. More specifically, the difference between the lattice constant of the side surface portion of the convex portion and the lattice constant of the CVD film formation layer can be increased. In other words, the CVD film-forming layer has a low affinity with the convex side surface portion. Therefore, layer growth starting from the bottom of the recess can be realized. Therefore, the effect demonstrated above can be expressed.

  From the above, it can be said that both the process window for the seed layer forming process and the process window for the pattern flattening process are expanded by satisfying all of the requirements 1, 2 and 3 simultaneously. That is, by using the LED substrate 3, among the effects described above, in particular, the enlargement of the process window with respect to the entire CVD process can be made more remarkable. This not only means that the margin for the CVD process conditions is widened, but also means that the margin for variation of the LED substrate is widened. In other words, it is possible to achieve both improvement in yield for manufacturing the LED substrate and improvement in yield for LED manufacturing.

  Next, a more preferable range of requirement 1 which is a requirement common to LED substrates 1, 2, and 3 will be described. According to Requirement 1, the shortest length C of the bottom of the recess is limited, and this restriction makes it possible to realize CVD layer growth starting from the bottom of the recess. With regard to CVD film formation, the killer factor for realizing layer growth starting from the bottom of the recess is to control the deposition and growth of the CVD film nucleus on the bottom of the recess. The CVD film formation is a film formation on the molecular order, but the CVD component supplied to the surface of the pattern of the LED substrate performs surface movement by thermal diffusion. As a result of this thermal diffusion, a certain amount of CVD components are collected and become the core. Here, when the shortest length C of the bottom of the recess is smaller than the minimum stable size of the core, the probability that a stable core is formed at the bottom of the recess is extremely reduced. That is, it becomes difficult to form a CVD layer starting from the bottom of the recess. From this point of view, the lower limit of requirement 1 of 30 nm was derived. Here, considering that the process window in the CVD process is enlarged from the viewpoint of the choice of the CVD component, it can be said that it is necessary to consider a larger minimum stable size of the nucleus. In general, it is sufficient to add about 35 nm as the minimum stable size of the core, considering the CVD components generally used for LEDs. From this viewpoint, it is more preferable that the shortest length C of the bottom of the recess is 40 nm or more in consideration of 20% as a safety factor. That is, for requirement 1, the lower limit value of the shortest length C of the bottom of the recess is more preferably 40 nm or more. In order to enlarge the process window as much as possible, the lower limit of the shortest length C of the bottom of the recess is most preferably 80 nm or more. On the other hand, the upper limit of 300 nm is determined from the viewpoints of the internal quantum efficiency IQE and the light extraction efficiency LEE. Even if the growth starting from the bottom of the recess is realized, collision (association) between the growing CVD layers may occur within the surface of the bottom of the recess and dislocations may be generated. In this case, the crystal quality is lowered and the internal quantum efficiency IQE is reduced. In terms of the dislocation density of general LEDs, the above association can be effectively suppressed if the shortest length C of the bottom of the recess is 300 nm or less. On the other hand, in order to improve the light extraction efficiency LEE, it is necessary to extract light confined in the LED (generally referred to as guided light) to the outside of the LED. What is important here is the viewpoint of how many times the light that is originally guided light is reflected inside the LED layer and then extracted outside the LED. That is, as the number of reflections increases, the amount of light absorption in the conductive type layer and the active layer constituting the LED increases, and therefore the degree of increase in light extraction efficiency LEE decreases. From these viewpoints, with respect to requirement 1, the upper limit value of the shortest length C of the bottom of the recess is more preferably 230 nm or less, and most preferably 200 nm or less.

Next, requirement 2 and requirement 3 will be described. In the following description, a range of 10 ° or more and 40 ° or less that is presumed to be preferable from the calculation result of the mismatching property of the lattice constant is also taken into consideration. Further, the following symbols are used to describe the inclination angle Θ more finely. The inclination angle Θ3 will be described later.
Inclination angle Θ1L: Inclination angle Θ1 indicating a region of 10 ° to 40 °
Inclination angle Θ1H: Inclination angle Θ1 indicating a region of 63 ° to 86 °
Inclination angle Θ2L: Inclination angle Θ2 indicating a region of 10 ° to 40 °
Inclination angle Θ2H: Inclination angle Θ2 indicating a region of 63 ° to 86 °
Inclination angle Θ3L: Inclination angle Θ3 indicating a region of 10 ° to 40 °
Inclination angle Θ3H: Inclination angle Θ3 indicating a region of 63 ° to 86 °

  A more preferable range of requirement 2 common to the LED substrate 1 and the LED substrate 3 will be described. Requirement 2 limits the tilt angle Θ1. Thereby, in particular, the process window for the seed layer forming step can be enlarged and voids can be suppressed. In Requirement 2, the tilt angle that is the region of 63 ° or greater and 86 ° or less was defined as the tilt angle Θ1H. Here, regarding the inclination angle Θ1, the region of 10 ° or more and 40 ° or less is considered to be preferable from the above calculation, and therefore, the inclination angle Θ1L is set.

  By using the LED substrate having the inclination angle Θ1H, in addition to the expansion of the process window in the seed layer forming step, the expansion effect of the process window in the planarization step is also exhibited. This is because the discontinuity between the concave bottom and the convex bottom is increased. In other words, the energy barrier when the CVD component thermally diffusing at the bottom of the concave portion rises to the side surface of the convex portion can be increased. From this viewpoint, with respect to requirement 2, the inclination angle Θ1 (Θ1H) is more preferably 63 ° to 79 °, and most preferably 63 ° to 75 °. Further, regarding the inclination angle Θ1 of requirement 2, it is more preferable to satisfy the inclination angle Θ1H from the viewpoint of maximizing the effects of the LED substrate 1.

  By using the LED substrate having the range of the inclination angle Θ1L, it is considered that the effect of expanding the process window with respect to the seed layer forming step becomes more remarkable. This is due to the improved continuity of the seed layer due to the increased continuity between the bottom of the concave portion and the bottom of the convex portion. From this viewpoint, it is considered that the inclination angle Θ1L is more preferably 20 ° or more and 30 ° or less.

  Next, a more preferable range of requirement 3 common to the LED substrate 2 and the LED substrate 3 will be described. Requirement 3 limits the tilt angle Θ2. Thereby, in particular, the process window for the flattening step can be enlarged and voids can be suppressed. In Requirement 3, the inclination angle Θ2 is preferably in the range of 63 ° to 86 °, and the inclination angle Θ2H is set. Further, an area that is estimated to be preferable from the above calculation and is 10 ° or more and 40 ° or less is defined as an inclination angle Θ2L.

  By using the LED substrate having the inclination angle Θ2H, the expansion of the process window in the planarization process becomes more remarkable. This is because the effect of inhibiting the growth of CVD starting from the side surface of the convex portion is high. In order to further enhance this effect, it is necessary to further reduce the affinity of the interface between the CVD layer and the pattern side surface. From this viewpoint, with respect to requirement 3, the inclination angle Θ2 (Θ2H) is more preferably 63 ° or greater and 79 ° or less, and most preferably 63 ° or greater and 75 ° or less. Further, regarding the inclination angle Θ2 of requirement 3, it is more preferable to satisfy the inclination angle Θ2H from the viewpoint of maximizing the effect of the LED substrate 2.

  By using the LED substrate having the range of the inclination angle Θ2L, it is presumed that the effect of reducing the void can be exhibited more significantly in addition to the effect of expanding the process window for the seed layer forming step. This is because the interface stress between the CVD film formation layer and the pattern surface is relaxed. From this viewpoint, it is considered that the inclination angle Θ2L is more preferably 20 ° or more and 30 ° or less.

  The LED substrate 3 of the present embodiment is an LED substrate that satisfies all of the above requirements 1, 2, and 3. That is, the shortest length C of the bottom of the concave portion has a concave portion that is 30 nm or more and less than 300 nm, and both the inclination angle Θ1 and the inclination angle θ2 satisfy 63 ° or more and 86 ° or less. As a result, the efficiency of the LED is higher and the long-term reliability is also longer. And the yield of LED which is more excellent in luminous efficiency can be improved at the same time the yield concerning LED manufacture improves more based on the window of a CVD process being expanded more. In particular, the enlargement of the process window with respect to the CVD process can be made more remarkable. This not only means that the margin for the CVD process conditions is widened, but also means that the margin for variation of the LED substrate is widened. In other words, it is possible to achieve both improvement in yield for manufacturing the LED substrate and improvement in yield for LED manufacturing.

  When the range of the inclination angle Θ is treated as the inclination angle Θ1H, the inclination angle Θ2H, the inclination angle Θ1L, and the inclination angle Θ1L including the above calculation results, there are four combinations that simultaneously satisfy the requirement 2 and the requirement 3. Become. When the combination of (tilt angle Θ1 / tilt angle Θ2) and the combination are described, the effect of the LED substrate 3 is markedly (Θ1L / Θ2H) or (Θ1H / Θ2H). When these two are better compared, the combination of (Θ1H / Θ2H) is the best. The same contents are listed in Table 1 below. Hereinafter, the combination of (Θ1L / Θ2H) is also referred to as LED substrate 3A, and the combination of (Θ1H / Θ2H) is also referred to as LED substrate 3B.

  In the case of the LED substrate 3A, the effects of the LED substrate 3 described above can be remarkably exhibited. In particular, both the process window for the seed layer forming step and the process window for the planarization step are significantly enlarged. This is because the continuity between the bottom of the concave portion and the bottom of the convex portion is increased, the continuity of the seed layer is improved, and the effect of inhibiting the growth of CVD starting from the side surface of the convex portion is high. In other words, resistance to the variable element of the CVD process is increased. In this case, it is more preferable to satisfy the preferable ranges of the inclination angle Θ1L and the inclination angle Θ2H already described.

  Next, in the case of the LED substrate 3B, the effects of the LED substrate 3 described above can be remarkably exhibited. In particular, in addition to the enlargement of the process window in the seed layer forming step, the effect of enlarging the process window in the planarization step becomes particularly significant. For this reason, the board | substrate 3B for LED is more preferable. This is because the CVD barrier that thermally diffuses at the bottom of the concave portion has a high energy barrier when rising to the side surface of the convex portion, and at the same time has a high effect of inhibiting the growth of CVD starting from the side surface of the convex portion. is there. In other words, resistance to the variable element of the CVD process is increased. In this case, it is more preferable to satisfy the preferable ranges of the inclination angle Θ1H and the inclination angle Θ2H already described.

  A case where the LED substrate 3 is also restricted with respect to the inclination angle Θ3 at a position of 80% of the height of the convex portion is referred to as an LED substrate 4. See also FIG. 1 for the tilt angle Θ3. The LED substrate 4 is a combination of an inclination angle Θ1, an inclination angle Θ2, and an inclination angle Θ3. Further, the inclination angle Θ3 is classified into the inclination angle Θ3L and the inclination angle Θ3H in the same range as the inclination angle Θ1 and the inclination angle Θ2. That is, the total number of combinations is eight. In this, when the combination is described as (tilt angle Θ1, tilt angle Θ2, tilt angle Θ3), (Θ1L, Θ2H, Θ3L), (Θ1L, Θ2H, Θ3H), (Θ1H, Θ2H, Θ3L), or ( An LED substrate that satisfies the combination of (Θ1H, Θ2H, Θ3H) is more preferable. When these are compared, a combination of (Θ1H, Θ2H, Θ3L) or (Θ1H, Θ2H, Θ3H) is more preferable. The same contents are also shown in Table 2 below. Further, in the order of the combination described above, hereinafter, they are also referred to as an LED substrate 4A, an LED substrate 4B, an LED substrate 4C, and an LED substrate 4D.

  In the case of the LED substrate 4A, in addition to the effect of the LED substrate 3A described above, the effect of suppressing voids generated at the interface between the CVD film formation layer and the pattern is further increased. This is because the interface stress between the layer formed by CVD and the pattern surface tends to be relaxed. In this case, it is more preferable to satisfy the preferable ranges of the inclination angle Θ1L and the inclination angle Θ2H already described. Further, it is more preferable that the inclination angle Θ3L satisfies a suitable numerical range of the inclination angle Θ2L already described. In particular, the inclination angle Θ3L preferably satisfies 20 ° to 40 ° from the viewpoint of void reduction effect, and more preferably satisfies 63 ° to 80 ° from the viewpoint of LED efficiency.

  In the case of the LED substrate 4B, in addition to the effect of the LED substrate 3A described above, the improvement effect of the light extraction efficiency LEE becomes more remarkable. This is because, as the continuity of the convex contour of the pattern is improved, the number of times of reflection inside the LED is reduced when the light that is originally guided light is extracted from the LED to the outside. In this case, it is more preferable to satisfy the preferable ranges of the inclination angle Θ1L and the inclination angle Θ2H already described. Further, it is more preferable that the inclination angle Θ3H satisfies a suitable numerical range of the inclination angle Θ2H already described. In particular, the inclination angle Θ3L preferably satisfies 20 ° to 40 ° from the viewpoint of void reduction effect, and more preferably satisfies 63 ° to 80 ° from the viewpoint of LED efficiency.

  In the case of the LED substrate 4C, in addition to the effect of the LED substrate 3B described above, the effect of suppressing voids generated at the interface between the CVD film formation layer and the pattern is further enhanced. For this reason, in LED board 4, LED board 4C is more preferable with LED board 4D mentioned below. This is because the interface stress between the layer formed by CVD and the pattern surface tends to be relaxed. In this case, it is more preferable to satisfy the preferable ranges of the inclination angle Θ1H and the inclination angle Θ2H already described. Further, it is more preferable that the inclination angle Θ3L satisfies a suitable numerical range of the inclination angle Θ2L already described. In particular, the inclination angle Θ3L preferably satisfies 20 ° to 40 ° from the viewpoint of void reduction effect, and more preferably satisfies 63 ° to 80 ° from the viewpoint of LED efficiency.

  In the case of the LED substrate 4D, in addition to the effect of the LED substrate 3B described above, the improvement effect of the light extraction efficiency LEE becomes more remarkable. For this reason, in LED board 4, LED board 4D is more preferable with LED board 4C mentioned above. This is because, as the continuity of the convex contour of the pattern is improved, the number of times of reflection inside the LED is reduced when the light that is originally guided light is extracted from the LED to the outside. In this case, it is more preferable to satisfy the preferable ranges of the inclination angle Θ1H and the inclination angle Θ2H already described. Further, it is more preferable that the inclination angle Θ3H satisfies a suitable numerical range of the inclination angle Θ2H already described. In particular, the inclination angle Θ3L preferably satisfies 20 ° to 40 ° from the viewpoint of void reduction effect, and more preferably satisfies 63 ° to 80 ° from the viewpoint of LED efficiency.

  Next, the arrangement of patterns formed by convex portions and concave portions in the present embodiment will be described. In the present embodiment, the regularity regarding the pattern arrangement is not limited, and various kinds of arrangements can be selected from random complete irregularity to complete regular arrangement. For example, an array with low regularity can be realized by utilizing self-organization utilizing anodization of aluminum, an alternating lamination method (Layer by Layer method), phase separation by a block polymer, or the like. On the other hand, an array with high regularity can be realized by using electron beam drawing, photolithography, thermal lithography, interference exposure, and the like. For example, a line and space arrangement, a four-way arrangement, or a six-way arrangement. In addition, there is an array in which elements composed of a line-and-space array, a tetragonal array, a hexagonal array, and the like have a greater period variation (modulation). For example, microscopically, convex portions arranged in a hexagonal manner are macroscopically arranged in a line-and-space arrangement, a tetragonal arrangement, or a hexagonal arrangement. In addition, there is an array in which a plurality of arrays are composited.

  The shape of the pattern is not particularly limited as long as the requirements described above are satisfied, and the shape of the contour when the pattern is observed from the surface is circular, elliptical, contour shape with five or more irregularities, triangular And the like. Examples of the cross-sectional shape of the pattern include a rectangular shape, a dome shape, a bell shape, a lens shape, a bullet shape, and a cone shape. Among these, it is preferable to satisfy the following shape.

  The shape of the top of the convex portion of the pattern can improve the crystallinity of the layer formed by the CVD process, particularly the internal quantum efficiency IQE. Such a shape is a shape in which the size of the table top (also referred to as a flat portion) existing at the top of the convex portion is not more than the shortest length C of the bottom of the concave portion. The size of the table top at the top of the convex portion is defined as the length T of the table top. The definition of the table top length T will be described later. By satisfying the relationship of the length of the table top T ≦ the shortest length C of the bottom of the recess, layer growth starting from the table top in the CVD process can be suppressed. That is, the layer growth in the CVD film formation starts from the bottom of the recess. In particular, when layer growth starting from the table top occurs, the density of threading dislocations penetrating the active layer of the LED increases and the internal quantum efficiency IQE decreases because the action of eliminating dislocations generated in the layer is weak. Tend to. That is, by satisfying the table top length T ≦ the minimum length C of the bottom of the recess, the threading dislocation density can be reduced and the internal quantum efficiency IQE can be improved. From the viewpoint of exerting this effect more preferably, the table top length T ≦ the shortest length C / 2 of the recess bottom is preferably satisfied, and the table top length T ≦ the shortest length C / 4 of the recess bottom is satisfied. Is more preferable. In addition, the length T of the table top is preferably as small as possible, and is most preferably a state where the radius of curvature of the top portion of the convex portion is a corner portion exceeding zero. That is, it is most preferable that the table top length T is asymptotic to zero.

  The length T of the table top described above is the longest length of the contour of the area forming the table top. More specifically, it is defined according to the following procedure.

(1) The surface of the LED substrate pattern is observed with a scanning electron microscope. At this time, observation is performed at a magnification at which there are 10 or more and 20 or less pattern convex portions in one observation image.
(2) As shown in FIG. 4, an arbitrary convex part is selected, and points A and B are set on the contour of the table top of the convex part. Note that the points A and B are points that can be freely traversed on the outline of the table top.
(3) Regarding the line segment AB connecting the point A and the point B, the length of the longest line segment AB when the point A and the point B are moved on the contour of the table top is Length T.

  Next, the aspect of the convex portion, that is, the ratio (height H / bottom diameter φ) particularly affects the light extraction efficiency LEE, and is preferably 0.45 or more and 1.85 or less. By satisfying this range, it is possible to reduce the number of times the light is reflected inside the LED in the process of taking out the light that is originally guided light to the outside of the LED. That is, since the amount of light absorbed by the conductive type layer and the active layer can be reduced, the light extraction efficiency LEE is further improved. In this respect, the aspect is more preferably from 0.5 to 1.55, and most preferably from 0.75 to 1.25.

  The height H of the convex part demonstrated above is defined as the shortest distance to the vertex of a convex part on the basis of the bottom part of a concave part.

  The diameter φ of the bottom portion of the convex portion described above is the longest length of the contour that forms the bottom portion of the convex portion. More specifically, it is defined according to the following procedure. In other words, the diameter of the circumscribed circle with respect to the contour of the bottom of the convex portion is the diameter φ of the bottom of the convex portion.

(1) The surface of the LED substrate pattern is observed with a scanning electron microscope. At this time, observation is performed at a magnification at which there are 10 or more and 20 or less pattern convex portions in one observation image.
(2) As shown in FIG. 5, an arbitrary convex portion is selected, and points A and B are set on the contour of the bottom of the convex portion. In addition, the point A and the point B are points that can travel freely on the outline of the bottom of the convex portion.
(3) Regarding the line segment AB connecting the point A and the point B, the length of the longest line segment AB when the point A and the point B are moved on the contour of the bottom of the convex part is convex. The diameter φ of the bottom of the part.

  Regardless of whether the pattern is convex or concave, the pitch is defined as the shortest distance between the closest convex parts (or concave parts). Detailed definitions will be described later. A suitable range of the pattern pitch, that is, the pattern interval is determined from the viewpoint of both the CVD process and the light extraction efficiency LEE. First, in the CVD process, in order to improve the crystallinity of the CVD film-forming layer, it is necessary to reduce the film speed until the pattern is flattened. That is, as the pattern height decreases, the time and the amount of members required for the planarization process can be reduced. This planarization process is a heavy process related to LED manufacturing, and the effect of reducing is very large. Next, as the pattern pitch decreases, the optical phenomenon changes to reflection, light scattering, and light diffraction. Here, it is important to reduce the number of reflections inside the LED as much as possible, considering that the light that is originally guided light is extracted from the LED by changing its traveling direction from the pattern. Recognize. This is because the light is absorbed and attenuated with respect to the conductive type layer and the active layer constituting the LED as the light is reflected. From this viewpoint, it is most preferable to use optical diffraction. From the above consideration, it can be said that the pitch is preferably 100 nm or more and 1800 nm or less. 100 nm or more and 1500 nm or less are more preferable from the viewpoint of easy planarization and optical phenomena. In particular, from the viewpoint of further reducing the load related to the planarization step, it is more preferable to satisfy 1300 nm or less as the upper limit value. Moreover, since the load concerning manufacture of the board | substrate for LED can also be reduced significantly, it is most preferable that the upper limit of a pitch is 900 nm or less. On the other hand, the lower limit of the pitch is more preferably 200 nm or more, and most preferably 230 nm or more, from the viewpoint of improving the resistance of the CVD process to the variation in the pattern of the LED substrate. By satisfying such a lower limit range, the expansion of the process window of the CVD process becomes better.

  The pattern pitch P described above is the length between the vertices of the nearest convex portions, but is simply defined as follows.

(1) Find the diameter φ of the bottom of the convex portion in accordance with the method already described.
(2) Find the shortest length C of the bottom of the recess in accordance with the method already described.
(3) The pitch P is defined as the sum of the diameter φ of the bottom of the convex portion and the shortest length C of the bottom of the concave portion.

  Next, the material of the LED substrate will be described. The LED substrate of the present embodiment is not limited in any way as long as the conductive type layer and the active layer are formed on at least the pattern side and used as an LED. For example, sapphire, silicon carbide (SiC), silicon nitride, gallium nitride (GaN), copper tungsten alloy (W-Cu), silicon (Si), zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron oxide, Magnesium aluminum oxide, zirconium boride, gallium oxide, indium oxide, lithium gallium oxide, lithium aluminum oxide, neodymium gallium oxide, lanthanum strontium aluminum tantalum oxide, strontium titanium oxide, titanium oxide, hafnium, tungsten, molybdenum, gallium phosphide, gallium Arsenic or the like can be used. In particular, sapphire, gallium nitride, gallium phosphide, gallium arsenide, silicon carbide, and spinel are more preferable from the viewpoint of stabilizing the film formability in the CVD process. Furthermore, regarding the film formability of the layer in the CVD process, from the viewpoint of further reducing dislocations, a substrate partially provided with a dielectric, metal oxide, or metal is used for the above-described substrate. May be. Further, the substrate may be used alone or may be a heterostructure substrate in which another substrate is provided on the substrate body using these. In addition, the effect based on the requirements 1 to 3 described above is particularly remarkable by using a sapphire, silicon carbide (SiC), or gallium nitride (GaN) substrate.

  Next, the CVD process will be described. In the LED of the present embodiment, at least a first conductivity type layer, an active layer, and a second conductivity type layer are arranged on the pattern surface side of the LED substrate of the present embodiment. By setting it as such a structure, the effect of the board | substrate for LED demonstrated above can be expressed. In the CVD process, a layer is epitaxially grown on the pattern surface side of the LED substrate. In other words, the material for the LED substrate is preferably one suitable for epitaxial growth. From this point of view, an insulating substrate such as sapphire or spinel, or a conductive material such as SiC or nitride semiconductor (for example, GaN). A substrate is preferred. The first conductivity type layer is, for example, an n-type semiconductor layer, and the second conductivity type layer is, for example, a p-type semiconductor layer.

  Examples of CVD in the present specification include metal organic chemical vapor deposition (MOCVD), hydride vapor deposition (HVPE), molecular beam epitaxy (MBE), and the like.

  It is preferable to form a buffer layer before forming the first conductivity type layer. Thereby, the effect of the process window expansion with respect to the seed layer formation process regarding the CVD process described above is further expressed. As the buffer layer, for example, a GaN structure, an AlGaN structure, an AlN structure, an AlInN structure, an InGaN / GaN superlattice structure, an InGaN / GaN stacked structure, or an AlInGaN / InGaN / GaN stacked structure can be employed. In addition, for the film formation of the buffer layer, the film formation temperature can be in the range of 350 ° C. to 600 ° C. Thereby, the influence on the CVD process which the variation of the shortest length C of a recessed part bottom gives can be made small. In other words, the process window of the CVD process is enlarged. In particular, the thickness of the buffer layer is desirably 1/5 or less with respect to the height H of the pattern. This is to effectively suppress the adhesion of nuclei to the side surface of the convex portion with respect to the re-diffusion and recrystallization behavior of the buffer layer in the RAMP process. From this viewpoint, the film thickness of the buffer layer is more preferably 1/10 or less, and most preferably 1/20 or less with respect to the height H of the pattern. The buffer layer is preferably formed by MOCVD (Metal Organic Chemical Deposition) or sputtering. In particular, it is more preferable to employ a sputtering method from the viewpoint of improving the uniformity of the buffer layer.

  The first conductive type layer (n-type layer such as an n-type contact layer), the active layer, and the second conductive type layer (p-type layer) are formed on the LED substrate on which the base layer as described above is formed. A semiconductor element structure can be manufactured by forming.

The first conductivity type layer is preferably composed of at least an undoped first conductivity type layer and a doped first conductivity type layer. As the undoped first conductivity type layer, for example, an elemental semiconductor such as silicon or germanium, or a compound semiconductor such as a III-V group, a II-VI group, or a VI-VI group can be applied. In particular, an undoped nitride layer is preferable. The undoped nitride layer, for example, at a growth temperature of 900 ° C. to 1500 ° C., on the buffer layer or the LED substrate for film can be formed by supplying NH ₃ and TMGa. The film thickness is preferably 1 μm or more and 10 μm or less from the viewpoint of the pattern flattening step. In particular, from the viewpoint of effectively reducing dislocations, the thickness is more preferably 1.5 μm or more and 8 μm or less, and most preferably 2.3 μm or more and 5 μm or less. As the doped first conductivity type layer, for example, an element semiconductor such as silicon or germanium, or a compound semiconductor such as III-V group, II-VI group, VI-VI group, etc., appropriately doped with various elements Can be applied. In particular, an n-type GaN layer is desirable. As the n-type GaN layer, for example, NH ₃ is 3 × 10 ^{−2 to} 4.2 × 10 ⁻² mol / min, and trimethylgallium (TMGa) 0.8 × 10 ^{−4 to} 1.8 × 10 ⁻⁴ mol. Silane gas containing n-type dopant typified by / min and Si can be formed by supplying 5.8 × 10 ^{−9 to} 6.9 × 10 ⁻⁹ mol / min. From the viewpoint of electron injection into the active layer, the film thickness is preferably 800 nm or more, more preferably 1500 nm or more, and most preferably 2000 nm or more. On the other hand, the upper limit value is preferably 5000 nm or less from the viewpoint of reducing warpage.

The active layer is not particularly limited as long as it has light emitting characteristics as an LED. For example, a semiconductor layer such as AsP, GaP, AlGaAs, InGaN, GaN, AlGaN, ZnSe, AlHaInP, or ZnO can be applied. Moreover, you may dope various elements suitably according to the characteristic. The active layer is an active layer having a single or multiple quantum well structure. For example, at a growth temperature of 600 ° C. to 850 ° C., NH ₃ , TMGa, and trimethylindium (TMIn) are supplied using nitrogen as a carrier gas, and an active layer made of INGaN / GaN is formed to a thickness of 100 to 1250 mm. Can be grown. In the case of a multiple quantum well structure, the concentration of In element can be changed with respect to InGaN constituting one layer. An electron blocking layer can be provided between the active layer and the second conductivity type layer. The electron block layer is made of, for example, p-AlGaN.

There is no restriction | limiting in particular as long as it can be used as a p-type semiconductor layer suitable for the use of LED as a 2nd conductivity type layer. For example, elemental semiconductors such as silicon and germanium, and compound semiconductors such as III-V, II-VI, and VI-VI can be appropriately doped with various elements. For example, in the case of a p-type GaN layer, the growth temperature can be raised to 900 ° C. or higher, TMGa and CP ₂ Mg can be supplied, and the film can be formed to a thickness of several hundreds to several thousands.

  In the above, although explained as an LED substrate, it is not limited to an LED, and is a substrate for a light emitting element such as an organic EL, and includes a pattern composed of a convex portion and a concave portion on the surface of the substrate, The present embodiment can be applied as long as the substrate undergoes a CVD process.

  Hereinafter, the present invention will be described in detail with reference to examples carried out in order to clarify the effects of the present invention. In addition, this invention is not limited at all by the following examples.

Example 1
An LED substrate was prepared, CVD film formation was performed on the LED substrate, and a process window was confirmed. Furthermore, LED was manufactured and luminous efficiency was compared.

First, an LED substrate was prepared. The pattern of the LED substrate was prepared using a nano-processed sheet. The nano-processed sheet will be described later. A 4-inch single-sided mirror c-plane sapphire was prepared and washed. Subsequently, sapphire was placed on a 120 ° C. hot plate. Next, the nano-processed sheet was bonded to sapphire using a laminate roll heated to 120 ° C. The bonding was performed at a pressure of 0.5 MPa and a linear speed of 50 mm / second. The sapphire bonded with the nano-processed sheet was irradiated with ultraviolet rays through the sapphire. The ultraviolet rays were irradiated from a UV-LED light source having a wavelength of 365 nm, and the integrated light amount was set to 1500 mJ / cm ² . Next, the nano-processed sheet and sapphire were sandwiched between two parallel flat plates heated to 120 ° C. The sandwiching pressure was 0.3 MPa and the time was 10 seconds. Subsequently, it was cooled to room temperature by air cooling, and the nano-processed sheet was peeled from sapphire at a speed of 50 mm / second. With the above operation, a two-layer resist layer was transferred onto the main surface of sapphire. An uneven structure is provided on the surface of the resist layer. The pattern of the concavo-convex structure and the arrangement of the two-layer resist, and the pattern of the LED substrate were controlled by the dry etching conditions described below.

  The nano-processed sheet is a molded body that can transfer and apply a processing mask onto the object to be processed by a bonding operation and a peeling operation. The configuration includes a resin mold, a first resist layer, and a second resist layer. The resin mold has a concavo-convex structure on the surface, and the first resist layer is filled inside the concave portion of the concavo-convex structure. Then, the second resist layer is disposed so as to flatten the uneven structure of the resin mold and the first resist layer.

  First, a resin mold was manufactured using a roll-to-roll optical nanoimprint method. The width is 500 mm and the length is 180 m. As a layer structure, there is a structure in which a transfer layer having a thickness of 1.5 μm is provided on an easily adhesive surface of a PET film having a thickness of 50 μm, and there is a concavo-convex structure transferred onto the surface of the transfer layer by an optical nanoimprint method. Moreover, the contact angle of the water droplet with respect to the concavo-convex structure surface of the resin mold was between 140 ° and 153 °.

  Next, the 1st resist layer was formed into a film with the die-coating method with respect to the uneven structure of a resin mold. The first resist layer is a titanium-containing organic-inorganic composite resist. The titanium-containing organic-inorganic composite resist was diluted with a mixed solvent in which a solvent A having a surface tension of 24.0 mN / m or less and a solvent B having a surface tension of 27.0 or more were mixed to prepare a coating solution. When coating by the die coating method, the upstream side of the die lip was decompressed. The filling speed of the first resist layer was controlled by controlling the discharge rate at a coating speed of 10 m / min. After coating, air at 120 ° C. was blown and dried, and then wound up and collected. Here, the resin mold on which the first resist layer was formed was analyzed to grasp the state of the first resist layer. For the analysis, a scanning electron microscope, a transmission electron microscope, and energy dispersive X-ray spectroscopy were used in combination. The first resist layer was filled in the concave portion of the concave-convex structure of the resin mold. On the other hand, although a residue (aggregate) of the first resist layer on the order of several nanometers was observed on the upper surface of the convex portion of the concavo-convex structure of the resin mold, the first resist layer was formed on the upper surface. A thick film was not formed. Further, regarding die coating, it was confirmed that the filling amount of the first resist layer was changed by changing the discharge amount of the coating liquid, and the filling diameter of the first resist layer was changed accordingly.

  Next, a second resist layer was formed on the resin mold filled with the first resist layer. The film forming method was the same as that for the first resist layer. The second resist layer is a novolac resin having an acryloyl group in the side chain, and diluted with a solvent having a surface tension of 25.0 mN / m or less to obtain a coating solution. Drying was performed at 105 ° C. After drying, a PE / EVA protective film having a haze (turbidity) of 10% or less was bonded, wound and collected. Here, the manufactured nano-processed sheet was analyzed, and the states of the first resist layer and the second resist layer were grasped. For the analysis, a scanning electron microscope, a transmission electron microscope, and energy dispersive X-ray spectroscopy were used in combination. The first resist layer did not change before and after the second resist layer was formed. The second resist layer could be formed so as to flatten the uneven structure of the resin mold and the first resist layer. In addition, it was confirmed that the film thickness can be controlled by changing the discharge amount of the die coat film formation. That is, the discharge amount of the die coat film formation was controlled to change the filling diameter of the first resist layer and the film thickness of the second resist layer.

Using the manufactured nano-processed sheet, as already described, a two-layer resist layer composed of a first resist layer and a second resist layer was transferred onto the main surface of sapphire. Next, etching for processing the resist layer and etching for processing sapphire were continuously performed in the same chamber. Oxygen gas was used for etching the resist layer. Here, the first resist layer functions as an etching mask for the second resist layer, and the second resist layer is etched until the main surface of sapphire is partially exposed. The etching conditions were a processing gas pressure of 1 Pa and a processing power of 300 W. Subsequently, reactive ion etching using a mixed gas of BCl ₃ gas and Cl ₂ gas was performed to etch sapphire. Here, sapphire was etched using the second resist layer as an etching mask. The processing conditions were ICP: 150 W, BIAS: 50 W, and pressure 0.2 Pa.

  The etched sapphire was taken out and washed with a solution in which sulfuric acid and hydrogen peroxide were mixed at a weight ratio of 2: 1. At this time, the temperature of the treatment liquid was controlled to 100 ° C. or higher.

  A pattern was formed on the main surface of the manufactured sapphire. The shape of the pattern (projection bottom diameter φ, height H, inclination angle Θ, recess bottom minimum length C, etc.) is the filling diameter of the first resist layer of the nano-processed sheet and the thickness of the second resist layer. And can be arbitrarily adjusted according to the processing conditions of dry etching.

A CVD process was applied to the manufactured patterned sapphire to manufacture an LED. First, a low-temperature growth buffer layer of Al _x Ga _1-x N (0 ≦ x ≦ 1) was formed as a buffer layer in a thickness of 100 mm. Next, undoped GaN was deposited as the undoped first conductivity type layer, and Si doped GaN was deposited as the doped first conductivity type layer. In order to perform the evaluation, sapphire was taken out in this state.

  The first evaluation is void. In order to observe the void, the sapphire was cleaved, and the interface between the pattern and the CVD film formation layer was observed by a scanning electron microscope. The observation distance of one observation image was 5 μm, and observations were arbitrarily made at 10 locations, and a total length of 50 μm was observed. The number of voids in each observation image was counted and used as an evaluation value.

  The second evaluation was a process window in the CVD process. The condition that allows suitable film formation on one sapphire was used as a reference point. This condition is referred to as a basic condition. First, sapphire to be evaluated and dissimilar sapphire having a large pattern with respect to the sapphire were placed in a CVD chamber, and film formation was performed under basic conditions. At this time, the sapphire to be evaluated may be whitened. The degree of whitening was quantified and evaluated as the whitening rate. The whitening ratio is an area ratio and is an area ratio of a whitened region with respect to the main surface of the sapphire wafer. Next, the temperature difference (ΔT) until whitening was evaluated by changing the temperature stepwise from the basic conditions.

  As the doped first conductivity type layer, after forming Si-doped GaN, a strain absorption layer was provided. Thereafter, an active layer of a multiple quantum well was formed as an active layer. The active layer was composed of a well layer and a barrier layer composed of undoped InGaN and Si-doped GaN. In addition, the thicknesses of the layers were 25 mm and 130 mm, respectively, and the layers were alternately stacked so that there were 6 well layers and 7 barrier layers. On the active layer, Mg-doped AlGaN, undoped GaN, and Mg-doped GaN were stacked as a second conductivity type layer so as to include an electroblocking layer. Subsequently, an ITO film was formed and etched, and then an electrode pad was attached. The efficiency of the LED was evaluated by the light emission output when a current of 20 mA was passed between the p electrode pad and the n electrode pad using a prober. The evaluation results are shown in Table 3 below.

  Table 3 can be roughly divided into two. First, information on the sapphire pattern is posted on the left side of the table. Second, the evaluation results described above are posted on the right side of the table. In addition, how to read the evaluation result in Table 3 is as follows.

Void: From the influence on LED efficiency and long-term reliability, 50/50 μm or less is preferable, and 20/50 μm or less is more preferable.
Whitening rate: This means that a macro phenomenon called whitening occurs even if a small change is made only by placing different types of substrates. That is, a large whitening rate means that the process window is very narrow. Taking the LED yield into consideration, it is preferably 5% or less, and most preferably 0%.
ΔT: For example, when forming an undoped GaN film, the film formation temperature is about 1100 ° C. It means that even a fluctuation of about 10 ° C. with respect to such a high temperature has a great influence on the film formation. That is, the larger ΔT is better. In consideration of temperature fluctuation in the actual process, it is sufficient that ΔT is 25 ° C. or more.
LED efficiency: Patterned sapphire substrates are already on the market. This commercially available product is called PSS (Patterned Sapphire Substrate), and the pattern pitch is 3 μm to 6 μm. Other efficiencies were standardized with LED efficiencies when using PSS with a pitch of 3500 nm which is considered to be the most popular. It is important that the LED efficiency is greater than 1.
-Comprehensive symbol: Regarding the evaluation described above, a case where all the evaluations were favorable results was indicated as “◯”, and other cases were indicated as “X”.

  A part of the results in Table 3 is shown in the drawing. That is, FIG. 7 shows the relationship between the shortest length C of the recess bottom and the tilt angle Θ1, and FIG. 8 shows the relationship between the shortest length C of the recess bottom and the tilt angle Θ2. Note that the symbols on the graphs shown in FIG. 7 and FIG.

  As described above, from Table 3, FIG. 7, and FIG. 8, it has been found that there is a numerical range in which the void can be reduced and the process window of the CVD process can be enlarged by the shortest length C and the inclination angle Θ of the bottom of the recess. Specifically, it has been found that it is important that the minimum length C of the bottom of the recess satisfies 30 nm to 230 nm in the numerical range verified this time. Further, it was found that it is important for the inclination angle Θ1 to satisfy 64 ° to 86 ° in the numerical range verified this time. Further, it was found that it is important for the inclination angle Θ2 to satisfy 63 ° or more and 83 ° or less in the numerical range verified this time. That is, a pattern in which the shortest length C of the bottom of the recess satisfies 30 nm to 230 nm and a tilt angle Θ1 satisfies 64 ° to 86 °, and the shortest length C of the bottom of the recess satisfies 30 nm to 230 nm, and The pattern in which the inclination angle Θ2 satisfies 63 ° or more and 83 ° or less, or the shortest length C of the bottom of the recess satisfies 30 nm or more and 230 nm or less, the inclination angle Θ1 satisfies 64 ° or more and 86 ° or less, and the inclination angle Θ2 is By using an LED substrate having a pattern satisfying 63 ° or more and 83 ° or less, a CVD layer with reduced voids can be formed by enlarging the process window, and at the same time, the efficiency of the manufactured LED Can be said to improve. Moreover, by satisfying these ranges, an LED having excellent long-term reliability can be manufactured as the void is reduced.

  The reason why such a suitable numerical range expressed by the shortest length C and the inclination angle Θ of the bottom of the recess exists can be considered as follows.

  First, the shortest length C of the bottom of the recess has a strong influence on the nucleation to nucleation stages of the CVD process. When the shortest length C of the bottom of the recess is equal to or greater than a predetermined value, it is possible to realize the layer growth of the CVD film starting from the bottom of the recess. This increases the unity of crystal axes of the layer formed by CVD. That is, since it is possible to balance the growth of the pattern convex portion in the height direction and the growth of the convex portion in the radial direction, voids can be reduced. Furthermore, resistance to fluctuations in the conditions of the CVD process increases. On the other hand, when the shortest length C of the bottom of the recess is equal to or less than a predetermined value, the number of times of reflection inside the LED can be reduced when the light that is originally guided inside the LED is taken out of the LED. You can think that you can. Thereby, since attenuation | damping of light can be suppressed, light extraction efficiency LEE improves and LED efficiency improves.

  On the other hand, when the inclination angle Θ satisfies the predetermined range, the growth starting point of the layer formed by the CVD process is defined as the crystal plane, and growth from the convex side surface portion is suppressed. I can think of it. Thereby, since the growth starting from the bottom of the recess can be realized, the process window of the CVD process becomes large. In particular, it is presumed that the process window for the initial process of the CVD process, for example, the seed layer forming process, becomes larger when the tilt angle Θ1 satisfies the predetermined range. This is because the crystal plane on which the seed layer can be grown is defined by defining the rising angle of the side surface portion of the convex portion with respect to the bottom of the concave portion. Therefore, a seed layer is formed preferentially at the bottom of the recess, and the CVD film growth can be realized starting from this seed layer. Since this is a layer growth starting from the bottom of the recess, the process window of the CVD process is expanded. It can be considered that the process window for the flattening step for flattening the pattern becomes larger in the initial step of the CVD step when the inclination angle Θ2 satisfies the predetermined range. This is because, in the process of growing the nuclei generated by CVD film formation and flattening the pattern, the crystal plane of the CVD film layer with respect to the side surface part of the convex part can be defined. This is because the difference between the lattice constant of the layers can be increased. In other words, the CVD film-forming layer has a low affinity with the convex side surface portion. Therefore, layer growth starting from the bottom of the recess can be realized. Therefore, the enlargement of the process window of the CVD process is promoted.

  From Table 3, it can also be seen that there is a more suitable range when attention is paid to the reduction of voids. From this point of view, it was found that it is more important that the shortest length C of the bottom of the recess satisfies the range of 40 nm to 170 nm in the numerical range verified this time. As the inclination angle Θ1, it was found that it is more important to satisfy the range of 64 ° to 79 ° in the numerical range verified this time. As for the inclination angle Θ2, it was found that it is more important to satisfy the range of 63 ° to 78 ° in the numerical range verified this time.

  The range described here corresponds to the portion of FIG. 7 and FIG. 8 excluding the circle (●) that is blacked out. Furthermore, it has also been found that the void is further reduced when the shortest length C of the bottom of the recess is 80 nm or more. This corresponds to a portion excluding the black circle (●) and the hatched circle regarding the circle (◯) in FIGS. 7 and 8.

  Furthermore, the result of having examined the detailed pattern shape was described in Table 4 below. The numerical values in Table 4 correspond to the case where the dry etching conditions are changed and the inclination angle Θ3 is changed by using the case where the general symbol is “◯” regarding the examination of Table 3.

  From Table 4, it can be seen that a more favorable evaluation result can be obtained by adjusting the inclination angle Θ3. Specifically, if the inclination angle Θ3 is in the range of 22 ° to 38 ° within the numerical value demonstrated this time, the reduction of voids is further promoted. This can be considered because the interface stress between the layer formed by CVD and the pattern surface tends to be relaxed. On the other hand, it was found that the efficiency of the LED can be further improved when the inclination angle Θ3 satisfies the range of 63 ° to 77 °. This can be considered because the traveling direction of light is further optimized. More specifically, it can be considered that the number of times of reflection inside the LED decreases before the LED is taken out from the LED, and accordingly, the absorption attenuation becomes smaller.

The present invention relates to a substrate for a light-emitting element that can be used for a light-emitting element such as an LED, and in particular, by using the substrate for a light-emitting element of the present invention, a light-emitting element with high luminous efficiency and excellent long-term reliability is manufactured. it can. The light-emitting element is specifically an LED, an organic EL, or the like, but can be particularly effectively applied to an LED.

Claims (6)

A substrate for a light emitting device comprising a pattern composed of convex portions and concave portions,
The pattern has the recess having the shortest length C of the bottom of the recess of 30 nm or more and less than 300 nm, and the inclination angle Θ1 of the side wall starting from the recess bottom adjacent to the protrusion is 63 ° or more and 86 ° or less. A substrate for a light emitting element, comprising the convex portion satisfying the above.   The light emitting element substrate according to claim 1, wherein the inclination angle Θ <b> 1 is not less than 63 ° and not more than 79 °.   3. The light emitting device according to claim 1, further comprising the convex portion satisfying an inclination angle Θ <b> 2 of a side wall at a position of 40% of the height of the convex portion of 63 ° or more and 86 ° or less. Substrate. A substrate for a light emitting device comprising a pattern composed of convex portions and concave portions,
The pattern has the concave portion in which the shortest length C of the concave bottom portion is 30 nm or more and less than 300 nm, and the inclination angle Θ2 of the side wall at a position of 40% of the height of the convex portion is 63 ° or more and 86 ° or less. A substrate for a light-emitting element, characterized by having the convex portion that fills.   The substrate for a light emitting element according to claim 4, wherein the inclination angle Θ2 is 63 ° or more and 79 ° or less. The light emitting device substrate according to claim 1, further comprising at least a first conductivity type layer, a light emitting layer, and a second conductivity type layer on the pattern side. Light emitting element.

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