JP2016136564A - Manufacturing method of semiconductor element mounting substrate - Google Patents

Manufacturing method of semiconductor element mounting substrate Download PDF

Info

Publication number
JP2016136564A
JP2016136564A JP2015010936A JP2015010936A JP2016136564A JP 2016136564 A JP2016136564 A JP 2016136564A JP 2015010936 A JP2015010936 A JP 2015010936A JP 2015010936 A JP2015010936 A JP 2015010936A JP 2016136564 A JP2016136564 A JP 2016136564A
Authority
JP
Japan
Prior art keywords
etching
plating
metal plate
mask
etching mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2015010936A
Other languages
Japanese (ja)
Other versions
JP6418601B2 (en
Inventor
高橋 俊弘
Toshihiro Takahashi
俊弘 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SH Materials Co Ltd
Original Assignee
SH Materials Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SH Materials Co Ltd filed Critical SH Materials Co Ltd
Priority to JP2015010936A priority Critical patent/JP6418601B2/en
Publication of JP2016136564A publication Critical patent/JP2016136564A/en
Application granted granted Critical
Publication of JP6418601B2 publication Critical patent/JP6418601B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor element mounting substrate that facilitates control of half etching.SOLUTION: A manufacturing method includes the steps of: forming a first etching mask 5 that covers a portion to be resin-sealed while excluding a penetration portion on a front side to which plating 4 is applied, and forming a first etching mask 5 for covering the plating and applying half etching from a rear side while excluding the penetration portion at the rear side; performing first etching processing from the rear side in a portion where half etching is applied from both sides in the penetration portion; sticking a film 6 to the rear side to which the half etching processing has been applied, and forming a second etching mask 7 for covering the plating at the front side and applying etching from the front side; performing second etching processing from the front side in a portion where the second etching mask is formed at the front side and the film is stuck at the rear side; and exfoliating the second etching mask at the front side after the second etching processing.SELECTED DRAWING: Figure 1

Description

本発明は、ハーフエッチングのコントロールを容易にするとともに不要箇所にめっきを施す必要をなくした半導体素子搭載用基板の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor element mounting substrate that facilitates half-etching control and eliminates the need for plating unnecessary portions.

特許文献1として示す特開2011−181964号公報には、金属板の両面にレジストによるめっきマスクを形成してめっきを施し、めっきマスクを剥離した後、リードフレーム形状を形成するためにレジストによるエッチングマスクを金属板の両面に形成し、両面からハーフエッチング加工を行なって、金属板の厚さ方向の中央付近に極薄の金属部分を残すことで、パッド部やリード部の相対位置関係を確保し、粘着テープを貼着けた後に、前記極薄の金属部分をエッチング加工によって溶解除去する技術が記載されている。   In Japanese Patent Application Laid-Open No. 2011-181964 shown as Patent Document 1, a resist plating mask is formed on both surfaces of a metal plate, plating is performed, and after the plating mask is peeled off, etching with a resist is performed to form a lead frame shape. A mask is formed on both sides of the metal plate, half-etching is performed from both sides, and an extremely thin metal part is left near the center of the metal plate in the thickness direction, ensuring the relative positional relationship between the pad and lead. In addition, a technique is described in which after the adhesive tape is attached, the ultrathin metal portion is dissolved and removed by etching.

特開2011−181964号公報JP 2011-181964 A

しかし、特許文献1に示すような金属板の両面からハーフエッチング加工を行なって金属板の厚さ方向の中央付近に極薄の金属部分を残す工程の場合、ハーフエッチング加工を行うに際して平面上で面積が広い部位と狭い部位で残す極薄の金属部分の厚さが等しくなるようにコントロールすることは非常に難しく、量産には不向きであるという問題点があった。そして極薄の金属部分が貫通してしまった場合には、その部分の相対位置関係が崩れてしまい、設計上の位置と異なる位置を粘着テープで固定することになり、不良品を生産することになる問題もあった。   However, in the process of performing half-etching from both sides of a metal plate as shown in Patent Document 1 and leaving an extremely thin metal portion near the center in the thickness direction of the metal plate, when performing half-etching, on the plane There is a problem that it is very difficult to control the thickness of the ultra-thin metal portion left in the wide area and the narrow area to be equal, and it is not suitable for mass production. And if an extremely thin metal part penetrates, the relative positional relationship of that part will collapse, and the position different from the design position will be fixed with adhesive tape, producing defective products There was also a problem.

また、めっき層をエッチングレジストとして使用するためには本来必要でないパイロットホール周辺部分までめっきを施す必要があり、その上エッチング加工に耐えるようにするためにはエッチングに耐え得る高価なめっきを厚く付ける必要もあることから、めっきコストが上昇してしまうという問題もあった。加えてめっき層をエッチング加工に耐えるように厚くすると、より強固で丈夫なめっきバリがエッチング後に発生してしまう事になり、このめっきバリの除去に余分なコストが発生するばかりか、除去することが不可能なめっきバリの発生も想定され歩留まりに大きく影響してしまうという問題もあった。   In addition, in order to use the plating layer as an etching resist, it is necessary to perform plating up to a pilot hole peripheral portion which is not originally necessary. In addition, in order to withstand etching processing, an expensive plating that can withstand etching is thickened. There is also a problem that the plating cost increases because it is necessary. In addition, if the plating layer is made thick enough to withstand the etching process, a stronger and stronger plating burr will be generated after etching, which will not only cause extra cost for removing this plating burr, but also remove it. However, there is also a problem that the yield is greatly affected by the occurrence of plating burrs that cannot be achieved.

本発明は、この様な問題点を解決するためになされたものであり、その目的とするところは、ハーフエッチングのコントロールを容易にするとともに不要箇所にめっきを施す必要をなくした半導体素子搭載用基板の製造方法を提供することである。   The present invention has been made in order to solve such problems, and the object of the present invention is to mount a semiconductor element that facilitates half-etching control and eliminates the need for plating unnecessary portions. It is to provide a method for manufacturing a substrate.

上記の目的を達成するため、本発明の半導体素子搭載用基板の製造方法は、金属板の両面にめっきマスクを形成し、露出した前記金属板に必要なめっきを施す工程と、前記めっきマスクを剥離し、前記金属板の半導体素子を搭載することとなる表面側に貫通部分となる部分を除いて半導体装置として樹脂封止される部分を覆う所望形状の第一のエッチングマスクを形成するとともに、前記金属板の裏面側に前記貫通部分となる部分を除いて前記めっきを覆い且つ前記金属板の裏面側からハーフエッチングを施すための所望形状の第一のエッチングマスクを形成する工程と、前記第一のエッチングマスク形成後、前記貫通部分となる部分については前記金属板の両側から、前記ハーフエッチングを施す部分については前記金属板の裏面側から第一のエッチング加工を行なう工程と、前記第一のエッチング加工後、前記金属板の両面に形成した前記第一のエッチングマスクを剥離し、前記ハーフエッチング加工を施した前記金属板の裏面側には接着層を有するフィルムを貼付け、前記金属板の表面側は前記めっきを覆い且つ前記金属板に表面側からエッチングを施すための所望形状の第二のエッチングマスクを形成する工程と、表面側に前記第二のエッチングマスクが形成され、裏面側に前記フィルムが貼付けられた前記金属板の表面側から第二のエッチング加工を行う工程と、前記第二のエッチング加工後、前記金属板の表面側の第二のエッチングマスクを剥離する工程を含むことを特徴とするとする。   In order to achieve the above object, a method for manufacturing a substrate for mounting a semiconductor element according to the present invention includes a step of forming a plating mask on both surfaces of a metal plate, and applying the necessary plating to the exposed metal plate; A first etching mask having a desired shape is formed to cover the portion to be resin-sealed as a semiconductor device except for a portion that becomes a penetrating portion on the surface side where the semiconductor element of the metal plate is to be peeled off, Forming a first etching mask having a desired shape for covering the plating except for a portion serving as the penetrating portion on the back surface side of the metal plate and performing half etching from the back surface side of the metal plate; After forming one etching mask, the portion to be the penetrating portion is from both sides of the metal plate, and the portion to be half-etched is from the back side of the metal plate. And after the first etching process, the first etching mask formed on both surfaces of the metal plate is peeled off and bonded to the back side of the metal plate subjected to the half etching process. Attaching a film having a layer, forming a second etching mask having a desired shape for covering the plating on the surface side of the metal plate and etching the metal plate from the surface side; and A second etching mask is formed, and a second etching process is performed from the surface side of the metal plate with the film pasted on the back surface side; The method includes a step of removing the second etching mask.

また、本発明の半導体素子搭載用基板の製造方法においては、前記めっきマスクおよび前記第一と第二のエッチングマスクはレジストにより形成し、前記接着層を有するフィルムはポリイミドフィルムであることが好ましい。   Moreover, in the manufacturing method of the board | substrate for semiconductor element mounting of this invention, it is preferable that the said plating mask and said 1st and 2nd etching mask are formed with a resist, and the film which has the said contact bonding layer is a polyimide film.

本発明の半導体素子搭載用基板の製造方法によれば、ハーフエッチングのコントロールが容易となり、めっきバリの発生もなく、各部の相対位置関係が崩れることなく設計上の位置に固定された半導体素子搭載用基板を得ることが可能となる。またドライフィルムレジストによるエッチングマスクによって端子形状を形成するため、不要箇所にめっきを施す必要がなくなり、エッチング加工後のめっきバリの発生も無くなる。   According to the method for manufacturing a substrate for mounting semiconductor elements of the present invention, half-etching can be easily controlled, plating burrs are not generated, and the relative positional relationship between the respective parts is not disturbed. A substrate for use can be obtained. Further, since the terminal shape is formed by an etching mask made of dry film resist, it is not necessary to perform plating on unnecessary portions, and generation of plating burrs after etching processing is eliminated.

本発明の半導体素子搭載用基板の製造方法を工程順に示した説明図である。(a)は、金属板1の両面にレジスト層2を形成した後、露光・現像を行ってめっきマスク3を形成し、めっきマスク3から露出した金属板1にめっき4を形成した時の断面図である。(b)は、両面のめっきマスク3を剥離し、再び両面にレジスト層2を形成した後、露光・現像を行って、第一のエッチングマスク5を形成し、第一のエッチング加工を行って貫通形状10とハーフエッチング形状を形成した時の断面図である。(c)は、両面の第一のエッチングマスク5を剥離し、表面側にレジスト層2を形成した後、露光・現像を行って第二のエッチングマスク7を形成し、裏面側に接着層を有するフィルム6を貼付けた時の断面図である。(d)は、第二のエッチングマスク7から露出している金属板1を表面側から第二のエッチング加工した時の断面図である。(e)は、第二のエッチングマスク7を剥離して得られた、半導体素子搭載用基板の断面図である。It is explanatory drawing which showed the manufacturing method of the board | substrate for semiconductor element mounting of this invention in order of the process. (A) is a cross section when the resist layer 2 is formed on both surfaces of the metal plate 1 and then exposed and developed to form the plating mask 3, and the plating 4 is formed on the metal plate 1 exposed from the plating mask 3. FIG. (B) peels the plating masks 3 on both sides, forms the resist layer 2 on both sides again, and then performs exposure and development to form the first etching mask 5 and performs the first etching process. It is sectional drawing when the penetration shape 10 and a half etching shape are formed. (C) After peeling the first etching mask 5 on both sides and forming the resist layer 2 on the front surface side, exposure and development are performed to form the second etching mask 7 and an adhesive layer is formed on the back surface side. It is sectional drawing when the film 6 which has is stuck. (D) is sectional drawing when the metal plate 1 exposed from the 2nd etching mask 7 carries out the 2nd etching process from the surface side. (E) is sectional drawing of the board | substrate for semiconductor element mounting obtained by peeling the 2nd etching mask 7. FIG. 本発明の方法により製造された半導体素子搭載用基板を用いて半導体装置を製造する工程を示した説明図である。It is explanatory drawing which showed the process of manufacturing a semiconductor device using the board | substrate for semiconductor element mounting manufactured by the method of this invention.

次に、本発明の半導体素子搭載用基板の製造方法を図1に基づいて説明する。
まず、図1(a)に示すように金属板1の両面にレジスト層2を形成し、そのレジスト層2で、めっきを形成するためのめっきマスク3を形成する。
Next, the manufacturing method of the semiconductor element mounting substrate of this invention is demonstrated based on FIG.
First, as shown in FIG. 1A, a resist layer 2 is formed on both surfaces of a metal plate 1, and a plating mask 3 for forming plating is formed with the resist layer 2.

そして、必要なめっき加工を行なってめっき4形成後、両面に形成しためっきマスク3を剥離する。   Then, after the necessary plating process is performed to form the plating 4, the plating mask 3 formed on both surfaces is peeled off.

次に、図1(b)に示すようにめっき4が形成された金属板1の両面に再びレジスト層2を形成し、両面に第一のエッチングマスク5を形成する。表面側の第一のエッチングマスク5は、パイロットホール等の一部の貫通形状10が形成されるように形成する。また裏面側の第一のエッチングマスク5は、パイロットホール等の一部の貫通形状に加えて、半導体素子搭載用基板として必要なパターンが形成されるように形成する。   Next, as shown in FIG. 1B, a resist layer 2 is formed again on both surfaces of the metal plate 1 on which the plating 4 is formed, and a first etching mask 5 is formed on both surfaces. The first etching mask 5 on the surface side is formed so that a part of the penetrating shape 10 such as a pilot hole is formed. The first etching mask 5 on the back side is formed so as to form a pattern necessary for a substrate for mounting a semiconductor element, in addition to a part of the penetrating shape such as a pilot hole.

この時、裏面側の第一のエッチングマスク5は、次工程のエッチング加工によってめっき直下の金属板がエッチングされてめっきバリが発生することがないよう、先に形成しためっき4を十分に覆った形状のエッチングマスクとなるように形成する。   At this time, the first etching mask 5 on the back side sufficiently covered the previously formed plating 4 so that the metal plate directly under the plating was not etched by the etching process of the next step and plating burrs were not generated. A shape etching mask is formed.

そして、第一のエッチング加工を行なう。このとき、貫通形状10の部分については一部または全部を両面からエッチングを行って形成する。また、裏面側は半導体素子搭載用基板として必要な形状が残るようハーフエッチングを行う。この裏面側のハーフエッチング深さ(距離)は、金属板の厚さの55〜80%程度をエッチング処理することが望ましい。ハーフエッチングは片面側(裏面側)のみから行うようにしているため、エッチング深さのコントロールが両面から同時にエッチングする場合と比べ飛躍的に容易となる。   Then, a first etching process is performed. At this time, part or all of the portion of the penetrating shape 10 is formed by etching from both sides. In addition, half etching is performed on the back surface side so that a shape necessary for a semiconductor element mounting substrate remains. As for the half etching depth (distance) on the back surface side, it is desirable to etch about 55 to 80% of the thickness of the metal plate. Since half etching is performed only from one side (back side), the control of the etching depth is greatly facilitated as compared to the case where etching is performed simultaneously from both sides.

次に、図1(c)に示すように両側の第一のエッチングマスク5を剥離する。そして、ハーフエッチングした裏面側全体に接着層を有するフィルム6を貼り付ける。また、表面側はレジスト層2を形成し、先に形成した貫通形状10はエッチング加工されないように覆って、半導体素子搭載用基板として必要な形状を得るための第二のエッチングマスク7を形成する。   Next, as shown in FIG. 1C, the first etching masks 5 on both sides are peeled off. And the film 6 which has a contact bonding layer is affixed on the whole back side by which half etching was carried out. Further, a resist layer 2 is formed on the surface side, and the previously formed through shape 10 is covered so as not to be etched, and a second etching mask 7 for obtaining a shape necessary as a semiconductor element mounting substrate is formed. .

次に、図1(d)に示すように表面側から第二のエッチング加工を行なうと、フィルム6に貼り付いた半導体素子搭載用基板が得られる。   Next, when a second etching process is performed from the surface side as shown in FIG. 1D, a semiconductor element mounting substrate attached to the film 6 is obtained.

次に、図1(e)に示すように表面側の第二のエッチングマスク7を剥離することで目的とする半導体素子搭載用基板を得ることができる。   Next, as shown in FIG. 1E, the target semiconductor element mounting substrate can be obtained by removing the second etching mask 7 on the surface side.

金属板1として厚さが0.127mmの銅材を用いて、両面にドライフィルムレジスト(旭化成イーマテリアルズ株式会社:AQ−2058)を貼り付け、レジスト層2を形成した。   Using a copper material having a thickness of 0.127 mm as the metal plate 1, a dry film resist (Asahi Kasei E-Materials Co., Ltd .: AQ-2058) was pasted on both sides to form a resist layer 2.

次に、めっき4を形成するためのパターンが形成された表面側用と裏面側用のガラスマスクを用いて、露光・現像を行うことで、めっき4を形成する部分のレジストを除去して部分的に金属板表面を露出させためっきマスク3を形成した。   Next, by performing exposure and development using the glass mask for the front side and the back side on which the pattern for forming the plating 4 is formed, the resist in the part where the plating 4 is formed is removed. Thus, the plating mask 3 with the metal plate surface exposed was formed.

次に、めっき加工を行なって金属板表面の露出部分にめっき4を形成した。本実施例では、金属板表面側から順に、設定値1.0μmのNiめっき、設定値0.05μmのPdめっき、設定値0.02μmのAuめっきを施して、3層のめっき4を形成した。(図1(a)参照。)   Next, the plating process was performed and the plating 4 was formed in the exposed part of the metal plate surface. In this example, Ni plating with a set value of 1.0 μm, Pd plating with a set value of 0.05 μm, and Au plating with a set value of 0.02 μm were applied in order from the metal plate surface side to form three layers of plating 4. . (See FIG. 1 (a).)

次に、金属板1の両面に形成されているめっきマスク3を3%の水酸化ナトリウム水溶液により剥離し、更に3%の硫酸による洗浄処理を行なった。   Next, the plating mask 3 formed on both surfaces of the metal plate 1 was peeled off with a 3% aqueous sodium hydroxide solution, and further washed with 3% sulfuric acid.

次に、めっき4が形成された金属板1の両面にドライフィルムレジスト(旭化成イーマテリアルズ株式会社:AQ−4096)を貼り付け、レジスト層2を形成し、貫通形状10部分のみのパターンが形成された表面側用と貫通形状10部分に加えて半導体素子搭載用基板のパターンが形成された裏面側用のガラスマスクを用いて、露光・現像を行なって第一のエッチングマスク5を形成した。   Next, a dry film resist (Asahi Kasei E-Materials Co., Ltd .: AQ-4096) is pasted on both surfaces of the metal plate 1 on which the plating 4 is formed, and the resist layer 2 is formed, thereby forming a pattern only for the through shape 10 part. The first etching mask 5 was formed by performing exposure and development using the glass mask for the front surface side and the back side glass pattern on which the pattern of the substrate for mounting the semiconductor element was formed in addition to the 10 portions of the through shape.

この時、半導体素子が搭載される表面側の第一のエッチングマスク5は、パイロットホール等の一部の貫通孔を形成する部分以外を除いて全面を覆うエッチングマスクとなるように形成する。また、裏面側の第一のエッチングマスク5は、貫通孔に加えて半導体素子搭載用基板を得るために必要なパターンであって、先に形成しためっき4を覆うエッチングマスクとなるように形成する。なお、この「めっきを覆うエッチングマスク」とは、エッチング加工によってめっきバリが発生しないようにするために、めっき直下の銅材がエッチングされないで残るのに必要な距離を有するエッチングマスクのことである。   At this time, the first etching mask 5 on the surface side on which the semiconductor element is mounted is formed so as to be an etching mask that covers the entire surface except for a part that forms a part of the through hole such as a pilot hole. Further, the first etching mask 5 on the back surface side is a pattern necessary for obtaining a semiconductor element mounting substrate in addition to the through hole, and is formed so as to be an etching mask covering the previously formed plating 4. . The “etching mask covering the plating” refers to an etching mask having a distance necessary for the copper material immediately under the plating to remain without being etched in order to prevent plating burrs from being generated by the etching process. .

次に、塩化第二鉄液を用いてスプレーエッチング加工により第一のエッチング加工を行った。このとき、貫通形状10部分については両面からエッチング加工をした。また、半導体素子搭載用基板を得るために必要なパターンについては裏面側からエッチングマスク5の開口部が0.095〜0.10mmの深さのハーフエッチングとなるようにエッチング加工をした。ハーフエッチング加工は裏面側のみから行うようにしているため、エッチング深さのコントロールが容易となる。(図1(b)参照。)   Next, the 1st etching process was performed by the spray etching process using the ferric chloride liquid. At this time, the penetration shape 10 portion was etched from both sides. The pattern necessary for obtaining the semiconductor element mounting substrate was etched so that the opening of the etching mask 5 was half-etched with a depth of 0.095 to 0.10 mm from the back side. Since the half etching process is performed only from the back side, the etching depth can be easily controlled. (See FIG. 1 (b).)

この第一のエッチング加工は、液温70℃、比重1.47の塩化第二鉄液を用い、搖動するスプレーノズルによって0.3MPaの設定圧力で噴射させ、約110秒間の処理を行なった。   In this first etching process, a ferric chloride solution having a liquid temperature of 70 ° C. and a specific gravity of 1.47 was used, sprayed at a set pressure of 0.3 MPa by a peristaltic spray nozzle, and the treatment was performed for about 110 seconds.

その後、水酸化ナトリウム水溶液を用いて両面の第一のエッチングマスク5を剥離し、硫酸による酸処理を行った。   Then, the 1st etching mask 5 of both surfaces was peeled using sodium hydroxide aqueous solution, and the acid treatment with a sulfuric acid was performed.

次に、ハーフエッチングされた裏面側の全体に接着層付きのポリイミドテープ(INNOX 05F)6を貼り付けた。貼り付けは、加圧ローラーを用いて、搬送速度1.0m/min.で貼り付けた。   Next, a polyimide tape (INNOX 05F) 6 with an adhesive layer was attached to the entire back side subjected to half etching. Affixing is performed using a pressure roller at a conveyance speed of 1.0 m / min. Pasted with.

表面側は、ドライフィルムレジスト(旭化成イーマテリアルズ株式会社:AQ−4096)を貼り付け、貫通形状10として形成したパイロットホールを基準位置として使用して、半導体素子搭載用基板のパターンが形成されたガラスマスクを用いて、露光・現像を行い、第二のエッチングマスク7を形成した。(図1(c)参照。)   On the surface side, a dry film resist (Asahi Kasei E-Materials Co., Ltd .: AQ-4096) was applied, and the pattern of the semiconductor element mounting substrate was formed using the pilot hole formed as the through shape 10 as a reference position. Exposure and development were performed using a glass mask to form a second etching mask 7. (See FIG. 1 (c).)

次に、前述と同様の塩化第二鉄液を用いて約20秒間の第二のエッチング加工を行なった。(図1(d)参照。)   Next, a second etching process was performed for about 20 seconds using the same ferric chloride solution as described above. (See FIG. 1 (d).)

このとき、既に形成した貫通形状10について、表面側はドライフィルムレジストにより覆われた第二のエッチングマスク7により、裏面側はポリイミドテープ6によりそれぞれ覆われているので、貫通形状10の部分が再びエッチング加工されることはない。また、表面側の第二のエッチングマスク7は、「めっきを覆うエッチングマスク」となるようにしているので、エッチング加工によってめっきバリが発生しないように、めっき直下の銅材がエッチングされないで残るのに必要な距離を有するエッチングマスクとなっている。   At this time, since the surface shape side of the already formed through shape 10 is covered with the second etching mask 7 covered with the dry film resist and the back surface side is covered with the polyimide tape 6, the portion of the through shape 10 is again formed. It is not etched. Further, since the second etching mask 7 on the surface side becomes an “etching mask covering the plating”, the copper material immediately below the plating remains without being etched so that no plating burr is generated by the etching process. Thus, the etching mask has a necessary distance.

次に、第二のエッチングマスク7の剥離処理を行い、後洗浄を行なった。これらの加工を行なうことで、裏面側にポリイミドテープ6が貼り付けられた半導体素子搭載用基板を得ることができた。(図1(e)参照。)   Next, the second etching mask 7 was stripped and post-cleaning was performed. By performing these processes, it was possible to obtain a semiconductor element mounting substrate in which the polyimide tape 6 was adhered to the back side. (See FIG. 1 (e).)

上記の通り本発明の製造方法では、ハーフエッチング加工が片面側から行なわれるのでエッチング深さのコントロールが容易となり、ハーフエッチング部分が貫通してしまうことがないためパッド部やリード部の相対位置関係が崩れる問題がない。また、パイロットホールは両面からの1回のエッチング加工で形成されるため寸法変化もないことから、寸法的に安定した半導体素子搭載用基板を得ることができる。   As described above, in the manufacturing method of the present invention, since the half etching process is performed from one side, the etching depth can be easily controlled, and the half etching part does not penetrate, so the relative positional relationship between the pad part and the lead part. There is no problem that collapses. In addition, since the pilot hole is formed by one etching process from both sides, there is no dimensional change, so that a dimensionally stable substrate for mounting a semiconductor element can be obtained.

なお、本発明の方法により製造された半導体素子搭載用基板を用いて半導体装置を製造する場合は、図2(a)に示すようにパッド部11に半導体素子12を搭載し、半導体素子12とリード部13とを電気的に接続し、パッド部11、半導体素子12及びリード部13を樹脂封止し、樹脂封止体14を形成する。そして、図2(b)に示すようにポリイミドテープ6を剥離除去する。その後、図2(c)に示すように、個々の半導体装置に切断する。樹脂封止後にポリイミドテープ6を剥離除去するため、パッド部11やリード部13の相対位置が正確に保たれることとなる。   When a semiconductor device is manufactured using a semiconductor element mounting substrate manufactured by the method of the present invention, the semiconductor element 12 is mounted on the pad portion 11 as shown in FIG. The lead part 13 is electrically connected, and the pad part 11, the semiconductor element 12 and the lead part 13 are resin-sealed to form a resin sealing body 14. Then, as shown in FIG. 2B, the polyimide tape 6 is peeled and removed. Thereafter, as shown in FIG. 2C, the semiconductor device is cut into individual semiconductor devices. Since the polyimide tape 6 is peeled and removed after the resin sealing, the relative positions of the pad portion 11 and the lead portion 13 are accurately maintained.

1・・・金属板
2・・・レジスト層
3・・・めっきマスク
4・・・めっき
5・・・第一のエッチングマスク
6・・・接着層を有するフィルム(ポリイミドテープ)
7・・・第二のエッチングマスク
10・・・貫通形状
11・・・パッド部
12・・・半導体素子
13・・・リード部
14・・・樹脂封止体
DESCRIPTION OF SYMBOLS 1 ... Metal plate 2 ... Resist layer 3 ... Plating mask 4 ... Plating 5 ... 1st etching mask 6 ... Film which has an adhesive layer (polyimide tape)
7 ... Second etching mask 10 ... Through shape 11 ... Pad part 12 ... Semiconductor element 13 ... Lead part 14 ... Resin sealing body

Claims (2)

金属板の両面にめっきマスクを形成し、露出した前記金属板に必要なめっきを施す工程と、
前記めっきマスクを剥離し、前記金属板の半導体素子を搭載することとなる表面側に貫通部分となる部分を除いて半導体装置として樹脂封止される部分を覆う所望形状の第一のエッチングマスクを形成するとともに、前記金属板の裏面側に前記貫通部分となる部分を除いて前記めっきを覆い且つ前記金属板の裏面側からハーフエッチングを施すための所望形状の第一のエッチングマスクを形成する工程と、
前記第一のエッチングマスク形成後、前記貫通部分となる部分については前記金属板の両側から、前記ハーフエッチングを施す部分については前記金属板の裏面側から第一のエッチング加工を行なう工程と、
前記第一のエッチング加工後、前記金属板の両面に形成した前記第一のエッチングマスクを剥離し、前記ハーフエッチング加工を施した前記金属板の裏面側には接着層を有するフィルムを貼付け、前記金属板の表面側は前記めっきを覆い且つ前記金属板に表面側からエッチングを施すための所望形状の第二のエッチングマスクを形成する工程と、
表面側に前記第二のエッチングマスクが形成され、裏面側に前記フィルムが貼付けられた前記金属板の表面側から第二のエッチング加工を行う工程と、
前記第二のエッチング加工後、前記金属板の表面側の第二のエッチングマスクを剥離する工程を含むことを特徴とする半導体素子搭載用基板の製造方法。
Forming a plating mask on both surfaces of the metal plate, and applying the necessary plating to the exposed metal plate;
A first etching mask having a desired shape covering the portion to be resin-sealed as a semiconductor device excluding the portion to be a through portion on the surface side where the plating element is peeled off and the semiconductor element of the metal plate is mounted. Forming a first etching mask having a desired shape for forming a half-etching from the back side of the metal plate, covering the plating except for a portion to be the through portion on the back side of the metal plate When,
After the first etching mask is formed, a step of performing a first etching process from the both sides of the metal plate for the portion to be the through portion, and a portion to be half-etched from the back side of the metal plate;
After the first etching process, the first etching mask formed on both surfaces of the metal plate is peeled off, and a film having an adhesive layer is pasted on the back side of the metal plate subjected to the half etching process, Forming a second etching mask having a desired shape for covering the plating on the surface side of the metal plate and etching the metal plate from the surface side;
A step of performing a second etching process from the surface side of the metal plate in which the second etching mask is formed on the front side and the film is attached to the back side;
A method of manufacturing a substrate for mounting a semiconductor element, comprising the step of peeling off the second etching mask on the surface side of the metal plate after the second etching process.
前記めっきマスクおよび前記第一と第二のエッチングマスクはレジストにより形成し、前記接着層を有するフィルムはポリイミドフィルムであることを特徴とする請求項1に記載の半導体素子搭載用基板の製造方法。
2. The method for manufacturing a substrate for mounting a semiconductor element according to claim 1, wherein the plating mask and the first and second etching masks are formed of a resist, and the film having the adhesive layer is a polyimide film.
JP2015010936A 2015-01-23 2015-01-23 Manufacturing method of semiconductor device mounting substrate Active JP6418601B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2015010936A JP6418601B2 (en) 2015-01-23 2015-01-23 Manufacturing method of semiconductor device mounting substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015010936A JP6418601B2 (en) 2015-01-23 2015-01-23 Manufacturing method of semiconductor device mounting substrate

Publications (2)

Publication Number Publication Date
JP2016136564A true JP2016136564A (en) 2016-07-28
JP6418601B2 JP6418601B2 (en) 2018-11-07

Family

ID=56512723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015010936A Active JP6418601B2 (en) 2015-01-23 2015-01-23 Manufacturing method of semiconductor device mounting substrate

Country Status (1)

Country Link
JP (1) JP6418601B2 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07211836A (en) * 1994-01-19 1995-08-11 Sony Corp Lead frame and its manufacture
JP2004319816A (en) * 2003-04-17 2004-11-11 Fujitsu Ltd Lead frame and its manufacturing method
JP2006210807A (en) * 2005-01-31 2006-08-10 Mitsui High Tec Inc Method for manufacturing semiconductor device
JP2007227503A (en) * 2006-02-22 2007-09-06 Sanyo Electric Co Ltd Plate member, and manufacturing process of circuit device employing it
JP2009302095A (en) * 2008-06-10 2009-12-24 Seiko Epson Corp Semiconductor device and method for manufacturing the same
JP2010192695A (en) * 2009-02-18 2010-09-02 Mitsui High Tec Inc Methods of manufacturing semiconductor device and lead frame of the same
JP2011181964A (en) * 2001-06-19 2011-09-15 Sumitomo Metal Mining Co Ltd Lead frame, and manufacturing method therefor

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07211836A (en) * 1994-01-19 1995-08-11 Sony Corp Lead frame and its manufacture
JP2011181964A (en) * 2001-06-19 2011-09-15 Sumitomo Metal Mining Co Ltd Lead frame, and manufacturing method therefor
JP2004319816A (en) * 2003-04-17 2004-11-11 Fujitsu Ltd Lead frame and its manufacturing method
JP2006210807A (en) * 2005-01-31 2006-08-10 Mitsui High Tec Inc Method for manufacturing semiconductor device
JP2007227503A (en) * 2006-02-22 2007-09-06 Sanyo Electric Co Ltd Plate member, and manufacturing process of circuit device employing it
JP2009302095A (en) * 2008-06-10 2009-12-24 Seiko Epson Corp Semiconductor device and method for manufacturing the same
JP2010192695A (en) * 2009-02-18 2010-09-02 Mitsui High Tec Inc Methods of manufacturing semiconductor device and lead frame of the same

Also Published As

Publication number Publication date
JP6418601B2 (en) 2018-11-07

Similar Documents

Publication Publication Date Title
JP6362111B2 (en) Lead frame manufacturing method
JPS5826828B2 (en) Manufacturing method of tape carrier
JP4670931B2 (en) Lead frame
JP2016021515A (en) Lead frame for semiconductor device and manufacturing method of lead frame
JP4620584B2 (en) Circuit member manufacturing method
JP6418601B2 (en) Manufacturing method of semiconductor device mounting substrate
JP6214431B2 (en) LED lead frame
CN111163590B (en) Manufacturing method of pure copper circuit
JP5299411B2 (en) Lead frame manufacturing method
JP6320879B2 (en) Mask for printing and manufacturing method thereof
JP6489615B2 (en) Semiconductor element mounting substrate, semiconductor device and manufacturing method thereof
JP6644978B2 (en) Semiconductor element mounting substrate, semiconductor device, and manufacturing method thereof
JP6615654B2 (en) Semiconductor element mounting substrate, semiconductor device, semiconductor element mounting substrate manufacturing method, and semiconductor device manufacturing method
JP6156745B2 (en) Lead frame for semiconductor device and manufacturing method thereof
JP2003078076A (en) Semiconductor device and manufacturing method therefor
JP2014138155A (en) Semiconductor element mounting substrate and semiconductor device
JP6626639B2 (en) Method of manufacturing substrate for semiconductor device
JP2018029214A (en) Semiconductor device and semiconductor device manufacturing method
JP2013042187A (en) Semiconductor device
JP6460407B2 (en) Semiconductor element mounting substrate, semiconductor device and manufacturing method thereof
JP5098452B2 (en) Manufacturing method of semiconductor device
JP2008186869A (en) Lead frame and its manufacturing method
JP6380805B2 (en) Semiconductor element mounting substrate, semiconductor device and manufacturing method thereof
JPH10135387A (en) Manufacturing method of lead frame
JP6056472B2 (en) Lead frame manufacturing method, semiconductor device manufacturing method, lead frame, and semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170413

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20180117

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20180227

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20180315

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180404

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180511

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20180525

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20180911

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20181003

R150 Certificate of patent or registration of utility model

Ref document number: 6418601

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350