JP2016131339A - Clock generation device, clock generation module, and clock source selection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock generation device capable of automatically discriminating between a passive drive type and an active drive type of a connected oscillator.SOLUTION: A clock generation device comprises: a first terminal connected with a vibrator or a predetermined potential; a second terminal connected with the vibrator or an oscillator; a first clock signal generator that generates a first clock signal on the basis of a signal from the first terminal; a second clock signal generator that generates a second clock signal on the basis of a signal from the second terminal; an output part that outputs the first clock signal or the second clock signal as a master clock signal; and a counter that counts the number of pulses of the master clock signal. In a case where a count value does not reach a predetermined value within a predetermined period of time, the first terminal and the first clock signal generator are connected with each other, and the first clock signal is outputted as the master clock signal. In a case where the count value reaches the predetermined value within the predetermined period of time, the second terminal and the second clock signal generator are connected with each other, and the second clock signal is outputted as the master clock signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a clock generation device, a clock generation module, and a clock source selection method.

  As a clock generator that generates a clock signal based on an oscillation signal from an oscillator, it is possible to connect two oscillators with different accuracy, and switch the connection of internal circuits according to the type of the connected oscillator to generate a clock signal The thing which made it do is proposed (for example, refer patent document 1). In such a device, the connection of internal circuits is selectively switched according to the magnitude of the current value based on the difference in input potential and resistance value according to the type of the connected oscillator, and the clock signal is generated.

JP 2005-057478 A

  In such a clock generation device, the voltage value or current value is compared with a reference value to determine the magnitude, thereby selecting the clock source, that is, switching the connection of the internal circuit in accordance with the type of the oscillator. Therefore, since analog values such as voltage values and current values are used, malfunctions may occur due to changes in environmental temperature, manufacturing variations, and the like.

  In addition, such a clock generator can operate when two connectable oscillators are both composed of passive drive type oscillators that do not include a circuit for driving an oscillation source such as a crystal oscillator or an RC oscillator. However, when one of the two oscillators is connected to an active drive type oscillator such as a TCXO (temperature compensated crystal oscillator) including a circuit for driving an oscillation source, this is not supported.

  The present invention has been made to solve the above problem, and a clock generator that generates a master clock signal when a vibrator that oscillates by applying a voltage or an oscillator that oscillates and generates an oscillation signal is connected. A first terminal to which one end of the vibrator is connected or a reference potential is applied; a second terminal to which the other end of the vibrator or the oscillator is connected; and the first and second A first clock signal generator for generating a first clock signal by applying a voltage to the terminal; and a second clock signal is generated based on the oscillation signal when the oscillation signal is supplied via the second terminal. A second clock signal generating unit, an output unit outputting one of the first clock signal and the second clock signal as the master clock signal, and a parameter of the master clock signal. A counter that counts the number of pulses, and the output unit outputs the second clock signal as the master clock signal when the number of pulses reaches a predetermined number within a predetermined period. The first clock signal is output as the master clock signal when the number of pulses does not reach the predetermined number within a predetermined period.

  The clock source selection method according to the present invention is a clock source selection method in a clock generation device that generates a master clock signal when a vibrator that oscillates by applying a voltage or an oscillator that oscillates and generates an oscillation signal is connected. A step of outputting a signal supplied via the second terminal of the clock generation device as an output signal, a step of counting the number of pulses of the output signal, and the number of pulses within a predetermined period If not, the master clock is generated and output by applying a voltage to the first terminal and the second terminal of the clock generator, and the number of pulses reaches a predetermined number within the predetermined period. In some cases, the method includes a step of outputting a signal supplied via the second terminal as the master clock.

  According to the present invention, it is possible to automatically determine whether a connected vibrator or oscillator is a passive drive type or an active drive type and generate a clock regardless of temperature changes and manufacturing variations. It is possible to provide a possible clock generation device.

It is a block diagram which shows the circuit structure of the clock generator based on this invention. It is a block diagram which shows the structure of a clock source selection circuit. It is a block diagram which shows the circuit structure of the clock generation apparatus when the crystal oscillator XT is connected. It is a time chart which shows operation | movement of the clock generation apparatus when the crystal oscillator XT is connected. It is a block diagram which shows the circuit structure of the clock generation apparatus when TCXO is connected. It is a time chart which shows operation | movement of the clock generation apparatus when TCXO is connected.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a clock generator 10 according to the present invention. The XI terminal 11 is a first terminal for connecting a crystal resonator or a ground potential (GND). The XO / TCXO terminal 12 is a second terminal for connecting a crystal resonator XT or a TCXO (Temperature Compensated Crystal Oscillator) as an oscillator. The clock generation device 10 constitutes a clock generation module by connecting a crystal resonator or a TCXO.

  The crystal resonator is a passive resonator that oscillates when a voltage is applied from the clock generation device 10 via the XI terminal 11 and the XO / TCXO terminal 12. Therefore, when a crystal resonator is used, the crystal resonator is connected to the XI terminal 11 and the XO / TCXO terminal 12 and a voltage is applied.

  The TCXO is provided with a temperature compensation circuit for correcting the frequency temperature characteristic, an inverting amplifier, and the like together with a crystal resonator, and is an active device that generates an oscillation signal by self-oscillation without receiving a voltage supply from the clock generator 10 side. It is a drive type oscillator. Therefore, when TCXO is used as the oscillator, a TCXO vibrator is connected to the XO / TCXO terminal 12 and a ground potential is applied to the XI terminal 11.

  The switch 13 connects or disconnects the switching terminal 13a and the switching terminal 13b in accordance with the clock source selection signal CS from the clock source selection circuit 19. For example, when the clock source selection signal CS is at logic level 1, the switching terminals 13a and 13b are connected (that is, turned on), and when the clock source selection signal CS is at logic level 0, the switching terminals 13a and 13b are connected. Are not connected (that is, OFF). That is, the switch 13 connects the XI terminal 11 and the inverter 15 when the clock source selection signal CS is at the logic level 1, and connects the XI terminal 11 and the inverter 15 when the clock source selection signal CS is at the logic level 0. Block the connection between. The switch 13 is set to be in an OFF state when the clock generator 10 is turned on.

  The switch 14 connects the switching terminal 14a to one of the switching terminal 14b and the switching terminal 14c according to the clock source selection signal CS. For example, when the clock source selection signal CS is at logic level 1, the switching terminals 14a and 14b are connected, and when the clock source selection signal CS is at logic level 0, the switching terminals 14a and 14c are connected. That is, the switch 14 connects the XO / TCXO terminal 12 and the hysteresis comparator 16 when the clock source selection signal CS is at logic level 1, and the XO / TCXO terminal when the clock source selection signal CS is at logic level 0. 12 and the buffer 17 are connected. The switch 14 is set so that the switching terminals 14a and 14c are connected when the clock generator 10 is turned on.

  The inverter 15 inverts the oscillation signal supplied from the XI terminal 11 through the switch 13 and supplies a signal obtained by amplifying the signal to the hysteresis comparator 16 and the switching terminal 14b of the switch 14 as an inverted amplification signal AS.

  The hysteresis comparator 16 binarizes the inverted amplified signal AS and supplies it to the selector 18 as the clock signal CK1.

  The buffer 17 binarizes and amplifies the oscillation signal supplied from the XO / TCXO terminal 12 via the switch 14, and supplies this to the selector 18 as the clock signal CK2.

  The selector 18 selects either CK1 or CK2 according to the clock source selection signal CS, and outputs the selected signal as the master clock MC. That is, the selector 18 is a clock signal output unit that outputs a clock signal. For example, when the clock source selection signal CS is at logic level 1, the selector 18 selects CK1 and supplies it to the internal circuit and the clock source selection circuit 19 as the master clock MC. On the other hand, when the clock source selection signal CS is at logic level 0, the selector 18 selects CK2, and supplies this to the internal circuit and the clock source selection circuit 19 as the master clock MC. The selector 18 is set so that CK2 is selected when the clock generator 10 is turned on.

  The clock source selection circuit 19 generates a clock source selection signal CS based on the master clock MC and supplies the clock source selection signal CS to the switch 13, the switch 14, and the selector 18.

  FIG. 2 is a block diagram showing a configuration of the clock source selection circuit 19. The clock source selection circuit 19 includes a counter 21, a register 22, a comparison circuit 23, an inverter 24, an inverter 25, a selector 26, an FF (Flip Flop) 27, and a low-speed clock oscillation circuit 28.

  The counter 21 receives the master clock MC and performs up-counting using this as the operation clock. That is, the counter 21 counts signal pulses of the master clock MC. The counter 21 supplies the count value CN to the comparison circuit 23.

  The register 22 stores a predetermined fixed value FN (FN is a natural number) and supplies it to the comparison circuit 23. The FN is, for example, “7”.

  The comparison circuit 23 compares the count value CN and the fixed value FN, and if they match, the comparison signal TS of the logic level 1 is sent to the inverter 24 and the selector 26 if they do not match. Supply.

  The inverter 24 supplies an enable signal EN obtained by inverting the level of the comparison signal TS to the counter 21.

  The inverter 25 inverts the clock source selection signal CS output from the FF 27 and supplies this to the selector 26 as an inverted signal RS.

  The selector 26 selects one of the clock source selection signal CS and the inverted signal RS according to the comparison signal TS, and supplies this to the FF 27 as the selection signal SS. For example, the selector 26 selects the clock source selection signal CS when the comparison signal TS is at the logic level 1, and selects the inverted amplification signal RS when the comparison signal TS is at the logic level 0, and supplies this to the FF 27 as the selection signal SS. .

  The FF 27 latches the selection signal SS in synchronization with the rising edge of the low-speed clock signal LS supplied from the low-speed clock oscillation circuit 28, and outputs this as the clock source selection signal CS. That is, the FF 27 as the clock source selection signal output unit supplies the clock source selection signal CS to the switch 13, the switch 14, and the selector 18.

  The low-speed clock oscillation circuit 28 generates a low-frequency low-speed clock signal LS that rises after a predetermined time T1 has elapsed since the clock generator 10 was turned on, and supplies this to the clock input terminal of the FF 27.

  Next, the operation of the clock generator 10 will be described.

[When a crystal unit is connected]
FIG. 3 is a block diagram showing the configuration of the clock generation device 10 immediately after the power is turned on with the crystal resonator XT connected. The crystal resonator XT has one end connected to the XI terminal 11 and the other end connected to the XO / TCXO terminal 12. One end of the crystal unit XT and the XI terminal 11 are connected to the ground potential via the capacitor C1. The other end of the crystal unit XT and the XO / TCXO terminal 12 are connected to the ground potential via the capacitor C2. The switch 13 is in an OFF state, and the switch 14 is in a state where the switching terminals 14a and 14c are connected.

  FIG. 4 is a time chart showing the internal operations of the clock generation device 10 and the clock source selection circuit 19 immediately after the power is turned on with the crystal resonator XT connected. Hereinafter, the operation of each unit will be described by taking as an example the case where the low-speed clock signal LS, which is the output signal of the low-speed clock oscillation circuit 28, rises at time T1.

(From power on until T1)
Since the switch 13 is in an OFF state immediately after the clock generator 10 is turned on, the crystal resonator XT does not oscillate, and the oscillation signal is not input to the XI terminal 11 (FIG. 4A). In addition, since the crystal resonator XT does not oscillate, no oscillation signal is input to the XO / TCXO terminal 12 (FIG. 4B).

  Since the oscillation signal is not input from the XI terminal 11, the hysteresis comparator 16 supplies the clock signal CK1 having the logic level 0 to the selector 18 (FIG. 4C). Further, since the oscillation signal from the XO / TCXO terminal 12 is not input, the buffer 17 supplies the clock signal CK2 having the logic level 0 to the selector 18 (FIG. 4 (d)).

  Since the selector 18 selects the buffer 17 immediately after the clock generator 10 is powered on, the selector 18 outputs the clock signal CK2 as the master clock MC. Therefore, the master clock MC becomes a logic level 0 (FIG. 4 (e)).

  The counter 21 of the clock source selection circuit 19 counts signal pulses of the master clock MC. Therefore, the counter 21 does not count up while the master clock MC is at the logic level 0 (FIG. 4 (f)).

  Since the count value CN supplied from the counter 21 is 0, the comparison circuit 23 has a logic level 0 indicating that the fixed value FN stored in the register 22, for example, “7” does not match the count value CN. The comparison signal TS is supplied to the selector 26 (FIG. 4G).

  The selector 26 selects the inverted signal RS from the inverter 25 according to the comparison signal TS of the logic level 0, and supplies this to the FF 27 as the selection signal SS. That is, the selector 26 supplies the FF 27 with a logic level 1 signal obtained by inverting the logic level 0 clock source selection signal CS as the selection signal SS (FIG. 4 (h)).

  The low-speed clock oscillation circuit 28 outputs a low-speed clock signal LS having a logic level 0 until time T1 (FIG. 4 (i)).

  While the low-speed clock signal LS supplied from the low-speed clock oscillation circuit 28 is at the logic level 0, the FF 27 does not latch the selection signal SS from the selector 26 and outputs the clock source selection signal CS at the logic level 0 (FIG. 4). (J)).

(After time T1)
The low-speed clock signal LS rises at time T1 and becomes a logic level 1. The low-speed clock oscillation circuit 28 outputs a low-speed clock signal LS having a logic level 1 after time T1 (FIG. 4 (h)).

  At time T1, the output signal of the inverter 25, that is, the logic level 1 selection signal SS obtained by inverting the logic level 0 clock source selection signal CS is supplied to the FF 27. Therefore, the FF 27 latches the logic level 1 selection signal SS supplied from the selector 26 in synchronization with the rising edge of the low-speed clock signal LS, and switches the logic level 1 clock source selection signal CS to the logic level 1 (FIG. 4 (i)).

  In response to the clock source selection signal CS of logic level 1, the switch 13 is turned on, and the switch 14 is connected to the switching terminals 14a and 14b. As a result, the input terminal of the inverter 15 is connected to the XI terminal 11 and the output terminal is connected to the XO / TCXO terminal 12, voltage is applied to the XI terminal 11 and the XO / TCXO terminal 12, and the crystal resonator XT oscillates. (FIGS. 4A and 4B).

  The hysteresis comparator 16 supplies an oscillation signal obtained by binarizing the inverted amplification signal AS supplied via the inverter 15 to the selector 18 as the clock signal CK1 (FIG. 4C).

  During this time, the switching terminals 14a and 14c of the switch 14 are disconnected and no oscillation signal is supplied to the buffer 17, so the buffer 17 supplies the clock signal CK2 of logic level 0 to the selector 18 (FIG. 4 (d) )).

  The selector 18 receives the logic level 1 clock source selection signal CS, selects the clock signal CK1, and outputs it as the master clock MC (FIG. 4E).

  The counter 21 counts up the signal pulse of the master clock MC. When the count value of the counter 21 reaches “7”, the comparison circuit 23 supplies the inverter 24 and the selector 26 with a comparison signal TS having a logic level 1 indicating that the count value CN matches the fixed value FN. (FIG. 4 (g)).

  The inverter 24 supplies the counter 21 with a logic level 0 signal obtained by inverting the logic level 1 comparison signal TS. At time T2 when the count value becomes “7”, the counter 21 is disabled and stops the counting operation (FIG. 4 (f)).

  The selector 26 selects the clock source selection signal CS according to the comparison signal TS of the logic level 1 and supplies it to the FF 27 (FIG. 4 (i)).

  Therefore, the FF 27 maintains the output of the clock source selection signal CS at the logic level 1 even after the time T2 (FIG. 4 (j)).

[When TCXO is connected]
FIG. 5 is a block diagram illustrating a configuration of the clock generation device 10 immediately after power is turned on with the TCXO connected. The TCXO is connected to the XO / TCXO terminal 12. A ground potential is applied to the XI terminal 11. The switch 13 is in an OFF state, and the switch 14 is in a state where the switching terminals 14a and 14c are connected.

  FIG. 6 is a time chart showing the internal operations of the clock generation device 10 and the clock source selection circuit 19 immediately after the power is turned on with the TCXO connected.

  A ground potential is applied to the XI terminal 11 (FIG. 6A), and a TCXO oscillation signal is input to the XO / TCXO terminal 12 (FIG. 6B).

  Since the oscillation signal is not input from the XI terminal 11, the hysteresis comparator 16 supplies the clock signal CK1 having the logic level 0 to the selector 18 (FIG. 6C). A TCXO oscillation signal is supplied to the buffer 17 via the XO / TCXO terminal 12 and the switch 14. The buffer 17 supplies an oscillation signal obtained by binarizing this to the selector 18 as a clock signal CK2 (FIG. 6 (d)).

  During this time, the selector 18 selects the clock signal CK2, and outputs it as the master clock MC (FIG. 6 (e)).

  The counter 21 of the clock source selection circuit 19 up-counts the signal pulses of the master clock MC (FIG. 6 (f)).

  Until the count value CN of the counter 21 reaches “7”, the comparison circuit 23 outputs a comparison signal TS of logic level 0 indicating that the count value CN and the fixed value FN do not match with the inverter 24 and the selector 24. 26. When the count value becomes “7”, the comparison circuit 23 supplies the inverter 24 and the selector 26 with the comparison signal TS of the logic level 1 indicating that the count value CN matches the fixed value FN (FIG. 6 (g )).

  The inverter 24 supplies the counter 21 with a logic level 0 enable signal EN obtained by inverting the logic level 1 comparison signal TS. At the time T0 when the count value becomes “7”, the counter 21 is disabled and stops the counting operation (FIG. 6 (f)).

  Since the selector 26 receives the comparison signal TS of the logic level 0 from the comparison circuit 23 until the time T0, the selector 26 selects the inverted signal RS from the inverter 25 and supplies it to the FF 27. That is, until the time point T0, the selector 26 supplies the selection signal SS of the logic level 1 to the FF 27. After time T0, since the comparison signal TS of the logic level 1 is received from the comparison circuit 23, the selector 26 selects the clock source selection signal CS and supplies it to the FF 27. That is, after the time point T0, the selector 26 supplies the selection signal SS of logic level 0 to the FF 27 (FIG. 6 (h)).

  The low-speed clock oscillation circuit 28 outputs the low-speed clock signal LS having the logic level 0 until time T1, and maintains the output of the low-speed clock signal LS having the logic level 1 after time T1 (FIG. 6 (i)).

  The selection signal SS of logic level 0 is supplied to the FF 27 at the time T1 when the low-speed clock signal LS rises. Therefore, the FF 27 outputs the clock source selection signal CS having the logic level 0 regardless of the time (FIG. 6 (j)).

  As described above, in the clock generation device 10 shown in FIG. 1, first, the connection between the oscillation circuit (15, 16) for the crystal resonator of the passive drive type and the first input terminal (11) is the first. The number of pulses of the signal from the second input terminal (12) is counted by the counter (21) while being shut off by the switch (13).

  Here, when the count value (CN) of the counter does not reach the predetermined value (FN) at the time (T1) when a predetermined period has elapsed since the power was turned on, the clock generation device 10 performs the first and second operations. It is determined that a crystal resonator is connected to the input terminal, and the first input terminal and the oscillation circuit are connected by the first switch. Thereby, the crystal resonator connected to the first and second input terminals starts an oscillation operation. Therefore, at this time, the clock generation device 10 outputs the clock signal (CK1) generated in the oscillation circuit as the master clock (MC).

  On the other hand, when the count value of the counter reaches a predetermined value when a predetermined period has elapsed since the power was turned on, the clock generation device 10 is connected to the second input terminal of the TCXO that is an active drive type oscillator. The clock signal (CK2) obtained by binarizing and amplifying (17) the signal supplied from the second input terminal is output as a master clock.

  With this configuration, the clock generation device 10 automatically determines whether the connected oscillator or oscillator is a passive drive oscillator such as a crystal oscillator or an active drive oscillator such as TCXO. The clock signal generated by the processing circuit corresponding to the connected vibrator or oscillator is output as a master clock.

  Therefore, according to the clock generation device 10, the environment is compared with the case of determining whether the vibrator or the oscillator is an active type or a passive type based on the output level of the connected vibrator or the oscillator itself. It is possible to avoid the risk of malfunction due to the effects of temperature and manufacturing variations. That is, according to the clock generation device 10, even if environmental temperature changes and manufacturing variations occur, the connected vibrator or oscillator is an active oscillator (eg, TCXO) or a passive vibrator ( Therefore, it is possible to correctly determine whether it is a crystal resonator and generate a clock signal corresponding to the resonator or oscillator.

  In the above embodiment, an example in which a crystal resonator is used as the resonator has been described. However, the present invention is not limited to this, and other passive drive type vibrators such as ceramic oscillators may be used. Moreover, the example using TCXO as an oscillator was demonstrated. However, the present invention is not limited to this, and other active drive type oscillators such as SPXO (Single Package Crystal Oscillator) may be used.

  In the above-described embodiment, an example in which the XI terminal 11 is connected to the ground potential when TCXO is used has been described. However, the present invention is not limited to this, and any connection is possible as long as it is connected to a predetermined fixed potential.

  In the above embodiment, the configuration in which the hysteresis comparator 16 binarizes the inverted amplified signal AS supplied from the inverter 15 and the buffer 17 binarizes the oscillation signal input from the XO / TCXO terminal 12 has been described. However, a hysteresis comparator may be used as the buffer 17, and the hysteresis comparator 16 may be constituted by a buffer. That is, the hysteresis comparator 16 only needs to generate a binarized clock signal based on the oscillation signal supplied via the first terminal 11. The buffer 17 only needs to generate a binarized clock signal based on the oscillation signal supplied via the second terminal 12.

  In the above embodiment, immediately after the power is turned on, the clock generator 10 is in the state in which the switch 13 is OFF, the switch 14 is connected to the switching terminals 14a and 14c, and the selector 18 is in the state of selecting the clock signal CK2. The example set as described above has been described. However, unlike this, the clock generator 10 is in a state in which the switch 13 is turned on immediately after the power is turned on, the switch 14 is connected to the switching terminals 14a and 14b, and the selector 18 is in the state in which the clock signal CK1 is selected. It may be set.

DESCRIPTION OF SYMBOLS 10 Clock generator 11 XI terminal 12 XO / TCXO terminal 13, 14 Switch 15 Inverter 16 Hysteresis comparator 17 Buffer 18 Selector 19 Clock source selection circuit 21 Counter 22 Register 23 Comparison circuit 24, 25 Inverter 26 Selector 27 FF
28 Low-speed clock oscillation circuit

Claims (9)

A clock generator that generates a master clock signal when a vibrator that oscillates by applying a voltage or an oscillator that oscillates and generates an oscillation signal is connected,
A first terminal to which one end of the vibrator is connected or a reference potential is applied;
A second terminal to which the other end of the vibrator or the oscillator is connected;
A first clock signal generator for generating a first clock signal by applying a voltage to the first and second terminals;
A second clock signal generator that generates a second clock signal based on the oscillation signal when the oscillation signal is supplied via the second terminal;
An output unit for outputting one of the first clock signal and the second clock signal as the master clock signal;
A counter for counting the number of pulses of the master clock signal,
The output unit outputs the second clock signal as the master clock signal when the number of pulses reaches a predetermined number within a predetermined period, while the number of pulses reaches the predetermined number within the predetermined period. If not, the clock generation apparatus outputs the first clock signal as the master clock signal. A first connection switching unit for connecting or disconnecting the first terminal and the first clock signal generation unit;
A second connection switching unit that connects the second terminal to one of the first connection switching unit and the second clock signal generation unit;
Including
The counter starts counting from the time of power-on,
The first connection switching unit disconnects the first terminal and the first clock signal generation unit from the power-on time to the elapse of the predetermined period, and the number of pulses at the elapse of the predetermined period When the predetermined number has not been reached, the first terminal and the first clock signal generation unit are connected, and when the predetermined number of pulses has reached the predetermined number when the predetermined period has elapsed, the first terminal and Maintaining the first clock signal generator unconnected;
The second connection switching unit connects the second terminal to the second clock signal generation unit from the power-on time to the elapse of the predetermined period, and the number of pulses is set to the predetermined time at the elapse of the predetermined period. When the number does not reach the number, the second terminal is connected to the first connection switching unit, and when the number of pulses reaches the predetermined number when the predetermined period elapses, the second terminal and the Maintaining the connection with the first connection switching unit;
The clock generation device according to claim 1. A clock source selection signal generator for generating a clock source selection signal based on the master clock signal;
The first connection switching unit switches the first terminal and the first clock signal generation unit to connection or non-connection according to the clock source selection signal,
The second connection switching unit switches the connection destination of the second terminal to the first connection switching unit or the second clock signal generation unit according to the clock source selection signal,
The output unit switches a signal to be output as the master clock signal to the first clock signal or the second clock signal according to the clock source selection signal.
The clock generation device according to claim 2, wherein: A low-speed clock oscillation circuit that generates a low-speed clock signal that rises at the time when the predetermined period has elapsed since the power-on time;
The clock source selection signal generator is
From the power-on time to the elapse of the predetermined period, the clock source selection signal of logic level 0 is generated,
When the predetermined number of pulses has not reached the predetermined number of pulses, the clock source selection signal of logic level 1 is generated in synchronization with the rising edge of the low-speed clock signal,
When the number of pulses reaches the predetermined number at the elapse of the predetermined period, the clock source selection signal of logic level 0 is generated.
The clock generator according to claim 3. A register for storing the predetermined number of values;
Compare the count value of the counter with the predetermined number of values, enable the counter if the counter count value does not match the predetermined number of values, and if the counter value matches the predetermined number of values, A comparison circuit for disabling the counter;
The clock generation device according to claim 1, further comprising: The first clock signal generation unit inverts an input signal from the first terminal, amplifies a signal level, binarizes and generates the first clock signal,
The second clock signal generation unit amplifies the signal level of the oscillation signal and binarizes to generate the second clock signal.
The clock generation device according to claim 1, wherein the clock generation device is a clock generation device. A crystal resonator as the resonator;
The clock generation device according to any one of claims 1 to 6, wherein the first terminal is connected to one end of the crystal resonator, and the second terminal is connected to the other end of the crystal resonator.
A clock generation module comprising: A temperature compensated crystal oscillator as the oscillator;
The clock generation device according to claim 1, wherein the reference potential is applied to the first terminal, and the temperature-compensated crystal oscillator is connected to the second terminal.
A clock generation module comprising: A clock source selection method in a clock generator that generates a master clock signal when a vibrator that oscillates by applying a voltage or an oscillator that generates an oscillation signal by self-oscillation is connected,
Outputting a signal supplied via the second terminal of the clock generator as an output signal;
Counting the number of pulses of the output signal;
When the number of pulses does not reach a predetermined number within a predetermined period, the master clock is generated and output by applying a voltage to the first terminal and the second terminal of the clock generation apparatus, and within the predetermined period And when the number of pulses reaches a predetermined number, outputting a signal supplied via the second terminal as the master clock;
Including a clock source selection method.

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