JP2016130927A - Dma controller and inter-bus data transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DMA controller and inter-bus data transfer method that improve the efficiency of data transfer between different buses.SOLUTION: A DMA controller of the present invention includes a transfer information registration unit, a transmission FIFO memory, and a control unit. In the transfer information registration unit, transfer information (which indicates a transfer source address indicating the address of first data storage means connected to a first bus and a transfer destination address indicating the address of second data storage means connected to a second bus) is registered. The control unit transfers, when the transfer information is registered in the transfer information registration unit, data which is read from the transfer source address, to the transfer FIFO memory; and when the storing of the data to the transmission FIFO memory is started, transfers the data which is stored in the transmission FIFO memory to the transfer destination address.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a DMA controller and an inter-bus data transfer method for transferring data between memories, devices, and the like.

  In a computer composed of a CPU, memory, various devices, etc., when data is transferred between memories or between memory and devices, the control is performed not only by the CPU but also by the DMA controller. It is coming. Here, the CPU is an abbreviation for “Central Processing Unit”. DMA is an abbreviation for “Direct Memory Access”.

  When data is transferred in a computer, data is transferred between a memory, a device, and the like via a bus in the computer.

  The DMA controller not only controls data transfer on one bus but also performs data transfer between a plurality of buses (see, for example, Patent Document 1).

  The following description is made in Patent Document 1 “Data Transfer Method and Apparatus” described above.

  That is, as shown in FIG. 11, the first bus 11 and the second bus 12 are connected via a bus repeater 13 having a buffer memory such as a FIFO, and each of the buses 11 and 12 has a DMA ( Direct memory access) controllers 22 and 27 are connected. The bus repeater 13 can issue a DMA transfer request to each of the DMA controllers 22 and 27. The DMA controller 22 DMA-transfers data from the device 23 and the memory 24 on the bus 11 to the buffer memory in the bus relay 13, and the DMA controller 27 transfers the device 28 on the bus 12 from the buffer memory in the bus relay 13. Or DMA transfer to the memory 29. Similarly, data on the bus 12 is DMA-transferred onto the bus 11 via the buffer memory in the bus repeater 13 by the DMA controllers 27 and 22.

  This makes it possible to efficiently perform DMA transfer between different buses.

JP-A-10-293742 (pages 3-7, FIGS. 1-5)

  In the method described in Patent Document 1 described above, the DMA controller 22 first DMA-transfers data from the device 23 and the memory 24 on the bus 11 to the buffer memory in the bus repeater 13. Then, the bus repeater 13 requests the DMA controller 27 to perform DMA transfer. Then, the DMA controller 27 is configured to transfer the data in the buffer memory in the bus repeater 13 to the device 28 and the memory 29. This makes it possible to efficiently transfer data between different buses.

  However, in the method described in Patent Document 1, the DMA transfer of the DMA controller 27 is performed after the DMA transfer of the DMA controller 22 is completed. For this reason, the time required for data transfer between different buses is the sum of the operation time of the DMA controller 22 and the operation time of the DMA controller 27.

  Here, with respect to the technique described in Patent Document 1, from the viewpoint of the usage pattern of the bus, when the DMA transfer of the DMA controller 22 is performed, only the bus 11 to which the DMA controller 22 is connected is used. Has been. Further, when the DMA transfer of the DMA controller 27 is performed, only the bus 12 to which the DMA controller 27 is connected is used. That is, different buses are used independently in time. Since the bus 11 is used by the DMA controller 22 and the bus 12 is used by the DMA controller 27, it is difficult to use the bus 11 and the bus 12 in parallel rather than being independent in time. It has a problem.

  If different buses are used in parallel with the above-described form in which different buses are used independently, the overall time required for data transfer between different buses is shortened, and data transfer is more efficient. Can be performed.

  The present invention has been made to solve the above-described problems. Therefore, an object of the present invention is to provide a DMA controller and an inter-bus data transfer method that improve the efficiency of data transfer between different buses.

  The DMA controller of the present invention includes a transfer information registration unit, a transmission FIFO memory, and a control unit.

  Here, transfer information is registered in the transfer information registration unit. The transfer information includes a transfer source address indicating the address of the first data storage means connected to the first bus, and a second data storage means connected to a second bus different from the first bus. The transfer destination address indicating the address of the address. This transfer information is registered from the CPU connected to the first bus.

  The transmission FIFO memory temporarily stores data read from the transfer source address.

  The control unit performs the following operations. That is, when the transfer information indicating the transfer source address and the transfer destination address is registered in the transfer information registration unit, the data read from the transfer source address is transmitted to the transmission FIFO memory. When the storage of the data starts in the transmission FIFO memory, the data stored in the transmission FIFO memory is transmitted to the transfer destination address.

  The inter-bus data transfer method of the present invention is executed in a DMA controller including a transfer information registration unit for registering transfer information and a transmission FIFO memory for temporarily storing data read from the data storage means. That is, in the transfer information registration unit, a transfer source address indicating the address of the first data storage means connected to the first bus, and a second connected to the second bus different from the first bus When the transfer information indicating the transfer destination address indicating the address of the data storage means is registered, the following is executed.

First, the data read from the transfer source address is transmitted to the transmission FIFO memory. When the storage of the data starts in the transmission FIFO memory, the data stored in the transmission FIFO memory is transmitted to the transfer destination address.

  According to the present invention, the efficiency of data transfer between different buses can be improved.

1 is a block diagram showing a first embodiment of a DMA controller of the present invention. FIG. It is a 1st timing chart explaining operation | movement of 1st Embodiment. It is a 2nd timing chart explaining operation | movement of 1st Embodiment. It is a block diagram which shows 2nd Embodiment of the DMA controller of this invention. It is a figure which shows an example of the transfer information registration part. It is a timing chart explaining operation of a 2nd embodiment. It is a 3rd timing chart explaining operation | movement of 1st Embodiment. It is a block diagram which shows 3rd Embodiment of the DMA controller of this invention. It is a figure which shows an example of the transfer information registration part of 3rd Embodiment. It is a timing chart explaining operation of a 3rd embodiment. It is a figure which shows an example of the conventional DMA controller.

Next, embodiments of the present invention will be described with reference to the drawings.
[First embodiment]
FIG. 1 is a block diagram showing a first embodiment of the DMA controller of the present invention. In the following, a DMA controller (Direct Memory Access Controller) is abbreviated as DMAC. Further, the central processing unit is described as CPU.

  The DMAC 100 shown in FIG. 1 includes a control unit 110, a transmission FIFO (First-In First-Out) memory 120, and a transfer information registration unit 130. The DMAC 100 is connected to a plurality of buses 30 (30-1, 30-2,..., 30-n) which are data paths, and data transfer is performed between the plurality of buses 30. Control is to be performed.

  A CPU 10 (10-1, 10-2,..., 10-n) and a memory 20 (20-1, 20-2,..., 20-n) are connected to each bus 30. It is configured. The CPU 10 operates to access the memory 20 via the bus 30 and read data from the memory 20 or write data to the memory 20. The memory 20 is a storage device such as a random access memory (RAM) or a read only memory (ROM). Further, the memory 20 may be a device such as a peripheral device capable of storing data.

  When receiving a data transfer start instruction from the CPU 10, the control unit 110 of the DMAC 100 controls data transfer between the memories 20 using the bus 30 according to the content of the instruction.

  The transmission FIFO memory 120 is a storage device that temporarily stores data read from a certain memory 20. The data once stored is data to be written in another memory 20 at a later time.

  For data transferred from one memory 20 to another memory 20, the transfer information registering unit 130 stores the address of the memory 20 that is the data transfer source, the address of the memory 20 that is the data transfer destination, and the transfer data This is a storage device for registering transfer information including size and the like. This transfer information is registered by the CPU 10 that intends to execute the data transfer process.

  Note that the data transfer in this embodiment is performed between the memory 20 that is the transfer source and the memory 20 that is the transfer destination, which are connected to different buses 30. For example, when the transfer source memory 20 is the memory 20-2 connected to the bus 30-2, the transfer destination memory 20 is connected to a bus 30 (eg, bus 30-1) other than the bus 30-2. Memory 20 (eg, memory 20-1).

  Next, the operation of the present embodiment will be described with reference to FIG. In FIG. 2, a case where the transfer source is the memory 20-2 connected to the bus 30-2 and the transfer destination is the memory 20-1 connected to the bus 30-1 will be described as an example. To do.

  FIG. 2 is a first timing chart for explaining the operation of the first embodiment. In FIG. 2, the horizontal axis indicates the passage of time, and the time passes from the left side to the right side in FIG. Here, the time is indicated by “T ○”.

  First, the CPU 10-2 registers “transfer source address = memory 20-2, transfer destination address = memory 20-1, transfer size = A” in the transfer information registration unit 130, thereby transferring data to the DMAC 100. Instruct transfer start.

  Recognizing that the transfer information is registered in the transfer information registration unit 130, the control unit 110 of the DMAC 100 registers “transfer source address = memory 20-2, transfer destination address = memory 20-1, transfer size = A”. In order to carry out the process of FIG.

  That is, the control unit 110 of the DMAC 100 transmits a read request for data of the transfer size A to the memory 20-2 connected to the bus 30-2 that is the transfer source address (time T1 in FIG. 2). The memory 20-2 that has received the read request starts transmission of the read data to the transmission FIFO memory 120 (time T2). Then, from time T2 to time T4, data of transfer size = A read from the memory 20-2 is sequentially stored in the transmission FIFO memory 120.

  When the control unit 110 recognizes that the read data from the memory 20-2 starts to be stored in the transmission FIFO memory 120, the control unit 110 operates to start data transfer to the memory 20-1 at time T2. That is, the control unit 110 writes the data received from the memory 20-2 together with the write request to the memory 20-1 of the bus 30-1 that is the transfer destination address, that is, the data in the transmission FIFO memory 120 as the write data. Send. The memory 20-1 that has received the write request starts to receive data stored in the transmission FIFO memory 120 from the memory 20-2 (time T3). Then, from time T3 to time T5, data of transfer size = A read from the memory 20-2 is sequentially stored in the memory 20-1.

  At time T5, the transfer of all data of transfer size A is completed.

  The operation of the first embodiment of the present invention has been described above.

  As described above, the DMA controller (100) of the first embodiment includes the transfer information registration unit (130), the transmission FIFO memory (120), and the control unit (110).

  Here, transfer information is registered in the transfer information registration unit. This transfer information includes a transfer source address indicating the address of the first data storage means (memory 20) connected to the first bus, and a second bus connected to a second bus different from the first bus. And a transfer destination address indicating the address of the data storage means (memory 20). This transfer information is registered from the CPU connected to the first bus.

  The transmission FIFO memory temporarily stores data read from the transfer source address.

  The control unit performs the following operations. That is, when the transfer information indicating the transfer source address and the transfer destination address is registered in the transfer information registration unit, the data read from the transfer source address is transmitted to the transmission FIFO memory. When the storage of the data starts in the transmission FIFO memory, the data stored in the transmission FIFO memory is transmitted to the transfer destination address.

  As described above, according to the DMA controller of the first embodiment, when the data read from the transfer source address starts to be stored in the transmission FIFO memory, transmission to the transfer destination address is started immediately. That is, even when the bus connecting the data storage means of the transfer source address is being used, the use of the bus connecting the data storage means of the transfer destination address is started. In other words, different buses are used in parallel.

Therefore, according to the present embodiment, the efficiency of data transfer between different buses can be improved.
[Second Embodiment]
Next, a second embodiment according to the present invention will be described as a modification of the first embodiment shown in FIG.

  The second embodiment shows a case where two data transfers are continuously performed from a memory 20 connected to a certain bus 30 to a memory 20 connected to another bus 30. Note that when two data transfers to different buses 30 are continuously performed, if the DMAC 100 shown in the first embodiment is used as it is, unused time occurs on a certain bus 30. Therefore, the second embodiment provides a DMAC 100 that can improve the efficiency of data transfer between different buses by reducing the unused time generated on the bus 30.

  Here, before explaining the second embodiment, how unused time occurs on the bus 30 when continuous data transfer is performed in the first embodiment will be described with reference to FIG. Shall.

  FIG. 3 is a second timing chart for explaining the operation of the first embodiment. FIG. 3 illustrates a case where the DMAC 100 according to the first embodiment performs two data transfers in succession and the transfer destinations of the two data transfers are on the same bus 30. As an example of the case where the data transfer destination is the same, the case where the data transfer from the memory 20-2 to the memory 20-1 and the data transfer from the memory 20-3 to the memory 20-1 are continuously performed. explain. In FIG. 3, the horizontal axis indicates the passage of time, and the time passes from the left side to the right side in FIG. Here, the time is indicated by “T ○”.

  First, the CPU 10-2 registers “transfer source address = memory 20-2, transfer destination address = memory 20-1, transfer size = A” in the transfer information registration unit 130, thereby transferring data to the DMAC 100. Instruct transfer start.

  Further, the CPU 10-3 registers “transfer source address = memory 20-3, transfer destination address = memory 20-1, transfer size = B” in the transfer information registration unit 130.

  Recognizing that the transfer information is registered in the transfer information registration unit 130, the control unit 110 of the DMAC 100 first registers “transfer source address = memory 20-2, transfer destination address = memory 20-1, transfer size = In order to implement the process “A”, the operation is performed as shown in FIG.

  First, the control unit 110 of the DMAC 100 transmits a read request for the transfer size A to the memory 20-2 connected to the bus 30-2 that is a transfer source address (time T11 in FIG. 3). The memory 20-2 that has received the read request starts transmission of the read data to the transmission FIFO memory 120 (time T12). Then, the control unit 110 writes the data received from the memory 20-2 together with the write request to the memory 20-1 of the bus 30-1 that is the transfer destination address, that is, the data of the transmission FIFO memory 120 as the write data. Transmit (time T13).

  When the transfer of all data of transfer size A is completed (time T14), the control unit 110 registers “transfer source address = memory 20-3, transfer destination address = memory 20− second registered in the transfer information registration unit 130. 1, the process of “transfer size = B” is started.

  That is, at time T14, the control unit 110 transmits a transfer size B read request to the memory 20-3 connected to the bus 30-3 that is the transfer source address (time T14 in FIG. 3). The memory 20-3 that has received the read request starts transmission of the read data to the transmission FIFO memory 120 (time T15). Then, the control unit 110 writes the data received from the memory 20-3 together with the write request to the memory 20-1 of the bus 30-1 that is the transfer destination address, that is, the data in the transmission FIFO memory 120 as the write data. Transmit (time T16). Then, the transfer of all data of transfer size B to the memory 20-1 ends at time T17.

  At time T17, the data transfer from the memory 20-2 to the memory 20-1 and the data transfer from the memory 20-3 to the memory 20-1 that were the initial targets are continuously performed, and Data transfer has been completed.

  Here, referring to FIG. 3 again, the bus 30-1 connecting the memory 20-1, which is the transfer destination of the two data transfers, is not used between the time T14 and the time T16. Yes. In the present embodiment, the period from time T14 to T16 is referred to as “unused time” as shown as (1) in FIG.

  Here, the unused time is the sum of the external delay time shown as (2) in FIG. 3 and the internal processing time shown as (3).

  The external delay time is the time when the control unit 110 transmits a read request to the memory 20-3 connected to the bus 30-3 (time T14), and the data read from the memory 20-3 is the transmission FIFO memory 120. It takes time to arrive at (time T15). The external delay time is a delay time generated outside the DMAC 100, and is a delay time required for reading data in the memory 20, a bus arbitration for controlling the right to use the bus 30, and the like.

  The internal processing time is from when a write request to the memory 20-1 connected to the bus 30-1 is transmitted (time T15) until data in the transmission FIFO memory 120 arrives at the memory 20-1 (time T16). ). The internal processing time is a time required in the DMAC 100 for processing of transmitting data in the transmission FIFO memory 120 to the memory 20-1.

  As described above, when two data transfers to different buses 30 are performed in succession, if the DMAC 100 shown in the first embodiment is used as it is, the above-described unused state is used on a certain bus 30. Time will occur. Therefore, the second embodiment provides a DMAC 100 that can improve the efficiency of data transfer between different buses by reducing the unused time generated on the bus 30.

  Here, in order to reduce the unused time generated on the bus 30, in the second embodiment, it is assumed in advance what kind of method is being performed.

  Referring to FIG. 3 again, the data received from the memory 20-2 is transmitted to the memory 20-1 of the bus 30-1 from time T13 to time T14. The data received from the memory 20-3 is transmitted to the memory 20-1 of the bus 30-1 from time T16 to time T17.

  Here, if the data received from the memory 20-3 is transmitted to the memory 20-1 retroactively to the time T14, the unused time occurring between the time T14 and the time T16 can be reduced. It becomes possible. In other words, when the data read from the memory 20-2 is completely transmitted to the memory 20-1, the data from the memory 20-3 is immediately transmitted to the memory 20-1. Good. In order to realize this, the transmission of the read request to the memory 20-3 performed at time T14 may be advanced by an amount corresponding to the unused time.

  Thus, in the second embodiment, when the read request to the memory 20-3 is to be transmitted (referred to as “request transmission time”) is calculated and the memory request is reached when the time is reached. A read request for 20-3 is transmitted.

  Hereinafter, a second embodiment of the present invention will be described.

  FIG. 4 is a block diagram showing a second embodiment of the DMA controller of the present invention. FIG. 4 is a block diagram in which functions are added to the DMAC 100 shown in FIG. 1 and the configuration of the transfer information registration unit 130 is changed. Therefore, in FIG. 4, the same reference numerals or symbols are assigned to the components corresponding to those in FIG. 1, and the description thereof is omitted as much as possible.

  The DMAC 100-2 illustrated in FIG. 4 includes a control unit 110-2, a transmission FIFO memory 120, and a transfer information registration unit 130-2. The DMAC 100-2 is connected to a plurality of buses 30 (30-1, 30-2,..., 30-n) that are data paths, and performs data transfer performed between the plurality of buses 30. It comes to perform control.

  As in FIG. 1, each bus 30 has a CPU 10 (10-1, 10-2,..., 10-n), a memory 20 (20-1, 20-2,..., 20-n). ) Are connected. The CPU 10 operates to access the memory 20 via the bus 30 and read data from the memory 20 or write data to the memory 20.

  When receiving a data transfer start instruction from the CPU 10, the control unit 110-2 of the DMAC 100-2 controls data transfer between the memories 20 using the bus 30 according to the content of the instruction. In particular, the control unit 110-2 in the present embodiment calculates the “request transmission time” described above in order to reduce the unused time of the bus 30. When the request transmission time is reached, the read request is transmitted to the memory 20.

  The transmission FIFO memory 120 is a storage device that temporarily stores data read from a certain memory 20 as in FIG. The data once stored is data to be written in another memory 20 at a later time.

  For data transferred from one memory 20 to another memory 20, the transfer information registration unit 130-2 stores the address of the memory 20 that is the data transfer source, the address of the memory 20 that is the data transfer destination, and the transfer data This is a storage device for registering transfer information consisting of size and external delay time. This transfer information is registered by the CPU 10 that intends to execute the data transfer process.

  Note that data transfer in this embodiment is performed between the memory 20 that is the transfer source and the memory 20 that is the transfer destination, as in the first embodiment.

  Here, the transfer information registration unit 130-2 will be described with reference to FIG.

  FIG. 5 is a diagram illustrating an example of the transfer information registration unit.

  The transfer information registration unit 130-2 illustrated in FIG. 5 includes a number (column 50-11), a transfer source address (column 50-12), and a transfer destination address (50-13) as illustrated in line 50-0 in FIG. Column), transfer size (50-14 columns), and external delay time (50-15 columns).

  The number (50-11 column) column is a column indicating the row number of the transfer information registration unit 130-2, and one transfer information is registered in one row.

  The column of transfer source address (columns 50-12) indicates the address of the memory 20 that stores the original data to be transferred when performing data transfer. In the example of line 50-1, “memory 20-2” is described in the transfer source address column. This is because a certain address of “memory 20-2” is the start address of data to be transferred. It shows that there is.

  The column of transfer destination address (columns 50-13) indicates the address of the memory 20 where the transferred data is stored when data transfer is performed. In the example of the line 50-1, “memory 20-1” is described in the transfer destination address column, and this is stored in a certain address of the “memory 20-1”. It indicates that it is the start address.

  The column of transfer size (columns 50-14) indicates the size of data to be transferred. In the example of line 50-1, “A” is described in the transfer size column, which indicates that the size of the transferred data is “A”. The unit of size may be, for example, the number of bytes.

  The column of the external delay time (columns 50-15) is a delay time generated outside the DMAC 100-2 when performing data transfer. As described above, the external delay time is a delay time required for reading data in the memory 20 or a time required for bus arbitration for controlling the right to use the bus 30. In the example of line 50-1, “○○” is described in the column of the external delay time. The unit of the external delay time may be milliseconds, for example.

Note that another example of the second registered transfer information is shown in line 50-2 (line number “2”) of the transfer information registration unit 130-2 shown in FIG.

  Next, the operation of the second embodiment will be described.

  FIG. 6 is a timing chart for explaining the operation of the second embodiment. FIG. 6 illustrates a case where the DMAC 100-2 performs two data transfers in succession and the transfer destinations of the two data transfers are on the same bus 30. As an example of the case where the data transfer destination is the same, the case where the data transfer from the memory 20-2 to the memory 20-1 and the data transfer from the memory 20-3 to the memory 20-1 are continuously performed. explain. This corresponds to the case where the transfer information illustrated in the row with the number “1” and the row with the number “2” in FIG. 5 is registered in the transfer information registration unit 130-2. In FIG. 6, the horizontal axis indicates the passage of time, and the time passes from the left to the right in FIG. Here, the time is indicated by “T ○”.

  First, the CPU 10-2 instructs the DMAC 100-2 to start data transfer by registering the transfer information shown in the row of the number “1” in FIG. 5 in the transfer information registration unit 130-2. .

  Further, the CPU 10-3 registers the transfer information indicated in the row of the number “2” in FIG. 5 in the transfer information registration unit 130-2.

  Recognizing that the transfer information is registered in the transfer information registration unit 130-2, the control unit 110-2 of the DMAC 100-2 first registers “transfer source address = memory 20-2, transfer destination address = memory 20”. −1, transfer size = A, external delay time = ◯◯ ”. That is, it operates as shown in FIG.

  First, the control unit 110-2 of the DMAC 100-2 transmits a transfer size A read request to the memory 20-2 connected to the bus 30-2 that is the transfer source address (time T21 in FIG. 6). ). The memory 20-2 that has received the read request starts transmission of the read data to the transmission FIFO memory 120 (time T22). Then, the control unit 110-2 writes the data received from the memory 20-2, that is, the data of the transmission FIFO memory 120, together with the write request, to the memory 20-1 of the bus 30-1 that is the transfer destination address. Data is transmitted (time T23).

  Here, the control unit 110-2 performs a calculation for obtaining the above-described “request transmission time”. A method for calculating the “request transmission time” will be described later.

  Next, the control unit 110-2 determines whether the current time has reached the requested transmission time. When the current time reaches the requested transmission time or when the requested transmission time has passed, a read request is transmitted to the memory 20-3 (T25 in FIG. 6). By transmitting a read request at time T25, “transfer source address = memory 20-3, transfer destination address = memory 20-1, transfer size = B, externally registered in the transfer information registration unit 130-2. This means that the processing of “delay time = ○ Δ” has started.

  The memory 20-3 that has received the read request starts transmission of the read data to the transmission FIFO memory 120 (time T27). Then, the control unit 110-2 writes the data received from the memory 20-3, that is, the data of the transmission FIFO memory 120, together with the write request, to the memory 20-1 of the bus 30-1 that is the transfer destination address. Data is transmitted (time T28). Then, the transfer of all data of transfer size B to the memory 20-1 ends at time T29.

  At time T29, the data transfer from the memory 20-2 to the memory 20-1 and the data transfer from the memory 20-3 to the memory 20-1 that were the initial targets are continuously performed, and Data transfer has been completed.

  Here, looking at the time point T28 in FIG. 6, it can be seen that the unused time shown as (1) in FIG. 3 is reduced on the bus 30-1. This is because the read request to the memory 20-3 was issued at the time T14 in FIG. 3 (corresponding to the time T28 in FIG. 6), but in FIG. 6, it was advanced to the time T25. Is.

  Here, a method of calculating the “request transmission time” performed by the control unit 110-2 will be described.

  The control unit 110-2 predicts a time (T28 in FIG. 6) when transmission of the write data started at time T23 in FIG. 6 ends on the bus 30-1. The prediction here is predicted in consideration of the transfer size (for example, transfer size = A) registered in the transfer information registration unit 130-2 and the operation speed of the bus 30-1. Then, the external delay time and the internal processing time are subtracted from the predicted time. This is the required request transmission time. As the external delay time, the value (“◯ Δ”) registered in the external delay time column (50-2 line, 50-15 column) of the transfer information registration unit 130-2 in FIG. 5 is used. Good. Further, the internal processing time may be calculated and calculated by the control unit 110-2 as a time required for processing for transmitting the data in the transmission FIFO memory 120 to the memory 20-1.

  The operation of the second embodiment has been described above.

  As described above, the DMA controller (100-2) of the second embodiment includes the transfer information registration unit (130-2), the transmission FIFO memory (120), and the control unit (110-2). ing.

  Then, the first transfer information and the second transfer information are registered in the transfer information registration unit. The first transfer information includes a first transfer destination address indicating an address of the first data storage means connected to the first bus, and a second bus connected to a second bus different from the first bus. 2 shows a first transfer source address indicating the address of the second data storage means. The second transfer information is connected to a second transfer destination address indicating the address of the first data storage means connected to the first bus, and to a third bus different from the first bus. And a second transfer source address indicating the address of the third data storage means.

  When the first transfer information and the second transfer information are registered in the transfer information registration unit, the control unit operates as follows.

  That is, the control unit transmits data read from the first transfer source address to the first transfer destination address. Then, a request transmission time, which is an appropriate time for reading data from the second transfer source address, is calculated. Next, the control unit transmits a read request to the second transfer source address when the current time has reached the request transmission time or exceeds the request transmission time, and transmits the second request to the second transfer source address. The data of the transfer source address is transmitted to the transmission FIFO memory. Then, when the storage of the data of the second transfer source address in the transmission FIFO memory starts to be started, the data of the second transfer source address stored in the transmission FIFO memory is transferred to the second transfer Send to the destination address.

  The request transmission time is a time obtained by subtracting the internal processing time of the control unit and the external delay time indicated in the second transfer information from the predicted time. Here, the predicted time is a time estimated for the time until all data read from the first transfer source address is transmitted to the first transfer destination address. The internal processing time is a time required until the data of the second transfer source address transmitted to the transmission FIFO memory starts to be transmitted to the second transfer destination address.

  As described above, the DMA controller according to the second embodiment calculates a request transmission time which is an appropriate time for reading data from the second transfer source address. The request transmission time is such that when all data read from the first transfer source address has been transmitted to the first transfer destination address, the data from the second transfer source address is immediately transferred to the first transfer source address. This is the time for transmission to the forwarding address.

  Then, when the current time reaches the request transmission time or exceeds the request transmission time, the DMA controller transmits a read request to the second transfer source address. As a result, the data of the second transfer source address is transmitted to the transmission FIFO memory. Then, when the storage of the data of the second transfer source address in the transmission FIFO memory starts to be started, the data of the second transfer source address stored in the transmission FIFO memory is transferred to the second transfer Send to the destination address.

  As a result, the data of the second transfer source address transmitted to the transmission FIFO memory is immediately after the data of the first transfer source address is completely transmitted to the first transfer destination address. 1 is transmitted to the transfer destination address.

Therefore, according to this embodiment, when data transfer to the same transfer destination address is continuously performed, the use efficiency of the bus connecting the data storage means of the same transfer destination address is improved.
[Third embodiment]
Next, a third embodiment according to the present invention as a modification of the second embodiment shown in FIG. 4 will be described.

  The third embodiment shows a case where two data transfers from a memory 20 connected to a certain bus 30 to a memory 20 connected to another bus 30 are performed in succession. This is the same as the premise in the second embodiment, but the third embodiment is an embodiment for “when the transfer source is on the same bus 30” of two data transfers.

  Even in the case of two data transfers “when the transfer source is on the same bus 30”, when the DMAC 100 shown in the first embodiment is used as it is, unused time is generated on a certain bus 30. End up. Therefore, the third embodiment provides a DMAC 100 that can improve the efficiency of data transfer between different buses by reducing the unused time generated on the bus 30 as in the second embodiment. It is.

  Here, before describing the third embodiment, when the continuous data transfer of “when the transfer source is on the same bus 30” is performed in the first embodiment, it is not used on the bus 30. The manner in which time occurs will be described with reference to FIG.

  FIG. 7 is a third timing chart for explaining the operation of the first embodiment. FIG. 7 illustrates a case where the DMAC 100 according to the first embodiment performs two data transfers in succession and the transfer source of the two data transfers is on the same bus 30. As an example of the case where the data transfer source is the same, the data transfer from the memory 20-1 to the memory 20-2 and the data transfer from the memory 20-1 to the memory 20-3 are continuously performed. explain. In FIG. 7, the horizontal axis indicates the passage of time, and the time passes from the left to the right in FIG. Here, the time is indicated by “T ○”.

  First, the CPU 10-1 registers “transfer source address = memory 20-1, transfer destination address = memory 20-2, transfer size = C” in the transfer information registration unit 130, thereby transferring data to the DMAC 100. Instruct transfer start.

  Further, the CPU 10-1 registers “transfer source address = memory 20-1, transfer destination address = memory 20-3, transfer size = D” in the transfer information registration unit 130.

  Recognizing that the transfer information is registered in the transfer information registration unit 130, the control unit 110 of the DMAC 100 first registers “transfer source address = memory 20-1, transfer destination address = memory 20-2, transfer size = In order to implement the process “C”, the operation is performed as shown in FIG.

  First, the control unit 110 of the DMAC 100 transmits a read request for the transfer size C to the memory 20-1 connected to the bus 30-1 that is the transfer source address (time T31 in FIG. 7). The memory 20-1 that has received the read request starts transmission of the read data to the transmission FIFO memory 120 (time T32). Then, the control unit 110 writes the data received from the memory 20-1 together with the write request to the memory 20-2 of the bus 30-2 that is the transfer destination address, that is, the data of the transmission FIFO memory 120 as the write data. Transmit (time T33). The data from the memory 20-1 that has started transmission to the transmission FIFO memory 120 at the time T32 has been transmitted at the time T34.

  When the transfer of all data of transfer size C to the memory 20-2 is completed (time T35), the control unit 110 registers “transfer source address = memory 20-1, transfer destination second registered in the transfer information registration unit 130”. The processing of “address = memory 20-3, transfer size = D” is started.

  That is, at time T35, the control unit 110 transmits a read request for the transfer size D to the memory 20-1 connected to the bus 30-1 that is the transfer source address (time T35 in FIG. 7). The memory 20-1 that has received the read request starts transmission of the read data to the transmission FIFO memory 120 (time T36). Then, the control unit 110 writes the data received from the memory 20-1 together with the write request to the memory 20-3 of the bus 30-3 as the transfer destination address, that is, the data in the transmission FIFO memory 120 as the write data. Transmit (time T37). Then, the transfer of all data of transfer size D to the memory 20-3 ends at time T38.

  At time T38, the initial target data transfer from the memory 20-1 to the memory 20-2 and the data transfer from the memory 20-1 to the memory 20-3 are continuously performed, and Data transfer has been completed.

  Here, referring to FIG. 7 again, the bus 30-1 connecting the memory 20-1, which is the transfer source of the two data transfers, is not used between the time T34 and the time T36. Yes. In the present embodiment, as in the second embodiment, the period from time T34 to T36 is referred to as “unused time” as shown in FIG. 7 (1).

  Here, the unused time is the sum of the external delay time shown as (2) in FIG. 7 and the internal processing time shown as (3).

  The external delay time refers to the data read from the memory 20-1 after the controller 110 transmits a read request to the memory 20-1 connected to the bus 30-1 (time T35). This is the time taken to arrive at (time T36). As in the second embodiment, the external delay time is a delay time generated outside the DMAC 100, and is used for delay time required for reading data in the memory 20, bus arbitration for controlling the right to use the bus 30, and the like. It takes time.

  The internal processing time is from the time when data read first from the memory 20-1 starts to be transmitted to the transmission FIFO memory 120 (time T32) until it reaches the memory 20-2 as write data ( This is the time taken for time T33). As in the second embodiment, the internal processing time is a time required inside the DMAC 100 for processing to transmit data in the transmission FIFO memory 120 to the memory 20-2. The time length from time T32 to time T33 is the same as the time length from time T34 to T35. Therefore, in FIG. 7, for the sake of convenience, the time from time T34 to T35 is described as the internal processing time indicated by (3).

  As described above, when two data transfers to different buses 30 are continuously performed and the transfer source of the two data transfers is on the same bus 30, the DMAC 100 described in the first embodiment is used. If it is used as it is, unused time will occur on a certain bus 30. Therefore, the third embodiment provides a DMAC 100 that can improve the efficiency of data transfer between different buses by reducing the unused time generated on the bus 30.

  Here, in order to reduce the unused time generated on the bus 30, in the third embodiment, it is assumed in advance what kind of method is being performed.

  Referring to FIG. 7 again, the first data received from the memory 20-1 is transmitted to the transmission FIFO memory 120 from time T32 to time T34. The second data received from the memory 20-1 has been transmitted to the transmission FIFO memory 120 from time T36.

  Here, if the data received second from the memory 20-1 is transmitted to the transmission FIFO memory 120 retroactively to the time T34, the unused time generated between the time T34 and the time T36 is reduced. It becomes possible to make it. That is, at the time when the first data read from the memory 20-1 is completely transmitted to the transmission FIFO memory 120 (time T34), the second data from the memory 20-1 is immediately transmitted to the transmission FIFO memory. 120 may be transmitted. In order to realize this, the transmission of the second data read request to the memory 20-1 performed at time T35 may be advanced by an amount corresponding to the unused time.

  Therefore, in the third embodiment, the second data read request to the memory 20-1 is calculated by calculating when it should be transmitted (referred to as "second request transmission time"). When the time is reached, a read request to the memory 20-1 is transmitted.

  Hereinafter, a third embodiment of the present invention will be described.

  FIG. 8 is a block diagram showing a third embodiment of the DMA controller of the present invention. FIG. 8 is a block diagram when the function of the DMAC 100-2 shown in FIG. 4 is changed and the transfer information registered in the transfer information registration unit 130-2 is changed. Therefore, in FIG. 8, the same reference numerals or symbols are assigned to components corresponding to those in FIG. 4, and the description thereof is omitted as much as possible.

  The DMAC 100-3 illustrated in FIG. 8 includes a control unit 110-3, a transmission FIFO memory 120, and a transfer information registration unit 130-3. The DMAC 100-3 is connected to a plurality of buses 30 (30-1, 30-2,..., 30-n) as data paths, and performs data transfer performed between the plurality of buses 30. It comes to perform control.

  As in FIG. 4, each bus 30 has a CPU 10 (10-1, 10-2,..., 10-n) and a memory 20 (20-1, 20-2,..., 20-n). ) Are connected. The CPU 10 operates to access the memory 20 via the bus 30 and read data from the memory 20 or write data to the memory 20.

  When receiving a data transfer start instruction from the CPU 10, the control unit 110-3 of the DMAC 100-3 controls data transfer between the memories 20 using the bus 30 according to the content of the instruction. In particular, the control unit 110-3 in the present embodiment calculates the above-described “second request transmission time” in order to reduce the unused time of the bus 30. When the second request transmission time is reached, the read request is transmitted to the memory 20.

  The transmission FIFO memory 120 is a storage device that temporarily stores data read from a certain memory 20 as in FIG. The data once stored is data to be written in another memory 20 at a later time.

  The transfer information registration unit 130-3, for data transferred from one memory 20 to another memory 20, the address of the memory 20 that is the data transfer source, the address of the memory 20 that is the transfer destination of the data, This is a storage device for registering transfer information consisting of size and external delay time. This transfer information is registered by the CPU 10 that intends to execute the data transfer process.

  As in the second embodiment, the data transfer in the present embodiment involves two consecutive data transfers from the memory 20 connected to a certain bus 30 to the memory 20 connected to another bus 30. The case where it is performed is shown. However, it differs from the second embodiment in that it is “when the transfer source is on the same bus 30” for the two data transfers.

  Here, transfer information registered in the transfer information registration unit 130-3 will be described with reference to FIG.

  FIG. 9 is a diagram illustrating an example of a transfer information registration unit according to the third embodiment.

  The transfer information registration unit 130-3 shown in FIG. 9 has a number (90-11 column), a transfer source address (90-12 column), and a transfer destination address (90-13) as shown in the 90-0 line of FIG. Column), transfer size (90-14 column), and external delay time (90-15 column). These columns shown in the 90-0 line are the same as those shown in FIG.

  An example of the first transfer information is shown in the row of the number “1” of 90-1 in FIG. 9, and the row of the second transfer information is shown in the row of the number “2” of 90-2. An example is shown.

  In the row of the number “1”, a transfer source address (memory 20-1), a transfer destination address (memory 20-2), a transfer size (C), and an external delay time (□□) are registered. In the row of the number “2”, a transfer source address (memory 20-1), a transfer destination address (memory 20-3), a transfer size (D), and an external delay time (□ Δ) are registered. That is, the transfer source address (memory 20-1) of the row with the number “1” is the same as the transfer source address (memory 20-1) of the row with the number “2”.

  Next, the operation of the third embodiment will be described.

  FIG. 10 is a timing chart for explaining the operation of the third embodiment. FIG. 10 illustrates a case where the DMAC 100-3 performs two data transfers in succession and the transfer source of the two data transfers is on the same bus 30. As an example of the case where the data transfer source is the same, the case where the data transfer from the memory 20-1 to the memory 20-2 and the data transfer from the memory 20-1 to the memory 20-3 are continuously performed. explain. This corresponds to the case where the transfer information illustrated in the row with the number “1” and the row with the number “2” in FIG. 9 is registered in the transfer information registration unit 130-3. In FIG. 10, the horizontal axis indicates the passage of time, and the time passes from the left side to the right side of FIG. Here, the time is indicated by “T ○”.

  First, the CPU 10-1 instructs the DMAC 100-3 to start data transfer by registering the transfer information shown in the row of the number “1” in FIG. 9 in the transfer information registration unit 130-3. .

  Further, the CPU 10-1 registers the transfer information indicated in the row of the number “2” in FIG. 9 in the transfer information registration unit 130-3.

  The controller 110-3 of the DMAC 100-3, which has recognized that the transfer information is registered in the transfer information registration unit 130-3, first registers “transfer source address = memory 20-1, transfer destination address = memory 20”. -2, transfer size = C, external delay time = □□ ”. That is, it operates as shown in FIG.

  First, the control unit 110-3 of the DMAC 100-3 transmits a read request for the transfer size C to the memory 20-1 connected to the bus 30-1 that is the transfer source address (time T41 in FIG. 10). ). The memory 20-1 that has received the read request starts transmission of the read data to the transmission FIFO memory 120 (time T42). Then, the control unit 110-3 writes the data received from the memory 20-1, that is, the data of the transmission FIFO memory 120, together with the write request, to the memory 20-2 of the bus 30-2 that is the transfer destination address. Data is transmitted (time T43). This write data is transmitted to the memory 20-2 from time T43 to time T48.

  Here, the control unit 110-3 performs a calculation for obtaining the above-described “second request transmission time”. A method of calculating “second request transmission time” will be described later.

  Next, the control unit 110-3 determines whether the current time has reached the second request transmission time. Then, when the current time reaches the second request transmission time or when the second request transmission time has passed, a read request is transmitted to the memory 20-1 (time in FIG. 10). T45). By transmitting a read request at time T45, “transfer source address = memory 20-1, transfer destination address = memory 20-3, transfer size = D, externally registered in the transfer information registration unit 130-3. This means that the processing of “delay time = □ Δ” has started.

  The memory 20-1 that has received the read request transmitted at time T45 starts to transmit the read data to the transmission FIFO memory 120 (time T47). Then, the control unit 110-3 writes the data received from the memory 20-1, that is, the data of the transmission FIFO memory 120, together with the write request, to the memory 20-3 of the bus 30-3 that is the transfer destination address. Data is transmitted (time T49). Then, the transfer of all data of transfer size D to the memory 20-3 ends at time T50.

  At time T50, the data transfer from the memory 20-1 to the memory 20-2 and the data transfer from the memory 20-1 to the memory 20-3, which were the initial targets, are continuously performed, and Data transfer has been completed.

  Here, looking at the time point T47 in FIG. 10, it can be seen that the unused time shown as (1) in FIG. 7 is reduced on the bus 30-1. This is because the read request to the memory 20-1 was issued at time T35 in FIG. 7 (corresponding to time T48 in FIG. 10), but is accelerated to time T45 in FIG. Is.

  Here, a method of calculating the “second request transmission time” performed by the control unit 110-3 will be described.

  The control unit 110-3 predicts the time (T48 in FIG. 10) when transmission of the write data started at time T43 in FIG. 10 ends on the bus 30-2. The prediction here is performed in consideration of the transfer size (for example, transfer size = C) of the first transfer information registered in the transfer information registration unit 130-3, the operation speed of the bus 30-2, and the like. Then, the external delay time and the internal processing time are subtracted from the predicted time. This is the second request transmission time to be obtained. As the external delay time, the value (“□ Δ”) registered in the external delay time column (row 90-2, column 90-15) of the transfer information registration unit 130-3 in FIG. 9 is used. Good. Further, the internal processing time may be calculated and calculated by the control unit 110-3 as a time required for processing for transmitting the data in the transmission FIFO memory 120 to the memory 20-2.

  The operation of the third embodiment has been described above.

  As described above, the DMA controller (100-3) of the third embodiment includes the transfer information registration unit (130-3), the transmission FIFO memory (120), and the control unit (110-3). ing.

  Then, the first transfer information and the second transfer information are registered in the transfer information registration unit. The first transfer information includes a first transfer source address indicating an address of the first data storage means connected to the first bus, and a second bus connected to a second bus different from the first bus. 2 shows a first transfer destination address indicating the address of the second data storage means. The second transfer information is connected to a second transfer source address indicating the address of the first data storage means connected to the first bus, and to a third bus different from the first bus. And a second transfer destination address indicating the address of the third data storage means.

  When the first transfer information and the second transfer information are registered in the transfer information registration unit, the control unit operates as follows.

  That is, the control unit transmits data read from the first transfer source address to the first transfer destination address. Then, a second request transmission time which is an appropriate time for reading data from the second transfer source address is calculated. Next, the control unit transmits a read request to the second transfer source address when the current time reaches the second request transmission time or exceeds the second request transmission time. Then, the data of the second transfer source address is transmitted to the transmission FIFO memory. Then, when the storage of the data of the second transfer source address in the transmission FIFO memory starts to be started, the data of the second transfer source address stored in the transmission FIFO memory is transferred to the second transfer Send to the destination address.

  The second request transmission time is a time obtained by subtracting the internal processing time of the control unit and the external delay time indicated in the second transfer information from the predicted time. Here, the predicted time is a time estimated for the time until all data read from the first transfer source address is transmitted to the first transfer destination address. The internal processing time is a time required until the data of the first transfer source address transmitted to the transmission FIFO memory starts to be transmitted to the first transfer destination address.

  As described above, the DMA controller according to the third embodiment calculates the second request transmission time, which is an appropriate time for reading data from the second transfer source address. The second request transmission time is such that when data read from the first transfer source address is completely transmitted to the transmission FIFO memory, the data from the second transfer source address is immediately transmitted. This is the time for transmission to the FIFO memory.

  Then, if the current time reaches the second request transmission time or exceeds the second request transmission time, the DMA controller transmits a read request to the second transfer source address. As a result, the data of the second transfer source address is transmitted to the transmission FIFO memory. When the storage of the data of the second transfer source address is started in the transmission FIFO memory, the data of the second transfer source address stored in the transmission FIFO memory is changed to the second transfer destination. Send to address.

  As a result, as soon as the data of the first transfer source address has been transmitted to the transmission FIFO memory, the data of the second transfer source address starts to be transmitted to the transmission FIFO memory.

  Therefore, according to the present embodiment, when data transfer from the same transfer source address is continuously performed, the use efficiency of the bus connecting the data storage means of the same transfer source address is improved.

10 CPU
20 memory 30 bus 100 DMAC
DESCRIPTION OF SYMBOLS 110 Control part 120 Transmission FIFO memory 130 Transfer information registration part 11 Bus 12 Bus 13 Bus repeater 21 CPU
22 DMA controller 23 Device 24 Memory 26 CPU
27 DMA controller 28 Device 29 Memory

Claims (10)

A transfer source address indicating the address of the first data storage means connected to the first bus and a transfer indicating the address of the second data storage means connected to a second bus different from the first bus Transfer information indicating a destination address is registered from a CPU connected to the first bus;
A transmission FIFO memory for temporarily storing data read from the transfer source address;
When the transfer information indicating the transfer source address and the transfer destination address is registered in the transfer information registration unit, the data read from the transfer source address is transmitted to the transmission FIFO memory,
A controller that transmits the data stored in the transmission FIFO memory to the transfer destination address when storage of the data starts in the transmission FIFO memory;
A DMA controller comprising: In the transfer information registration unit,
A first transfer destination address indicating the address of the first data storage means connected to the first bus, and an address of the second data storage means connected to a second bus different from the first bus A first transfer source address indicating a first transfer information indicating;
A second transfer destination address indicating an address of the first data storage means connected to the first bus; and a third data storage means connected to a third bus different from the first bus. When the second transfer information indicating the second transfer source address indicating the address of
The control unit transmits data read from the first transfer source address to the first transfer destination address,
Calculating a request transmission time which is an appropriate time for reading data from the second transfer source address;
If the current time has reached the request transmission time or exceeds the request transmission time, a read request is transmitted to the second transfer source address and the data of the second transfer source address is transmitted. Send it to the FIFO memory,
When the storage of the data of the second transfer source address starts in the transmission FIFO memory, the data of the second transfer source address stored in the transmission FIFO memory is changed to the second transfer destination address. Send to
The DMA controller according to claim 1. The request transmission time is based on an estimated time in which the time until all data read from the first transfer source address is transmitted to the first transfer destination address is predicted.
The internal processing time of the control unit required until the data of the second transfer source address transmitted to the transmission FIFO memory starts to be transmitted to the second transfer destination address, and the second transfer information Is the time obtained by subtracting the external delay time being
The DMA controller according to claim 2. In the transfer information registration unit,
A first transfer source address indicating the address of the first data storage means connected to the first bus, and an address of the second data storage means connected to a second bus different from the first bus First transfer information indicating a first transfer destination address;
A second transfer source address indicating an address of the first data storage means connected to the first bus; and a third data storage means connected to a third bus different from the first bus. When the second transfer information indicating the second transfer destination address indicating the address of
The control unit transmits data read from the first transfer source address to the first transfer destination address,
Calculating a second request transmission time which is an appropriate time for reading data from the second transfer source address;
If the current time has reached the second request transmission time or exceeds the second request transmission time, a read request is transmitted to the second transfer source address to send the second transfer source The address data is transmitted to the transmission FIFO memory,
When the storage of the data of the second transfer source address starts in the transmission FIFO memory, the data of the second transfer source address stored in the transmission FIFO memory is changed to the second transfer destination address. Send to
The DMA controller according to claim 1. The second request transmission time is calculated from an estimated time in which a time until data read from the first transfer source address is all transmitted to the first transfer destination address is predicted.
The internal processing time of the control unit required until the data of the first transfer source address transmitted to the transmission FIFO memory starts to be transmitted to the first transfer destination address, and the second transfer information Is the time obtained by subtracting the external delay time being
The DMA controller according to claim 4. In a DMA controller comprising a transfer information registration unit for registering transfer information and a transmission FIFO memory for temporarily storing data read from the data storage means,
In the transfer information registration unit, a transfer source address indicating the address of the first data storage means connected to the first bus, and second data connected to a second bus different from the first bus When transfer information indicating the transfer destination address indicating the address of the storage means is registered, the data read from the transfer source address is transmitted to the transmission FIFO memory,
When the storage of the data in the transmission FIFO memory starts to be transmitted, the data stored in the transmission FIFO memory is transmitted to the transfer destination address.
A bus-to-bus data transfer method. In the transfer information registration unit,
A first transfer destination address indicating the address of the first data storage means connected to the first bus, and an address of the second data storage means connected to a second bus different from the first bus A first transfer source address indicating a first transfer information indicating;
A second transfer destination address indicating an address of the first data storage means connected to the first bus; and a third data storage means connected to a third bus different from the first bus. When the second transfer information indicating the second transfer source address indicating the address of the second transfer information is registered, the data read from the first transfer source address is transmitted to the first transfer destination address.
Calculating a request transmission time which is an appropriate time for reading data from the second transfer source address;
If the current time has reached the request transmission time or exceeds the request transmission time, a read request is transmitted to the second transfer source address and the data of the second transfer source address is transmitted. Send it to the FIFO memory,
When the storage of the data of the second transfer source address starts in the transmission FIFO memory, the data of the second transfer source address stored in the transmission FIFO memory is changed to the second transfer destination address. Send to
The inter-bus data transfer method according to claim 6. The request transmission time is based on an estimated time in which the time until all data read from the first transfer source address is transmitted to the first transfer destination address is predicted.
The internal processing time required until the data of the second transfer source address transmitted to the transmission FIFO memory starts to be transmitted to the second transfer destination address, and the external data indicated in the second transfer information It is the time obtained by subtracting the delay time.
The inter-bus data transfer method according to claim 7. In the transfer information registration unit,
A first transfer source address indicating the address of the first data storage means connected to the first bus, and an address of the second data storage means connected to a second bus different from the first bus First transfer information indicating a first transfer destination address;
A second transfer source address indicating an address of the first data storage means connected to the first bus; and a third data storage means connected to a third bus different from the first bus. When the second transfer information indicating the second transfer destination address indicating the address of the first transfer destination is registered, the data read from the first transfer source address is transmitted to the first transfer destination address.
Calculating a second request transmission time which is an appropriate time for reading data from the second transfer source address;
If the current time has reached the second request transmission time or exceeds the second request transmission time, a read request is transmitted to the second transfer source address to send the second transfer source The address data is transmitted to the transmission FIFO memory,
When the storage of the data of the second transfer source address starts in the transmission FIFO memory, the data of the second transfer source address stored in the transmission FIFO memory is changed to the second transfer destination address. Send to
The inter-bus data transfer method according to claim 6. The second request transmission time is calculated from an estimated time in which a time until data read from the first transfer source address is all transmitted to the first transfer destination address is predicted.
The internal processing time required until the data of the first transfer source address transmitted to the transmission FIFO memory starts to be transmitted to the first transfer destination address, and the external data indicated in the second transfer information It is the time obtained by subtracting the delay time.
The inter-bus data transfer method according to claim 9.

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