JP2016130350A - Structure including coating film and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure having a high insulation property and a high heat resistance, the structure being applicable to a micro-sized electronic component, and a manufacturing method of the structure.SOLUTION: A structure includes a ceramic substrate, a ceramic coating film of 1 to 10 μm in thickness, the ceramic coating film being formed directly on at least a part of the ceramic substrate using an aerosol deposition method. The coating film has a volume electric resistivity of 1.5×10Ω m or more and a heat resistance of 10 seconds or more, the heat resistance being measured with a solder bath of 270°C.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a structure including a coating film and a method for manufacturing the structure. More specifically, the present invention relates to a structure including a coating film formed by an aerosol deposition method and a method for manufacturing the structure using the aerosol deposition method.

  In recent years, communication devices such as mobile phones, tablet terminals, and wearable terminals have rapidly increased in number of mounted components due to the need for miniaturization and higher functionality. For this reason, in addition to downsizing, electronic chip components to be mounted are also required to have performance equal to or better than conventional products, high durability, and high reliability.

  In addition, an electronic chip component manufacturing method that satisfies these requirements is simultaneously required to be a low-cost manufacturing method suitable for mass production. As a conventional method for manufacturing an electronic chip component, for example, in the case of a chip inductor or MLCC (multilayer ceramic capacitor), the following method is employed. That is, the green sheets on which the internal electrode patterns are printed are stacked so as to have a required thickness, and the internal electrode patterns are cut leaving a margin that ensures electrical insulation. Then, it manufactures by baking each cut piece. However, in the case of ultra-small size chips such as 0402 type and 0201 type, which have been required in recent years, in the conventional manufacturing method, a reduction in inductance value occurs due to securing a margin, and in addition, electrical insulation with respect to the internal electrode pattern It has become difficult to ensure. Therefore, it is technically difficult to realize characteristics at a low cost and at least the same size as that of the conventional product by using the conventional manufacturing method.

  Therefore, in place of the above-described conventional technique for cutting while leaving the surplus width, a method for ensuring electrical insulation by cutting without leaving the surplus width and covering with a thin coating film in a later process has been proposed. (Side-Gap coating method). Along with this, there is a strong demand for thin film coating technology suitable for mass production that achieves high electrical insulation.

  Conventionally known thin film coating techniques include a wet coating method and a dry coating method. For example, the dip coating method, which is a kind of wet coating method, is a method of forming a coating film by dissolving or dispersing a coating material in a solvent and immersing the substrate, and is a manufacturing method that reduces costs. It is difficult to produce a thin film thickness of 5 μm or less.

  On the other hand, as typical examples of the dry coating method, a physical vapor deposition method (PVD method), a chemical vapor deposition method (CVD method), a thermal spray method, a cold spray method, and the like are known. Among these methods, for example, the formation of a coating film by the PVD method can be expected to form a dense and uniform thin film, but it has the disadvantages that a high vacuum environment is required and the film formation rate is extremely low. In addition, although the CVD method has a slightly improved film formation rate compared to the PVD method, it uses a toxic flammable gas such as tetraethylorthosilicate, which is not preferable in terms of environmental compatibility and handling. . Further, the thermal spray method and the cold spray method have a large thermal shock or mechanical shock, and are not suitable for manufacturing a coating film on a hard and brittle ceramic material used for electronic parts.

  In recent years, a dry coating technique called an aerosol deposition method (hereinafter also referred to as an AD method) has attracted attention for these techniques. The AD method is a technique in which a raw material powder aerosolized with argon gas or helium gas is sprayed on a substrate and a dense coating film is formed using a normal temperature impact solidification phenomenon (Non-patent Document 1 below). Unlike other coating methods, it can be carried out in a low vacuum, and since there is no thermal shock applied to the substrate, there are few alterations in the coating film, and there are advantages such as a relatively high deposition rate compared to other methods. . As a method for forming ultrafine particles using such an AD method, a method of irradiating ultrafine particles or a substrate with a high energy beam is known (Patent Document 1 below).

JP 2000-212766 A

S. K. Ahuja, Powder Technol. 16, 17 (1977)

  As described above, in response to the recent demand for miniaturization of electronic components, there is a situation that electronic components with sufficient performance are not provided depending on the conventional technology. Moreover, in order to mount an electronic component on an electronic board with solder, sufficient solder heat resistance is also required. Therefore, an object of the present invention is to provide a structure having a high insulation property and solder heat resistance, which is provided with a thin coating film, which can be used for a microelectronic component such as a chip inductor or MLCC, using the AD method. To do. Furthermore, it aims at providing the manufacturing method of a structure provided with the coating film relevant to this technique.

  As a result of intensive studies to solve the above problems, the present inventor has found that the above-described problems can be solved by the following structure and manufacturing method.

That is, one embodiment of the present invention includes a ceramic substrate,
A ceramic coating film having a thickness of 1 to 10 μm formed directly on at least a part of the ceramic substrate by an aerosol deposition method;
With
The coating film has a volume electrical resistivity of 1.5 × 10 ⁷ Ω · m or more and a solder heat resistance measured in a solder bath at 270 ° C. of 10 seconds or more.

Another aspect of the present invention is a preparation step of preparing a material powder having a volume-based median diameter D ₅₀ of 0.50 μm <D ₅₀ <1.0 μm;
A film forming step of forming a ceramic coating film on a ceramic substrate by an aerosol deposition method in which an aerosol gas containing the material powder is injected from a nozzle and the material powder is deposited;
It is a manufacturing method of the structure which has.

  ADVANTAGE OF THE INVENTION According to this invention, the structure which has high insulation and solder heat resistance which can be used for the electronic component of a very small size is provided by providing the thin coating film by AD method. In addition, according to the manufacturing method of the present invention, a structure having a high insulation property and solder heat resistance is provided at a low cost by using an AD method using a powder material having a specific particle size distribution and having a thin coating film. Can do. Moreover, by providing the structure of the present invention, an electronic component having a higher performance and a minimum size than that produced by a conventional method can be obtained.

(A) is a schematic perspective view which shows an example of a chip inductor provided with the structure of this invention, (b) is sectional drawing of (a). (A) is a schematic perspective view which shows an example of the chip inductor by a prior art, (b) is sectional drawing of (a). (A) is a figure for demonstrating the manufacturing method of an example of an electronic component provided with the structure of this invention, (b) is a figure for demonstrating the manufacturing method of an example of an electronic component by a prior art. It is a schematic diagram which shows an example of the film-forming apparatus by AD method. It is a schematic diagram which shows an aerosol generator. 2 is a surface observation image by SEM of the chip manufactured in Example 1. FIG. 2 is a cross-sectional observation image of the chip manufactured in Example 1 by SEM. It is a cross-sectional observation image by SEM after the thermal cycle test of the chip manufactured in Example 1. It is a cross-sectional observation image by SEM after the solder heat resistance test of the chip manufactured in Example 1. It is the surface observation image by the optical microscope after the scratch test of the chip | tip manufactured in Example 1. FIG. It is a surface observation image of the example which shows the brittle fracture behavior in a scratch test. 4 is a surface observation image by SEM of a chip manufactured in Example 2. FIG. 4 is a cross-sectional observation image of the chip manufactured in Example 2 by SEM. It is a cross-sectional observation image by SEM after the thermal cycle test of the chip manufactured in Example 2. It is a cross-sectional observation image by SEM after the solder heat resistance test of the chip manufactured in Example 2. It is the surface observation image by the optical microscope after the scratch test of the chip | tip manufactured in Example 2. FIG. 4 is a surface observation image by SEM of a chip manufactured in Example 3. FIG. It is a cross-sectional observation image by SEM of the chip manufactured in Example 3. It is a cross-sectional observation image by SEM after the thermal cycle test of the chip manufactured in Example 3. It is a cross-sectional observation image by SEM after the solder heat resistance test of the chip manufactured in Example 3. It is the surface observation image by the optical microscope after the scratch test of the chip | tip manufactured in Example 3. FIG.

  Hereinafter, the present invention will be described in detail by dividing it into a structure and a manufacturing method thereof.

[Structure]
The structure of the present invention comprises a ceramic substrate (hereinafter also simply referred to as a substrate) and a ceramic coating film (hereinafter simply coated) having a film thickness of 1 to 10 μm formed directly on the ceramic substrate by an aerosol deposition method. Also referred to as a membrane). The coating film has a volume electrical resistivity of 1.5 × 10 ⁷ Ω · m or more and a solder heat resistance measured in a solder bath at 270 ° C. of 10 seconds or more. The structure of the present invention only needs to include a ceramic substrate and a ceramic coating film that is in direct contact with at least a portion of the ceramic substrate, and the ceramic substrate may include other members such as internal electrodes, A portion where the ceramic substrate and the coating film are not in contact with each other may be included.

  For comparison with the present invention, FIG. 2A shows a schematic perspective view of a conventional chip inductor. In the chip inductor 20, external electrodes 23 are arranged on both end surfaces of the ceramic base 21, and the internal electrodes 22 are included in the ceramic base 21. Moreover, FIG.2 (b) is sectional drawing of the 2B-2B direction of Fig.2 (a). In the cross section of FIG. 2B, the laminated internal electrodes 22 and 22 'have a plurality of flat semi-elliptical shapes. There is a distance of an extra width 24 between the outer ends of the internal electrodes 22 and 22 ′ and the end of the ceramic substrate 21, and the internal electrodes 22 and 22 ′ are completely enclosed in the ceramic substrate. . The extra width 24 is necessary to maintain the high insulation of the chip inductor. In the prior art, the size of the chip inductor 20 has been reduced, and it has been technically difficult to cut the green sheet serving as the ceramic substrate 21 with the extra width 24 provided.

  On the other hand, FIG. 1A is a schematic perspective view showing a chip inductor as an example of an electronic component including the structure of the present invention. In the chip inductor 10, external electrodes 13 are arranged on both end surfaces of the ceramic base material 11, and internal electrodes 12 are inherent in the ceramic base material 11. Further, in FIG. 2A, the side surfaces of the ceramic substrate 11 and the external electrode 13 are covered with a ceramic coating film 14.

  FIG.1 (b) is sectional drawing of the 1B-1B direction of Fig.1 (a). Internal electrodes 12 and 12 ′ are present inside the ceramic substrate 11, but the laminated internal electrodes 12 and 12 ′ have a plurality of flat semi-elliptical shapes in the cross section of FIG. The outer ends of the plurality of internal electrodes 12, 12 ′ are exposed from the ceramic substrate 11 and are in contact with the coating film 14. Even if the internal electrodes 12 and 12 ′ are exposed from the ceramic base material 11, high insulation can be maintained as a whole chip by being covered with the coating film 14. Further, unlike the prior art, a difficult process of cutting the green sheet with the extra width 24 becomes unnecessary. Furthermore, since the internal electrodes 12 and 12 ′ can be arranged at positions where the outer end portions are exposed from the ceramic base material 11, the distance between the internal electrode 12 and the internal electrode 12 ′ is larger than that of the chip inductor according to the prior art. Can be taken widely. As a result, the inductance value of the chip inductor 10 can be increased. For example, in the case of the same size, stacking conditions, and internal electrode printing conditions, the inductance value is 2.2 times or more than that manufactured by the prior art in a specific frequency band. Further, according to the AD method, the adhesion between the substrate and the coating film is improved, so that the solder heat resistance is improved and the volume electrical resistivity is also improved.

  The ceramic coating film of the structure of the present invention has a thickness of 1 to 10 μm. When the film thickness is less than 1 μm, depending on the material of the coating film, it may be difficult to maintain sufficient high insulation when the structure is used for an electronic component. On the other hand, if it exceeds 10 μm, the size of the electronic component itself increases, and it is not possible to sufficiently meet the demand for miniaturization. The thickness of the coating film is more preferably 3 to 8 μm. The film thickness can be measured by cross-sectional observation with a scanning electron microscope (SEM).

The coating film of the structure of the present invention has a volume electric resistivity of 1.5 × 10 ⁷ Ω · m or more. The volume electrical resistivity is more preferably 2.7 × 10 ⁷ Ω · m or more, and still more preferably 3.6 × 10 ⁷ Ω · m or more. The upper limit is not particularly limited because it is better as it is higher, but it is 1.0 × 10 ¹⁴ Ω · m. When used for ultra-small electronic components, volume resistivity of 1.5 × 10 ⁷ Ω · m or more for ferrite coating and 1.0 × 10 ¹⁰ Ω · m or more for Al ₂ O ₃ and BaTiO ₃ coatings. If it can be ensured, it is more preferable because high insulation properties are easily maintained. The volume electrical resistivity is a value obtained by the method described in Examples described later.

  The coating film of the structure of the present invention has a solder heat resistance of 10 seconds or more measured in a solder bath at 270 ° C. In order to mount an electronic component with solder, heat resistance of 270 ° C. or higher is required, but the structure of the present invention has sufficient solder heat resistance. The solder heat resistance was tested by a solder heat resistance test (thermal shock test) based on JIS C 60068-2-58: 2006 described in the examples described later. The solder heat resistance is 10 seconds or more. "

  The ceramic coating film of the present invention is formed by the AD method. According to the AD method, a ceramic thin film of 10 μm or less can be formed at room temperature (25 ° C.) without passing through a sintering step. As will be described later, the coating film having the above-described volumetric electrical resistivity and solder heat resistance can be obtained by using the AD method and selecting the material of the ceramic substrate and the ceramic coating film.

  The structure of the present invention preferably has an in-film fracture strength (critical fracture strength) with respect to the substrate of the coating film of 7 N or more and a complete peel strength of 40 N or more. When the in-film fracture strength is 7 N or more and the complete peel strength is 40 N or more, the coating film has a sufficient film strength as a coating for electronic components. More preferably, the in-film fracture strength is 8N or more and the complete peel strength is 45N or more. Although the upper limit is preferably as high as possible, there is no particular limitation, but the in-film fracture strength is 60 N or less, and the complete peel strength is 200 N or less. The in-film fracture strength and the complete peel strength are values obtained by the scratch test method described in Examples described later.

  In the structure of the present invention, the relative density of the coating film is preferably 80% or more. When the relative density is 80% or more, a dense film suitable for the coating of the electronic component is obtained. The relative density is more preferably 82% or more. The upper limit of the relative density is 100%. The relative density is a value obtained by the method described in Examples described later.

  When the coating film is a soft magnetic material, the permeability at 10 kHz is preferably 200 to 1200, the saturation magnetic susceptibility at 2.4 kA / m is 300 to 500 mT, and the coercive force is preferably 10 to 100 A / m. Having such magnetic characteristics is suitable for electronic components such as chip inductors.

(Ceramic substrate)
There is no restriction | limiting in particular as a ceramic base material which can be used for the structure of this invention, You may use what kind of thing. Preferably, a sintered body obtained by sintering a green sheet or a laminate thereof used for manufacturing an electronic component can be used as the ceramic substrate.

For example, examples of the ceramic substrate include metal oxides, transition metal oxides, metal nitrides, metal carbides, boride-based ceramics, and silicon. The metal oxide or transition metal oxide may include a composite oxide. More specifically, metal oxides such as aluminum oxide, zinc oxide, silicon oxide, magnesium oxide, and calcium oxide; diamond, sapphire, cordierite, β sponge clay, forsterite, cermet, steatite, aluminum titanate, Composite oxides such as barium titanate, calcium titanate, strontium titanate, zinc titanate, mullite, spinel, calcium zirconate, strontium zirconate, barium zirconate titanate, bismuth titanate, strontium bismuth titanate; silicon carbide Metal carbides such as silicon nitride, aluminum nitride, boron nitride, titanium nitride, etc .; zirconium oxide, yttrium oxide, nickel oxide, iron oxide, titanium oxide, tantalum oxide, tin oxide, barium oxide Transition metal oxides such as palladium, cerium oxide, chromium oxide; Mg—Zn ferrite, Mn—Zn ferrite, Mn—Mg ferrite, Cu—Zn ferrite, Mg—Mn—Sr ferrite, Ni—Zn ferrite, Ni—Cu— Examples thereof include soft magnetic materials such as ferrite such as Zn ferrite, Ni—Cu—Zn—Mg ferrite, and Ba ferrite; silicon; and boride-based ceramics. These materials may be used alone or in combination of two or more. More preferably, aluminum oxide (Al ₂ O ₃ ), ferrite, barium titanate (BaTiO ₃ ), silicon (Si), silicon oxide (SiO ₂ ), silicon carbide (SiC), silicon nitride (SiN), titanium oxide ( Examples thereof include TiO ₂ ), titanium nitride (TiN), zirconium oxide (ZrO ₂ ), magnesium oxide (MgO), calcium oxide (CaO), and boron nitride (BN).

Among these, it is preferable that the base material contains at least one selected from Al ₂ O ₃ , ferrite, and BaTiO ₃ because it is more suitable for use as an electronic component. As the ferrite, Ni—Cu—Zn ferrite is more preferable. The Ni-Cu-Zn _{ferrite, Fe 2 O 3 - (9.8~14.2} ) mol% NiO- (25.3~29.1) mol% ZnO- (8.9~11.5) mol A composition of% CuO is more preferable.

(Ceramic coating film)
The ceramic coating film of the present invention is a 1-10 μm thin film ceramic having the above volume resistivity. Such a coating film is not particularly limited as long as it is formed by the AD method. The coating film by the AD method can be confirmed by observing the cross section of the structure by SEM observation or transmission electron microscope (TEM). Since the ceramic coating film of the present invention is formed by the AD method, the particles of the material powder are observed in a flattened state and are deposited in parallel along the direction of the interface between the substrate and the coating film Is observed. Also, the particle size distribution and shape of the coating film material powder can be confirmed by SEM observation, TEM observation, or particle size distribution mapping by EBSD.

  Examples of the formed coating film include ceramic materials similar to those of the substrate, and examples thereof include metal oxides, transition metal oxides, metal nitrides, metal carbides, and boride-based ceramics. The metal oxide or transition metal oxide may include a composite oxide.

More specifically, metal oxides such as aluminum oxide, zinc oxide, silicon oxide, magnesium oxide, and calcium oxide; cordierite, β sponge sponge, forsterite, cermet, steatite, aluminum titanate, barium titanate, Complex oxides such as calcium titanate, strontium titanate, zinc titanate, mullite, spinel, calcium zirconate, strontium zirconate, barium zirconate titanate, bismuth titanate, strontium bismuth titanate; metal carbides such as silicon carbide Metal nitrides such as silicon nitride, aluminum nitride, boron nitride, titanium nitride; zirconium oxide, yttrium oxide, nickel oxide, iron oxide, titanium oxide, tantalum oxide, tin oxide, vanadium oxide, cerium oxide, acid Transition metal oxides such as chromium; Mg—Zn ferrite, Mn—Zn ferrite, Mn—Mg ferrite, Cu—Zn ferrite, Mg—Mn—Sr ferrite, Ni—Zn ferrite, Ni—Cu—Zn ferrite, Ni—Cu -Soft magnetic materials such as ferrite such as Zn-Mg ferrite and Ba ferrite; silicon; boride-based ceramics. These materials may be used alone or in combination of two or more. More preferably, aluminum oxide (Al ₂ O ₃ ), ferrite, barium titanate (BaTiO ₃ ), silicon oxide (SiO ₂ ), silicon carbide (SiC), silicon nitride (SiN), titanium oxide (TiO ₂ ), nitriding Examples thereof include at least one of titanium (TiN), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), magnesium oxide (MgO), calcium oxide (CaO), and boron nitride (BN). These may be used alone or in combination of two or more.

Among these, it is preferable that the coating film contains at least one selected from Al ₂ O ₃ , ferrite, and BaTiO ₃ because it is more excellent in adhesion to the substrate and heat resistance. As the ferrite, Ni—Cu—Zn ferrite is more preferable. The Ni-Cu-Zn _{ferrite, Fe 2 O 3 - (9.8~14.2} ) mol% NiO- (25.3~29.1) mol% ZnO- (8.9~11.5) mol A composition of% CuO is more preferable.

There is no restriction | limiting in particular as a combination of a ceramic base material and a ceramic coating film | membrane, It can be set as the structure of a desired combination. Preferably, from the viewpoint of mutual adhesion, volumetric electrical resistivity improvement and heat resistance improvement, the base material contains ferrite and the coating film contains at least one of ferrite and Al ₂ O ₃ , or the base material is Al ₂ O ₃ and the coating film include Al ₂ O ₃ , or the substrate includes BaTiO ₃ and the coating film includes Al ₂ O ₃ .

[Production method]
The structure manufacturing method of the present invention includes a preparation step of preparing a material powder having a volume-based median diameter D ₅₀ of 0.50 μm <D ₅₀ <1.0 μm, and injecting an aerosol gas containing the material powder from a nozzle And forming a ceramic coating film on the ceramic substrate by an aerosol deposition method for depositing the material powder.

  In order to describe the manufacturing method of the present invention, first, a method for manufacturing an electronic component called a side gap method (hereinafter also referred to as an SG method) will be briefly described.

  FIG. 3B is a schematic diagram showing a part of a conventional chip inductor manufacturing method for comparison. A cross section of the green chip 40 is shown on the left side of FIG. The green chip 40 is manufactured as follows. The internal electrode conductive paste film 42 is formed on the green sheet 41 by screen printing the internal electrode conductive paste in a predetermined shape. Next, a plurality of green sheets 41 on which the internal electrode conductive paste film 42 is formed are stacked, and a green sheet 41 on which the conductive paste film 42 is not formed is stacked so as to sandwich the green sheets 41. And crimp. Thereafter, the stacked green sheets 41 are aligned and cut so as to have an extra width necessary for the inductor obtained after sintering. Thereby, the green chip 40 is obtained. Thereafter, the green chip 40 is sintered to obtain the chip inductor 20 whose cross section is shown on the right side of FIG. In the inductor 20, the ceramic base material 21 includes the internal electrode 22, and a margin 24 is provided between the outer end of the internal electrode 22 and the side surface of the ceramic base material. As the chip inductor 20 is reduced in size, it is technically difficult to align the green sheet and secure the necessary extra width 24 for cutting.

  On the other hand, FIG. 3A shows an example of a manufacturing method of the chip inductor of the present invention using the SG method. A cross section of the green chip 50 is shown on the left side of FIG. In the SG method, the green chip 50 is manufactured as follows. In the same manner as in the prior art described above, the internal electrode conductive paste film 52 is formed on the green sheet 51, and a plurality of green sheets 41 on which the internal electrode conductive paste film 42 is formed are stacked. The green sheets 41 on which the conductive paste film 42 is not formed are stacked and pressure-bonded so as to be sandwiched. Next, in the SG method, the green sheet 41 is cut so that the conductive paste film 52 is slightly exposed from the end of the green sheet 51 to obtain the green chip 50. Thereafter, the green chip 50 is sintered to obtain the bare chip 30 whose cross section is shown in the center of FIG. In the bare chip 30, the ceramic substrate 11 does not completely enclose the internal electrode 12, and the internal electrode 12 is exposed from the side surface of the bare chip 30. Finally, the side surface of the bare chip 30 where the internal electrode 12 is exposed is covered with the coating film 14 to obtain the chip inductor 10. According to the SG method, when the green chip 50 is manufactured, it is not necessary to cut it while leaving a strict alignment and a surplus width, so that the chip inductor 10 can be manufactured more easily technically. The manufacturing method of the present invention relates to a technique for forming the coating film 14 particularly in the SG method.

<Preparation process>
In the preparation step, a material powder having a volume-based median diameter D ₅₀ of 0.50 μm <D ₅₀ <1.5 μm is prepared. The material powder is in the range median diameter D ₅₀ of the above, as long as the above-mentioned ceramic coating layer can be formed by the AD method is not particularly limited. When the median diameter D ₅₀ is in such a range, volume resistivity required for the electronic component and the solder heat resistance of the ceramic coating film.

In order to obtain a powder having a median diameter D ₅₀ of 0.50 μm <D ₅₀ <1.5 μm, a commercially available product may be used or it may be prepared by itself. For example, a lump of material described later may be crushed to prepare a fine particle powder, or the fine particle powder may be heat-treated to obtain a powder having a larger particle size. Median diameter D ₅₀ based on volume is determined by the method of measurement in Examples described later.

The material powder preferably has a flat shape with an aspect ratio of 100> D ₅₀ /t>1.3, where t is the thickness of the powder particles. Such a flat shape is preferable because it is easily deposited on the substrate by the AD method and the film forming speed is also high. The method for measuring the aspect ratio is based on the method described in Examples described later.

(Material powder)
The material powder that can be used in the present invention is preferably at least one powder selected from a highly insulating oxide material, a soft magnetic material, and a ferroelectric oxide material because it is suitable for use in electronic parts. The highly insulating oxide material means a material having a volume electrical resistivity in the range of 1.0 × 10 ^{8 to} 1.0 × 10 ¹⁷ Ω · m at room temperature. The soft magnetic material is a material having a saturation magnetization Ms of 300 to 500 mT (2.4 kA / m) and a coercive force of 0.1 to 100 A / m. The ferroelectric oxide material refers to a material having a relative dielectric constant of 1000 to 20000 at a measurement frequency of 1 MHz.

  More specifically, the material powder includes metal oxides, transition metal oxides, metal nitrides, metal carbides, highly insulating oxide materials such as boride ceramics, soft magnetic materials such as ferrite, and simple perovskites. Examples thereof include ferroelectric oxide materials such as Ba, Pb, and Bi-based ferroelectric compounds included in the basic structure. More specifically, examples of highly insulating oxide materials, soft magnetic materials, and ferroelectric oxide materials include metal oxides such as aluminum oxide, zinc oxide, silicon oxide, magnesium oxide, and calcium oxide; cordierite, β Sponge, forsterite, cermet, steatite, aluminum titanate, barium titanate, calcium titanate, strontium titanate, zinc titanate, mullite, spinel, calcium zirconate, strontium zirconate, barium zirconate titanate, Composite oxides such as bismuth titanate and strontium bismuth titanate; metal carbides such as silicon carbide; metal nitrides such as silicon nitride, aluminum nitride, boron nitride, and titanium nitride; zirconium oxide, yttrium oxide, nickel oxide, iron oxide, Oxidation Transition metal oxides such as tan, tantalum oxide, tin oxide, vanadium oxide, cerium oxide, chromium oxide; Mg—Zn ferrite, Mn—Zn ferrite, Mn—Mg ferrite, Cu—Zn ferrite, Mg—Mn—Sr ferrite, Examples include soft magnetic materials such as ferrite such as Ni—Zn ferrite, Ni—Cu—Zn ferrite, Ni—Cu—Zn—Mg ferrite, and Ba ferrite; silicon; and boride-based ceramics. These may be used alone or in combination of two or more.

Among these, since it is suitable for use in electronic parts, highly insulating oxide materials include Al ₂ O ₃ , SiO ₂ , MgO, CaO, transition metal oxides, metal nitrides, metal carbides, and boride-based ceramics. It is preferable that at least one kind is used, the soft magnetic material is ferrite, and the ferroelectric oxide material is at least one kind of Ba, Pb, and Bi-based ferroelectric compounds including simple perovskite in the basic structure. As the ferroelectric oxide material, BaTiO ₃ is more preferable. Furthermore, it is preferable to include at least one selected from Al ₂ O ₃ , ferrite, and BaTiO ₃ because a coating film that is superior in adhesion to the substrate and heat resistance can be obtained. That is, it is preferable that the highly insulating oxide material is Al ₂ O ₃ , the soft magnetic material is ferrite, and the ferroelectric oxide material is BaTiO ₃ . As the ferrite, transition metal ferrite is preferable, and Ni—Cu—Zn ferrite is more preferable. The Ni-Cu-Zn _{ferrite, Fe 2 O 3 - (9.8~14.2} ) mol% NiO- (25.3~29.1) mol% ZnO- (8.9~11.5) mol A composition of% CuO is more preferable.

There is no restriction | limiting in particular as a combination of a ceramic base material and material powder, It can be set as a desired combination. Preferably, from the viewpoints of adhesion when the coating film is formed, volume electric resistivity and heat resistance, the base material contains ferrite and the material powder contains ferrite, or the base material is Al ₂ O. ₃ and the material powder contains ferrite, or the substrate contains Al ₂ O ₃ and the material powder contains Al ₂ O ₃ .

<Film formation process>
In the film forming step, an aerosol gas containing material powder is ejected from a nozzle to form a ceramic coating film on the ceramic substrate by an aerosol deposition method in which the material powder is deposited.

  FIG. 4 is a schematic diagram showing an example of a film forming apparatus using the AD method. The film forming apparatus 60 includes a vacuum chamber 61, an exhaust pump 62 for exhausting the vacuum chamber 61, and an aerosol generator 63 disposed outside the vacuum chamber 61. In the vacuum chamber 61, a stage 64 that can move in the horizontal direction for placing the ceramic substrate 11 is installed, and a nozzle 66 that injects an aerosol gas is arranged. The aerosol gas from the aerosol generator 63 is transported to the nozzle 66 by the transport pipe 67. In the aerosol generator 63, the carrier gas is introduced from the carrier gas cylinder 70 through the carrier pipe 69 and the carrier gas through the carrier pipe 68. The aerosol generator 63 contains a powder material 71, and the aerosol gas generated by winding the powder material 71 with the winding gas is led out to the transfer pipe 67 by the transfer gas. The aerosol gas ejected from the nozzle 66 deposits powder on the ceramic substrate 11 that is placed opposite to the nozzle 66 through the mask 65. At that time, the material powder 71 in the aerosol gas forms a dense ceramic coating film on the ceramic substrate 11 by a normal temperature impact solidification phenomenon.

  FIG. 5 is a schematic diagram of the aerosol generator 63. The carrier tube 69 is inserted into the powder material 71 deposited at the lower part of the aerosol generator, and a rolled-up gas diffusion member 72 is attached to the tip of the carrier tube 69. The powder material 71 is wound up by the winding gas introduced into the transport pipe 69, and aerosol gas is generated in the aerosol generator 63. The aerosol gas is led out from the transport pipe 67 connected above the aerosol generator 63 by the transport gas from the transport pipe 68 connected to the upper surface of the aerosol generator 63. The flow rate of the aerosol gas is controlled by two systems of the winding gas flow rate and the carrier gas flow rate. The transport pipes 67, 68, and 69 are preferably arranged in the aerosol generator 63 in a positional relationship that does not hinder the flow rate of the generated aerosol gas as much as possible. That is, it is preferable that the carrier gas carrier pipe 68 and the hoist gas carrier pipe 69 are installed separately from the carrier pipe 67 to the nozzle 66 so as not to disturb the flow rate of the generated aerosol gas.

  In the present invention, as described above, in the film forming process, the aerosol gas is generated by introducing the winding gas and the carrier gas into the aerosol generator 63 containing the powder, and is conveyed to the nozzle 66. The carrier gas flow rate is preferably 0 to 30 SLM, and the hoisting gas flow rate is preferably 20 to 120 SLM. When the carrier gas flow rate and the winding gas flow rate are within such ranges, it is suitable for forming a ceramic coating film having a desired volume electric resistivity and solder heat resistance. The carrier gas flow rate is more preferably 20-30 SLM, and the winding gas flow rate is more preferably 40-60 SLM.

  Further, the ratio of the carrier gas flow rate to the hoisting gas flow rate is preferably 1: 1.5 to 1: 7. Within such a range, it is more preferable to form a ceramic coating film having a desired volume electrical resistivity and solder heat resistance. The ratio between the carrier gas flow rate and the hoisting gas flow rate is more preferably 1: 1.5 to 1: 5.5.

  The scanning speed of the nozzle 66 is preferably 200 to 400 mm / min. When the scanning speed is within such a range, it is more preferable to form a ceramic coating film having a desired volume resistivity and solder heat resistance. To scan the nozzle 66, the nozzle 66 may be fixed and the stage 64 may be moved as described above, or the stage 64 may be fixed and the nozzle 66 may be moved. The scanning speed of the nozzle 66 is more preferably 250 to 350 mm / min. The nozzle 66 preferably has a horizontal width of 1.0 to 200 mm and a vertical width of 0.1 to 2.0 mm, more preferably a horizontal width of 50 to 100 mm and a vertical width of 0.1 to 0.5 mm.

  In the manufacturing method of the present invention, a preferable pressure in the vacuum chamber is 10 to 100 kPa. This range is preferable because it is suitable for the AD method.

[Electronic parts]
The present invention further provides an electronic component including the structure or the structure manufactured by the manufacturing method. Although there is no restriction | limiting in particular as an electronic component, A chip inductor, a multilayer ceramic capacitor, a chip resistor etc. are mentioned. Since these electronic components have the structure of the present invention, they have high insulation and high heat resistance even if they are extremely small. In addition, since there is no need for a conventional process of cutting the green sheet while leaving a surplus width, the electronic component can be manufactured more easily and at a low cost. In particular, when the electronic component is a chip inductor, the internal electrode can be disposed at a position exposed from the side surface of the chip, so that the inductance value can be increased and a high capacity can be realized.

  EXAMPLES Hereinafter, although this invention is demonstrated through an Example, this invention is not limited to an Example.

<Example 1>
In Example 1, ferrite powder (aspect ratio D ₅₀ /t=0.56 μm / 0.068 μm) was used as the material powder, and the base materials shown in Table 1 below were used. According to the following procedure, coating by the AD method was performed using the film forming apparatus shown in FIG. 4, and the fabricated structure was evaluated.

First, Ni-Zn-Cu-ferrite powder (manufactured by SAMSUNG) having a volume-based median diameter ₀ of D ₅₀ = 0.56 μm was prepared, and heat treatment was performed at 300 ° C. for 24 hours to remove residual moisture and impurities. did. The composition of Ni-Zn-Cu-ferrite was Ni: 13 mol%, Zn: 29 mol%, Cu: 9 mol%. Thereafter, the powder was put into an aerosol generator. As carrier gas, flow rate of N ₂ gas: 30 SLM (Standard Litter per Minutes), as winding gas, flow rate of N ₂ gas: 60 SLM, nozzle scanning speed: 300 mm / min, vacuum chamber pressure: 1.0 × 10 ⁻² Coating was repeated 30 times on the substrate under the conditions of Pa, nozzle diameter: 100 mm × 0.3 mm.

<Comparative Examples 1-4>
In Comparative Example 1, a ferrite sintered body (bulk) was prepared in order to use as a reference for evaluation of density and volume electric resistivity. In Comparative Examples 2 to 4, structures were prepared in the same manner as in Example 1 except that the materials and conditions shown in Table 1 below were used. However, for Comparative Example 2, no ceramic coating film was formed.

<Evaluation method>
The structures of Examples and Comparative Examples were evaluated by conducting the following tests. The evaluation results are shown in Tables 1 to 3 below.

(Relative density)
The film density (relative density) of the coating film was calculated based on the input amount of powder and the change in the weight of the substrate before and after coating. Further, in order to examine the surface state of the produced coating film and the interface state of (ferrite substrate) / (coating film), appearance observation and cross-sectional observation of the sample were performed using a scanning electron microscope (SEM).

(Volume electrical resistivity)
Regarding the electrical insulation of the coating film, a coating film is separately formed on the Si wafer under the same conditions, and then an Ag-counter electrode (φ = 2.0 mm) having a thickness of about 200 nm is produced by sputtering. Then, the volume electrical resistivity was measured with a high resistance meter (4339B) manufactured by Hewlett Packard at an applied voltage of 100 mV to 10 V using the circular electrode portion.

(Volume-based median diameter D ₅₀ and aspect ratio)
The particle size distribution of the raw material powder used _{(D 50),} was measured using a DT1200 (Disperion Technology, Inc.). Regarding also the aspect ratio characterizing the flat powder particles, (D value of ₅₀₎ / (the powder particles thickness: t) was calculated by. The thickness t of the powder particles is measured by observing a polished sample after embedding the raw material powder in an acrylic resin with an SEM and analyzing the photographed powder particle cross-sectional image. Further, the aspect ratio is obtained by measuring 30 randomly selected powder particles and calculating an average value thereof.

(Solder heat resistance test)
In order to actually apply it as an electronic chip component, it is necessary that the produced coating film withstands the thermal shock at the time of soldering or bonding a Ni or Ag terminal electrode. Therefore, the solder heat resistance test was performed according to the procedure shown in JIS C 60068-2-58: 2006. Specifically, a rosin ethanol 25 wt% solution was applied to the sample as a flux and preheated 150 ± 10 ° C. (60 to 90 seconds). Thereafter, in a Sn-3.0Ag-0.5Cu composition solder bath adjusted to a temperature of 270 ± 5 ° C., immersion time: 10 ± 0.5 seconds (stationary solder) and immersion speed: 25 mm / s. A thermal shock was applied. Then, it was left at room temperature for 48 ± 4 hours.

  Regarding the evaluation of the prepared sample, after the above test, the appearance and cross-sectional observation of the sample were performed by SEM, and the presence or absence of peeling of the coating film and cracks were confirmed. As an evaluation standard, the one in which peeling from the substrate and cracks were not confirmed was regarded as acceptable. Moreover, evaluation was implemented with respect to ten samples selected at random out of 100 produced structures. In Tables 1 to 3, the evaluation criteria are described as “◯” if all 10 samples are acceptable, and “x” as unacceptable if any one is defective.

(Thermal cycle test)
Since the electronic chip component to which the present invention is applied may cause a short circuit due to moisture intrusion, it should not crack when used for a long time. Therefore, the thermal cycle test was performed based on the procedure shown in JIS C60068-2-14: 2011. Specifically, the sample is held in a −55 ° C. bath for 30 min, held at room temperature (25 ° C.) for a maximum of 5 min, held in a 125 ° C. bath for 30 min, and held at a room temperature (25 ° C.) for a maximum of 5 min. The procedure of applying a load to the body was performed 100 cycles.

  The obtained sample was subjected to SEM to observe the appearance and cross section of the sample, and confirmed the presence or absence of peeling of the coating film and cracks. As an evaluation standard, the one in which peeling from the substrate and cracks were not confirmed was regarded as acceptable. In Tables 1 to 3, a sample that passed was marked with ◯, and a sample that failed was marked with ×. As for the evaluation criteria, among all 10 samples, if all 10 were acceptable, they were marked with ◯, and if any were defective, they were marked as unacceptable with x. The thermal cycle test was premised on passing the solder heat resistance test, and therefore only the test that passed the solder heat resistance test was performed.

(Scratch test)
The adhesion between the coating film and the ferrite substrate is evaluated by the scratch test method, and the in-film fracture strength is based on the characteristics of applied load, coefficient of friction, acoustic emission (AE), and texture change of scratch marks. (Internal Delamination: ID, critical fracture strength) and complete peel strength (CD) were determined. The test conditions for the scratch test were as follows. In addition, regarding the scratch test, it implemented only to the sample which passed the above-mentioned thermal cycle test and solder heat resistance test.

Diamond indenter diameter: 200 μm
Additional load: 0N to 100N (0N to 80N for ferrite substrate)
Scanning speed: 0.17mm / sec
Scanning distance: 10 mm.

<Evaluation of Example 1>
6 is an SEM surface observation image of the structure of Example 1, and FIG. 7 is a cross-sectional observation image of the structure of Example 1 by SEM. From FIG. 6, it can be seen that no abnormality in the appearance such as cracks, impurity phases, and peeling of the coating film is observed on the surface of the produced coating film. In the cross section of the sample shown in FIG. 7, the black area at the top is the acrylic resin used to support the sample, the band-shaped area at the middle is the ceramic coating film, and the area containing the lower spotted contrast is the ferrite base It is a material. As a feature of the sample cross-sectional photograph, although an unevenness of about 1 μm is observed at the (acrylic resin) / (coating film) interface, cracks and peeling of the coating film are not confirmed. Further, the (coating film) / (ferrite substrate) interface does not show a clear boundary indicating the presence of the interface, suggesting that the adhesion between both regions is high. Regarding the observation of the sample cross section, in FIGS. 8 to 9, 13 to 15, and 18 to 20, the upper region is the acrylic resin used to support the sample, and the middle band-like region is the ceramic. The coating film and the lower region are base materials.

  8 and 9 are SEM observation images of a cross section of the structure after the thermal cycle test and the solder heat resistance test of Example 1. FIG. In any case, no cracks or peeling of the coating film was observed at the (acrylic resin) / (coating film) and (coating film) / (ferrite substrate) interfaces, and the state before the test (FIG. 7) and the state It can be seen that there is no change. Therefore, the structure of Example 1 is suitable for actual solder mounting of electronic chip components and terminal electrode baking processes.

  FIG. 10 is an optical micrograph of the surface of the structure after the scratch test was performed on the surface of the structure of Example 1. In FIG. 10, white linear scratch marks are clearly observed on the ferrite substrate exhibiting black contrast. It can be seen that there is no noticeable abnormality in appearance on the scratch line, and even when the maximum load value of 80 N is applied, no trace of complete peeling of the coating film is confirmed. Further, as a result of examining whether the coating film and the substrate were broken or not by the AE sensor, a large AE peak was observed when the applied load was 17.8N. From the characteristics of these scratch marks, it was found that the in-film fracture strength of Example 3 was 17.8 N, and the complete peel strength was 80 N or higher. When the in-film fracture strength is a critical load value, the in-film fracture strength of this test is a diamond-like carbon (DLC) in-film fracture strength of 7.5 N or more used for surface coating such as super tool steel. This shows that a sufficient value is secured as the adhesion strength of the coating film at room temperature of the electronic chip component. For comparison, FIG. 11 shows an example of scratch marks showing brittle fracture behavior. In FIG. 10, shell-like peeling outside the scratch line as shown in FIG. 11 is not observed, so it can be said that the film breakage is not brittle and is close to an ideal breakage behavior.

From the results shown in Table 1, the relationship between the film thickness and the film formation rate with respect to the volume-based median diameter D _{50 is} that the film formation rate of the ferrite powder having the median diameter of D ₅₀ = 0.56 μm in Example 1 is the highest. It can be seen that the numerical value is about twice that of Comparative Example 3 in which ₅₀ = 2.00 μm. On the other hand, as seen in Comparative Example 2, the median diameter D ₅₀ is more than 3.00, formation of the coating film to the substrate was not confirmed.

Regarding the film density, reflecting the characteristics of the film formation rate, a dense coating film was obtained in the ferrite powder of D ₅₀ = 0.56 μm of Example 1, and showed a high numerical value of a relative density of 94.3%. ing. Regarding the electrical resistivity, the coating film of Example 1 has a numerical value equal to or higher than that of the sintered body of Comparative Example 1, and can be applied to an electronic chip component as a coating film for insulation purposes. . Further, when Example 1 and Comparative Example 4 are compared, Example 1 using a material powder having a median diameter of D ₅₀ = 0.56 μm is more preferable in terms of the adhesion strength of the film and the volume resistivity. It can be seen that excellent results are obtained. In the case of Comparative Example 3, it is possible to determine that the electrical resistivity has a numerical value equivalent to that of the bulk, but there is a problem with the solder heat resistance, and that the result of Example 1 is superior.

<Example 2>
In Example 2, Al ₂ O ₃ powder having a median diameter D ₅₀ shown in Table 2 below was used as the material powder of the ceramic coating film, and an Al ₂ O ₃ substrate was used as the substrate. As the Al ₂ O ₃ powder, a flat powder having a median diameter D ₅₀ adjusted by a pulverization method was used (aspect ratio D ₅₀ /t=0.52 μm / 0.079 μm).

In Example 2, a structure was produced in the same manner as in Example 1 except that the Al ₂ O ₃ powder and the base material were used and the film formation conditions were as follows. Moreover, the same evaluation as Example 1 was performed. The evaluation results are shown in Table 2 below.

Carrier gas N ₂ gas flow rate: 20 SLM
Winding gas N ₂ gas flow rate: 40 SLM
Nozzle scanning speed: 300 mm / min
Number of coatings: 50 times.

<Comparative Examples 5-6>
In Comparative Example 5, an Al ₂ O ₃ sintered body (bulk) was prepared in order to use as a reference for evaluating relative density and volume resistivity. In Comparative Example 6, a structure was fabricated in the same manner as in Example 2 except that the materials and conditions shown in Table 2 below were used. However, for Comparative Example 6, no ceramic coating film was formed.

<Evaluation of Example 2>
12 and 13 are SEM surface appearance and cross-sectional observation images of the coating film formed on the Al ₂ O ₃ substrate using the flat Al ₂ O ₃ powder produced in Example 2. FIG. . It can be seen that the coating film surface state shown in FIG. 12 shows no abnormalities such as foreign matters or cracks in appearance. Moreover, in the photograph of the cross section of the structure in FIG. 13, no cracks or peeling of the coating film was observed at the (acrylic resin) / (coating film) and (coating film) / (Al ₂ O ₃ base material) interfaces. .

14 and 15 are SEM observation images of the cross section of the structure after the thermal cycle test and solder heat resistance test of Example 2. FIG. At the (coating film) / (Al ₂ O ₃ substrate) interface, no abnormalities in appearance such as cracks are observed, and it can be seen that there is no change from the sample before the test (FIG. 13). Therefore, it can be concluded that the structure of Example 2 can withstand the actual solder mounting of electronic chip components and the terminal electrode baking process.

FIG. 16 is an optical micrograph of the sample surface after the scratch test was performed on the structure surface of Example 2. In FIG. 16, white linear scratch marks are clearly observed on the Al ₂ O ₃ base material showing black contrast. From the scratch line trace and the AE peak shape change, the in-film fracture strength of Example 2 was 19.4 N and the complete peel strength was 46 N. Since this value shows a strength of 7.5 N or more of the diamond-like carbon in-film fracture strength, it can be determined that a sufficient value is secured as the adhesion strength of the coating film of the electronic chip component. Further, since shell-like peeling outside the scratch line as shown in FIG. 11 is not observed, the membrane breakage is not brittle and is an ideal fracture behavior.

With respect to the shape of the Al ₂ O ₃ powder, in Example 2 produced using a flat powder with D ₅₀ = 0.52 μm, an Al ₂ O ₃ coating film having a maximum thickness of 8 μm was formed. The speed was as high as 0.23 μm / min. From this, in the case of Al ₂ O ₃ coating, it can be said that the use of flat powder is preferable for film formation. Further, as the material of the base material, there is a tendency that a dense film is obtained when an Al ₂ O ₃ and BaTiO ₃ substrate is used. Further, regarding the relationship between the adhesion strength of the substrate and the coating film to be selected, there is a tendency that the peeling strength of the coating film can be secured when an Al ₂ O ₃ substrate is selected. Although the volume electrical resistivity is lower than that of the Al ₂ O ₃ sintered body, it can be seen that the electrical resistivity equivalent to that of the ferrite sintered body is exhibited. Example 2 passed the thermal cycle test and the solder heat resistance test, and it can be determined that the produced coating film can be applied to an electronic chip component as a coating film for insulation purposes.

<Example 3>
In Example 3, except that BaTiO ₃ powder (aspect ratio D ₅₀ /t=0.874 μm / 0.131 μm) having a median diameter D ₅₀ shown in Table 3 below was used as a material powder, and the following film formation conditions were used. A structure was manufactured in the same manner as in Example 1. The obtained structure was evaluated in the same manner as in Example 1. The evaluation results are shown in Table 3 below.

N ₂ gas flow rate as carrier gas: 20 SLM
Winding gas N ₂ gas flow rate: 100 SLM
Nozzle scanning speed: 300 mm / min
Number of coatings: 30 times.

<Comparative Examples 7-11>
In Comparative Example 7, a BaTiO ₃ sintered body (bulk) was prepared in order to use as a reference for evaluating density and volume electric resistivity. In Comparative Examples 8 to 11, structures were produced in the same manner as in Example 3 except that the materials and conditions shown in Table 3 below were used. However, in Comparative Examples 8 to 11, the ceramic coating film was not formed in w.

<Evaluation of Example 3>
17 and 18 are SEM observation images of the surface appearance and cross-section of the coating film of the structure manufactured in Example 3. FIG. It can be seen that the coating film surface state shown in FIG. 17 shows no abnormalities such as foreign matters or cracks in appearance. Also, in the photograph of the cross section of the structure in FIG. 18, no cracks or peeling of the coating film was observed at the (acrylic resin) / (coating film) and (coating film) / (Al ₂ O ₃ base material) interfaces. .

19 and 20 are SEM observation images of the cross section of the structure after the thermal cycle test and solder heat resistance test of Example 3. FIG. It can be seen that no appearance abnormality such as cracks is observed at the (coating film) / (Al ₂ O ₃ base material) interface shown in FIGS.

  FIG. 21 is an optical micrograph after the scratch test was performed on the coating film on the surface of the structure of Example 3. In FIG. 21, white line-shaped scratch marks are clearly observed on the substrate exhibiting black contrast. From the scratch line trace and the AE peak shape change, the in-film fracture strength of Example 3 was 34.0 N, and the complete peel strength was 52.2 N. Since this value shows a strength of 7.5 N or more of the diamond-like carbon in-film fracture strength, it can be determined that a sufficient value is secured as the adhesion strength of the coating film of the electronic chip component. Moreover, since shell-like peeling outside the scratch line as shown in FIG. 11 is not observed, it can be said that the destruction of the film is not brittle and is an ideal breaking behavior.

As a characteristic regarding D ₅₀ (volume-based median diameter) of the BaTiO ₃ powder used, in Example 3 produced using a powder of D ₅₀ = 0.874 μm, a coating film was confirmed on the substrate. On the other hand, in Comparative Examples 8 to 11 using BaTiO ₃ powder having a D ₅₀ of less than 0.5 μm and a D ₅₀ of more than 1 μm, the substrate itself is scraped even with respect to the glass substrate that is most easily formed. Only a green compact deposit was obtained, and the formation of the coating film could not be confirmed. Further, regarding the density of the obtained coating film, there was a tendency that the densest film was obtained when an Al ₂ O ₃ substrate was used.

Regarding the relationship between the adhesion strength of the base material and the coating film, there is a tendency that the peeling strength of the coating film can be ensured when an Al ₂ O ₃ substrate is selected.

Although the volume electrical resistivity of Example 3 is slightly lower than that of the BaTiO ₃ sintered body, it exhibits an electrical insulation equivalent to or higher than that of the ferrite sintered body. Accordingly, it can be seen that the coating film for insulation purposes has a problem-free performance. Furthermore, since the structure of Example 3 passed the thermal cycle test and the solder heat resistance test, it can be determined that the produced coating film can be applied to an electronic chip component as a coating film for insulation purposes.

10, 20 chip inductor,
11, 21 base material,
12, 12 ', 22, 22' internal electrodes,
13, 23 External electrode,
14 coating film,
24 extra width,
30 Bare chips,
40, 50 Green chips,
41, 51 Green sheet,
42, 52 conductive paste film,
60 film forming apparatus,
61 vacuum chamber,
62 exhaust pump,
63 aerosol generator,
64 stages,
65 mask,
66 nozzles,
67, 68, 69 Conveying pipe,
70 Carrier gas cylinder,
71 Powder material.

Claims (14)

A ceramic substrate;
A ceramic coating film having a thickness of 1 to 10 μm formed directly on at least a part of the ceramic substrate by an aerosol deposition method;
With
A structure in which the coating film has a volume electrical resistivity of 1.5 × 10 ⁷ Ω · m or more and a solder heat resistance measured by a solder bath at 270 ° C. of 10 seconds or more.   The structure according to claim 1, wherein an in-film fracture strength of the coating film with respect to the substrate is 7 N or more and a complete peel strength is 40 N or more.   The structure according to claim 1, wherein a relative density of the coating film is 80% or more.   The structure according to any one of claims 1 to 3, wherein the substrate includes at least one selected from metal oxides, transition metal oxides, metal nitrides, metal carbides, and boride-based ceramics.   The structure according to any one of claims 1 to 4, wherein the coating film contains at least one selected from metal oxides, transition metal oxides, metal nitrides, metal carbides, and boride-based ceramics. The substrate contains ferrite, and the coating film contains at least one of ferrite and Al ₂ O ₃ , or
The substrate includes Al ₂ O ₃ and the coating film includes Al ₂ O ₃ , or
The structure according to claim 4, wherein the substrate includes BaTiO ₃ and the coating film includes Al ₂ O ₃ . A preparation step of preparing a material powder having a volume-based median diameter D ₅₀ of 0.50 μm <D ₅₀ <1.0 μm;
A film forming step of forming a ceramic coating film on a ceramic substrate by an aerosol deposition method in which an aerosol gas containing the material powder is injected from a nozzle and the material powder is deposited;
The manufacturing method of the structure which has this.   The manufacturing method according to claim 7, wherein the material powder has a flat shape with an aspect ratio of 100> a / b> 1.3 when the horizontal axis is a and the vertical axis is b.   The manufacturing method according to claim 7 or 8, wherein the material powder is at least one powder selected from a highly insulating oxide material, a soft magnetic material, and a ferroelectric oxide material. The highly insulating oxide material is at least one of Al ₂ O ₃ , SiO ₂ , MgO, CaO, transition metal oxide, metal nitride, metal carbide, and boride-based ceramics, and the soft magnetic material is ferrite. The method according to claim 9, wherein the ferroelectric oxide material is at least one of Ba, Pb, and Bi-based ferroelectric compounds containing simple perovskite in the basic structure. In the film forming step, the aerosol gas is generated by introducing a winding gas and a carrier gas into an aerosol generator containing the powder, and is conveyed to the nozzle.
9. The manufacturing method according to claim 7, wherein the carrier gas flow rate is 0 to 30 SLM and the hoisting gas flow rate is 20 to 120 SLM.   The manufacturing method according to claim 11, wherein the ratio of the carrier gas flow rate and the hoisting gas flow rate is 1: 1.5 to 1: 7.   The manufacturing method according to claim 7, wherein an operation speed of the nozzle is 200 to 400 mm / min.   An electronic component provided with the structure manufactured by the structure as described in any one of Claims 1-6, or the manufacturing method as described in any one of Claims 7-13.