JP2016127526A - Binarization circuit and pulse count device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a binarization circuit which is high in robust performance to unknown offset variation components, and capable of coping with even frequency variation.SOLUTION: A binarization circuit includes: a hold circuit part (101) for detecting the peak value and bottom value of an input signal as an analog input signal; a threshold formation circuit for determining a threshold on the basis of the peak value and bottom value to be output from the hold circuit part (101); hold state detection circuits (200, 300) for detecting on or off of the hold state of the hold circuit part (101) from the states of the input signal, the peak value and the bottom value; a reset timing generation circuit part (104) for generating a reset signal on the basis of the on or off of the hold state of the hold circuit part (101) detected by the hold state detection circuits (200, 300); and a comparison circuit part (105) for comparing the input signal with the threshold to output a binarized signal. The hold circuit part (101) resets the peak value or bottom value on the basis of the reset signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a binarization circuit and a pulse count device.

  The analog signal input signal level varies depending on the sensor's inherent sensitivity, external factors (temperature / humidity, vibration, static electricity, etc.) due to the sensor's usage environment, or the energy level (allowable range) of an unspecified number of objects to be measured There is already known a technique for accurately binarizing an analog signal by suppressing the influence of an offset when an unknown changing offset component is included depending on (width) (or when an offset is intentionally included).

  For example, in Patent Document 1, an AND circuit that receives a comparator, an output of the comparator and a predetermined clock signal, an output of the AND circuit is input to a counter circuit, and the counter value is D / A converted to obtain a hold voltage value. In the hold circuit, there is disclosed a technique for accurately detecting a hold value for each period of an input signal with respect to an input signal in which a slowly varying component is synthesized in addition to the input signal component.

  And the technique of binarizing an input signal correctly using the hold value obtained by the said technique is disclosed.

  However, in the above-described method, the slow fluctuation component allowed by the system is performed by adjusting the second clock, and the robustness to unknown fluctuation is low.

  That is, when a fluctuation that cannot be followed by the adjusted second clock occurs, there occurs a period in which the threshold voltage obtained based on the hold value cannot obtain an intersection with the input signal, and the input signal is accurately binarized. You may not be able to.

  In addition, when trying to improve robustness against unknown fluctuations (any fluctuation including those whose fluctuations are not slow), that is, when the second clock period is made closer to the first clock period, the robustness against fluctuations is certainly increased. However, for systems where the frequency of the input signal varies (for example, systems where the frequency may be extremely low), the potential difference between the peak hold and bottom hold becomes narrower. There is a problem in that the orthogonality of the intersection between the threshold voltage obtained based on the hold value and the input signal is lost, false detection (noise) occurs in the vicinity of the intersection, and the approximation of the duty of the input signal is significantly impaired.

  In view of the above problems, an object of the present invention is to provide a binarization circuit that has high robustness with respect to an unknown offset fluctuation component and can cope with frequency fluctuation.

  In order to solve the above problems, the present invention provides a hold circuit unit that detects a peak value and a bottom value of an input signal that is an analog input signal, and determines a threshold value based on the peak value and the bottom value output from the hold circuit unit. A threshold value forming circuit, a hold state detection circuit for detecting on / off of the hold state of the hold circuit unit from the state of the input signal, the peak value, and the bottom value, and the hold state of the hold circuit detected by the hold state detection circuit A reset timing generation circuit unit that generates a reset signal based on whether the input signal is on or off, and a comparison circuit unit that outputs a binary signal by comparing the input signal with a threshold value. A binarization circuit for resetting the peak value or the bottom value based on the above is provided.

  According to the present invention, it is possible to provide a binarization circuit that has high robustness with respect to an unknown offset fluctuation component and can cope with frequency fluctuation.

It is a block diagram of a binarization circuit. It is the figure which showed the structure of the peak hold circuit part of a hold circuit part. It is a figure which shows the waveform which showed the operation | movement of the hold state detection circuit in FIG. It is the figure which showed the structure of the bottom hold circuit part of a hold circuit part. It is the figure which showed the structure of the reset timing generation circuit part. It is a figure which shows operation | movement of a reset timing generation circuit part. It is a figure which shows the waveform which showed the operation | movement of each signal of a reset timing generation circuit part. It is the figure which showed the structure of the comparison circuit part. It is a figure which shows the operation | movement waveform of the comparison circuit part of a binarization circuit. It is a figure which shows the operation | movement waveform of the comparison circuit part of a binarization circuit. It is a figure which shows the operation | movement waveform of the comparison circuit part of a binarization circuit. It is a figure which shows the operation | movement waveform of the comparison circuit part of a binarization circuit. It is a figure which shows the waveform explaining the problem in a prior art. It is a figure which shows the waveform explaining the problem in a prior art. It is a figure which shows the waveform explaining the problem in a prior art. It is a figure which shows the waveform explaining the problem in a prior art. It is the figure which showed the structure of the pulse count apparatus using a binarization circuit.

  Hereinafter, a binarization circuit according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a configuration diagram of the binarization circuit 100 of the present embodiment. As shown in FIG. 1, the binarization circuit 100 includes a hold circuit unit 101 including a peak hold circuit unit 102 and a bottom hold circuit unit 103, a reset timing generation circuit unit 104, and a comparison circuit unit 105.

  The analog input signal 106 is branched and input to a hold circuit unit 101 and a comparison circuit unit 105 that detect a peak hold value that is a peak value and a bottom hold value that is a bottom value of the input analog input signal 106. The peak hold circuit unit 102 includes a peak hold state detection circuit 200 that outputs a peak hold state detection signal 107 that is a binary signal indicating a hold state or a non-hold state. The bottom hold circuit unit 103 includes a bottom hold state detection circuit 300 that outputs a bottom hold state detection signal 108 that is a binary signal indicating a hold state or a non-hold state. The peak hold state detection signal 107 and the bottom hold state detection signal 108 are input to the reset timing generation circuit unit 104.

  The reset timing generation circuit unit 104 outputs a reset signal to the hold circuit unit 101 at a predetermined timing based on the signal logic of the peak hold state detection signal 107 and the bottom hold state detection signal 108. Here, a signal for resetting the hold state of the peak hold circuit unit 102 is referred to as a first reset signal 109, and a signal for resetting the hold state of the bottom hold circuit unit 103 is referred to as a second reset signal 110.

  The comparison circuit unit 105 receives the peak hold value 111 and the bottom hold value 112 that are normally analog voltage values of the peak hold circuit unit 102, and the threshold value is dynamically set by the peak hold value 111 and the bottom hold value 112. Generated. The threshold value and the analog input signal 106 are compared by a comparator, and a desired binarized signal output is obtained.

  More specifically, when the input signal has an offset, the voltage of the input signal is lower than the threshold used by the binarization circuit to output HIGH or LOW, and the minimum voltage is lower than the maximum voltage. Sometimes. In this case, an accurate binarized signal cannot be obtained. Therefore, it is necessary to change the threshold according to the change of the input voltage.

  In the present embodiment, the threshold is increased according to the input voltage when the voltage of the input signal tends to increase, and the threshold is decreased when the voltage of the input signal tends to decrease. This threshold value is determined by a threshold value forming circuit that determines the threshold value (Vref) based on the peak hold value (Vph) and the bottom hold value (Vbh) output from the hold circuit unit 101 provided in the comparison circuit unit 105.

  The comparison circuit unit 105 compares the input signal with a threshold value and outputs a binarized signal. Specifically, the comparison circuit unit 105 outputs HIGH as Vout_bin when the input voltage Vin is higher than the threshold value Vref, and outputs LOW as Vout_bin when the input voltage Vin is lower than the threshold value Vref. The threshold value Vref is a voltage within the range of the peak hold value Vph and the bottom hold value Vbh. For example, when R5 = R6, Vref = (Vph + Vbh) / 2, that is, an intermediate voltage between the peak hold value Vph and the bottom hold value Vbh, or an average voltage between the peak hold value Vph and the bottom hold value Vbh.

  Here, the bottom hold value Vbh is reset when the voltage of the input signal changes from an upward trend to a downward trend, and the peak hold value Vph is reset when the voltage of the input signal changes from a downward trend to an upward trend. After that, it is necessary to turn off the hold for maintaining the peak hold value Vph or the bottom hold value Vbh so as to follow the input signal Vin.

  In the present embodiment, the peak hold state detection circuit 200 determines the peak hold state detection signal 107 (State_PH), which is a status signal, based on the peak hold value Vph and the input voltage Vin, and the bottom hold value Vbh and the input signal Vin. The bottom hold state detection circuit 300 outputs a bottom hold state detection signal 108 (State_BH), which is a status signal, to the reset timing generation circuit unit 104. Then, the reset timing generation circuit unit 104 outputs a reset signal to the hold circuit unit 101 at a predetermined timing based on the signal logic of the peak hold state detection signal 107 and the bottom hold state detection signal 108.

  FIG. 2 is a diagram illustrating a configuration of the peak hold circuit unit 102 of the hold circuit unit 101. As shown in FIG. 2, the peak hold circuit unit 102 has a first operational amplifier OP1 that compares the input signal Vin and the fed back peak hold value Vph, and an anode connected to the output terminal of the first operational amplifier OP1. A diode D2 having a cathode connected to the + terminal of the second operational amplifier OP2, a capacitor C2 having one end connected to the cathode of the diode D2 and the + terminal of the second operational amplifier OP2 via a resistor R3, and the other end grounded; And a peak hold state detection circuit 200.

  The peak hold state detection circuit 200 includes a first comparator COMP1 that compares the output of the first operational amplifier OP1 and the input signal Vin.

  The peak hold circuit unit 102 is a circuit that obtains a peak hold voltage Vph by inputting an analog input signal 106 to Vin in the figure. The operational amplifier OP1 detects the voltage difference between Vin and Vph and charges the capacitor C2 via the diode D2.

  That is, when the voltage of Vin is higher than the voltage of Vph, the diode D2 causes a current to flow in the forward direction (contact point a → contact point b), and increases the voltage (Vb) of the contact point b. On the contrary, when the voltage of Vin is lower than the voltage of Vph, the charging current is stopped, so that the voltage Vb is maintained. Thereby, the peak voltage Vph is obtained. However, it may be gradually discharged by the discharge resistor R2.

  The operational amplifier OP2 constitutes a voltage follower and performs impedance conversion of the output Vph. The first reset signal 109 is input from Reset_PH in FIG. 2 and connected to the contact b. When the first reset signal 109 performs a reset operation, the voltage at the contact b becomes equal to the GND level, so that the charge charged in the capacitor C2 is discharged. At this time, the discharge time is determined by the time constant of the resistor R3 and the capacitor C2.

  This embodiment is characterized in that the peak hold circuit unit 102 includes a peak hold state detection circuit 200. As shown in FIG. 2, in the present embodiment, the peak hold state detection circuit 200 uses the comparator COMP1 to generate the voltage of the analog input signal 106 (Vin voltage) and the output voltage of the operational amplifier OP1 (same as the voltage at the contact a). The binary signal is output by comparison.

  That is, during the period in which Vin rises higher than Vph (the period in which the capacitor C2 is charged), the voltage at the contact a is higher than the voltage at Vin, so the output State_PH of the peak hold state detection circuit 200 is During the period when the HIGH level is output and the voltage Vin is lower than the voltage Vph, the voltage of the contact a is lower than the voltage of Vin. Therefore, the output State_PH of the peak hold state detection circuit 200 outputs the LOW level. The Note that the capacitor C1 in the circuit diagram is set as necessary for the purpose of preventing malfunction of the peak hold state detection circuit 200 because an effect of reducing noise generated at the contact point a can be obtained.

  FIG. 3 is a diagram showing waveforms showing the operation of the peak hold state detection circuit 200 in FIG. As shown in FIG. 3, the result of the peak hold state detection signal 107 (State_PH) which is a state detection signal is obtained by the change in the state of the voltage Va at the contact point a with respect to Vin. That is, while the State_PH is Hi, the hold state is released and the capacitor C2 is charged (hold off). During the period when State_PH is LOW, the hold state is maintained (hold on).

  FIG. 4 is a diagram illustrating a configuration of the bottom hold circuit unit 103 of the hold circuit unit 101. As shown in FIG. 4, the bottom hold circuit unit 103 has a third operational amplifier OP3 that compares the input signal Vin and the fed back bottom hold value Vbh, and a cathode connected to the output terminal of the third operational amplifier OP3. A diode D3 whose anode is connected to the + terminal of the fourth operational amplifier OP4, a capacitor C3 whose one end is connected to the anode of the diode D3 and the + terminal of the fourth operational amplifier OP4 via a resistor R5, and the other end is connected to the power supply And a bottom hold state detection circuit 300.

  The bottom hold state detection circuit 300 includes a second comparator COMP2 that compares the output of the third operational amplifier OP3 with the input signal Vin.

  The operation of the bottom hold circuit unit 103 is opposite to the operation of the peak hold circuit unit 102. When the voltage of Vin is higher than the voltage of Vbh, the charging current stops in the diode D3. The voltage (Vd) of the contact d is maintained. Conversely, when the voltage at Vin is lower than the voltage at Vbh, the diode D2 causes a current to flow in the forward direction (contact point d → contact point c), and raises the voltage at the contact point Vd. Thereby, the bottom voltage Vbh is obtained. In the present embodiment, the bottom hold state detection circuit 300 has a logic opposite to that of the peak hold state detection circuit 200 in the peak hold circuit unit. That is, the bottom hold state detection signal 108, which is a state detection signal, is in a hold-on state when State_BH is HIGH, and is in a hold-off state when State_BH is LOW. The other operations are the same as those of the peak hold circuit unit 102 described in the description of FIG.

  FIG. 5 is a diagram illustrating a configuration of the reset timing generation circuit unit 104. As shown in FIG. 5, State_PH of the peak hold state detection signal 107 which is an output signal of the peak hold state detection circuit 200 of the peak hold circuit unit 102 and an output signal of the bottom hold state detection circuit 300 of the bottom hold circuit unit 103 State_BH of a certain bottom hold state detection signal 108 is input to the reset timing generation circuit unit 104. The reset timing generation circuit unit 104 includes a logic operation circuit (Inverter, XOR, AND) and a sequential circuit (D-FlipFlop) DFF, and a circuit can be assembled using a general-purpose logic IC. In this case, the component cost can be kept lower than when dedicated components are used.

  State_PH is inverted by Inverter (INV) and input to the first AND gate (AND1) and the second AND gate (AND2). State_PH and State_BH are input to the XOR gate, and the output of the XOR gate is input to the CLK terminal of the D-FlipFlop (DFF). DFF_ to Q, which are outputs from the Q bar terminal of the D-FlipFlop (DFF), are input to the D terminal of the D-FlipFlop (DFF) and the second AND gate (AND2). DFF_Q, which is the output of the Q terminal of D-FlipFlop (DFF), is input to the first AND gate (AND1). State_BH is input to the second AND gate (AND2).

  FIG. 6 is a diagram illustrating the operation of the reset timing generation circuit unit 104. In FIG. 6A, State_PH (1) indicates the current State_PH state, State_BH (0) indicates the previous State_BH state, and State_BH (1) indicates the current State_BH state. FIG. 6B is a timing chart of the reset timing generation circuit unit 104.

  As shown in FIG. 6A, the state sequence of State_PH repeatedly changes in the order of H → L → L → L, and the state sequence of State_BH changes in the order of H → H → L → H except for the initial state. When State_PH = L and State_BH = H, one of the first reset signal 109 and the second reset signal 110 operates. Which reset signal operates depends on the relationship with the previous state of State_BH.

  As shown in FIG. 6B, rst_s_ph that is the output of the first AND gate (AND1) is the same signal as DFF_Q that is the output of the Q terminal of D-FlipFlop (DFF). The first AND gate (AND1) determines the initial value of the reset signal.

  FIG. 7 is a diagram illustrating waveforms illustrating the operation of each signal of the reset timing generation circuit unit 104. The reset timing is determined as follows.

  The first reset signal 109 is reset when the bottom hold state detection signal (State_BH) is turned from OFF to ON (3), and reset when the peak hold state detection signal (State_PH) is turned from ON to OFF (4). Take action to cancel.

  The second reset signal 110 is reset when the peak hold state detection signal (State_PH) changes from OFF to ON (1), and reset when the bottom hold state detection signal (State_BH) changes from ON to OFF (2). Take action to cancel.

  Thus, the first reset signal 109 that resets the peak hold voltage when the bottom value hold state is hold-on (State_BH = H) is generated (Reset_PH = ON), and the peak value hold state is hold-on (State_PH = A logic circuit that generates a second reset signal 110 (Reset_BH = ON) that resets the bottom hold voltage when the signal is L) can be configured. Note that the reset period of the reset signal is determined by the time from the start of the reset operation to the hold-off. That is, the reset release of the first reset signal 109 is a time until the peak hold state detection signal 107 is held off, and this period can be adjusted by the constants R3 and C2 shown in FIG.

  FIG. 8 is a diagram showing the configuration of the comparison circuit unit 105. As shown in FIG. 8, a peak hold value 111 (voltage Vph) and a bottom hold value 112 (voltage Vbh) are divided to generate a reference voltage Vref, a comparison operation is performed by an analog input voltage Vin and a comparator (COMP2). A value signal output Vout_bin is obtained.

  Here, the optimum voltage division ratio between the peak hold value 111 (voltage Vph) and the bottom hold value 112 (voltage Vbh) is appropriately set according to the system, but normally R5: R6 = 1: 1. The Since the reference voltage Vref is an analog voltage, a capacitor C4 may be added to suppress the influence of noise or the like, and a resistor R7 may be added to provide hysteresis for the reference voltage Vref.

  9 to 12 are diagrams illustrating operation waveforms of the comparison circuit unit 105 of the binarization circuit 100. FIG. FIG. 9 shows an operation waveform when there is no offset variation in the analog input signal 106. FIG. 10 shows an operation waveform when an offset fluctuation occurs in the analog input signal 106. FIG. 11 shows an operation waveform when the signal frequency of the analog input signal 106 changes to the low frequency side. FIG. 12 shows an operation waveform when the signal frequency of the analog input signal 106 changes to the high frequency side.

  As shown in FIG. 9 to FIG. 12, even if the circuit constants are set to the same value, the analog input signal can be reliably transmitted when the offset component is superimposed on the analog input signal or when the frequency of the input signal changes. Can be binarized.

FIG. 13 to FIG. 16 are diagrams showing waveforms for explaining problems in the prior art. First,
FIG. 13 shows the operation when there is no offset variation when the circuit constants are the same at the same frequency as in FIG. FIG. 14 shows operation waveforms when offset fluctuations are superimposed. Since the peak / bottom hold voltage (Vph, Vbh) does not follow the offset variation, there occurs a period in which the reference voltage (Vref) deviates from the amplitude of the analog input signal (Vin) and cannot be binarized accurately.

  In order to improve this problem, FIG. 15 shows a waveform when the circuit constant is changed to accelerate the discharge of the hold voltage. It can be seen that the problem with offset variation is certainly improved.

  However, if the frequency is changed low as in FIG. 11 with this circuit constant, the potential difference between the peak hold voltage (Vph) and the bottom hold voltage (Vbh) narrows as shown in FIG. The reference voltage (Vref) has a period that substantially overlaps with the analog input signal (Vin). Depending on the setting of the constant, this may overlap in the entire period. In this case, since robustness against external noise is reduced, erroneous detection occurs and accurate binarization cannot be performed.

  As described above, the conventional technique can improve the offset fluctuation, but in a system in which the frequency of the desired input signal changes, it can cope with it unless it has a plurality of corresponding constant setting means within the range in which the frequency changes. It becomes difficult. However, providing such constant setting means complicates the configuration and increases the cost.

  FIG. 17 is a diagram showing a configuration of a pulse count device 800 using the binarization circuit 100. As shown in FIG. 17, the pulse count device 800 has a pulse count circuit unit 801 that counts the rising edge and / or falling edge of the binary output signal that is the output waveform of the binarization circuit 100. doing. The pulse count circuit unit 801 is an 8-bit binary counter, but is not limited thereto. Further, it may be an up counter or a down counter, and both functions may be provided. Further, the pulse count circuit unit 801 may be configured to clear the count value by inputting a reset signal.

  As described above, in the binarization circuit of the present embodiment, the peak hold state detection circuit 200 generates the peak hold state detection signal 107 (State_PH) based on the peak hold value Vph and the input voltage Vin, and the bottom hold value Vbh. Based on the input signal Vin, the bottom hold state detection circuit 300 outputs a bottom hold state detection signal 108 (State_BH) to the reset timing generation circuit unit 104. Then, the reset timing generation circuit unit 104 outputs a reset signal to the hold circuit unit 101 at a predetermined timing based on the signal logic of the peak hold state detection signal 107 and the bottom hold state detection signal 108.

  Therefore, there is an effect that it is possible to provide a binarization circuit that has high robustness with respect to an unknown offset fluctuation component and can cope with frequency fluctuation.

  Although the present invention has been described with reference to the preferred embodiment, the binarization circuit of the present invention is not limited to the configuration of the above embodiment.

  Those skilled in the art can appropriately modify the binarization circuit of the present invention in accordance with conventionally known knowledge. Of course, such modifications are included in the scope of the present invention as long as the configuration of the binarization circuit of the present invention is provided.

100 Binary circuit 101 Hold circuit unit 102 Peak hold circuit unit 103 Bottom hold circuit unit 104 Reset timing generation circuit unit 105 Comparison circuit unit 200 Peak hold state detection circuit 300 Bottom hold state detection circuit

JP 2008-032706 A

Claims (3)

A hold circuit unit for detecting a peak value and a bottom value of an input signal which is an analog input signal;
A threshold value forming circuit for determining a threshold value based on a peak value and a bottom value output from the hold circuit unit;
From the state of the input signal, the peak value, and the bottom value, a hold state detection circuit that detects on or off of the hold state of the hold circuit unit, and
A reset timing generation circuit unit that generates a reset signal based on a state detection signal indicating ON or OFF of the hold state of the hold circuit unit detected by the hold state detection circuit;
A comparison circuit unit that compares the input signal with the threshold value and outputs a binarized signal;
With
The hold circuit unit is
A binarization circuit that resets the peak value or the bottom value based on the reset signal. The hold circuit unit is
The state detection signal detected by the hold state detection circuit is output to the reset timing generation circuit unit,
The reset timing generation circuit unit includes:
Based on the result of the state detection signal, generates a first reset signal that resets the peak value when the hold state of the bottom value is turned on, and the bottom value when the hold state of the peak value is turned on The binarization circuit according to claim 1, further comprising a logic circuit that generates a second reset signal for resetting the signal. The binarization circuit according to claim 1 or 2,
A pulse count circuit for counting edges of the output waveform of the binarization circuit;
A pulse counting device comprising: