JP2008066807A - Signal processing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify a signal processing circuit configuration for properly processing an input signal, such as a reading signal of a non-contact IC card, in which a binary signal is superimposed on a clock signal and noise is mixed. <P>SOLUTION: The circuit is provided with a comparator 11 for inputting an input signal S1 into a non-inverting input terminal via reverse-parallel connected diodes D1, D2, and a capacitor C with one end connected to the non-inverting input terminal while the other end is connected to earth ground. The input signal S1 is branched and inputted into the non-inverting input terminal of the comparator 11. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention is a signal that is particularly useful for appropriately processing an input signal in which a binary signal is superimposed on a clock signal and noise is mixed, such as a read signal of a non-contact type IC card. It relates to a processing circuit.

When the DC level of an analog signal including a binary signal varies randomly due to noise, the threshold value (threshold value) of the comparator is appropriately varied in order to process the analog signal and convert it to a digital signal. A special signal processing circuit is used. For example, a circuit that generates an appropriate threshold value for a comparator in real time by paying attention to the positive and negative peak values of fluctuations of an input signal is known (Patent Document 1). A circuit system has also been proposed in which the hysteresis characteristic of the comparator is varied in real time in accordance with changes in the input signal (Patent Document 2).
JP 2000-22509 A JP 2003-198342 A

  According to such a conventional technique, an auxiliary circuit required for generating a threshold and changing a hysteresis characteristic is complicated, so that the entire circuit design is complicated and the manufacturing cost tends to be high.

  Therefore, in view of the problems of the prior art, an object of the present invention is to charge and discharge a capacitor with an input signal via a diode connected in reverse parallel to generate a threshold value for a comparator, thereby forming an overall circuit configuration. An object of the present invention is to provide a signal processing circuit capable of accurately extracting a binary signal from an input signal including noise while being extremely simplified.

  The configuration of the first invention according to this application for achieving the above object (referring to the invention according to claim 1, the same applies hereinafter) is a comparison in which an input signal is input to a non-inverting input terminal via an anti-parallel connected diode. And a capacitor having one end grounded connected to the non-inverting input terminal, and the gist of the invention is to branch the input signal to the inverting input terminal of the comparator.

  The configuration of the second invention (referring to the invention according to claim 2, hereinafter the same) includes a comparator that inputs an input signal to an inverting input terminal via a diode connected in reverse parallel, and a one-end grounding that is connected to the inverting input terminal. The gist of the present invention is to branch the input signal to the non-inverting input terminal of the comparator.

  In the first aspect of the invention, the capacitor is connected to the non-inverting input terminal of the comparator, and the charging voltage of the capacitor is a threshold value for the input signal input to the inverting input terminal of the comparator. . On the other hand, since the capacitor is charged and discharged by the input signal through the diode connected in antiparallel, the threshold value of the comparator can be appropriately varied according to the change of the DC level of the input signal, and the comparison A binary signal can be extracted on the output side of the instrument. However, the time constant during charging and discharging of the capacitor is determined by the output impedance of the linear amplifier in the previous stage and the capacitance of the capacitor, and is sufficiently larger than the cycle of the clock signal included in the input signal, for example, 5-10 of the cycle of the clock signal It is better to set to about double.

  According to the configuration of the second invention, in contrast to the first invention, since the inverting input terminal and the non-inverting input terminal of the comparator are merely replaced, the first output except that the polarity of the output signal of the comparator is inverted. It can be operated in the same way as the invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  The signal processing circuit 10 includes diodes D1 and D2 connected in antiparallel, a capacitor C, and a comparator 11 (FIG. 1). The signal processing circuit 10 is provided with an input terminal T1 for inputting the input signal S1 and an output terminal T2 for outputting the output signal S2.

  In the signal processing circuit 10, the input terminal T1 is connected to the non-inverting input terminal of the comparator 11 via anti-parallel connected diodes D1 and D2. A non-inverting input terminal of the comparator 11 is connected to a capacitor C that is grounded at one end. The input terminal T1 is also branchedly connected to the inverting input terminal of the comparator 11. The output side of the comparator 11 is drawn to the output terminal T2.

  A linear amplifier 21 is installed in the preceding stage of the signal processing circuit 10. An input terminal To for inputting an input signal So from a signal source (not shown) is provided on the input side of the linear amplifier 21.

  In the signal processing circuit 10, the charging voltage Vc of the capacitor C is the threshold value of the comparator 11 for the input signal S1. This is because the capacitor C is connected to the non-inverting input terminal of the comparator 11 and the input signal S 1 is input to the inverting input terminal of the comparator 11.

  On the other hand, as the instantaneous voltage Va of the input signal S1, when Va.gtoreq.Vc, the forward diode D1 conducts and charges the capacitor C, thereby increasing the charging voltage Vc of the capacitor C, that is, the threshold value of the comparator 11. . When Va <Vc, the diode D2 in the reverse direction is turned on to discharge the capacitor C and reduce the threshold value of the comparator 11. However, the time constant during charging and discharging of the capacitor C is determined by the output impedance of the linear amplifier 21 in the previous stage and the capacitance of the capacitor C. Therefore, the threshold value of the comparator 11 with respect to the input signal S1 is appropriately varied in accordance with the fluctuation of the input signal S1, and the comparator 11 accurately extracts the binary signal included in the input signal S1. The output signal S2 can be output to the outside.

  When noise is mixed in the input signal S1 in which the binary signal S1b is superimposed on the clock signal S1c and the direct current level fluctuates randomly, the operation of the signal processing circuit 10 is as shown in FIGS. 2 and 3, for example. However, FIG. 3 is a partially enlarged view illustrating the time scale of the horizontal axis in FIG. 2 and the voltage scale of the vertical axis being appropriately compressed. 2 and 3, the frequency of the clock signal S1c is 200 kHz, and the pulse rate of the binary signal S1b is 6800 bps. By setting the time constant during charging / discharging of the capacitor C to be sufficiently larger than the period of the clock signal S1c and the noise component, the binary signal S1b can be correctly extracted as the output signal S2. The input signal S1 in FIGS. 2 and 3 is an actual example of the read signal of the non-contact type IC card.

  In the above description, even if the non-inverting input terminal and the inverting input terminal of the comparator 11 in FIG. 1 are replaced with each other, the same operation can be achieved and the same performance can be realized.

Overall configuration circuit diagram Operating signal waveform diagram (1) Operating signal waveform diagram (2)

Explanation of symbols

C ... Capacitors D1, D2 ... Diode S1 ... Input signal 10 ... Signal processing circuit 11 ... Comparator

Patent applicant F.C. Co., Ltd.
Attorney Tadaaki Matsuda, Attorney

Claims (2)

  Comparing an input signal to a non-inverting input terminal via a diode connected in reverse parallel, and a one-end grounded capacitor connected to the non-inverting input terminal, the inverting input terminal of the comparator includes: A signal processing circuit for branching an input signal.   Comprising a comparator that inputs an input signal to an inverting input terminal via a diode connected in reverse parallel, and a one-end grounded capacitor that is connected to the inverting input terminal. The non-inverting input terminal of the comparator has an input A signal processing circuit for branching and inputting a signal.

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