JP2016122794A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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JP2016122794A
JP2016122794A JP2014263376A JP2014263376A JP2016122794A JP 2016122794 A JP2016122794 A JP 2016122794A JP 2014263376 A JP2014263376 A JP 2014263376A JP 2014263376 A JP2014263376 A JP 2014263376A JP 2016122794 A JP2016122794 A JP 2016122794A
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semiconductor element
bonding material
lead frame
lead
semiconductor device
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正規 水野
Masaki Mizuno
正規 水野
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing peeling between a semiconductor element and a lead frame without increasing the number of manufacturing steps.SOLUTION: A semiconductor device comprises: a lead frame including a die pad and a lead; a semiconductor element mounted on the die pad of the lead frame via a joint material; a wire for interconnection between the semiconductor element and the lead of the lead frame; and a resin sealing body sealing the die pad of the lead frame, a part of the lead, the semiconductor element, and the wire. The joint material is composed of a first joint material surrounding the periphery of the semiconductor element, and a second joint material connected to a rear surface and a side surface of the semiconductor element.SELECTED DRAWING: Figure 1

Description

本発明は、半導体装置とその製造方法に関し、特にリードフレームに半導体素子を接合材で接合し、封止体で樹脂封止する半導体装置とその製造方法に関する。
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a semiconductor element is bonded to a lead frame with a bonding material and resin-sealed with a sealing body and a manufacturing method thereof.

一般的な半導体装置は、リードフレームに半導体素子を搭載・配線し、モールド樹脂（封止体）にて樹脂封止される。この時、半導体素子は接合材によりリードフレームと接合される。例えば、はんだや導電性接着材が使われる。導電性接着材は、Ａｇペーストがよくつかわれるが、熱に弱く、種々の対策が取られている。
In general semiconductor devices, a semiconductor element is mounted and wired on a lead frame, and resin-sealed with a mold resin (sealing body). At this time, the semiconductor element is bonded to the lead frame by the bonding material. For example, solder or conductive adhesive is used. As the conductive adhesive, Ag paste is often used, but it is weak against heat and various measures are taken.

例えば、特許文献１には、半導体素子の裏面と向かい合うアイランド（リードフレーム）の表面にそれぞれ凹凸を設け、Ａｇフィラーを凹凸の凹部のサイズよりも平均粒径が小さく全体が凹部に入り込んでいる第１のフィラーと、凹部のサイズよりも平均粒径が大きく凹部の外側に位置しつつ第１のフィラーと接触している第２のフィラーとを備え、さらに、第２のフィラーの平均粒径を半導体素子とアイランド間におけるダイマウント（接合）材の厚さよりも小さいものとしている。これにより、ダイマウント材を介した半導体素子とアイランド間の熱伝導性の向上と剥離抑制している。
For example, in Patent Document 1, irregularities are provided on the surface of an island (lead frame) facing the back surface of a semiconductor element, and Ag filler has an average particle size smaller than the size of the concave and convex portions, and the whole enters the concave portions. 1 and a second filler having an average particle size larger than the size of the recess and being in contact with the first filler while being located outside the recess, and further, an average particle size of the second filler The thickness is smaller than the thickness of the die mount (joining) material between the semiconductor element and the island. This improves the thermal conductivity between the semiconductor element and the island via the die mount material and suppresses the separation.

特開２００９−１１７４３５号公報JP 2009-117435 A

一般的に、半導体素子の接合は接合材が使われ、Ａｇペーストがよく使用されている。
Generally, a bonding material is used for bonding semiconductor elements, and an Ag paste is often used.

しかしながら、従来技術は、半導体素子の裏面とリードフレームの表面にそれぞれ凹凸部を設けているので、接合強度は強いが、凹凸を設ける製造工程が、半導体素子製造工程とリードフレーム製造工程の両方で必要になるため、製造工数が増加するという課題がある。
However, since the conventional technology has uneven portions on the back surface of the semiconductor element and the surface of the lead frame, the bonding strength is strong, but the manufacturing process for providing the unevenness is both in the semiconductor element manufacturing process and the lead frame manufacturing process. Since it becomes necessary, there is a problem that the number of manufacturing steps increases.

従って、本発明は、上述した課題を解決するためになされたものであり、製造工程を増やさずに、半導体素子とリードフレーム間の剥離を抑制した半導体装置を提供することを目的とする。
Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device in which peeling between a semiconductor element and a lead frame is suppressed without increasing the number of manufacturing steps.


上述の課題を解決するために、本発明は、以下に掲げる構成とした。
本発明の半導体装置は、ダイパッドとリードとを有するリードフレームと、リードフレームのダイパッド上に接合材を介して取り付けられた半導体素子と、半導体素子とリードフレームのリードとの間を相互接続させるワイヤと、リードフレームのダイパッドと、リードの一部と、半導体素子と、ワイヤとを樹脂封止体で封止し、接合材は、半導体素子の周囲を囲む第１の接合材と半導体素子の裏面と側面に接合される第２の接合材からなることを特徴とする。
In order to solve the above-described problems, the present invention has the following configurations.
A semiconductor device according to the present invention includes a lead frame having a die pad and leads, a semiconductor element mounted on the die pad of the lead frame via a bonding material, and a wire for interconnecting the semiconductor element and the lead of the lead frame. And a die pad of the lead frame, a part of the lead, the semiconductor element, and the wire are sealed with a resin sealing body, and a bonding material is a first bonding material surrounding the periphery of the semiconductor element and the back surface of the semiconductor element And a second bonding material bonded to the side surface.

本発明は、製造工程を増やさずに、半導体素子とリードフレーム間の剥離を抑制した半導体装置を提供することができる。
The present invention can provide a semiconductor device in which peeling between a semiconductor element and a lead frame is suppressed without increasing the number of manufacturing steps.

本発明の実施例１に係る半導体装置の内部構造を示す断面図である。It is sectional drawing which shows the internal structure of the semiconductor device which concerns on Example 1 of this invention. 本発明の実施例１に係る半導体装置の製造方法を示す平面図である。It is a top view which shows the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. 本発明の実施例１に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 1 of this invention.

以下、本発明を実施するための形態について、図を参照して詳細に説明する。ただし、本発明は以下の記載に何ら限定されるものではない。
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description.

本発明の実施例１に係る半導体装置１を説明する。図１は、半導体装置１の内部構造を示す。図２、図３は、半導体装置１の製造方法を示す。
A semiconductor device 1 according to Example 1 of the invention will be described. FIG. 1 shows the internal structure of the semiconductor device 1. 2 and 3 show a method for manufacturing the semiconductor device 1.

図１に示すように、半導体装置１は、リードフレーム２と接合材３と半導体素子４とワイヤ５と樹脂封止体６とから成っている。
As shown in FIG. 1, the semiconductor device 1 includes a lead frame 2, a bonding material 3, a semiconductor element 4, a wire 5, and a resin sealing body 6.

リードフレーム２は、ダイパッド２１、リード２２を備えている。例えば、材質は銅合金で厚さが０．５ｍｍのものを使用することができる。
The lead frame 2 includes a die pad 21 and leads 22. For example, a copper alloy having a thickness of 0.5 mm can be used.

ダイパット２１上には、接合材３を介して半導体素子４が搭載されている。例えば、半導体素子４はトランジスタチップである。
A semiconductor element 4 is mounted on the die pad 21 with a bonding material 3 interposed therebetween. For example, the semiconductor element 4 is a transistor chip.

接合材３は、第１の接合材３１と第２の接合材３２で構成されている。例えば、それぞれＡｇペーストを使うことができる。
The bonding material 3 includes a first bonding material 31 and a second bonding material 32. For example, an Ag paste can be used for each.

ワイヤ５は、半導体素子４とリード２２を電気的に接続しているが搭載されている。例えば、ワイヤ５は金ワイヤである。
The wire 5 is mounted to electrically connect the semiconductor element 4 and the lead 22. For example, the wire 5 is a gold wire.

樹脂封止体６は、トランスファーモールド装置によって、リードフレーム２のダイパッド２１とリード２２の一部と半導体素子４とワイヤ５を封止樹脂により樹脂成形したものである。
The resin sealing body 6 is obtained by resin-molding the die pad 21 and part of the lead 22, the semiconductor element 4, and the wire 5 of the lead frame 2 with a sealing resin by a transfer molding apparatus.

次に、上述の実施例１に係る半導体装置１の製造方法を説明する。
Next, a method for manufacturing the semiconductor device 1 according to Example 1 will be described.

まず、図２に示すように、リードフレーム２のダイパッド２１の半導体素子４を搭載する領域（点線部）の周囲に第1の接合材３１を塗布する。例えば、ディスペンサによる塗布するとよい。また、印刷でおこなってもよい。周囲は完全に囲まなくてよい。ここで、図３（ａ）は、図２のＡＡ断面であり、第1の接合材３１を塗布した断面図である。第1の接合材３１は壁をつくるように半導体素子４の厚み相当の高さにするとよい。
First, as shown in FIG. 2, a first bonding material 31 is applied around a region (dotted line portion) where the semiconductor element 4 of the die pad 21 of the lead frame 2 is mounted. For example, it may be applied by a dispenser. Moreover, you may carry out by printing. The surroundings do not have to be completely enclosed. Here, FIG. 3A is a cross-sectional view taken along the line AA of FIG. 2 and the first bonding material 31 is applied. The first bonding material 31 may have a height corresponding to the thickness of the semiconductor element 4 so as to form a wall.

次に、図３（ｂ）に示すように、リードフレーム２のダイパッド２１の半導体素子４を搭載する領域に第２の接合材３２を塗布する。ここでは、上述した点線部内で、第1の接合材３１を塗布した内側である。例えば、ディスペンサによる塗布するとよい。その後、半導体素子４を第２の接合材３２に押し付けるように搭載する。ここでは、公知の素子マウント技術が使える。
Next, as shown in FIG. 3B, a second bonding material 32 is applied to the region on the die pad 21 of the lead frame 2 where the semiconductor element 4 is mounted. Here, it is the inside where the first bonding material 31 is applied in the above-described dotted line portion. For example, it may be applied by a dispenser. Thereafter, the semiconductor element 4 is mounted so as to be pressed against the second bonding material 32. Here, a known element mounting technique can be used.

図３（ｃ）は、素子搭載後の接合材３の状態である。半導体素子４の側面は、第1の接合材３１に近接して囲まれている。第２の接合材３２は半導体素子４を適宜な圧力で取り付けるので、第1の接合材３１に当たり、半導体素子４の側面を上方向へ盛り上がる。
FIG. 3C shows the state of the bonding material 3 after mounting the element. A side surface of the semiconductor element 4 is surrounded in proximity to the first bonding material 31. Since the second bonding material 32 attaches the semiconductor element 4 with an appropriate pressure, the second bonding material 32 hits the first bonding material 31 and the side surface of the semiconductor element 4 rises upward.

図３（ｄ）は、適宜な温度でリフローされた、加熱後の接合材３の状態である。第1の接合材３１と第２の接合材３２とで、半導体素子４の側面でフィレットを形成する。この時、第1の接合材３１と第２の接合材３２が同じ材質の場合は、溶融し一体化する。
FIG. 3D shows a state of the heated bonding material 3 reflowed at an appropriate temperature. A fillet is formed on the side surface of the semiconductor element 4 by the first bonding material 31 and the second bonding material 32. At this time, when the first bonding material 31 and the second bonding material 32 are the same material, they are melted and integrated.

続いて、ワイヤボンディング装置によって、半導体素子４とリード２２対して、ワイヤ５を配線する。その後、封止樹脂により樹脂成形し、樹脂封止体６を形成する。さらに、リードフレームの不要部をカットして、半導体装置１が完成する。
Subsequently, the wire 5 is wired between the semiconductor element 4 and the lead 22 by a wire bonding apparatus. Thereafter, resin molding is performed with a sealing resin to form the resin sealing body 6. Further, unnecessary portions of the lead frame are cut to complete the semiconductor device 1.

次に、上述の実施例１に係る半導体装置１の効果を説明する。
Next, effects of the semiconductor device 1 according to the first embodiment will be described.

半導体素子の接合材は、第1の接合材３１と第２の接合材３２とで構成しているので、フィレット形状を大きく（容量が多く）できるので、接合材の厚さが確保できるので、応力吸収をすることができる。これにより、熱応力に対して強度が向上し、剥離の発生を抑制することができる。剥離は接合材のクラックから発生している。起因となる部位の接合材が厚いので、クラックが発生することも抑制できる。
Since the bonding material of the semiconductor element is composed of the first bonding material 31 and the second bonding material 32, the fillet shape can be increased (capacity is large), so the thickness of the bonding material can be secured. It can absorb stress. Thereby, intensity | strength improves with respect to a thermal stress, and generation | occurrence | production of peeling can be suppressed. Peeling occurs from a crack in the bonding material. Since the joining material of the part which becomes the cause is thick, it can also suppress that a crack generate | occur | produces.

また、製法は接合材の塗布のみで可能なので、半導体素子裏面やリードフレーム表面を粗面化する工程が必要ない。これにより、製造工程を増やさずに、半導体素子とリードフレーム間の剥離を抑制した半導体装置とすることができる。
Further, since the manufacturing method can be performed only by applying a bonding material, a process for roughening the back surface of the semiconductor element or the surface of the lead frame is not necessary. Thereby, it is possible to obtain a semiconductor device in which peeling between the semiconductor element and the lead frame is suppressed without increasing the number of manufacturing steps.

上述のように、本発明を実施するための形態を記載したが、この開示から当業者には様々な代替実施の形態、実施例が可能であることが明らかになるはずである。
As described above, the mode for carrying out the present invention has been described. From this disclosure, it should be apparent to those skilled in the art that various alternative embodiments and examples are possible.

半導体パッケージは、ＳＯＰ（Ｓｍａｌｌ Ｏｕｔｌｉｎｅ Ｐａｃｋａｇｅ）タイプを簡易的に示したが、ＳＩＰ（Ｓｉｎｇｌｅ Ｉｎｌｉｎｅ Ｐａｃｋａｇｅ）やＤＩＰ（Ｄｕａｌ Ｉｎｌｉｎｅ Ｐａｃｋａｇｅ）タイプとしてもよい。これによる効果は実施例と同様な効果である。
The semiconductor package is simply shown as a SOP (Small Outline Package) type, but may be a SIP (Single Inline Package) or DIP (Dual Inline Package) type. The effect by this is the same effect as an Example.

また、半導体素子を１個としたが、電力用半導体素子と制御用半導体素子を搭載したモジュール半導体装置としてもよい。これによる効果は実施例と同様な効果である。
In addition, although one semiconductor element is used, a module semiconductor device including a power semiconductor element and a control semiconductor element may be used. The effect by this is the same effect as an Example.

第１の接合材と第２の接合材の材料をＡｇペーストとしたが、それぞれの粘度を変えてもよい。第１の接合材の粘度を高くし、第２の接合材の粘度を低くしてもよい。これにより、第１の接合材を塗布した時の固定度を増すことができる。また、融合する材質であれば、それぞれを別な材質としてもよい。
Although the material of the first bonding material and the second bonding material is Ag paste, the respective viscosities may be changed. The viscosity of the first bonding material may be increased and the viscosity of the second bonding material may be decreased. As a result, the degree of fixation when the first bonding material is applied can be increased. Moreover, as long as it is the material to fuse | melt, each is good also as another material.

１、半導体装置
２、リードフレーム
２１、ダイパッド
２２、リード
３、接合材
３１、第１の接合材
３２、第２の接合材
４、半導体素子
５、ワイヤ
６、樹脂封止体 DESCRIPTION OF SYMBOLS 1, Semiconductor device 2, Lead frame 21, Die pad 22, Lead 3, Joining material 31, 1st joining material 32, 2nd joining material 4, Semiconductor element 5, Wire 6, Resin sealing body

Claims (2)

ダイパッドとリードとを有するリードフレームと、前記リードフレームの前記ダイパッド上に接合材を介して取り付けられた半導体素子と、前記半導体素子と前記リードフレームの前記リードとの間を相互接続させるワイヤと、前記リードフレームの前記ダイパッドと、前記リードの一部と、前記半導体素子と、前記ワイヤとを樹脂封止体で封止する半導体装置において、前記接合材は、前記半導体素子の周囲を囲む第１の接合材と前記半導体素子の裏面と側面に接合される第２の接合材からなることを特徴とする半導体装置。
A lead frame having a die pad and a lead; a semiconductor element mounted on the die pad of the lead frame via a bonding material; and a wire for interconnecting the semiconductor element and the lead of the lead frame; In the semiconductor device in which the die pad of the lead frame, a part of the lead, the semiconductor element, and the wire are sealed with a resin sealing body, the bonding material surrounds the periphery of the semiconductor element. And a second bonding material bonded to the back and side surfaces of the semiconductor element.
リードフレームのダイパッドに搭載される半導体素子のマウント領域よりも大きく周囲をあらかじめ囲うように第１の接合材を塗布する工程と、前記第１の接合材が塗布された領域の内部である前記半導体素子の搭載領域に前記第２の接合材を塗布する工程と、前記半導体素子を搭載する工程と、前記リードフレームと前記半導体素子を加熱し接合する工程とからなるを特徴とする半導体装置の製造方法。   A step of applying a first bonding material so as to enclose in advance a larger area than a mounting region of a semiconductor element mounted on a die pad of a lead frame, and the semiconductor inside the region to which the first bonding material is applied Manufacturing of a semiconductor device, comprising: a step of applying the second bonding material to an element mounting region; a step of mounting the semiconductor element; and a step of heating and bonding the lead frame and the semiconductor element. Method.
JP2014263376A 2014-12-25 2014-12-25 Semiconductor device and method for manufacturing the same Pending JP2016122794A (en)

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