JP2016119456A - Cpu package substrate with removable memory mechanical interface - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reconfigure the memory device arrangement after CPU package assembly.SOLUTION: A configurable central processing unit (CPU) package substrate is disclosed. A package substrate that includes a processing device interface is described. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.SELECTED DRAWING: Figure 2A

Description

  This embodiment relates generally to a package substrate, and more particularly to a central processing unit (CPU) package substrate that includes a removable memory mechanical interface.

  With the increasing demand for high performance computers, great efforts have been made to enhance the performance of internal device components. The performance of a computer's CPU largely depends on the bandwidth and capacity of the memory device accessible to the CPU. Such memory bandwidth and capacity limitations result in limited CPU performance. For this reason, industry leaders are eager to improve the access performance of memory devices to the CPU.

  According to one approach, the memory device can be attached directly to the CPU package substrate rather than to the motherboard. Various memory devices can be integrated on the CPU package substrate, but the memory device cannot be reconfigured after package assembly.

  The package assembly process includes mounting the CPU and memory device onto a CPU package substrate. Conventional methods integrate memory devices on the CPU package substrate by soldering the memory devices directly onto the CPU package substrate during the package assembly process. A conventional CPU package substrate 100 is shown in FIG. 1A. As shown in FIG. 1A, an interface 102 of a processing device such as a land grid array (LGA) is disposed on a CPU package substrate 104. In addition, an electrical interface 106 of the memory device is disposed on the CPU package substrate 104 beside the processing device interface 102. The memory device electrical interface 106 may be LGAs.

  FIG. 1B shows a conventional CPU package 101 after completion of the assembly process of the CPU package. A conventional CPU package 101 includes a processing device 108 and a memory device 110 mounted on a CPU package substrate 104. In the embodiment, the processing device 108 and the memory device 110 are directly mounted on the package substrate 104. For example, the processing device 108 and the memory device 110 may be flip-chip bonded onto the CPU package substrate 104 via an array (not shown) of solder joints. The soldered connection is a permanent connection that, once reflowed and cooled, cannot be removed without exposing the entire CPU package 101 to a reflow process. Thus, the memory device 110 is permanently attached to the CPU package substrate 104 and cannot be easily removed. Once the memory device 110 is installed and the customer purchases the assembled package, the customer cannot reconfigure the specific arrangement of the memory device 110. Thus, the assembled package is a very specific device that is useful in very few applications.

  As technology continues to evolve, the market becomes more fragmented by the diversifying requirements of memory capacity and bandwidth needs. In addition, customers are increasingly expecting the placement of custom memory for their particular application. Since the layout of memory devices after CPU package assembly cannot be reconfigured, current producers of these CPU package assemblies must generate numerous model variants to meet customer preferences. I must. Having numerous model variants is cumbersome, time consuming, and expensive to maintain.

It is a top perspective view of a conventional CPU package substrate. It is a top perspective view of a conventional CPU package. It is a top perspective view of a changeable CPU package substrate according to an embodiment of the present invention. It is an upper surface perspective view of the package which can change the memory which concerns on embodiment of this invention. It is a top perspective view of a changeable CPU package substrate including a socket as a mechanical interface of a removable memory according to an embodiment of the present invention. It is a top perspective view of a changeable CPU package substrate including a set of press-fitting holes as a mechanical interface of a removable memory according to an embodiment of the present invention. 1 is a top perspective view of a changeable CPU package substrate including a set of alignment pins as a mechanical interface of a removable memory according to an embodiment of the present invention. 1 is a top perspective view of a changeable CPU package substrate including a spring-loaded clip as a mechanical interface of a removable memory according to an embodiment of the present invention. 1 is a top perspective view of a package including a slide rail socket on a changeable CPU package substrate according to an embodiment of the present invention. FIG. It is a bottom perspective view of a corresponding part of a slide rail type socket concerning an embodiment of the present invention. It is an upper surface perspective view of the corresponding | compatible part of the slide rail type | mold socket which concerns on embodiment of this invention. It is a figure which shows the method of attaching the corresponding part of a slide rail type | mold socket to the slide rail type | mold socket which concerns on embodiment of this invention. It is a figure which shows the method of attaching the corresponding part of a slide rail type | mold socket to the slide rail type | mold socket which concerns on embodiment of this invention. FIG. 4 illustrates a package including a double edge socket on a changeable CPU package substrate according to an embodiment of the present invention. It is a front perspective view of the double edge socket which concerns on embodiment of this invention. It is a back perspective view of a double edge socket concerning an embodiment of the present invention. It is an upper surface perspective view of the corresponding part of the double edge socket concerning the embodiment of the present invention. It is a figure which shows the method of attaching the corresponding part of a double edge socket to the double edge socket which concerns on embodiment of this invention. It is a figure which shows the method of attaching the corresponding part of a double edge socket to the double edge socket which concerns on embodiment of this invention. FIG. 6 illustrates a package including a full edge pin grid array socket on a changeable CPU package substrate according to an embodiment of the present invention. 1 is a diagram illustrating a full edge pin grid array socket according to an embodiment of the present invention. FIG. FIG. 2 is a diagram illustrating a portion of a full edge pin grid array support system assembled to form a corresponding portion of a full edge pin grid array according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a portion of a full edge pin grid array support system assembled to form a corresponding portion of a full edge pin grid array according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a portion of a full edge pin grid array support system assembled to form a corresponding portion of a full edge pin grid array according to an embodiment of the present invention. FIG. 6 illustrates a method of forming a corresponding portion of a full edge pin grid array socket according to an embodiment of the present invention. FIG. 6 illustrates a method of forming a corresponding portion of a full edge pin grid array socket according to an embodiment of the present invention. It is a figure which shows the method of attaching the corresponding | compatible part of a full edge pin grid array socket to the full edge pin grid array socket which concerns on embodiment of this invention. It is a figure which shows the method of attaching the corresponding | compatible part of a full edge pin grid array socket to the full edge pin grid array socket which concerns on embodiment of this invention. FIG. 6 illustrates a package including a low insertion force socket on a changeable CPU package substrate according to an embodiment of the present invention. It is a top perspective view of a part of a low insertion force socket according to an embodiment of the present invention. It is sectional drawing of the contact pin of the low insertion force socket which concerns on embodiment of this invention. It is a bottom perspective view of the corresponding portion of the low insertion force socket according to the embodiment of the present invention. It is sectional drawing which shows the interconnection structure of the corresponding | compatible part of the low insertion force socket which concerns on embodiment of this invention. It is a figure which shows the method of attaching the corresponding | compatible part of a low insertion force socket to the low insertion force socket which concerns on embodiment of this invention. It is a figure which shows the method of attaching the corresponding | compatible part of a low insertion force socket to the low insertion force socket which concerns on embodiment of this invention. It is a figure which shows the method of attaching the corresponding | compatible part of a low insertion force socket to the low insertion force socket which concerns on embodiment of this invention. FIG. 5 is a top perspective view of a package including a low insertion force socket on a changeable CPU package substrate for corresponding portions of a flexible cable according to an embodiment of the present invention. It is a perspective view of the corresponding | compatible part of the flexible cable which concerns on embodiment of this invention. FIG. 6 is a top perspective view of a package including a corresponding portion of a flexible cable attached to a low insertion force socket according to an embodiment of the present invention. It is an upper surface perspective view of the corresponding part of the flexible cable attached to the heat sink concerning the embodiment of the present invention. 1 is a top perspective view of a package including a flexible cable socket according to an embodiment of the present invention. It is a bottom view of the flexible cable socket which concerns on embodiment of this invention. FIG. 6 is a top perspective view of a corresponding portion of a low insertion force socket for a flexible cable socket according to an embodiment of the present invention. FIG. 5 is a bottom perspective view of a corresponding portion of a low insertion force socket for a flexible cable socket according to an embodiment of the present invention. FIG. 6 is a top perspective view of a package including a corresponding portion of a low insertion force socket attached to a flexible cable socket according to an embodiment of the present invention. FIG. 6 is a top perspective view of a corresponding portion of a flexible cable socket and a low insertion force socket attached to a heat sink according to an embodiment of the present invention. 2 is a top perspective view of a package including a zero insertion force socket on a changeable CPU package substrate according to an embodiment of the present invention. FIG. It is a bottom perspective view of a zero insertion force socket according to an embodiment of the present invention. It is a top perspective view of a zero insertion force socket according to an embodiment of the present invention. It is a figure which shows the corresponding | compatible part of the zero insertion force socket which concerns on embodiment of this invention. It is a figure which shows the method of attaching the corresponding | compatible part of a zero insertion force socket to the zero insertion force socket which concerns on embodiment of this invention. It is a figure which shows the method of attaching the corresponding | compatible part of a zero insertion force socket to the zero insertion force socket which concerns on embodiment of this invention. It is a figure which shows the method of attaching the corresponding | compatible part of a zero insertion force socket to the zero insertion force socket which concerns on embodiment of this invention. FIG. 6 is a cross-sectional view of a heat sink on a package including a corresponding portion of a zero insertion force socket attached to a zero insertion force socket according to an embodiment of the present invention. FIG. 6 is a top perspective view of a package including a frame socket on a changeable CPU package substrate according to an embodiment of the present invention. 1 is a top perspective view of a reflowable grid array according to an embodiment of the present invention. 1 is a cross-sectional view of a reflowable grid array according to an embodiment of the present invention. It is an upper surface perspective view of the corresponding | compatible part of the frame socket which concerns on embodiment of this invention. It is a bottom perspective view of the corresponding portion of the frame socket according to the embodiment of the present invention. It is an upper surface perspective view of the corresponding part of the frame socket attached to the frame socket which concerns on embodiment of this invention. It is sectional drawing of the corresponding | compatible part of the frame socket attached to the frame socket which concerns on embodiment of this invention. FIG. 6 is a cross-sectional view of a different method of attaching a corresponding portion of a frame socket to a frame socket according to an embodiment of the present invention. FIG. 6 is a cross-sectional view of a different method of attaching a corresponding portion of a frame socket to a frame socket according to an embodiment of the present invention. FIG. 6 is a cross-sectional view of a different method of attaching a corresponding portion of a frame socket to a frame socket according to an embodiment of the present invention. It is a figure which shows the package containing the set of a press-fit hole in the changeable CPU package board | substrate which concerns on embodiment of this invention. It is a bottom perspective view of the corresponding portion of the press-fitting hole according to the embodiment of the present invention. It is a side view of the corresponding | compatible part of the press-fit hole which concerns on embodiment of this invention. It is a figure which shows the method of attaching the corresponding part of a press-fit hole to the set of the press-fit hole which concerns on embodiment of this invention. It is a figure which shows the method of attaching the corresponding part of a press-fit hole to the set of the press-fit hole which concerns on embodiment of this invention. FIG. 4 illustrates a package including a set of alignment pins on a changeable CPU package substrate according to an embodiment of the present invention. It is a bottom perspective view of the corresponding portion of the alignment pin according to the embodiment of the present invention. It is an upper surface perspective view of the corresponding part of the alignment pin concerning the embodiment of the present invention. It is a top perspective view of an intermediate structure about a set of alignment pins concerning an embodiment of the present invention. It is sectional drawing of the intermediate structure about the set of the alignment pin which concerns on embodiment of this invention. FIG. 6 is a diagram illustrating a method of attaching a corresponding portion of an alignment pin to an electrical interface of a memory device including a set of alignment pins and an intermediate structure according to an embodiment of the present invention. FIG. 6 is a diagram illustrating a method of attaching a corresponding portion of an alignment pin to an electrical interface of a memory device including a set of alignment pins and an intermediate structure according to an embodiment of the present invention. FIG. 6 shows a package including spring-loaded clips on a changeable CPU package substrate according to an embodiment of the present invention. It is a bottom perspective view of a corresponding part of a spring type clip concerning an embodiment of the present invention. It is a top perspective view of the corresponding part of the spring type clip concerning the embodiment of the present invention. FIG. 5 is a diagram illustrating a method for attaching a corresponding portion of a spring-type clip to an electrical interface of a memory device including a spring-type clip according to an embodiment of the present invention. FIG. 5 is a diagram illustrating a method for attaching a corresponding portion of a spring-type clip to an electrical interface of a memory device including a spring-type clip according to an embodiment of the present invention. FIG. 5 is a diagram illustrating a method for attaching a corresponding portion of a spring-type clip to an electrical interface of a memory device including a spring-type clip according to an embodiment of the present invention. FIG. 6 illustrates a computer system implemented using an implementation of the present invention.

  A CPU package substrate including a changeable / removable memory is disclosed. In the following detailed description, numerous specific details are set forth as specific integrations in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other instances, well-known features have not been described in detail in order not to obscure the embodiments of the invention. It should also be understood that the various embodiments shown in the drawings are exemplary representations and are not necessarily drawn to scale.

1.0 CPU Package Substrate Including Removable Memory Mechanical Interface Embodiments of the present invention include a changeable CPU package that includes a removable memory mechanical interface that allows memory devices to be easily removed and replaced. A substrate is disclosed. In an embodiment of the present invention, the changeable CPU package substrate includes a processing device interface and a memory device electrical interface. A processing device interface and a memory device electrical interface are coupled to the processing device (eg, CPU) and memory device (eg, DRAM chip), respectively. In an embodiment, the changeable CPU package substrate further includes a removable memory mechanical interface. The memory interface of the removable memory allows the memory device to be attached and detached after the CPU package is assembled. When attached by a removable memory mechanical interface, the memory device is physically and electrically coupled to the CPU package substrate.

  In an embodiment, the removable memory mechanical interface is a socket into which the memory device is inserted and coupled to the CPU package substrate. Although the removable memory mechanical interface is a socket in many embodiments, the removable memory mechanical interface can be implemented as other structures as well. For example, the removable memory mechanical interface may be a set of press-fit holes into which corresponding portions of the set of alignment pins are inserted. The removable memory mechanical interface may be a set of alignment pins designed to fit within a press-fit hole on the memory device substrate. The mechanical interface of the removable memory may be a spring type clip that clips the memory device onto the CPU package substrate.

  Despite their many variations, the removable memory mechanical interface of the embodiments disclosed herein generally allows the CPU package substrate to be easily re-used using different memory devices after package assembly. It becomes possible to configure. During the assembly of the CPU package, an electronic device such as a CPU is mounted on the CPU package substrate. Instead of permanently mounting the memory device directly on the CPU package substrate as is conventionally done, the removable memory mechanical interface is formed or mounted on the CPU package substrate during package assembly. Thus, a changeable CPU package substrate is formed. The processing device can then be attached to a changeable CPU package substrate, thereby forming a CPU package with changeable memory. Next, the memory device may be attached to the removable memory mechanical interface before and after sending the CPU package with changeable memory to the customer. After receiving a CPU package that can change memory, the customer can reconfigure the memory layout as desired.

  For example, a customer can remove an existing memory device and reinstall a new memory device as an upgrade. Therefore, the changeable CPU package substrate allows the memory device to be reconfigured after the package assembly process. By enabling reconfiguration after the package assembly process, several possible advantages arise. For example, by allowing reconfiguration after package assembly, the versatility of the CPU package substrate is increased. Thus, a single CPU package substrate can be used for several different applications as opposed to having several pre-assembled CPU package substrates that are each tailored for different applications. . In addition, the customer can reconfigure the memory device himself without having to send a CPU package capable of changing memory back to the manufacturer or using expensive tools.

  Embodiments of the present invention allow manufacturers to tailor products to customer needs in a cost effective manner. For example, instead of soldering the memory device on a packaged substrate, the memory device can simply be pushed into a socket on the CPU package substrate. Since there is no need to perform a soldering process, throughput is increased and costs are reduced. Furthermore, the ease of reconfiguration allows the potential of the CPU package assembly to be cut off from undesirable memory configurations.

  Furthermore, embodiments of the present invention are useful in quality assurance testing processes. For example, the memory device can be removed during the test. Therefore, when a memory failure occurs, this failure can be easily attributed to the internal memory of the CPU device. There is almost no uncertainty about the failure of the memory (internal or external). Subsequently, each memory device can be individually tested by adding one memory device at a time and performing the test procedure. For example, if it is known that the internal memory is functioning correctly, a failure during testing when only one external memory device is installed is that this failure occurs in a single external memory device I can clarify that. By enabling this test strategy, the removable memory mechanical interface increases throughput and reduces production costs.

  FIG. 2A shows a changeable CPU package substrate 200 according to an embodiment of the present invention. The changeable CPU package substrate 200 can include a CPU package substrate 204. CPU package substrate 204 may be any suitable circuit board that interconnects the integrated circuit to the system board. In an embodiment, the CPU package substrate 204 includes an array of solder balls 209 under the CPU package substrate 204, eg, for interconnection to a system / motherboard of a computer system. The modifiable CPU package substrate 200 may include a processing device interface 202 and a memory device electrical interface 206 (or simply “mechanical device interface” 206). The memory device electrical interface 206 may be any suitable configuration of electrical input / output structures formed on the CPU package substrate 204. For example, the memory device electrical interface 206 may be an LGA or an array of pins. Although FIG. 2A illustrates a changeable CPU package substrate 200 that includes one processing unit interface 202 and four memory device electrical interfaces 206, other embodiments may employ other numbers. A processing device interface and a memory device electrical interface. For example, the modifiable CPU package substrate 200 can include a plurality of processing device interfaces 202 and at least one memory device electrical interface 206.

  The processing device interface 202 may be any suitable interconnect structure for coupling to a processing device (eg, a multi-core processor chip). For example, the processing device interface 202 may be an LGA having a plurality of N rows and M columns organized as an N × M array. In such an arrangement, the processing device interface 202 may be coupled to the processing device (not shown) by an array of solder joints, for example, via flip chip bonding. Alternatively, the processing device interface 202 may be an array of pads arranged as a frame-like pattern. For example, the frame pattern of the pad may surround an area where no pad exists. In such an example, the processing device interface 202 may be coupled to the processing device by a plurality of wires using wire bonding.

  The memory device electrical interface 206 may be an electrical interconnect configuration for communicatively coupling to the memory device. For example, the electrical interface 206 of the memory device may be an LGA organized on the CPU package substrate 204 as an N × M array or any other array formation. The memory device electrical interface 206 may be directly coupled to an electrical connection integrated into a memory device substrate or a removable memory mechanical interface, as further disclosed herein. The removable memory mechanical interface may be located in an area 208 around the memory device electrical interface 206. Therefore, this area 208 is an area where the mechanical interface of the removable memory can be arranged. In an embodiment, region 208 extends proximate to the electrical interface of the memory device. The area 208 can be expanded to an area directly above the memory device electrical interface 206 as well as an area on the changeable CPU package substrate 204 immediately adjacent to the memory device electrical interface 206.

  FIG. 2B shows a CPU package 201 that can change the memory according to the embodiment of the present invention. The CPU package 201 capable of changing the memory includes a processing device 203 coupled to the CPU package substrate 204. The processing device 203 may be flip-chip bonded to a processing device interface 202 (not shown) formed on the CPU package substrate 204. The memory-modifiable CPU package 201 can also include a memory device 205 that is electrically coupled to an electrical interface 206 (not shown) of the respective memory device. According to various embodiments, the memory device 205 is connected to the memory device's electrical interface via a respective removable memory mechanical interface (not shown), such as a removable memory mechanical interface located in the region 208. 206. In the embodiment, the memory device 205 is coupled to the memory device substrate 207. Although the memory device 205 is shown on the top surface of the memory device substrate 207, in the embodiment, the memory device 205 is mounted on the bottom surface of the memory device substrate 207. In the embodiment, the memory device 205 is mounted on the upper surface of the memory device substrate 207, and additional devices such as another memory device 205 and another processing device 203 are mounted on the lower surface of the memory device substrate 207. In embodiments, the memory device board 207 may be any suitable circuit board known in the art and may also be part of a package for the memory device 205. The memory device board 207 allows the memory device 205 to be interconnected to the memory device electrical interface 206 via a removable memory mechanical interface.

  According to an embodiment of the present invention, the memory device 205 is detachable from a removable memory mechanical interface. In an embodiment, no separate tool is required to attach and detach the memory device to and from the mechanical interface. For example, the memory device can be removed from the memory device mechanical interface in region 208 by pulling the memory device from the removable memory mechanical interface. Also, another memory device can be attached to the removable memory mechanical interface by pushing the memory device into the removable memory mechanical interface. Drawing and pushing can be done manually without the need for a separate tool. By allowing the memory device to be installed by hand, the changeable CPU package substrate 204 can have substantial versatility. After manufacturing the CPU package that can change the memory, the memory device can be installed so that the customer can easily customize the performance of the CPU package that can change the memory according to the customer's specific application. it can.

  The removable memory mechanical interface may be any suitable structure for mechanically attaching and detaching the memory device to and from the CPU package substrate, whereby insertion and removal are easily repeated. Examples include sockets, press-fit holes, alignment pins, and clips. Some basic examples of these are confirmed immediately below.

  FIG. 3A shows that the mechanical interface of the removable memory is implemented as a socket 302. The socket 302 can be mounted on the changeable CPU package substrate 204 around the electrical interface 206 of the memory device. The socket 302 may be mounted in the area 208 referred to in FIG. In an embodiment, the memory device electrical interface 206 is an N × M array of pads. The socket 302 is a structure that is compatible with the memory device substrate and the memory device. The memory device can be electrically coupled to the electrical interface 206 when fitted in the socket. In accordance with embodiments of the present invention, the socket 302 can have a variety of embodiments, as described in further detail herein.

  As can be seen in FIG. 3B, as an alternative to socket 302, the removable memory mechanical interface may be implemented as a set of press-fit holes 304 formed in the CPU package substrate. As shown in FIG. 3B, the set of press-fit holes 304 may surround the electrical interface of the memory device. In the embodiment, the set of press-fit holes 304 is disposed in the region 208 referred to in FIG. The press-fit hole 304 allows the memory device such that the memory device package has a “peg” or “pin” that fits into the hole 304 for attachment and detachment between the CPU package substrate and the memory device electrical interface. Can be. In an embodiment, the memory device is mounted on a memory device substrate, and the device has alignment pins that attach directly to the press-fit holes 304. An alignment pin can be inserted into the press-fit hole 304 as further described herein.

  Alternatively, as shown in FIG. 3C, the removable memory mechanical interface may be a set of alignment pins 306. Alignment pins 306 may be placed around the memory device electrical interface 206 in the region 208 referenced in FIG. The alignment pin 306 allows the memory device to be attached to and detached from the CPU package substrate 204. In an embodiment, the memory device is mounted on a memory device substrate and the device has a press-fit hole that attaches directly to the alignment pin 306. As described further herein, alignment pins 306 can be inserted into the press-fit holes.

  Still alternatively, the removable memory mechanical interface may be a spring-loaded clip 308, as shown in FIG. 3D. The spring-loaded clip 308 may be placed over and around the memory device electrical interface 206 in the region 208 referenced in FIG. In an embodiment, the spring-loaded clip 308 clips the memory device to the memory device electrical interface 206 by pressing on the memory device substrate using the force generated by the spring, as further described herein. Can be fastened.

  As far as possible, the removable memory mechanical interface may be implemented by combining two or more types of mechanical interfaces, such as the two or more types of mechanical interfaces described above with respect to FIGS. 3A-3D.

1.1 Socket Embodiments The removable memory mechanical interface may be formed in a variety of structures, and some of these structures may be different variations of sockets. In order to better disclose these variations, in the following embodiments, a changeable CPU package substrate is shown that includes various sockets as a removable memory mechanical interface. Various removable memory mechanical interfaces may be located in region 208 as disclosed herein with respect to FIG. 2A. As shown in the following figure, the processing device 203 is attached to a changeable CPU package substrate, and how the memory device can be attached to the removable memory mechanical interface after package assembly. Is specifically shown. As defined herein, a socket is a structure into which a corresponding structure can be inserted. Once inserted, the corresponding structure can then be bonded to the underlying substrate.

1.1.1 Slide Rail Socket In an embodiment, the removable memory mechanical interface is a slide rail socket. FIG. 4A shows a package that includes a slide rail socket 402 on a changeable CPU package substrate 200. The slide rail socket 402 includes a pair of slide grooves 410A and 410B that help guide the corresponding structure within the slide rail socket 402. An array of input / output (I / O) connections 403 may be placed in the slide rail socket 402. In the embodiment, as shown in FIG. 4A, the array of I / O connections 403 is formed as an N × M array of pins. Although shown as an array of pins, in an alternative embodiment, the array of I / O connections 403 is an N × M array of pads. The memory device electrical interface (not shown) may be located under the slide rail socket 402. The array of I / O connections 403 may be electrically coupled to the electrical interface of the memory device. In the embodiment, the slide rail type socket 402 may face the outer edge of the changeable CPU package substrate 200. By facing the outer edge, the processing device 203 can prevent the structure from being inserted into the slide rail socket 402.

  An exemplary slide rail socket counterpart 401 for slide rail socket 402 is shown in FIGS. 4B-4C. Specifically, FIG. 4B shows a bottom perspective view of the corresponding portion 401 of the slide rail socket, and FIG. 4C shows a top perspective view of the corresponding portion 401.

  Referring to FIG. 4B, the corresponding portion 401 of the slide rail type socket is formed from the memory device substrate 440. The memory device substrate 440 may be any suitable circuit board known in the art. An array of interconnect structures 406 may be disposed on the bottom surface 404 of the memory device substrate 440. In an embodiment, the array of interconnect structures 406 is an array of pads. In an alternative embodiment, the array of interconnect structures 406 is an array of pins. Whether the array of interconnect structures 406 is an array of pads or an array of pins, the array of I / O connections 403 complements the interconnect structure 406 so that electrical connections can be formed. To do. For example, if the array of interconnect structures 406 is an array of pads, the array of I / O connections 403 is an array of pins, and vice versa.

  Referring now to FIG. 4C, the memory device 205 mounted on the memory device substrate 440 is shown. In embodiments, the memory device 205 is a flip chip bonded to the top surface 408 of the memory device substrate 440, although any other suitable bonding method, such as wire bonding, is envisioned in embodiments of the present invention. Memory device 205 can be interconnected to an array of interconnect structures 406 via memory device substrate 440.

  4D-4E illustrate a method of attaching memory device 205 to a removable memory mechanical interface. Specifically, FIGS. 4D to 4E show a method of attaching the corresponding portion 403 of the slide rail socket 402 to the slide rail socket 402.

  As shown in FIG. 4D, the corresponding portion 401 of the slide rail type socket moves toward the slide grooves 410A and 410B. The corresponding portion 401 of the slide rail socket can be aligned by mechanical interaction between the slide grooves 410A and 410B and the respective rails 411A and 411B of the corresponding portion 401 of the slide rail socket. For example, the rails 411A and 411B can slide in the slide grooves 410A and 410B when the corresponding portion 401 of the slide rail socket is inserted into the slide rail socket 402. In the embodiment, the slide grooves 410A and 410B are U-shaped to align the memory device substrate 440 in the X and Y directions. The rails 411A and 411B that fit into the slide grooves 410A and 410B, respectively, can be the edge of the memory device substrate 440.

  In the embodiment shown in FIG. 4D, the array of I / O connections 403 is an array of pins. In an embodiment, the array of pins is an array of cantilever pins that bend when pressed against a surface. Thus, the array of pins can follow a non-uniform height pad across the array of interconnect structures 406. The ability to follow non-uniform height pads allows the array of pins 403 to contact the entire array of interconnect structures 406 despite the difference in height among the structures 406. . In an embodiment, the array of pins 403 is inclined toward the stop wall 414 of the slide rail socket 402. A stop wall 414 may be disposed at the rear end of the slide rail socket 402. By tilting toward the stop wall 414 of the socket 402, frictional damage between the pin 403 and the pad 406 is minimized when the counterpart 401 of the slide rail socket is inserted into the socket 402. Can do. The stop wall 414 prevents the memory device substrate 440 from being excessively inserted into the slide rail socket 402. Accordingly, the stop wall 414 can align the memory device substrate 440 in the Z direction.

  The slide rail socket 402 may include a window 412. In an embodiment, as shown in FIG. 4E, the window 412 is an opening 412 in the slide rail socket 402 that allows the memory device 205 to slide within its slide rail socket. Because the memory device 205 is blocked by the top of the socket 402, the memory device substrate 440 cannot be fully inserted into the socket 402 without the opening 412.

  FIG. 4E shows the attachment of the slide rail socket counterpart 401 to the slide rail socket 402. The slide grooves 410A and 410B hold the memory device substrate 440 with the holding portions 420A and 420B of the slide grooves 410A and 410B, thereby fixing the corresponding portion 401 of the slide rail type socket at a predetermined position. In an embodiment, the height 416 of the groove 410 may be equal to this thickness 418 if it is not slightly greater than the thickness 418 of the memory device substrate 440. Thus, the height 416 allows the memory device substrate 440 to slide within the groove 410 while maintaining contact to prevent the slide rail socket counterpart 401 from substantially moving. Once installed, the memory device 205 can be electrically coupled to the changeable CPU package substrate 200 by an array of I / O connections 403 in the slide rail socket 402.

  In the embodiment, the memory device 205 is held at a predetermined position by static friction between the slide groove 410 and the corresponding portion 401 of the slide rail type socket. Therefore, the memory device 205 can be removed from the slide rail type socket 402 of the changeable CPU package substrate 200 with a force larger than the static friction force. The new slide rail socket counterpart 401 containing the new memory device 205 can then be replaced with the old counterpart 401 and attached to the slide rail socket 402. In an embodiment, no separate tool is required to remove the memory device 205 from the slide rail socket 402.

Multi-edge socket Besides the slide rail socket, the mechanical interface of the removable memory may be a multi-edge socket. For example, the removable memory mechanical interface may be a double edge socket or a full edge pin grid array socket, as further described herein.

1.1.2.1 Double Edge Socket FIG. 5A shows a package including a double edge socket 502 on a modifiable CPU package substrate 200 according to an embodiment of the present invention. The double edge socket 502 is an L-shaped socket including an opening 504 that faces laterally toward the outer edge of the changeable CPU package substrate 200. By facing laterally toward the outer edge, the processing device 203 can prevent the structure from being inserted into the double edge socket 502. In an embodiment, the double edge socket 502 is coupled to the corresponding memory device electrical interface 206 on the changeable CPU package substrate 200. For example, the memory device electrical interface 206 may be an array of pads coupled to an array of wire connections 520 of a double edge connector 502.

  Detailed front and back perspective views of the double edge socket 502 are shown in FIGS. 5B and 5C, respectively. As shown in FIG. 5B, the double edge socket 502 has a first portion 506 and a second portion 508 connected by a joint 510. The first and second portions 506/508 may form an offset angle 512. Accordingly, the first portion 506 may extend in the direction of the offset angle from the second portion 508. In an embodiment, the opening 504 extends along both portions 506/508 and extends through the junction 510. Accordingly, the corresponding structure can be inserted into the opening 504 to form a connection with the double edge socket 502. Specifically, two adjacent edges of the corresponding structure are coupled to a double edge socket 502. In embodiments, the opening 504 includes a chamfered corner 516 at the end of the opening 504 for insertion alignment, as further described herein.

  In an embodiment, opening 504 includes an array of I / O connections 514 for coupling to external structures. In an embodiment, the array of I / O connections 514 is an array of contacts, such as an array of pads or an array of cantilever pins. An array of I / O connections 514 may be disposed on the bottom inner surface of the opening 504. In an embodiment, the opening 504 includes a second array (not shown) of I / O connections. A second array of I / O connections may be placed on the upper inner surface of the opening 504. During installation, the array of I / O connections 514 are oriented along the insertion direction to prevent electrical shorting between adjacent contacts. In an embodiment, the insertion direction is an angle that is half the offset angle from the first or second portion 506/508. As described herein, a further description of the insertion direction is shown in FIG. 5D.

  The array of I / O connections 514 should have contact pitches designed to maximize the number of contacts while ensuring that each contact has sufficient surface area to form an electrical connection. Can do. In an embodiment, the contact pitch may be in the range between 0.3 and 0.5 mm. In certain embodiments, the array of I / O connections 514 has a contact pitch of about 0.4 mm. Thus, for a socket 520 that includes an inner array of bottom and top surfaces of I / O connections 514, a double edge socket 502 can have a total of about 160 pads. Also, a contact density of about 5 contacts per mm can be realized.

  As shown in FIG. 5C, both arrays of I / O connections 514 may be electrically coupled to corresponding arrays of wire connections 520 located behind double edge socket 502. The array of wire connections 520 allows the double edge socket 502 to be coupled to the electrical interface 206 of the corresponding memory device on the changeable CPU package substrate 200. In an embodiment, the array of wire connections 520 is a gull wing connection.

  FIG. 5D shows a top perspective view of the corresponding portion 503 of the double edge socket. In an embodiment, the double edge socket counterpart 503 includes an integrated circuit device such as the memory device 205. The memory device 205 may be flip-chip bonded to the memory device substrate 540. The memory device substrate 540 may have several edges 505A-505D. The two edges 505A and 505B can be joined at one end to form a corner 507. In an embodiment, the two edges 505A and 505B form a separation angle 511 from each other. This separation angle may be equal to the offset angle 512 of the double edge connector 502. In an embodiment, the separation angle 511 and the offset angle 512 are about 90 degrees.

  The memory device substrate 540 also includes a single connection interface 522. A single connection interface 522 can extend continuously across two adjacent edges, such as edges 505A and 505B. Thus, a single connection interface 522 can form an L-shaped profile along edges 505A and 505B. In an embodiment, the single connection interface 522 includes an array of pads 524 that extend to all edges of the memory device substrate 540. The array of pads 524 can have a contact pitch corresponding to the double edge connector 502. For example, the array of pads 524 can have a contact pitch of about 0.4 mm, thus forming an array of pads 524 that includes about 160 pads.

  In an embodiment, each pad of the array of pads 524 is aligned in the insertion direction 515. The insertion direction 515 can be a direction for inserting the corresponding portion 503 of the double edge socket into the double edge socket 502 to prevent a short circuit between each pad of the array of tape pads 524. In the embodiment, the insertion direction 515 is an angle 513 that is half of the separation angle 511. Thus, each pad of the array of pads 524 is aligned in the direction of angle 513 which is half of the separation angle 511. In an embodiment where the separation angle is 90 degrees, each pad of the array of pads 524 is aligned in a 45 ° direction from the edge 505A. In an embodiment, each pad of the array of pads 524 is aligned in the same direction as the array of I / O connections 514.

  Although FIG. 5D shows a single connection interface 522 having an array of pads 524 on only one side of the memory device substrate 540, embodiments are not limited thereto. For example, the single connection interface 522 may also have a set of pads (not shown) arranged in a mirror image relationship on the lower surface of the memory device substrate 540. The set of pads arranged in a mirror image relationship is the same size as the array of pads 524 and is aligned in the same direction as the array of pads 524.

  The memory device substrate 540 can also include a chamfer edge 518. The chamfered edge 518 can be located at a corner of the memory device substrate 540 such that the end of a single connection interface 522 is located. For example, chamfered edge 518 can be located at the corner between edges 505A and 505D as well as between edges 505B and 505C. The chamfer edge 518 may face along the insertion direction 515. Thus, in the embodiment, the chamfered edge 518 is parallel to the pad 524. As further described herein with respect to FIGS. 5E-5F, the chamfered edge 518 can assist in aligning the double edge socket counterpart 503 with the double edge socket 502 during insertion.

  FIGS. 5E-5F illustrate a method of attaching a memory device to a removable memory mechanical interface. Specifically, FIGS. 5E-5F illustrate a method of attaching a double edge socket counterpart 503 to a double edge socket 502. FIG.

  As shown in FIG. 5E, the corresponding portion 503 of the double edge socket is inserted toward the double edge socket 502. In the embodiment, the corresponding portion 503 of the double edge socket is inserted along the insertion direction 515. By inserting the corresponding portion 503 along the insertion direction 515, the pads are already oriented along the insertion direction 515 when installed, so that adjacent pads in each array of pads 524 and 514 A short circuit between the two is substantially prevented. The chamfered edge 518 of the memory device substrate 540 can be mechanically aligned with the socket 502 by sliding against the corresponding chamfered corner 516 of the socket 502. In an embodiment, the chamfered corner 516 of the double edge socket 502 extends along the insertion direction 515. Accordingly, the chamfered corner 516 guides the memory device substrate 540 along the insertion direction 515 during insertion.

  In FIG. 5F, the corresponding portion 503 of the double edge socket attached to the double edge socket 502 is shown. In an embodiment, the array of I / O connections 514 is electrically coupled to the array of pads 524. Accordingly, the array of pads 524 can be electrically coupled to the array of wire connections 520. Accordingly, the memory device 205 can be electrically coupled to the changeable CPU package substrate 200.

  In embodiments, the memory device 205 can be held in place by static friction between the array of pads 524 and the array of I / O connections 514. Accordingly, the memory device 205 can be removed from the double edge socket 502 of the changeable CPU package substrate 200 by a force larger than the static friction force. The new double edge socket counterpart 503 containing the new memory device 205 can then be replaced with the old counterpart 503 and attached to the double edge socket 502. In an embodiment, no separate tool is required to remove the memory device 205 from the double edge socket 502.

1.1.2.2 Full Edge Pin Grid Array Socket FIG. 6A shows a package including a full edge pin grid array socket 602 on a modifiable CPU package substrate 200 according to an embodiment of the present invention. Yes. The full edge pin grid array socket 602 allows the memory device to be removed from the changeable CPU package substrate 200. In the embodiment, the socket structure 604 has a frame-shaped profile disposed on the changeable CPU package substrate 200. An electrical interface (not shown) of the memory device may be disposed on the changeable CPU package substrate 200 below the frame-like structure 604. The electrical interface of the memory device can be electrically coupled to the socket 602.

  In FIG. 6B, a more detailed view of the full edge pin grid array socket 602 is shown. As shown, the full edge pin grid array socket 602 has a socket structure 604 that includes a plurality of openings 606. The plurality of openings 606 may be arranged along a frame-shaped profile. The opening 606 can correspond to a connection pin from a corresponding system, as further described herein. In the embodiment, the opening 606 is disposed on the upper surface 608 of the frame-like structure 604. That is, the plurality of openings 606 may extend from the top surface 608 of the socket 602 into the socket structure 604. Thus, the opening 606 allows pins to be inserted into the full edge pin grid array socket 602 to form an electrical connection with the changeable CPU package substrate 200.

  FIGS. 6C-6E illustrate exemplary portions of a response system that can be assembled to form a corresponding portion of a full edge pin grid array socket. Specifically, FIG. 6C shows a top perspective view of device portion 603, and FIGS. 6D-6E show top and bottom perspective views of interconnect 607, respectively. In an embodiment, one device portion 603 and two interconnect portions 607 are assembled to form a corresponding portion of a full edge pin grid array socket, as further described herein with respect to FIGS. 6F-6G. It is done.

  Referring to FIG. 6C, device portion 603 includes a memory device 205 mounted on a memory device substrate 640. Similar to the configuration of the double edge socket counterpart 503 previously disclosed herein, the memory device substrate 640 of the device portion 603 may have edges 605A-605D disposed at a separation angle 613 from each other. However, instead of having only one connection interface (522 in FIG. 5D), the memory device substrate 640 may have two connection interfaces 622A and 622B. Each connection interface 622 can span two adjacent edges, thus forming an L-shaped connection profile. For example, the first connection interface 622A can span across edges 605A and 605B, and the second connection interface 622B can span across edges 605C and 605D.

  Each of the connection interfaces 622A and 622B extending to the edge of the memory device substrate 640 can include an array of pads 624. An array of pads (not shown) arranged in a mirror image relationship may be arranged below the memory device substrate 640. The array of pads 624 can have a contact pitch that maximizes the number of pads while maintaining sufficient surface area to form a robust electrical connection. For example, an array of pads 624 can have a contact pitch of about 0.4 mm, thus forming a connection interface 622 that includes about 160 pads. Given that there are two connection interfaces 622A and 622B, the memory package 640 may therefore have a total of about 320 pads.

  Again, like the double edge socket counterpart 503, each pad of the array of pads 624 on the memory device substrate 640 of the device portion 603 is aligned in the insertion direction 615. The insertion direction 615 is the direction in which the interconnect portion 607 is assembled to the device portion 603 so as to prevent a short circuit between each pad of the array of pads 624. The insertion direction 615 can be an angle 613 that is half of the separation angle 611. Thus, each pad of the array of tape pads 624 is aligned at an angle 613 that is half of the separation angle 611.

  The chamfered edge 618 can be disposed at a corner of the memory device substrate 640 where the ends of the connection interfaces 622A and 622B are disposed. Further, the chamfered edge 618 may be faced along the insertion direction 615. Thus, in the embodiment, the chamfered edge 618 is parallel to the pad 624. The chamfered edge 618 assists in assembling the device portion 603 to the interconnect 607, as described herein with respect to FIGS. 6F-6G.

  Referring now to FIG. 6D, an interconnect portion 607 is shown having a first portion 606 and a second portion 608. Similar to the double edge socket 502, the first and second portions 606/608 of the interconnect 607 are arranged in an L-shaped profile, where these portions are arranged at an offset angle 612 from each other. ing. Interconnect portion 607 includes an opening 604 extending across both portions 606 and 608. An array of I / O connections 614 may be disposed within the opening 604 and may be disposed along the insertion direction 615. Thus, the array of I / O connections 614 can be aligned in the same direction as the array of pads 624. In embodiments, the array of I / O connections 614 is an array of pads or an array of cantilever pins. As shown in FIG. 6E, the I / O connection 614 can be coupled to an array of connection pins 620 disposed below the interconnect 607. The connection pin 620 may have a vertical shape in order to be inserted into the opening 606 of the socket structure 604. The interconnect portion 607 can be assembled to the device portion 603 to form a full edge pin grid array socket counterpart 621 as further described herein with respect to FIGS. 6F-6G.

  FIGS. 6F-6G illustrate a method of forming the corresponding portion 621 of the full edge pin grid array socket. In an embodiment, the two interconnects 607A and 607B are assembled to the device portion 603 to form a corresponding portion 621 of the full edge pin grid array socket. As shown in FIG. 6F, the first interconnect portion 607A is assembled to the device portion 603. In an embodiment, the first interconnect portion 607A is inserted toward the device portion 603 along the insertion direction 615 to avoid a short circuit between the pads of the array of pads 624. The chamfered edge 618 of the memory device substrate 640 can slide along the chamfered corner 616 of the interconnect 607A to assist in alignment during assembly. Details of chamfered edge 618 and chamfered corner 616 may refer to the disclosure relating to FIG. 5E. Once the first interconnect portion 607A is installed, the first connection interface 622A along edges 605A and 605B may be electrically coupled to the first interconnect portion 607A, while edges 605C and 605D. The second connection interface 622B along the line may be exposed.

  In FIG. 6G, the second interconnect portion 607B may be attached to the second connection interface 622B, thereby completing the assembly of the corresponding portion 621 of the full edge pin grid array socket. Once attached, the second connection interface 622B can be electrically coupled to the second interconnect portion 607B. Accordingly, the first and second connection interfaces 622A and 622B can be electrically coupled to the first and second interconnect portions 607A and 607B. Although the embodiments disclose attaching the first interconnect portion 607A before attaching the second interconnect portion 607B, the embodiments are not limited to such an attachment sequence. For example, the first interconnect portion 607A can be attached after or simultaneously with the second interconnect portion 607B.

  Once the full edge pin grid array socket counterpart 621 is assembled, the counterpart 621 can then be attached to the full edge pin grid array socket 602. FIGS. 6H-6I illustrate a method of attaching the full edge pin grid array socket counterpart 621 to the full edge pin grid array socket 602. In FIG. 6H, the corresponding portion 621 is pressed onto the socket 602. In an embodiment, the connection pin 620 is pushed toward the corresponding opening 606 in the socket structure 604. When fully pressed as shown in FIG. 6I, the connection pins 620 are fully inserted into the respective openings 606 to form an electrical connection between the counterpart 621 and the socket 602. Accordingly, the memory device 205 can be electrically coupled to the changeable CPU package substrate 200.

  In the embodiment, the memory device 205 can be held in a predetermined position by static friction between the connection pin 620 and the opening 606. Accordingly, the memory device 205 can be removed from the full edge pin grid array socket 602 of the changeable CPU package substrate 200 by a force larger than the static friction force. The new device portion 603 containing the new memory device 205 can then be replaced with the old device portion 603 and attached to the full edge pin grid array socket 602. In an embodiment, no separate tool is required to remove and reinstall the memory device 205 from the full edge pin grid array socket 602.

1.1.3 Low Insertion Force Socket According to an embodiment of the present invention, the mechanical interface of the removable memory may be a low insertion force socket. FIG. 7A illustrates a package including a low insertion force socket 702 on a changeable CPU package substrate 200 according to an embodiment of the present invention. The low insertion force socket 702 allows the memory device to be removed from the changeable CPU package substrate 200. The low insertion force socket 702 can be electrically coupled to an electrical interface (not shown) of a memory device disposed on the substrate 200 under the socket 702. In an embodiment, the low insertion force socket 702 includes a housing structure 706 and an array of openings 704 disposed within the housing structure 706. An enlarged view of the array of openings 704 is shown in FIG. 7B.

  An enlarged top perspective view of a portion of the low insertion force socket 702 is shown in FIG. 7B. As shown, each opening in the array of openings 704 includes an interconnect region 705 and a pin flex region 707. Interconnect region 705 is the region of opening 704 through which solder balls are inserted to form an electrical connection, as further described herein. Extending from the interconnect region 705 is a pin flex region 707. In an embodiment, the pin flex region 707 extends radially away from the center of the interconnect region 705. A pin deflection area 707 allows the contact pin 708 to traverse within the pin deflection area.

  In an embodiment, each opening in the array of openings 704 may include a contact pin 708. Contact pin 708 can be coupled to an interconnect structure of a corresponding portion of the low insertion force socket, as described herein. The structural profile of the contact pin 708 is shown in FIG. 7C.

  FIG. 7C shows a cross-sectional view of the contact pin 708 along line A-A ′ of FIG. 7B. In an embodiment, the contact pin 708 has a curved contact end 710 and an extension 712. The curved contact end 710 can be brought into contact with a corresponding interconnect structure to form an electrical connection. A force can be applied by the extension 712 to maintain contact between the curved contact end 710 and the corresponding interconnect structure. A solder connection 714 may be disposed on the base end 713 of the contact pin. The base end 713 may be part of a contact pin 708 disposed at the end opposite the curved contact end 710. The solder connection portion 714 can be electrically connected to the electrical interface of the memory device on the changeable CPU package substrate 200.

  Referring now to FIG. 7D, a bottom perspective view of the low insertion force socket counterpart 703 is shown in accordance with an embodiment of the present invention. The low insertion force socket counterpart 703 includes a memory device 205 mounted on an upper surface (not shown) of the memory device substrate 740. An array of electrical components 720 such as land side capacitors may be disposed on the bottom surface 722 of the memory device substrate 740. The electrical component 720 can be electrically coupled to the memory device 205 via the interconnects of the memory device substrate 740. Further, an array of interconnect structures 716 may be disposed on the bottom surface 722 of the memory device substrate 740. An array of interconnect structures 716 can be coupled to the connection pins 708 of the low insertion force socket 702, as further described herein. In an embodiment, an alignment frame 718 may be placed around the array of interconnect structures 716. An alignment frame 718 can assist in aligning the interconnect structure 716 with the respective opening 704 in the socket 702.

  In FIG. 7E, a close-up view of the interconnect structure 716 is shown. An interconnect structure 716 may be disposed on the pad 726. The pad 726 may be disposed on the bottom surface 722 of the memory device substrate 740. In an embodiment, the interconnect structure 716 is a conductive structure such as a solid copper ball or a solder ball. The conductive structure can be coated with a conductive material. The conductive material can prevent corrosion of the underlying conductive structure while maintaining sufficient electrical conductivity to form an electrical connection. In embodiments, the conductive material includes nickel (Ni), palladium (Pd), and / or gold (Au). In an embodiment, the conductive material is NiPdAu. Accordingly, the interconnect structure 716 may be formed of solder balls that are coated with a thin layer of NiPdAu.

  An exemplary method for attaching memory device 205 to a removable memory mechanical interface is shown in FIGS. 7F-7H. Specifically, FIGS. 7F-7H illustrate a method of attaching the interconnect structure 716 of the low insertion force socket counterpart 703 to the connection pin 708 of the low insertion force socket 702. FIG. The cross-sectional views of FIGS. 7F-7H are cut along line A-A ′ as shown in FIG. 7B during attachment of the corresponding portion 703 to the socket 702.

  In FIG. 7F, the interconnect structure 716 is pushed toward the opening 704 of the socket 702 along with the counterpart 703. In an embodiment, the interconnect structure 716 is inserted toward the interconnect region 705 of the opening 704. To align the interconnect structure 716 with the interconnect region 705, the inner edge 719 (see FIG. 7D) of the alignment frame 718 slides against the outer edge 721 (see FIG. 7A) of the housing structure 706. Can do. As shown in FIG. 7G, once the interconnect structure 716 contacts the connection pin 708, the interconnect structure 716 slides against the curved surface 728 of the curved contact end 710 of the connection pin 708. As the interconnect structure 716 is pushed further into the opening 704, the connection pin 708 is distorted within the pin deflection region 707 of the opening 704. In an embodiment, the curved surface 728 causes the pin to be laterally distorted within the pin deflection region 707. The interconnect structure 716 can continue to be inserted into the opening 704 until the bottom surface 722 of the memory device substrate 740 contacts the top surface 723 of the housing structure 706, as shown in FIG. 7H.

  FIG. 7H shows a low insertion force socket counterpart 703 attached to a low insertion force socket 702 according to an embodiment of the present invention. When attached, the connection pin 708 contacts the interconnect structure 716. In an embodiment, the curved surface 728 of the curved contact end 710 contacts the interconnect structure 716 at the contact 730. Contact 730 may be above equator 724 of interconnect structure 716. In an embodiment, the contact 730 is greater than 1 μm above the equator 724. Contacting the pin 708 with the interconnect structure 716 at the contact 730 depends on the position of the equator, respectively. For example, the distance 732 from the tip 736 to the equator 731 of the curved contact end 710 may be less than the distance 734 from the tip 725 to the equator 724 of the interconnect structure 716. When the contact 730 is above the equator 724, the connection pin 708 generates not only a lateral force but also a slightly downward force. The downward force pulls the interconnect structure 716 downward. Accordingly, the corresponding portion 703 of the low insertion force socket can be pulled toward the socket 702 and remain attached thereto.

  In the embodiment, the memory device 205 can be held in place by the downward force generated by the connection pin 708. Therefore, the memory device 205 can be removed from the low insertion force socket 702 of the CPU package substrate 200 that can be changed by a force larger than the downward force. The new low insertion force socket counterpart 703 that includes the new memory device 205 can then be replaced with the old low insertion force socket counterpart 703 and attached to the low insertion force socket 702. In an embodiment, no separate tool is required to remove the memory device 205 from the low insertion force socket 702.

1.1.3.1 Flexible Cable Variation of Corresponding Portion of Low Insertion Force Socket According to an embodiment of the present invention, the low insertion force socket 702 and the corresponding portion 703 may have a deformed design. it can. For example, the low insertion force socket counterpart 703 may be a flexible cable for forming a flexible cable counterpart 803 as shown in the embodiment shown in FIG. 8B of FIGS. 8A-8D. May be included. By incorporating a flexible cable into the socket counterpart 703, the memory device 205 or memory device substrate 840 can be attached directly to a heat sink, as disclosed herein. Although the embodiment shows a variant design utilizing a low insertion force socket 702, those skilled in the art may alternatively use the other types of removable memory mechanical interfaces described herein. I understand that. The embodiments show these variant designs that simply include a low insertion force socket 702 for ease of explanation.

  Referring now to FIG. 8A, there is shown a low insertion force socket 802 disposed on a changeable CPU package substrate 200 according to an embodiment of the present invention. The low insertion force socket 802 allows the memory device to be removed from the changeable CPU package substrate 200. The low insertion force socket 802 can be electrically coupled to an electrical interface (not shown) of a memory device disposed on the substrate 200 under the socket 802. In an embodiment, the low insertion force socket 802 includes an alignment notch 809 to achieve correct alignment when the memory device is installed. Details relating to the structure of the low insertion force socket 802 may be referenced in the disclosure herein with respect to the low insertion force socket 702 of FIGS. 7A-7C.

  FIG. 8B shows a corresponding portion 803 of a flexible cable according to an embodiment of the present invention. The flexible cable counterpart 803 includes a memory device 205 mounted on a memory device substrate 840. Further, the corresponding portion 803 of the flexible cable aligns to enclose an array of interconnect structures 816 (eg, solid copper balls or solder balls coated with NiPdAu) to align the corresponding portion 803 with the socket 802. A frame 818 is included. In an embodiment, the alignment frame 818 has alignment tabs 819 that ensure the correct orientation of the flexible cable counterpart 803 during installation. The alignment tabs 819 can be fitted into alignment notches 809 on the low insertion force sockets 802 to ensure that the pins in the sockets 802 are accurately coupled to the respective interconnect structures 816. . According to embodiments of the present invention, the memory device substrate 840 can be coupled to the interconnect structure 816 via a strip of flexible cable 804. The flexible cable 804 can be attached to the memory device substrate 840 using known methods. For example, the flexible cable 804 may be soldered to a pad (not shown) disposed on the memory device substrate 840. As is well known, a flexible cable can physically and electrically couple two structures together while allowing a wide range of motion. In this example, the flexible cable 804 makes it possible to dispose the memory device 205 at a position away from the changeable CPU package substrate 200 as shown in FIG. 8C. Memory device 205 may also be electrically coupled to interconnect structure 816.

  FIG. 8C shows a flexible cable counterpart 803 mated with a low insertion force socket 802. The flexibility of the flexible cable 804 allows the memory device 205 to face a wide range of positions. For example, as shown in FIG. 8C, the memory device 205 may be vertically oriented with respect to the changeable substrate 200. By orienting memory device 205 and memory device substrate 840 in a vertical direction relative to changeable substrate 200, memory device 205 can be attached to heat sink 820, as shown in FIG. 8D.

  In FIG. 8D, the memory device substrate 840 is attached to the heat sink 820. The memory device substrate 840 may be attached to the heat sink 820 using mechanical fasteners for easy removal. For example, the memory device substrate 840 may be clipped to the heat sink 820. By attaching the memory device substrate 840 directly to the heat sink 820, better heat dissipation is possible, thereby increasing the performance of the memory device 205. Although the embodiment shown in FIG. 8D shows the memory device substrate 840 attached to the heat sink 820, an arrangement for attaching the memory device 205 to the heat sink 820 is envisioned in embodiments of the present invention. For example, the memory device 205 and the substrate 840 may be turned over during manufacture of the flexible cable counterpart 803 such that the memory device 205 contacts the heat sink 820 inwardly.

  In an embodiment, memory device 205 is held in place by mechanical fasteners that attach memory device 205 to heat sink 820 as well as low insertion force socket 802. Therefore, by changing the clip of the mechanical fastener, removing the heat sink 820, and pulling out the flexible cable counterpart 803 from the socket 802 with a force greater than the downward force generated by the pins in the socket 802. The memory device 205 can be removed from the possible CPU package substrate 200. Next, the new flexible cable counterpart 803 containing the new memory device 205 is replaced with the old flexible cable counterpart 803 and attached to the low insertion force socket 802 of the changeable CPU package substrate 200. Can do.

1.1.3.2 Low Insertion Force Socket Flexible Cable Variation In another example, the low insertion force socket 702 is as shown in the embodiment shown in FIG. 9A of FIGS. 9A-9G. A flexible cable for forming the flexible cable socket 902 may be included. Similar to the socket counterpart 703, incorporating a flexible cable into the socket 702 allows the memory device 205 or memory device substrate 940 to be attached to a heat sink. Although the embodiments shown herein utilize a low insertion force socket 702, those skilled in the art will appreciate that other types of removable memory mechanical interfaces described herein may be used. . The embodiments are shown for those embodiments that simply include a low insertion force socket 702 for ease of explanation.

  In FIG. 9A, a flexible cable socket 902 is disposed on a changeable CPU package substrate 200 according to an embodiment of the present invention. The flexible cable socket 902 may include a strip of flexible cable 904 having two opposite ends 911 and 913. A low insertion force socket 702 may be disposed at each opposing end 911/913. The flexible cable 904 may have a connection portion 906 disposed between opposite ends 911 and 913. The connection 906 may be directly coupled to an electrical interface (not shown) of a memory device disposed on the substrate 200 under the connection 906 of the flexible cable 904. In an embodiment, the connection 906 has an array of interconnects 905 disposed at the bottom of the connection 906, as shown in FIG. 9B. The interconnect 905 allows the flexible cable socket 902 to be electrically coupled to the changeable CPU package substrate 200. In an embodiment, the interconnect 905 is a solder ball. The solder balls may be reflowed over the electrical interface of the memory device on the substrate 200 to form an electrical connection. In such embodiments, the electrical interface of the memory device may be an array of pads that connect to the interconnect 905.

  Given the flexible nature of the flexible cable 904, the flexible cable socket 902 can be placed in a wide range of locations. For example, the low insertion force socket 702 of the flexible cable socket 902 may be arranged vertically above the changeable CPU package substrate 200. Accordingly, as described further herein, the flexible cable socket 902 allows the memory device 205 to be attached to a heat sink.

  A low insertion force socket counterpart 903 is shown in FIGS. 9C-9D. Specifically, FIG. 9C shows a top perspective view of the corresponding portion 903 of the low insertion force socket, while FIG. 9D shows a bottom perspective view of the corresponding portion 903 of the low insertion force socket. Yes. As shown in FIG. 9C, the low insertion force socket counterpart 903 may be substantially similar to the low insertion force socket counterpart described herein with respect to FIG. 7D. In an embodiment, the corresponding portion 903 may include a plurality of memory devices 205 and a memory device substrate 940, as shown in FIG. 9C. The memory devices 205 may be stacked on each other by any suitable stacking method. The alignment frame 908 may be located at the bottom of the bottom memory device substrate 940, better shown in FIG. 9D. Although FIG. 9C illustrates one embodiment of a corresponding portion with stacked memory devices 205, it should be understood that corresponding portions disclosed herein also have similarly stacked memory devices.

  Referring to FIG. 9D, the low insertion force socket counterpart 903 can include an array of interconnect structures 912. The array of interconnect structures 912 can be any suitable conductive structure for making electrical connections. For example, the array of interconnect structures 912 is an array of solid copper balls. In the particular embodiment of FIG. 9D, the array of interconnect structures 912 is an array of pins. The low insertion force socket counterpart 903 can be attached to the flexible cable socket 902 as previously described herein with respect to FIGS. 7F-7H. Thus, the array of pins can have rounded chips having dimensions similar to the interconnect structure 716.

  Given the flexible nature of the flexible cable 904, the flexible cable socket 902 can be placed in a wide range of locations. For example, the flexible cable socket 902 may be configured such that the low insertion force socket 702 is positioned and positioned vertically above the changeable CPU package substrate 200 as shown in FIG. 9E. Good.

  FIG. 9E shows the corresponding portion 903 of the low insertion force socket fitted into the flexible cable socket 902. In certain embodiments, the counterpart 903 can be mated with the low insertion force socket 702 of the flexible cable socket 902. Once mated, the corresponding portion 903 can be positioned and positioned vertically above the changeable CPU package substrate 200. Thus, the corresponding portion 903 can be attached to the heat sink 920 as shown in FIG. 9F.

  In FIG. 9F, the low insertion force socket counterpart 903 is attached to the heat sink 920. In the embodiment, the memory device 205 of the corresponding portion 903 is attached to the heat sink 920. The memory device 205 can be attached to the heat sink 820 using mechanical fasteners (not shown) for easy removal. For example, the memory device 205 may be clipped to the heat sink 920. By attaching the memory device 205 directly to the heat sink 820, better heat dissipation is possible, thereby improving the performance of the memory device 205.

  In an embodiment, memory device 205 is held in place by a mechanical fastener that attaches memory device 205 to heat sink 920 as well as flexible cable socket 902. Accordingly, the memory device 205 is removed by unclipping the mechanical fastener and withdrawing the corresponding portion 903 of the low insertion force socket from the low insertion force socket 702 with a force greater than the downward force generated by the pins in the socket 702. Can be removed from the flexible cable socket 902 of the CPU package substrate 200. The new low insertion force counterpart 903 containing the new memory device 205 can then be replaced with the old low insertion force socket counterpart 903 and attached to the flexible cable socket 902.

1.1.4 “Zero” Insertion Force Socket According to an embodiment of the present invention, the removable memory mechanical interface may be a “zero” insertion force socket. A zero insertion force socket is a case where there is very little resistance to insertion of a corresponding portion that slides horizontally within the mechanical interface of the removable memory, as further described herein. FIG. 10A shows a package including a zero insertion force socket 1002 on a modifiable CPU package substrate 200 according to an embodiment of the present invention. Specifically, FIG. 10A shows a package including six zero insertion force sockets 1002, three of which are shown side by side on both sides of memory device 205, The embodiment is not limited to such a configuration. In the embodiment, each zero insertion force socket 1002 is formed of a pair of sockets 1002A and 1002B. Thus, in order to couple the corresponding portion of the zero insertion force socket to the socket 1002, the corresponding portion is connected to both sockets 1002A and 1002B as described herein.

  In an embodiment, each socket 1002A and 1002B of the zero insertion force socket 1002 includes a housing structure 1006A / 1006B and an opening 1004A / 1004B disposed within the respective housing structure 1006A / 1006B. The zero insertion force socket 1002 allows the memory device (not shown) to be removed from the changeable CPU package substrate 200. Zero insertion force socket 1002 may be electrically coupled to an electrical interface (not shown) of a memory device disposed on substrate 200 below socket 1002. A detailed view of the zero insertion force socket 1002B is shown in FIG. 10B.

  FIG. 10B shows an enlarged bottom perspective view of the zero insertion force socket 1002B. The following description relates to the socket 1002B, but this description also applies to the socket 1002A when the socket 1002A is the same as the socket 1002B or the same mirror image relationship with the socket 1002B.

  In an embodiment, the housing structure 1006B includes an opening 1004B. The opening 1004B may be located on the side of the housing structure 1006B so that the interconnect structure can be inserted laterally within the housing structure 1006B. In an embodiment, the opening 1004B is a single elongated opening that spans a portion (if not most) of the length 1009 of the socket 1002B. Alternatively, the openings 1004B may be a plurality of openings arranged over at least a part of the length 1009. A plurality of contacts 1012 may be disposed in the opening 1004B. Each contact 1012 may be disposed on the inner wall of the top and bottom surfaces of the opening 1004B so that each contact 1012 can be coupled to at least two sides of the interconnect structure. In an embodiment, the array of connectors 1010 is disposed on the side of the housing structure 1006B opposite the opening 1004. An array of connectors 1010 couples the socket 1002B to a changeable CPU package substrate 200. Specifically, the array of connectors 1010 can couple a plurality of contacts 1012 to an electrical interface (not shown) of a memory device on a changeable CPU package substrate 200.

  Referring now to FIG. 10C, a top perspective view of zero insertion force socket 1002B is shown. In an embodiment, the socket 1002B includes a locking lever 1008B. The lock lever 1008B can be in the locked position or the unlocked position by pushing the lock lever 1008 down or pulling the lock lever 1008B up, respectively, as further described herein. In the embodiment, the lock lever 1008B is a simple lever that is reversed between the locked position and the unlocked position.

  FIG. 10D shows a corresponding portion 1003 of a zero insertion force socket according to an embodiment of the present invention. In an embodiment, the zero insertion force socket counterpart 1003 includes a memory device 205 mounted on a memory device substrate 1040. In the embodiment, as shown in FIG. 10D, three memory devices 205 are mounted on the memory device substrate 1040. Although FIG. 10D shows three memory devices 205 mounted on the memory device substrate 1040, any number of memory devices 205 may be mounted on the memory device substrate 1040.

  The zero insertion force socket counterpart 1003 also includes a pair of flexible cables 1014A and 1014B. Each pair of flexible cables 1014A and 1014B can be attached to the memory device substrate 1040 at one end and have connection structures 1016A and 1016B at the other end. Connection structures 1016A and 1016B may each include an array of interconnects 1018. In an embodiment, the array of interconnects 1018 is an array of pads or a plurality of pins. As described further herein with respect to FIGS. 10E-10G, flexible cables 1014A and 1014B insert connection structures 1016A and 1016B into openings 1004 of zero insertion force socket 1002 to provide an electrical connection. It becomes possible to form.

  FIGS. 10E-10G illustrate a method of attaching the memory device 205 to a removable memory mechanical interface. Specifically, FIGS. 10E to 10G illustrate a method for attaching the corresponding portion 1003 of the zero insertion force socket to the zero insertion force socket 1002. A zero insertion force socket assembly 1005 is formed by attaching a corresponding portion 1003 of the zero insertion force socket to the zero insertion force socket 1002.

  To attach the corresponding portion 1003 of the zero insertion force socket, the connection structure 1016A can be inserted into the opening 1004A of the zero insertion force socket 1002A, as shown in FIG. 10E. The connection structure 1016A can be inserted into the opening 1004A with the lock lever 1008A in the unlock position. Accordingly, as shown in FIG. 10E, the lock lever 1008A may be in an upright position. When the lock lever 1008 is in the unlocked position, the interconnect structure can be inserted into the opening 1004A without overcoming a resistance greater than a slight frictional resistance. Once the connection structure 1016A is placed in the opening 1004A, the lock lever 1008A can be pressed into the locked position, as shown in FIG. 10F. When the lock lever 1008A is pressed, the array of contacts (eg, 1012 in FIG. 10B) disposed within the opening 1004A can then be pressed over the connection structure 1016A. Specifically, the array of contacts can be pressed over each interconnect (eg, 1018 in FIG. 10D) on the connection structure 1016A. Accordingly, in an embodiment, an electrical connection is formed between the substrate 200 and the memory device 205 via the socket 1002A and the flexible cable 1014A. The pressure applied by the array of contacts can hold the connection structure 1016A in place to prevent disconnection.

  Further, as shown in FIG. 10F, after attaching the connection structure 1016A to the socket 1002A, the connection structure 1016B can be attached to the socket 1002B to complete the attachment of the corresponding portion 1003 to the socket 1002. In an embodiment, after attaching the connection structure 1016A to the socket 1002A, the memory device substrate 1040 does not have enough space for lateral movement toward the socket 1002A. Thus, the corresponding portion 1003 utilizes the flexibility of the flexible cable 1014B. For example, the flexible cable 1014B may be bent as shown in FIG. 10F to insert the connection structure 1016B into the opening 1004B. Alternatively, instead of bending the flexible cable 1014B, the flexible cable 1014A is bent, or both the flexible cables 1014A and 1014B are bent and the connection structure 1016B is inserted into the opening 1004B. Can do. Once the connection structure 1016B is inserted, as shown in FIG. 10G, the lock lever 1008B can be pressed into the locked position to complete the attachment.

  In FIG. 10G, both connection structures 1016A and 1016B are coupled to sockets 1002A and 1002B, respectively. Accordingly, the zero insertion force socket counterpart 1003 is now attached to the zero insertion force socket 1002 to form a zero insertion force socket assembly 1005. In an embodiment, attaching the counterpart 1003 to the socket 1002 provides an electrical coupling between the memory device 205 and the changeable CPU package substrate 200. Thus, the memory device 205 can be electrically coupled to a processing device such as the processing device 203 shown in FIG. 2B. As can be seen in FIG. 10G, the memory device 205 and the memory device substrate 207 can be horizontally fitted between the sockets 1002A and 1002B.

  Although FIGS. 10E-10F illustrate a method of inserting the connection structure 1016A into the socket 1002A before inserting the connection structure 1016B into the socket 1002B, embodiments are limited to such an installation sequence. Is not to be done. In practice, any order may be used to attach the counterpart 1003 to the socket 1002. For example, the connection structure 1016B may be inserted into the socket 1002B before the connection structure 1016A is inserted into the socket 1002A.

  In an embodiment, as shown in FIG. 10H, zero insertion force socket 1002 is utilized to minimize the overall package height. FIG. 10H shows a cross-sectional view of the heat sink 1020 attached to the processing apparatus 203. The zero insertion force socket counterpart 1003 is attached to the zero insertion force socket 1002. In an embodiment, the corresponding portion 1003 and the socket 1002 are disposed completely below the heat sink 1020. Although FIG. 10H shows the heat sink 1020 directly attached to the processing apparatus 203, an intermediate structure such as a heat spreader may be disposed between the heat sink 1020 and the processing apparatus 203. The heat spreader can uniformly distribute the heat generated from the processing apparatus 203 to the entire heat sink 1020.

  The thickness 1026 of the zero insertion force socket assembly 1005 depends on the thickness of the counterpart 1003 and the socket 1002. For example, the thickness 1026 of the zero insertion force socket assembly 1005 is greater than the thickness of the corresponding portion and the thickness of the socket. In an embodiment, the thickness of the corresponding portion 1003 ranges between 1 and 1.5 millimeters. The thickness of the socket 1002 ranges between 3 and 3.5 millimeters. Thus, in such an embodiment, the thickness of the zero insertion force socket assembly 1005 is about 3 to 3.5 mm. Given the small thickness 1026, the separation gap 1024 between the heat sink 1020 and the changeable substrate 200 can be minimized. In an embodiment, the separation gap 1024 is between about 5-8 mm. By minimizing the separation gap 1024, the overall package size can be minimized as well.

  In an embodiment, the memory device 205 is held in place by a zero insertion force socket 1002. Accordingly, by lifting the lock levers 1008A and 1008B to unlock the socket 1002, the memory device 205 can be detached from the zero insertion force socket 1002 of the changeable CPU package substrate 200. The new zero insertion force counterpart 1003 containing the new memory device 205 can then be replaced with the old zero insertion force counterpart 1003 and attached to the zero insertion force socket 1002.

1.1.5 Frame Socket In addition to the socket already described herein, the removable memory mechanical interface may be a frame socket 1102 as shown in FIG. 11A. The frame socket 1102 may have a frame-shaped profile that surrounds the electrical interface 206 of the memory device. In the embodiment, the frame socket 1102 has a notch 1103 on one side of the socket 1102. The notch 1103 can expose a structure within the frame socket 1102 as further disclosed herein, whereby the structure can be accessed for removal. In the embodiment, the notch 1103 is disposed in the side surface of the frame socket 1002 near the end of the changeable CPU package substrate 200. This arrangement helps to ensure that the notch 1103 is not blocked by the processing device 203.

  In the embodiment, the frame socket 1102 allows the memory device 205 to be removed from the changeable CPU package substrate 200. Further, the frame socket 1102 allows the memory device 205 to be coupled to the electrical interface 206 of the memory device by simply placing the memory device 205 within the frame socket 1102. In an embodiment, an intermediate structure is used to easily attach the memory device 205 to the electrical interface 206 of the memory device. The intermediate structure may be any suitable interconnect structure that allows the two structures to be physically and electrically coupled to each other. For example, the intermediate structure may be a reflowable grid array (RGA) described herein in FIGS. 11B-11C below.

  11B to 11C show an RGA 1104 for attaching the memory device 205 according to the embodiment of the present invention to a changeable CPU package substrate 200. FIG. The RGA 1104 includes an RGA substrate 1107 and a first array of solder balls 1106 disposed on the top surface 1110 of the RGA substrate 1107. The RGA substrate 1107 can be formed of any suitable substrate that can withstand high heat, particularly high heat sufficient to reflow solder. In addition to the first array of solder balls 1106, a second array of solder balls 1108 can be disposed on the bottom surface 1111 of the RGA substrate 1107, as shown in FIG. 11C.

  FIG. 11C shows a cross-sectional view of RGA 1104 across line B-B ′ of FIG. 11B. A first array of solder balls 1106 can be electrically coupled to a second array of solder balls 1108 via an RGA substrate 1107. Thus, RGA 1104 can be used as an interconnect structure. As further described herein, the first and second arrays of solder balls 1106 and 1108 can be reflowed to attach the memory device 205 to the changeable substrate 200.

  In an embodiment, the RGA substrate 1107 includes a pair of internal heater grids: an upper internal heater grid 1110 and a lower internal heater grid 1112. Inner heater grids 1110 and 1112 are each formed from an array of wires composed of a conductive material such as metal. When current is passed through the array of wires, the array of wires generates heat. In an embodiment, the internal heater grids 1110 and 1112 are embedded in the RGA substrate 1107 and proximate to the upper and lower surfaces 1109 and 1111. For example, the upper internal heater grid 1110 may be placed close to the top surface 1109 and the lower internal heater grid 1112 may be placed close to the bottom surface 1111. In an embodiment, the heater grids 1110 and 1112 are arranged at a distance of between 1 and 3 mm, for example about 2 mm, away from their respective solder ball arrays. Accordingly, by bringing them close to the surface, when the heater grids generate heat, the heater grids 1110 and 1112 can reflow the array of solder balls disposed on the corresponding surfaces. Although FIG. 11C shows an RGA substrate 1107 having two heater grids 1110 and 1112, the embodiment is not limited to this. For example, the RGA substrate 1107 may have only the top internal heater grid 1110 or only the bottom internal heater grid 1112. In such embodiments, only one array of solder balls 1108/1110 may be reflowed.

  11D-11E show a bottom and top perspective view of the corresponding portion 1114 of the frame socket, respectively. In the embodiment shown in FIG. 11D, the frame socket counterpart 1114 includes a memory device substrate 1140 and an array of interconnect structures 1116 disposed on the bottom surface 1115 of the memory device substrate 1140. The memory device substrate 1140 has an edge portion 1105. The array of interconnect structures 1116 may be any suitable conductive structure, such as an array of metal pads. As shown in FIG. 11E, the array of interconnect structures 1116 may be I / O connections for the memory device 205 disposed on the top surface 1117 of the memory device substrate 1140.

  FIG. 11F shows a top perspective view of a frame socket package assembly 1120 according to an embodiment of the present invention. The frame socket package assembly is formed of a corresponding portion 1103 of the frame socket attached to the frame socket 1102. The frame socket package assembly 1120 includes a frame socket 1102 disposed on a changeable CPU package substrate 200. In an embodiment, the RGA 1104 is placed on top of the memory device electrical interface 206. As shown in FIG. 11F, the memory device electrical interface 206 may be an array of pads on the substrate 200. As will be further described, the memory device 205 and the memory device substrate 1140 may be disposed on the RGA 1104. Memory device 205 can be physically and electrically coupled to memory device substrate 1140 and then coupled to RGA 1104. Accordingly, the memory device 205 can be electrically coupled to the changeable substrate 200.

  In the embodiment, the edge portion 1105 of the memory device substrate 1140 contacts the inner surface 1123 of the frame socket 1102. In such an embodiment, the frame socket 1102 helps align the memory device substrate 1140 with the RGA 1104. In addition to the memory device substrate 1140, the RGA 1104 can also have an edge that contacts the inner surface 1123. Thus, the frame socket 1104 likewise serves to align the RGA 1104 with the electrical interface 206 of the memory device.

  The notch 1103 may be disposed within the edge of the frame socket 1102. In an embodiment, the notch 1103 is an opening formed in the side of the socket 1102 that allows access to the RGA 1104 after being attached to the electrical interface 206 of the memory device. Thus, RGA 1104 and / or memory device 205 can be removed after installation. For example, the top and / or bottom solder balls 1106/1108 can be reflowed to remove the memory device 205 from the socket 1102, and the memory device 205 can still have the solder balls 1106/1108 still in liquid form. In this case, the CPU package substrate 200 can be pulled out. In an embodiment, current flows through the top and / or bottom internal heater grids 1110/1112 and reflows the solder balls 1106/1108 while the memory device 205 is withdrawn. Thus, the RGA 1104 allows the memory device 205 to be removed after attachment. In an embodiment, a new RGA 1104 containing a new set of solder balls 1106/1108 may be used to attach a new memory device 205 to the frame socket 1102.

  FIG. 11G shows a cross-sectional view of the frame socket package assembly 1120. The cross-sectional view of FIG. 11G is from a perspective across line C-C ′ of the frame socket package assembly 1120 of FIG. 11F. In the embodiment, the memory device 205 is attached to the changeable CPU package substrate 200 by the RGA 1104. Specifically, memory device 205 is coupled to memory device substrate 1140 via an array of connections 1125. The memory device substrate 1140 is coupled to the changeable CPU package substrate 200 via the RGA 1104. The RGA 1104 can be coupled to the memory device substrate 1140 and the changeable substrate 200 by a top array of solder balls 1106 and a bottom array of solder balls 1108, respectively. In particular, the array of interconnect structures 1116 may be coupled to the top array of solder balls 1106 and the electrical interface 206 of the memory device may be coupled to the bottom array of solder balls 1108. Since the memory device 205 is coupled to the changeable CPU package substrate 200, the memory device 205 can be electrically coupled to the processing device 203 (see FIG. 11A) via the substrate 200. As previously described herein, an array of solder balls 209 can be placed under the changeable CPU package substrate 200 to couple the CPU package substrate 200 to the system substrate.

  The frame socket package assembly 1120 can be formed by at least three methods. Each of the at least three methods is illustrated in the exemplary embodiment shown in FIGS. 11H-11J.

  FIG. 11H shows a method of forming the frame socket package assembly 1120 by first attaching the RGA 1104 to the memory device substrate 1140. In an embodiment, the RGA 1104 is attached to the memory device substrate 1140 before being attached to the changeable CPU package substrate 200. For example, the RGA 1104 may be pre-attached to the memory device substrate 1140 during the manufacturing process. That is, the customer can purchase the memory device 205 with the memory device substrate 1140 and the RGA 1104 already attached. The RGA 1104 can be attached in advance by a conventional solder reflow method, for example, by processing in a solder reflow furnace. Alternatively, pre-attaching the RGA 1104 can be done by passing current through only the upper internal heater grid (not shown).

  In the embodiment, the RGA 1104 is then placed in the frame socket 1102 along with the memory device 205 and the memory device substrate 1140. The edge 1105 of the RGA 1104 can be slid relative to the inner surface 1123 of the frame socket 1102 to align the bottom array of solder balls 1108 with the memory device electrical interface 206 (eg, an array of pads). . Once the bottom solder ball 1108 is placed over the corresponding pad of the memory device electrical interface 206, the bottom solder ball 1108 can be reflowed to attach the memory device 205 to the changeable CPU package substrate 200. it can. In an embodiment, reflowing the bottom array of solder balls 1108 is performed by passing current through the bottom internal heater grid 1112 only. For example, a switch (not shown) is activated to allow current to flow through the bottom internal heater grid 1112. Thus, the RGA 1104 may have only one internal heater grid—the bottom internal heater grid 1112.

  Instead of pre-attaching the RGA 1104 to the memory device substrate 1140, the RGA 1104 may instead be pre-attached to the changeable CPU package substrate 200. FIG. 11I shows a method of forming the frame socket package assembly 1120 by first mounting the RGA 1104 on the changeable CPU package substrate 200. In an embodiment, the RGA 1104 is pre-attached to the changeable CPU package substrate 200 during the manufacturing process. For example, the customer can purchase a changeable CPU package substrate 200 with the RGA 1004 already attached to the frame socket 1102. As shown in FIG. 11I, RGA 1104 is pre-attached to memory device electrical interface 206 by a bottom array of solder balls 1108. In an embodiment, RGA 1104 is pre-attached by reflowing the bottom array of solder balls 1108. For example, the bottom array of solder balls 1108 may be reflowed in a conventional solder reflow furnace. Alternatively, pre-attaching the RGA 1104 can be done by flowing current only through a heater grid (not shown) inside the bottom.

  In order to attach the memory device 205 to the changeable CPU package substrate 200, the memory device substrate 1140 can be lowered onto the upper array of solder balls 1106. In the embodiment, the edge portion 211 of the memory device substrate 1140 slides with respect to the inner surface 1123 of the frame socket 1102. By sliding relative to the inner surface 1123, the memory device substrate 1140 can be aligned with respect to the RGA 1104. Specifically, the array of interconnect structures 1116 can be aligned with the top array of solder balls 1106. Once the interconnect structure 1116 is placed on the top array of solder balls 1106, the top array of solder balls 1106 can be reflowed to attach the memory device substrate 1140 to the RGA 1104. Accordingly, the memory device 205 can be coupled to the changeable CPU package substrate 200. In an embodiment, reflowing the upper array of solder balls 1106 is performed by passing current through only the upper internal heater grid 1110. For example, a switch (not shown) is activated to allow current to flow through the upper internal heater grid 1110. Thus, the RGA 1104 can have only one internal heater grid—the upper internal heater grid 1110.

  RGA 1104 can be attached to both substrates 1140 and 200 simultaneously, rather than pre-attaching RGA 1104 to either memory device substrate 1140 or changeable CPU package substrate 200. FIG. 11J illustrates a method of forming the frame socket package assembly 1120 by attaching the RGA 1104 to both the memory device substrate 1140 and the changeable CPU package substrate 200 simultaneously. In the embodiment, the RGA 1104 is disposed in the frame socket 1102, and the memory device substrate 1140 is disposed on the RGA 1104. Both the RGA 1104 and the memory device substrate 1140 can be aligned with each other when they are placed against the inner surface 1123 of the frame socket 1102. Once RGA 1104 and memory device board 1140 are placed in frame socket 1102, current flows through both upper and lower internal heater grids 1110 and 1112. Thus, both the top and bottom arrays of solder balls 1106 and 1108 can be reflowed to couple the memory device 205 to the changeable CPU package substrate 200. In such an embodiment, RGA 1104 may have internal heater grids 1110 and 1112 embedded therein.

  In the embodiment described above, the memory device 205 is attached to the changeable CPU package substrate 200 by the reflowed solder balls 1106/1108 of the RGA 1104. Accordingly, when the solder balls 1106/1108 are reflowed and the solder balls 1106/1108 are in liquid form, the memory device 205 can be pulled out of the socket 1102 to change the memory device 205 frame of the CPU package substrate 200. It can be removed from the socket 1102. The new memory device 205 and memory device board 1140 are then replaced with the old memory device 205 and memory device board 1140 and attached to the frame socket 1102 by the new RGA 1104.

1.2 Press-fit Set Embodiments The removable memory mechanical interface is formed as a socket in some embodiments, but in an alternative embodiment, the removable memory mechanical interface is as shown in FIG. 12A. Alternatively, it may be formed as a set of press-fitting holes. FIG. 12A shows a top perspective view of a set of press-fit holes 1202 formed in a changeable substrate 200 according to an embodiment of the present invention. By setting the press-fitting hole 1202, it becomes possible to remove the memory device from the changeable CPU package substrate 200. In the embodiment shown in FIG. 12A, the set of press-fit holes 1202 is formed by a set of four press-fit holes. The set of press-fit holes 1202 may be disposed around the memory device electrical interface 206 in the region 208 described herein with respect to FIG. 2A. In an embodiment, the memory device electrical interface 206 is an array of pads. As described further herein, press-fit holes 1202 allow corresponding pins to be inserted through these holes to attach corresponding portions of the press-fit holes to the changeable substrate 200. .

  FIG. 12B shows a bottom perspective view of the corresponding portion 1203 of the press-fit hole according to the embodiment of the present invention. In the embodiment, the corresponding portion 1203 of the press-fit hole includes the memory device 205 mounted on the top of the memory device substrate 1240. The separation frame 1208 may be disposed at the bottom of the memory device substrate 1240. The separation frame 1208 can ensure that the memory device substrate 1240 is separated from the changeable CPU package substrate 200 by a fixed distance when attached, as further described herein. In the embodiment, the separation frame 1208 may be disposed near the edge portion of the memory device substrate 1240.

  The press-fit corresponding portion 1203 may include a set of mounting pins 1206. The mounting pins 1206 may be disposed on the lower surface of the memory device substrate 1240. In the embodiment, the set of mounting pins 1206 may be arranged so as to correspond to the set of press-fitting holes 1202. Accordingly, each mounting pin 1206 can correspond to each press-fitting hole 1202. In certain embodiments, the mounting pins 1206 are located near the corners of the memory device substrate 1240. The mounting pin 1206 may also include a tapered end 1207. As further described herein, the tapered end 1207 helps guide the mounting pin 1206 into the press-fit hole 1202.

  Further, the press-fit corresponding portion 1203 may include an array of interconnect structures 1204. The array of interconnect structures 1204 can be disposed in the isolation frame 1208 at the bottom of the memory device substrate 1240. In an embodiment, the interconnect structure 1204 is a cantilever pin. Each interconnect structure of the array of interconnect structures 1204 may correspond to a pad of the memory device electrical interface 206.

  As shown in FIG. 12C, the interconnect structure 1204 may protrude below the isolation frame 1208. FIG. 12C shows a side view of the corresponding portion 1203 of the press-fitting hole. In an embodiment, the interconnect structure 1204 protrudes a distance 1210 below the bottom surface 1212 of the separation frame 1208. The distance 1210 may be any suitable distance to compensate for the difference in pad height and / or the height difference in the memory device electrical interface 206 interconnect structure. In an embodiment, the distance 1210 is about 1 mm.

  In addition to the interconnect structure 1204, the mounting pins 1206 may also protrude below the separation frame 1208. The mounting pin 1206 may protrude a certain distance 1214 below the bottom surface 1212 of the separation frame 1208. In an embodiment, the mounting pin 1206 protrudes further than the interconnect structure 1204. Accordingly, the distance 1214 may be greater than the distance 1210. Protruding the mounting pin 1206 further than the interconnect structure 1204 allows the mounting pin 1206 to be inserted into the set of press-fit holes 1202 while the interconnect structure 1204 is in contact with the electrical interface 206 of the memory device. . In an embodiment, the distance 1214 is at least 2 mm. In certain embodiments, the distance 1214 is between 2-4 mm.

  12D-12E illustrate a method of attaching memory device 205 to a removable memory mechanical interface. Specifically, FIGS. 12D to 12E show a method of attaching the corresponding portion 1203 of the press-fit hole to the set of press-fit holes 1202 according to the embodiment of the present invention.

  To attach the press-fit hole counterpart 1203, a set of mounting pins 1206 can be pushed toward the set of press-fit holes 1202, as shown in FIG. 12D. In an embodiment, the tapered end 1207 of the mounting pin 1206 helps guide the mounting pin 1206 into the press-fit hole 1202 as the corresponding portion 1203 is pushed toward the substrate 200. As the mounting pins 1206 are inserted through the press-fit holes 1202, the mounting pins 1206 align the interconnect structure 1204 with the pads of the electrical interface 206 of the memory device. In the embodiment, as shown in FIG. 12E, the mounting pin 1206 is pressed toward the press-fitting hole 1202 until the bottom surface 1212 of the separation frame 1208 contacts the changeable CPU package substrate 200. The isolation frame 1208 maintains an isolation distance between the memory device substrate 1240 and the changeable CPU package substrate 200 and prevents excessive stress on the interconnect structure 1204. Without the isolation frame 1208, the interconnect structure 1204 may be over-pressed on the substrate 200 and broken.

  As shown in FIG. 12E, the mounting pin 1206 can be substantially inserted into the set of press-fit holes 1202. Prior to installation, the interconnect structure 1204 that extends below the isolation frame 1208 does not extend below the isolation frame 1208. This is due to the compliance of the interconnect structure 1204 when the corresponding portion 1203 is pressed onto the substrate 200. As such, the interconnect structure 1204 is electrically connected to each pad of the memory device electrical interface 206. Accordingly, the memory device 205 is electrically coupled to the changeable CPU package substrate 200.

  In an embodiment, the diameter of the mounting pin 1206 above the tapered end 1207 is substantially equal to this diameter if not slightly larger than the diameter of the press-fit hole 1202. Thus, when the mounting pin 1206 is inserted into the press-fit hole 1202, the mount pin 1206 fits snugly within the press-fit hole 1202, thereby creating sufficient static friction to place the corresponding portion 1203 in place. maintain. Further, a possible heat (for example, downward force) can be applied by a heat sink (not shown) to keep the corresponding portion 1203 attached.

  In the embodiment, the memory device 205 is attached to the changeable CPU package substrate 200 by a static frictional force formed between the set of press-fitting holes 1202 and the set of attachment pins 1206. Therefore, the memory device 205 can be removed from the set of press-fitting holes 1202 of the changeable CPU package substrate 200 by pulling the corresponding portion 1203 of the press-fitting hole away from the changeable CPU package substrate 200 with a force larger than the static frictional force. Can be removed. The new press-fit counterpart 1203 containing the new memory device 205 can be replaced with the old press-fit counterpart 1203 containing the old memory device 205 and attached to the set of press-fit holes 1202.

1.3 Alignment Pin Set Embodiment In an embodiment, the set of alignment pins is placed on a changeable CPU package substrate instead of a set of press-fit holes. Accordingly, the set of alignment pins may be a removable memory mechanical interface according to an embodiment of the present invention. FIG. 13A shows a top perspective view of a set of alignment pins 1302 formed on a changeable substrate 200 according to an embodiment of the present invention. The set of alignment pins 1302 allows the memory device to be removed from the changeable CPU package substrate 200. In addition, the set of alignment pins 1302 allows for the implementation of multiple optical ports to increase I / O density.

  In the embodiment shown in FIG. 13A, the set of alignment pins 1302 is formed of two sets of alignment pins. Although two pins are shown, embodiments having more than two alignment pins are envisioned herein. The set of alignment pins 1302 may be disposed around the memory device electrical interface 206 (eg, an array of pads) in the region 208 described herein with respect to FIG. 2A. Alternatively, a set of alignment pins 1302 may be placed around the I / O array of the optical module. As described further herein, alignment pins 1302 allow corresponding press-fit holes to be fitted around the pins so that corresponding portions of the alignment pins can be attached to the changeable substrate 200. In embodiments, the alignment pins 1302 each include a tapered portion 1305 to assist in guiding the alignment pins 1302 into the press-fit holes.

  FIG. 13B is a bottom perspective view of the corresponding portion 1303 of the alignment pin according to the embodiment of the present invention. The alignment pin counterpart 1303 includes a memory device substrate 1340 and an array of interconnect structures 1306. The array of interconnect structures 1306 may be disposed on the bottom surface 1307 of the memory device substrate 1340. In the embodiment, the memory device substrate 1340 includes a set of press-fit holes 1304. The set of press-fit holes 1304 can correspond to the set of alignment pins 1302 on the changeable substrate 200 described above in this specification. Accordingly, the set of alignment pins 1302 can be inserted through the set of press-fit holes 1304 to connect the corresponding portions 1303 of the alignment pins to the changeable substrate 200.

  FIG. 13C shows a top perspective view of the alignment pin counterpart 1303. As shown, the memory device 205 may be mounted on a memory device substrate 1340. In an embodiment, interconnect structure 1306 is coupled to memory device 205 via memory device substrate 1340. In an embodiment, the press-fit hole 1305 extends through the memory device substrate 1340.

  FIG. 13D shows an intermediate structure 1308 used to interconnect the memory device 205 to the changeable CPU package substrate 200. In an embodiment, the intermediate structure forms a direct contact between both the interconnect structure 1306 and the memory device electrical interface 206. As shown in the exemplary embodiment of FIG. 13D, intermediate structure 1308 includes a flexible substrate 1316 bent into a U-shaped profile. The flexible substrate 1316 may be any suitable flexible substrate having various electrical wirings routed in or on its surface. In the embodiment, the flexible substrate 1316 is a flexible printed circuit (FPC).

  Since the flexible substrate 1316 has a U-shaped profile, the flexible substrate 1316 can thus have three different portions. For example, the flexible substrate 1316 can have an upper portion 1315 and a lower portion 1317 that are connected to each other by a bend 1319. In the embodiment, the upper portion 1315 is disposed directly above the lower portion 1317. In the embodiment, the elastic member 1318 may be disposed between the upper part and the lower part 1315, 1317. As described further herein, the elastic member 1318 allows a degree of compliance across the upper and lower portions 1315 and 1317 to compensate for non-uniform contact height.

  A set of press-fit holes 1314 may be disposed on both the upper portion 1315 and the lower portion 1317. The press-fit hole 1314 allows the intermediate structure 1308 to be aligned with both the memory device electrical interface 206 and the interconnect structure 1306 during mounting. In the embodiment, the alignment is performed when the set of alignment pins 1302 is inserted through the press-fit hole 1314.

  An array of upper interconnects 1310 may be disposed on the upper portion 1315 of the flexible substrate 1316. In an embodiment, as shown in FIG. 13E, an array of upper interconnects 1310 is disposed on the upper surface 1320 of the upper portion 1315.

  FIG. 13E shows a cross-sectional view of intermediate structure 1308 across line D-D ′ of FIG. 13D. The intermediate structure 1308 can include an array of lower interconnects 1312 as well as an array of upper interconnects 1310. In an embodiment, the array of lower interconnects 1312 is disposed on the bottom surface 1322 of the lower portion 1317. The array of top and bottom interconnects 1310 and 1312 may be any suitable interconnect structure. For example, the upper and lower interconnects 1310 and 1312 may be an array of solid copper balls. By utilizing an array of solid copper balls as interconnects 1310 and 1312, the interconnect pitch can be minimized. In an embodiment, the pitch of the top and bottom interconnects 1310 and 1312 may be less than 0.5 mm. In certain embodiments, this pitch may be about 0.3 mm or less. Thus, the memory device electrical interface 206, or any other corresponding I / O array, may have a reduced footprint. By reducing the installation area, more memory devices 205 and / or a plurality of land-side capacitors can be mounted on the memory device substrate 1340. In an embodiment, the array of upper interconnects 1310 is electrically coupled to the array of lower interconnects 1312 via flexible substrate 1316. Electrical wiring in or on the flexible substrate 1316 forms a path across the upper and lower portions 1315 and 1317 and forms a path along the bend 1319, thereby providing an upper and lower interconnect 1310 and 1312 can be interconnected.

  In an embodiment, utilizing the intermediate structure 1308 allows both the memory device electrical interface 206 and the interconnect structure 1306 to be formed as an array of pads. Thus, the memory device electrical interface 206 and interconnect structure 1306 may not protrude significantly from the changeable CPU package substrate 200 and memory device substrate 1340, respectively. Thus, the memory device electrical interface 206 and interconnect structure 1306 can withstand damage.

  FIGS. 13F to 13G show a method of attaching a memory device to a changeable CPU package substrate using alignment pins 1302. Specifically, FIGS. 13F-13G illustrate a method of attaching alignment pin counterpart 1303 to memory device electrical interface 206 using alignment pin 1302 and intermediate structure 1316.

  To attach the alignment pin counterpart 1303, the intermediate structure 1316 is first placed over the electrical interface 206 of the memory device, as shown in FIG. 13F. In an embodiment, the alignment pin 1302 is inserted into and through the press-fit hole 1314 in the upper and lower portions 1315 and 1317 of the flexible substrate 1316. The diameter of the alignment pin 1302 may be substantially equal to this diameter if it is not slightly larger than the diameter of the press-fit hole 1314. Accordingly, the intermediate structure 1316 is fixed at a predetermined position by static friction formed by the interaction between the press-fitting hole 1314 and the alignment pin 1302. In an embodiment, an array of bottom interconnects 1312 (not shown) is coupled to each pad of the memory device electrical interface 206.

  Thereafter, in FIG. 13G, the alignment pin counterpart 1303 is positioned on top of the intermediate structure 1316. In the embodiment, the alignment pin 1302 is inserted into the press-fitting hole 1304 in the memory device substrate 1340. Similar to the intermediate structure 1316, the alignment pin counterpart 1303 can be held in place by static friction between the alignment pin 1302 and the press-fit hole 1304. In an embodiment, the alignment pins 1302 help align the interconnect structure 1306 with the upper interconnect 1310. An array of interconnect structures 1306 can be coupled to each upper interconnect 1310 on the intermediate structure 1316 when alignment pin counterparts 1303 are disposed on the intermediate structure 1316. Accordingly, the memory device 205 can be electrically coupled to the changeable CPU package substrate 200.

  In an embodiment, the elastic member 1318 disposed between the upper and lower portions 1315 and 1317 allows a certain degree of vertical compliance in the top and bottom arrays of interconnects 1310 and 1312. By allowing a certain degree of vertical compliance, the elastic member 1318 helps to compensate for interconnect size anomalies in the upper and lower arrays of interconnects 1310 and 1312. In embodiments, the elastic member 1318 may be formed of any suitable elastic material. For example, the elastic member 1318 may be formed from an array of silicone slabs or linear springs. The elastic member 1318 may be formed with an appropriate thickness to allow for sufficient vertical compliance. In an embodiment, the thickness of the elastic member 1318 ranges between 1 and 3 millimeters. In certain embodiments, the elastic member 1318 is about 2 mm thick.

  If desired, an additional heat sink (not shown) can be used to apply more effective force. For example, a heat sink can apply a downward force over the alignment pin counterpart 1303 to ensure proper electrical coupling.

  In the embodiment, the memory device 205 is coupled to the changeable CPU package substrate 200 by a static friction force formed between the set of mounting pins 1302 and the set of press-fit holes 1304. Accordingly, the memory device 205 is removed from the set of mounting pins 1302 of the changeable CPU package substrate 200 by pulling the corresponding portion 1303 of the alignment pin from the changeable CPU package substrate 200 with a force larger than the static frictional force. Can do. Alternatively, if a heat sink is present, the heat sink may be removed first before withdrawing the alignment pin counterpart 1303 from the set of mounting pins 1302. The new press-fit counterpart 1303 containing the new memory device 205 is replaced with the old press-fit counterpart 1303 containing the old memory device 205 and attached to the set of alignment pins 1302.

  Although the illustrated embodiment utilizes an intermediate structure 1316 to attach the removable memory device 205, the embodiments are not limited to such applications. For example, an intermediate module 1316 may be used to attach an optical module for I / O. The optical module can benefit from a fine pitch array of upper and lower interconnects 1310 and 1312. For example, the reduction in footprint due to the fine pitch array allows additional optical modules to be coupled to the changeable CPU package substrate 200, thereby increasing device performance.

1.4 Spring Clip Embodiment In an embodiment, the removable memory mechanical interface may be formed of a spring clip, as shown in FIG. 14A. FIG. 14A shows a top perspective view of a spring-loaded clip 1402 on a modifiable substrate 200 according to an embodiment of the present invention. A spring-loaded clip 1402 can be used to attach the memory device to the changeable CPU package substrate 200. Further, the spring type clip 1402 allows the attached memory device to be removed from the changeable CPU package substrate 200. In the embodiment shown in FIG. 14A, the spring clip 1402 is formed by a top plate 1404 and a spring 1406. The upper plate 1404 includes an upper opening 1405 in which a structure such as a memory device can be adapted. The spring 1406 may be any suitable spring that generates a force to draw a portion of the top plate 1404 toward the changeable substrate 200. In the embodiment, the spring 1406 is a coil spring. The spring-loaded clip 1402 may be disposed about and over the electrical interface 206 (eg, an array of pads) of the memory device in the region 208 described herein with respect to FIG. 2A. Thus, the structure of the memory device or the like can be attached to the electrical interface 206 of the memory device by a spring-loaded clip 1402. In embodiments, the spring-loaded clip 1402 also allows the memory device to be removed.

  14B to 14C show a bottom and top perspective view of the corresponding portion 1403 of the spring clip according to the embodiment of the present invention. As shown in FIG. 14B, the spring clip counterpart 1403 is formed by the memory device substrate 1440 and the isolation frame 1410. The separation frame 1410 may be disposed on the bottom surface 1414 of the memory device substrate 1440. Further, the spring clip counterpart 1403 may include an array of interconnect structures 1412 disposed within the isolation frame 1410. The array of interconnect structures 1412 may be any suitable compliant interconnect, such as an array of cantilever pins. The cantilever pins can compensate for any non-uniform height across the memory device electrical interface 206 with a slight degree of compliance. In embodiments, as further described herein, the isolation frame 1410 prevents damage to the array of interconnect structures 1412 during installation. A pair of notches 1408 may be formed in the memory device substrate 1440. In the embodiment, the pair of cutouts 1408 extend from the edge portion of the substrate 1440 and are arranged at a constant distance 1415 in a direction away from the edge portion 1413 of the memory device substrate 1440. The notch 1408 not only helps align the corresponding portion 1403 to the changeable CPU package substrate 200, but also helps lock the corresponding portion 1403 in place when attached to the substrate 200.

  Referring briefly to FIG. 14C, the memory device 205 may be mounted on the top surface 1416 of the memory device substrate 1440. Memory device 205 may be electrically coupled to interconnect structure 1412 through memory device substrate 1440. In an embodiment, the interconnect structure 1412 protrudes below the isolation frame 1410 so that the interconnect structure 1412 can contact a corresponding pad on the isolation surface, as described herein.

  14D to 14F show a method of attaching a memory device to a changeable CPU package board using a spring-type clip 1402 according to an embodiment of the present invention. Specifically, FIGS. 14D-14F illustrate a method of attaching a spring clip counterpart 1403 to the memory device electrical interface 206 using a spring clip 1402.

  To attach the spring clip counterpart 1403, a downward force 1418 is first applied to the disengaged portion 1419 of the top plate 1404, as shown in FIG. 14D. In an embodiment, the downward force 1418 is generated with a finger, but any other object capable of applying a force may be used. When a downward force 1418 is applied, a corresponding upward force is generated at the engagement portion 1421 of the top plate 1404. An upward force 1419 lifts the engagement portion 1421 of the top plate 1404.

  Once the engagement portion 1421 is lifted, the corresponding portion 1403 of the spring clip is inserted between the engagement portion 1421 of the top plate 1404 and the changeable CPU package substrate 200 as shown in FIG. 14E. Can do. In an embodiment, the corresponding portion 1403 can be inserted until it contacts the stop projection 1422. Stop projection 1422 may be part of a changeable CPU package substrate 200 that extends vertically upward. The stop protrusion 1422 can prevent the corresponding portion 1403 from being excessively inserted into the clip 1402. In addition, the protrusions 1422 can align the corresponding portion 1403 with the electrical interface 206 of the memory device.

  After the counterpart 1403 contacts the stop projection 1422, the downward force is released 1420, thereby generating a downward clip force 1428 by the spring 1406. The engaging portion 1421 of the upper plate 1404 may be pulled toward the changeable CPU package substrate 200 by the clip force 1428. In an embodiment, the top plate 1404 may include a locking projection 1426 at the end of the engagement portion 1421. The locking protrusion 1426 can fit within a notch 1408 formed in the memory device substrate 1440. The locking protrusion 1426 cannot be inserted into the notch 1408 when the interconnect structure 1412 is offset from the electrical interface 206 of the memory device. Accordingly, the position of the corresponding portion 1403 is adjusted until the locking projection 1426 fits within the notch 1408. In the embodiment, the upper plate 1404 has two locking projections 1426, each locking projection corresponding to a respective notch shown in FIG. 14B.

  Once the counterpart 1403 is attached, a spring-loaded clip 1402 is pressed against the counterpart 1403 as shown in FIG. 14F, which then engages the interconnect structure 1412 with the electrical interface 206 of the memory device. Accordingly, an electrical connection is formed between the changeable CPU package substrate 200 and the memory device 205. In the embodiment, the opening 1405 provides clearance to the memory device 205 when the clip 1402 is closed.

  Once closed, the memory device substrate 1440 can project a predetermined distance 1415 away from the clip 1402. The protrusion allows the user to grip the substrate 1440 when the corresponding portion 1403 is attached or detached.

  In the embodiment, the memory device 205 is coupled to the changeable CPU package substrate 200 by the downward force generated by the spring 1406. Thus, by applying a downward force on the non-engaging region 1419 of the top plate 1404, the clip 1402 can be opened and the memory device 205 can be removed from the spring-loaded clip 1402 of the changeable CPU package substrate 200. . The new spring-loaded clip counterpart 1403 containing the new memory device 205 can be replaced with the old spring-loaded clip counterpart 1403 containing the old memory device 205 and attached to the spring-loaded clip 1402.

  It should be understood that the different embodiments of the removable memory mechanical interface disclosed herein generally allow the memory device to be removed from the CPU package substrate even after installation. No additional tools are required to remove the memory device. Therefore, all users such as customers can remove and / or replace the memory device on the CPU package substrate that can be changed according to the design requirements.

2.0 Computer System FIG. 15 illustrates a computer system 1500 implemented in one implementation of the present invention. The computer device 1500 accommodates the substrate 1502. The substrate 1502 can include a number of components including, but not limited to, a processor 1504 and at least one communication chip 1506. The processor 1504 is physically and electrically coupled to the substrate 1502. In some implementations, at least one communication chip 1506 is physically and electrically coupled to the substrate 1502. In a further implementation, communication chip 1506 is part of processor 1504.

  Depending on its application, computing device 1500 may include other components that may or may not be physically and electrically coupled to substrate 1502. These other components are volatile memory (eg DRAM), non-volatile memory (eg ROM), flash memory, graphic processor, digital signal processor, cryptographic processor, chipset, antenna, display, touch screen display, touch Screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (eg, hard disk drive, compact disc (CD) ), Digital versatile discs (DVD), etc.), but is not limited thereto.

  The communication chip 1506 enables wireless communication for transferring data to and from the computer device 1500. The term “wireless” and its derivatives are used to represent circuits, devices, systems, methods, technologies, communication channels, etc. that communicate data by use of electromagnetic radiation modulated over a non-solid medium. can do. The term does not mean that the associated device does not include any wires, but in some embodiments may not include wires. The communication chip 1506 includes Wi-Fi (IEEE802.11 standard), WiMAX (IEEE802.16 standard), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM (registered trademark). ), GPRS, CDMA, TDMA, DECT, Bluetooth, their derived standards, and many other wireless protocols designated as 3G, 4G, 5G and later standards, including but not limited to It can be implemented with either a wireless standard or a protocol. The computer device 1500 may include a plurality of communication chips 1506. For example, the first communication chip 1506 can be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and the second communication chip 1506 can be GPS, EDGE, GPRS, CDMA, WiMAX, LTE. , Ev-DO, and other communication standards can be dedicated to long-range wireless communication.

  The processor 1504 of the computing device 1500 includes an integrated circuit die packaged with a CPU package substrate having a removable memory mechanical interface in accordance with an implementation of the present invention. In some implementations of the invention, the integrated circuit die of the processor includes one or more semiconductor devices. The term “processor” refers to any device or device that processes electronic data from a register and / or memory to convert that electronic data that can be stored in the register and / or memory to other electronic data. Can refer to the part.

  Communication chip 1506 also includes an integrated circuit die packaged with a CPU package substrate having a removable memory mechanical interface, in accordance with an implementation of the present invention. According to another implementation of the invention, the integrated circuit die of the processor includes one or more semiconductor devices.

  In a further implementation, other components housed within the computing device 1500 may include a CPU package substrate having a removable memory mechanical interface, depending on the implementation of the present invention.

  In various implementations, the computing device 1500 can be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, It may be a monitor, set-top box, entertainment control device, digital camera, portable music player, digital video recorder. In further implementations, the computing device 1500 may be any other electronic device that processes data.

  In an embodiment, the package substrate includes a processing device interface, a memory device electrical interface disposed on the package substrate, and a removable memory mechanical interface disposed proximate to the memory device electrical interface. Including. The removable memory mechanical interface allows the memory device to be easily removed from the package substrate after the memory device is attached to the package substrate.

  The electrical interface of the memory device may include a land grid array. In an embodiment, the electrical interface of the memory device includes an array of pins. In an embodiment, the removable memory mechanical interface has electrical contacts that contact the electrical interface of the memory device, and is mated with and integrated with the removable memory mechanical interface. Has exposed electrical contacts for electrical contact to the mechanical counterpart.

  In an embodiment, the removable memory mechanical interface is a slide rail socket. A slide rail socket can include an array of angled pins, two opposing slide grooves on the socket, and a stop wall. The angled pin may be inclined toward the stop wall.

  In an embodiment, the removable memory mechanical interface is a multi-edge connector socket. The multi-edge connector socket is a first part and a second part connected at a joint, the first part extending in a direction of an offset angle from the second part, A second portion; an opening extending through the joint and extending along both the first and second portions; from one of the first and second portions in a direction half the offset angle A double edge socket including: an array of extending contacts; The first and second portions may have chamfered corners that extend in a direction parallel to the array of contacts. The multi-edge connector socket may be a full edge pin grid array socket including a frame-shaped structure and a plurality of openings on the upper surface of the structure.

  In an embodiment, the removable memory mechanical interface includes a housing structure, an array of openings in the housing structure, and an array of pins. Each pin of the array of pins may be placed in each opening in the array of openings. Each pin can have a curved contact end. In an embodiment, the first distance from the tip of the curved contact end to the equator of the curved contact end is less than the second distance from the tip of the interconnect solder ball to the equator of the interconnect solder ball. Each opening of the opening array can include an interconnect region and a pin flex region of the solder ball region, the pin flex region extending from the solder ball region.

  In an embodiment, the removable memory mechanical interface is coupled to a counterpart comprising a strip of flexible cable having two opposite ends and a memory device disposed at one of the opposite ends. Is done. The flexible cable has a connection portion at one of the opposite ends, and this connection portion fits with the electrical interface of the memory device. The flexible cable may have a second memory device on the other of the opposite ends and a connection portion between the memory devices, and the connection portion fits with an electrical interface of the memory device. . The memory device may be attached to a heat sink of the processing device connected to the processing device interface.

  In an embodiment, the removable memory mechanical interface includes a pair of sockets including openings disposed horizontally within each socket of the pair of sockets, and the memory device is horizontally adapted between the pair of sockets. To do. The socket pair may have a height that allows the socket pair and the memory device to reside under the heat sink of the processing device connected to the processing device interface.

  In an embodiment, the removable memory mechanical interface is a frame socket including an alignment frame and a land grid array, the alignment frame having a notch in one side. The frame socket can support reflow removal of the memory device from the package substrate. In an embodiment, the removable memory mechanical interface includes a set of alignment holes. In an embodiment, the removable memory mechanical interface includes a set of alignment pins. The removable memory mechanical interface may be a spring-loaded clip.

  In an embodiment, a package system is disposed proximate to a package substrate, a processing device coupled to the package substrate, an electrical interface of a memory device disposed on the package substrate, and an electrical interface of the memory device. A removable memory mechanical interface and a memory device attached to the memory device electrical interface by the removable memory mechanical interface, and the removable memory mechanical interface provides a memory device electrical interface to the memory device. It can be easily removed and reinstalled. The package system may further include a reflowable grid array disposed between the memory device electrical interface and the memory device. The memory device may be electrically coupled to a processing device on the package substrate.

  In an embodiment, a method for manufacturing a package system includes attaching a processing device to a package substrate, and connecting the memory device substrate to a mechanical interface of a removable memory disposed on the package substrate around the electrical interface of the memory device. Attaching the memory device to the package substrate by attaching.

  The memory device board can be attached by inserting the memory device board into the socket of the removable memory mechanical interface. In an embodiment, the memory device is attached by sliding the memory device substrate into the slide groove of the removable memory mechanical interface. In an embodiment, the memory device is attached by pushing the memory device substrate onto the housing structure of the removable memory mechanical interface. The housing structure has an array of openings corresponding to the array of solder balls on the memory device substrate. Each opening of the opening array can have a pin having a curved contact end disposed therein. The solder ball may contact the curved contact end at a point lower than the equator of the curved contact end.

  In an embodiment, the low insertion force connector includes a housing structure, an array of openings in the housing structure, and a pin in each opening of the array of openings, the pins having curved contact ends. Each opening of the array of openings may have an extended flexure extending from the opening.

  In an embodiment, the multi-edge connector is a substrate having at least two edge portions joined at one end, the two edge portions forming a separation angle with each other; and along the at least two edges A single connection interface extending continuously; and a plurality of pads on the connection interface, each pad of the plurality of pads extending from one of the at least two edges in the direction of half the separation angle; A plurality of pads; The multi-edge connector can include a chamfered edge portion disposed at a corner of the substrate, and the chamfered edge extends in a direction parallel to the plurality of pads.

  To utilize various aspects of the present invention, it will be apparent to those skilled in the art that combinations or variations of the above-described embodiments can form a CPU package substrate that includes a removable memory mechanical interface. Will. Although embodiments of the present invention have been described in terms specific to structural features and / or methodological operations, the invention as defined in the appended claims is not necessarily limited to the specific features or operations described. You should understand that. The specific features and acts disclosed should instead be understood as specific graceful implementations of the claimed invention useful for describing embodiments of the present invention.

Claims (25)

A package substrate, which is:
An interface of the processing device;
An electrical interface of a memory device disposed on the package substrate;
A removable memory mechanical interface disposed proximate to the electrical interface of the memory device;
After the memory device is attached to the package substrate, the removable memory mechanical interface allows the memory device to be easily removed from the package substrate.
Package substrate. The electrical interface of the memory device includes a land grid array,
The package substrate according to claim 1. The electrical interface of the memory device includes an array of pins,
The package substrate according to claim 1. The removable memory mechanical interface has electrical contacts that contact the electrical interface of the memory device, and is mated with and integrated with the removable memory mechanical interface. Having an exposed electrical contact for an electrical contact in contact with a mechanical counterpart
The package substrate according to claim 1. The mechanical interface of the removable memory is a slide rail type socket,
The package substrate according to claim 1. The slide rail socket includes an array of angled pins, slide grooves on two opposite sides of the socket, and a stop wall.
The package substrate according to claim 5. The mechanical interface of the removable memory is a multi-edge connector socket.
The package substrate according to claim 1. The multi-edge connector socket is:
A first portion and a second portion connected by a joint, wherein the first portion extends in a direction of an angle offset from the second portion; and ;
An opening extending through the junction and extending along both the first and second portions;
An array of contacts extending from one of the first and second portions in a direction half the offset angle;
A double edge socket with
The package substrate according to claim 7. The first and second portions have chamfered corners extending in a direction parallel to the array of contacts.
The package substrate according to claim 8. The multi-edge connector socket is a full edge pin grid array socket, the full edge pin grid array socket:
A frame-shaped structure;
A plurality of openings on the top surface of the structure;
The package substrate according to claim 7. The removable memory mechanical interface includes a housing structure, an array of openings in the housing structure, and an array of pins.
The package substrate according to claim 1. Each opening of the array of openings includes an interconnect region and a pin deflection region of the solder ball region, the pin deflection region extending from the solder ball region;
The package substrate according to claim 11. The removable memory mechanical interface is coupled to a counterpart comprising a strip of flexible cable having two opposite ends and a memory device located at one of the opposite ends.
The package substrate according to claim 1. The removable memory mechanical interface includes a pair of sockets, the pair of sockets having an opening disposed horizontally in the socket of the pair of sockets, and the memory device includes the pair of sockets. Fit horizontally between
The package substrate according to claim 1. The mechanical interface of the removable memory is a frame socket including an alignment frame and a land grid array, and the alignment frame has a notch on one side.
The package substrate according to claim 1. The removable memory mechanical interface includes a set of alignment holes;
The package substrate according to claim 1. The removable memory mechanical interface includes a set of alignment pins;
The package substrate according to claim 1. The mechanical interface of the removable memory is a spring-loaded clip;
The package substrate according to claim 1. A package system, which is:
A package substrate;
A processing apparatus coupled to the package substrate;
An electrical interface of a memory device disposed on the package substrate;
A removable memory mechanical interface disposed proximate to the electrical interface of the memory device;
A memory device attached to an electrical interface of the memory device by a mechanical interface of the removable memory;
The removable memory mechanical interface allows the memory device to be easily removed and replaced with respect to the electrical interface of the memory device.
Package system. A reflowable grid array disposed between the electrical interface of the memory device and the memory device;
The package system according to claim 19. The memory device is electrically coupled to the processing device on the package substrate;
The package system according to claim 19. A method for manufacturing a package system, the manufacturing method being:
Attaching the processing device to the package substrate;
Attaching the memory device to the package substrate by attaching the memory device substrate to a mechanical interface of a removable memory disposed on the package substrate around an electrical interface of the memory device;
Production method. The memory device board is attached by inserting the memory device board into a socket of a mechanical interface of the removable memory.
The manufacturing method according to claim 22. The memory device is attached by sliding the memory device substrate into a slide groove of a mechanical interface of the removable memory.
The manufacturing method according to claim 22. The memory device is mounted by pressing the memory device substrate onto a housing structure of a mechanical interface of the removable memory, the housing structure having openings corresponding to an array of solder balls on the memory device substrate. Having an array of parts,
The manufacturing method according to claim 22.

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