JP2016103610A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which achieves outputs different from each other without changing a layout.SOLUTION: A semiconductor device comprises: an active layer 2 formed on a semiconductor layer 1; a plurality of drain electrodes 4, a plurality of gate electrodes 6 and a plurality of source electrodes 7 which are connected to form a plurality of FETs. The plurality of drain electrodes 4 compose three drain bus lines 8 (8A, 8B, 8C) and the plurality of gate electrodes 6 compose three gate bus lines 9 (9A, 9B, 9C). All of the source electrodes 7 are grounded and the source electrodes 7 are provided in almost parallel with each other.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device.

  It is necessary to prepare an amplifier for an electric circuit by changing the output for each characteristic of a target circuit or element. Semiconductor devices used for amplifiers, etc., when preparing field effect transistors (hereinafter referred to as FETs) with different outputs, change the gate width of FETs, change the layout, and create FET chips It is common. However, changing the gate width of the FET to increase the variation of the FET chip has a problem that the manufacturing cost is high.

JP 2007-273918 A

  The problem to be solved by the present invention is to provide a semiconductor device capable of outputting different outputs without changing the layout.

  In order to solve the above problems, a semiconductor device according to an embodiment is electrically connected to a semiconductor layer and a first drain bus line, and has a first drain electrode provided in the semiconductor layer, and the first drain bus line. And a second drain electrode provided in the semiconductor layer substantially in parallel with the first drain electrode, and a second drain bus line, and is electrically connected to the semiconductor layer. At least one third drain electrode provided between the first drain electrode and the second drain electrode and a first gate bus line are electrically connected, and the semiconductor layer At least one first gate electrode provided between the first drain electrode and the second drain electrode and a second gate bus line are electrically connected to each other, and 1 At least one second gate electrode provided between the drain electrode and the second drain electrode, and between the first drain electrode and the second drain electrode of the semiconductor layer, And at least one source electrode.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. Sectional drawing in AA of FIG. Sectional drawing of the 2nd Embodiment of this invention. The semiconductor device which is the 3rd Embodiment of this invention. Sectional drawing of the 3rd Embodiment of this invention. Sectional drawing of the 4th Embodiment of this invention.

  Hereinafter, embodiments of a semiconductor device will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram of the first embodiment. An active layer 2 is formed on a semiconductor layer 1 made of a semiconductor, and a plurality of drain electrodes 4, a plurality of gate electrodes 6 and a plurality of source electrodes 7 are connected to the active layer 2 to form a plurality of FETs. doing.

  The plurality of drain electrodes 4 constitute three drain bus lines 8 (8A, 8B, 8C in FIG. 1). In FIG. 1, four drain electrodes 4A are connected to the drain bus line 8A, four drain electrodes 4B are connected to the drain bus line 8B, and four drain electrodes 4C are connected to the drain bus line 8C. Has been. The drain electrode 4 is a general term for the drain electrodes 4A, 4B, and 4C. These drain electrodes 4A, 4B, 4C are all called drain finger electrodes. Each drain electrode 4A, 4B, 4C is provided in the semiconductor layer 1 substantially in parallel.

  The plurality of gate electrodes 6 constitute three gate bus lines 9 (9A, 9B, 9C in FIG. 1). In FIG. 1, eight gate electrodes 6A are connected to the gate bus line 9A, eight gate electrodes 6B are connected to the gate bus line 9B, and eight gate electrodes 6C are connected to the gate bus line 9C. Has been. The gate electrode 6 is a general term for the gate electrodes 6A, 6B, and 6C. These gate electrodes 6A, 6B, and 6C are all called gate finger electrodes. Each gate electrode 6A, 6B, 6C is provided in the semiconductor layer 1 substantially in parallel.

  All the source electrodes 7 are grounded. These source electrodes 7 are called source finger electrodes. Each source electrode 7 is provided substantially in parallel.

  In this embodiment, the drain bus line 8 and the gate bus line 9 each have a drain electrode pad 3 and a gate electrode pad 5 for applying a voltage. The same number of drain electrode pads 3 as the drain bus lines 8 are provided. In this embodiment, a drain electrode pad 3A, a drain electrode pad 3B, and a drain electrode pad 3C are provided as shown in FIG. A drain bus line 8A is connected to the drain electrode pad 3A, a drain bus line 8B is connected to the drain electrode pad 3B, and a drain bus line 8C is connected to the drain electrode pad 3C.

  The same number of gate electrode pads 5 as the gate bus lines 9 are provided. In the present embodiment, a gate electrode pad 5A, a gate electrode pad 5B, and a gate electrode pad 5C are provided side by side as shown in FIG. A gate bus line 9A is connected to the gate electrode pad 5A, a gate bus line 9B is connected to the gate electrode pad 5B, and a gate bus line 9C is connected to the gate electrode pad 5C.

  In the semiconductor device of this embodiment, the drain electrodes 4 are repeatedly arranged in the order of the drain electrodes 4A, 4B, and 4C. That is, one drain electrode 4B and one drain electrode 4C are provided between one certain drain electrode 4A and another one drain electrode 4A. Similarly, one drain electrode 4A and one drain electrode 4C are provided between one certain drain electrode 4B and another one drain electrode 4B. Further, one drain electrode 4A and one drain electrode 4B are provided between one certain drain electrode 4C and another one drain electrode 4C.

  In the semiconductor device of this embodiment, the gate electrodes 6 are repeatedly arranged as a pair of two in the order of the gate electrodes 6A, 6B, and 6C. That is, one pair of gate electrodes 6B and one pair of gate electrodes 6C are provided between a certain pair of gate electrodes 6A and another pair of gate electrodes 6A. Similarly, a pair of gate electrodes 6A and a pair of gate electrodes 6C are provided one by one between a certain pair of gate electrodes 6B and another pair of gate electrodes 6B. A pair of gate electrodes 6A and a pair of gate electrodes 6B are provided one by one between a certain pair of gate electrodes 6C and another pair of gate electrodes 6C.

  A pair of gate electrodes 6A are arranged adjacent to both sides of the drain electrode 4A. Similarly, a pair of gate electrodes 6B are arranged adjacent to both sides of the drain electrode 4B. Further, a pair of gate electrodes 6C is arranged adjacent to both sides of the drain electrode 4C. The source electrode 7 is disposed between the gate electrode 6A and the gate electrode 6B, between the gate electrode 6B and the gate electrode 6C, and between the gate electrode 6C and the gate electrode 6A.

  2 is a cross-sectional view taken along the line AA of the embodiment of the semiconductor device of FIG. The semiconductor layer 1 is laminated on the substrate 11. Thereafter, an active layer 2 in which an impurity is added to the semiconductor layer 1 (hereinafter referred to as doping) is formed in the semiconductor layer 1. A drain electrode 4, a gate electrode 6, and a source electrode 7 are connected to the semiconductor layer 1 to form an FET. Furthermore, in this embodiment, a through electrode 12 is provided to connect the source electrode 7 and the back electrode 10 provided on the back surface of the substrate 11.

  For example, a compound semiconductor such as gallium nitride (hereinafter referred to as GaN) is used for the semiconductor layer 1. A compound semiconductor is a semiconductor in which a plurality of elements are combined. Compound semiconductors include III-V semiconductors in which a group III element such as aluminum (Al) or gallium (Ga) and a group V element such as nitrogen (N) or arsenic (As) are combined. A compound semiconductor containing nitrogen (N) such as GaN is called a nitride semiconductor. This nitride semiconductor is a III-V semiconductor.

  GaN has a larger band gap than silicon (hereinafter referred to as Si) and is excellent in pressure resistance against voltage, and thus is used as a power device capable of applying a high voltage. Furthermore, since the saturation electron velocity of GaN is larger than that of Si and the electron mobility is equivalent to that of Si, it is also used as a high-frequency semiconductor device for microwaves.

  For the production of FET by GaN, GaN is crystal-grown on the substrate 11 by MOCVD (Metal Organic Chemical Vapor Deposition) method or the like, and the semiconductor layer 1 is laminated. The MOCVD method is a method for forming a thin film by depositing gasified metal or the like on the substrate 11. However, in the present embodiment, the method for stacking the semiconductor layers 1 is not limited to the MOCVD method.

  Examples of the substrate 11 include Si, silicon carbide (hereinafter referred to as SiC), and sapphire. Si is inexpensive and widely used as a material for the substrate 11. The crystal structure of GaN has a hexagonal crystal structure. The crystal lattice of SiC or sapphire also has a hexagonal crystal structure like GaN. Therefore, the substrate 11 made of SiC or sapphire has an affinity for bonding with GaN atoms as compared with Si. For this reason, in a semiconductor using GaN, SiC, sapphire, or the like is used for the substrate 11. Since SiC has higher thermal conductivity than Si, it is excellent in heat dissipation of FET.

  The active layer 2 is a layer in which impurities are added to the stacked semiconductor layer 1 to contain electrons serving as carriers in a high concentration, and the electron travels. In order to create an n-type having a high electron density, a material having more valence electrons than the elements constituting the semiconductor layer 1 is doped. In the case of GaN, impurity doping includes, for example, Si atoms.

  The plurality of drain electrodes 4, the gate electrode 6, and the source electrode 7 are attached to the semiconductor layer 1 on which the active layer 2 is formed by ohmic contact.

  In FIG. 2, the source electrode 7 is connected to the back electrode 10 located on the back surface of the substrate 11 through the through electrode 12 from the semiconductor layer 1 to the substrate 11 with the source electrode 7 of the adjacent FET.

  In FIG. 2, the gate electrode 6A is arranged on both sides of the drain electrode 4A. Further, the source electrode 7 is arranged adjacent to the outside. The gate electrode 6B is adjacent to one of the source electrodes 7 and is disposed to face the gate electrode 6A. The drain electrode 4B is disposed adjacent to the gate electrode 6B and opposed to the source electrode 7. The drain electrode 4A is connected to the drain electrode pad 3A via the drain bus line 8A. The gate electrode 6A is connected to the gate electrode pad 5A via the gate bus line 9A. The drain electrode 4B is connected to the drain electrode pad 3B via the drain bus line 8B. Gate electrode 6B is connected to gate electrode pad 5B through gate bus line 9B. As a result, an FET that is driven by applying a voltage to the drain electrode pad 3A and the gate electrode pad 5A, and an FET that is driven by applying a voltage to the drain electrode pad 3B and the gate electrode pad 5B are configured.

  1 and 2, the present embodiment is a region in which two FETs that are driven by applying a voltage to the drain electrode pad 3A and the gate electrode pad 5A are provided between the source electrode 7 and the source electrode 7 (see FIG. Hereinafter, it is referred to as a first FET region). Similarly, a region in which two FETs that are driven by applying a voltage to the drain electrode pad 3B and the gate electrode pad 5B are provided between the source electrode 7 and the source electrode 7 (hereinafter referred to as a second FET region). Called). Further, a region in which two FETs that are driven by applying a voltage to the drain electrode pad 3C and the gate electrode pad 5C are provided between the source electrode 7 and the source electrode 7 (hereinafter referred to as a third FET region). Have The semiconductor device of this embodiment has four each of these first to third FET regions, constituting a total of 24 FETs.

  Accordingly, the FET to be operated is selected by selecting the voltage application to the drain electrode pad 3A, the drain electrode pad 3B, the drain electrode pad 3C, the gate electrode pad 5A, the gate electrode pad 5B, and the gate electrode pad 5C. Is possible.

  As a result, when the semiconductor device of this embodiment is used as an amplifier, the output of the FET can be adjusted by the characteristics of the connection destination circuit and the like. For example, when it is necessary to drive only 8 of the 24 FETs of the present embodiment, the FET to be driven can be selected by applying a voltage only to the drain electrode pad 3A and the gate electrode pad 5A. . A FET to be driven may be selected by applying a voltage only to the drain electrode pad 3B and the gate electrode pad 5B. A FET to be driven may be selected by applying a voltage only to the drain electrode pad 3C and the gate electrode pad 5C.

  For example, when it is necessary to drive only 16 of the 24 FETs of the present embodiment, a voltage is applied only to the drain electrode pad 3A, the drain electrode pad 3B, the gate electrode pad 5A, and the gate electrode pad 5B. The FET to be driven can be selected. A FET to be driven may be selected by applying a voltage only to the drain electrode pad 3B, the drain electrode pad 3C, the gate electrode pad 5B, and the gate electrode pad 5C. A FET to be driven may be selected by applying a voltage only to the drain electrode pad 3A, the drain electrode pad 3C, the gate electrode pad 5A, and the gate electrode pad 5C.

  Thus, in the above example, a chip with one layout can output a plurality of outputs without creating a chip by laying out 8 FETs and 16 FETs.

  In addition, in this embodiment, driving of eight or sixteen FETs can be selected with 24 FETs, so that the area is larger than the chip size of the pattern of only eight or sixteen FETs. For this reason, the amount of heat generated inside the FET is easily dispersed, and the heat dissipation is excellent. An increase in internal temperature due to heat generation inside the FET causes a decrease in electron mobility due to an increase in lattice vibration and electron scattering, a decrease in electron velocity, and an increase in resistance due to heat. For this reason, the heat generation in the FET causes a deterioration in the characteristics of the FET. Heat generation in the FET occurs mainly under the gate electrode 6.

  In the present embodiment, the first FET region, the second FET region, and the third FET region are disposed adjacent to each other. That is, one second FET region and one third FET region are provided between one certain first FET region and another one first FET region. The areas are arranged apart from each other. Similarly, one third FET region and one first FET region are provided between one certain second FET region and another one second FET region, and the second The FET regions are arranged apart from each other. Further, one first FET region and one second FET region are provided between one certain third FET region and another one third FET region, and the third FET is provided. The areas are arranged apart from each other.

  For this reason, for example, when driving only the FETs in the first FET region is selected to drive eight FETs, the gate electrode 6A in one first FET region and the other one first FET The region is disposed away from the gate electrode 6A, and the heat source generated under the gate electrode 6A is dispersed in the semiconductor device. Also from this, this embodiment is excellent in heat dissipation.

  As a result, the effect of the present embodiment is to enable selection of driving of the FET in the semiconductor device, thereby enabling a plurality of outputs to be output from one layout pattern. Further, by fixing the chip size of the semiconductor device and disposing the gate electrodes 6 of the FETs to be driven at an interval, the heat source for heat generation is dispersed, and heat dissipation is effective.

  Although the present embodiment has three drain electrode pads 3 and three gate electrode pads 5, the number of drain electrode pads 3 and gate electrode pads 5 is not limited to this. In the present embodiment, the total number of FETs is 24, but the number of FETs is not limited to this.

  In FIG. 2, the through electrode 12 has a metal rod shape, but may have a hollow cylindrical shape. In addition, the source electrode 7 of the present embodiment is connected to the back electrode 10 through the through electrode 12, but a source electrode pad may be formed on the semiconductor layer 1.

(Second Embodiment)
The plan view of the second embodiment is the same as that of the first embodiment, and the arrangement of the electrodes is the same as that of FIG. FIG. 3 is a cross-sectional view of the semiconductor device of the second embodiment, and is a cross-sectional view corresponding to the AA portion of FIG. The present embodiment is a semiconductor device in which the semiconductor layer 1 is composed of two different layers of a first compound semiconductor layer 1a and a second compound semiconductor layer 1b. The first compound semiconductor layer 1a and the second compound semiconductor layer 1b are stacked by combining those having a close lattice constant. The junction surface between the first compound semiconductor layer 1a and the second compound semiconductor layer 1b is referred to as a heterointerface.

  The first compound semiconductor layer 1a and the second compound semiconductor layer 1b have different band gaps. When the first compound semiconductor layer 1a and the second compound semiconductor layer 1b are joined, an energy level quantum well is formed in the vicinity of the heterointerface, and electrons are accumulated in the quantum well at a high density. The accumulated electrons are suppressed from moving in the substrate direction (Z direction in FIG. 3) and move only in the two-dimensional direction. This is called a two-dimensional electron gas (hereinafter referred to as 2DEG). Thus, a transistor with high electron mobility can be formed by moving high-density electrons only in the two-dimensional direction. This transistor is called a high electron mobility transistor (hereinafter referred to as HEMT). In the present embodiment, the FET structure of the first embodiment is a HEMT.

  Examples of the first compound semiconductor layer 1a include AlGaN containing group III elements Al and Ga, and group V element N. The second compound grain semiconductor layer 1b includes, for example, GaN. The first compound semiconductor layer 1a is called an electron supply layer that supplies electrons to the 2DEG. The second compound semiconductor layer 1b has 2 DEG and is called an electron transit layer because electrons travel. The active layer 2 becomes the first compound semiconductor layer 1a and the second compound semiconductor layer 1b. Further, in the HEMT structure, doping of impurities is performed on the first semiconductor layer 1a and the second semiconductor layer 1b below the drain electrode 4 and the source electrode 7. As a result, electrons can be supplied to the 2DEG.

  In the present embodiment, the arrangement of the electrodes and the arrangement of the electrode pads are the same as in the first embodiment. Therefore, in this embodiment, as shown in FIG. 3, two HEMTs that are driven by applying a voltage to the drain electrode pad 3A and the gate electrode pad 5A are provided between the source electrode 7 and the source electrode 7 (hereinafter, referred to as the following). , Referred to as a first HEMT region). Similarly, a region in which two HEMTs that are driven by applying a voltage to the drain electrode pad 3B and the gate electrode pad 5B are provided between the source electrode 7 and the source electrode 7 (hereinafter referred to as a second HEMT region). Called). Further, a region in which two HEMTs are provided between the source electrode 7 and the source electrode 7 to be driven by applying a voltage to the drain electrode pad 3C and the gate electrode pad 5C (hereinafter referred to as a third HEMT region). Have

  The semiconductor device of this embodiment has four each of these first to third HEMT regions, and constitutes a total of 24 HEMTs. When driving 8 or 16 HEMTs, the drain electrode pad 3A, the gate electrode pad 5A, the drain electrode pad 3B, the gate electrode pad 5B, the drain electrode pad 3C, and the gate electrode pad 5C are the same as in the first embodiment. Of these combinations, 1 or 2 may be selected.

  Accordingly, the HEMT to be operated is selected by selecting the voltage application to the drain electrode pad 3A, the drain electrode pad 3B, the drain electrode pad 3C, the gate electrode pad 5A, the gate electrode pad 5B, and the gate electrode pad 5C. Is possible. When the semiconductor device of this embodiment is used as an amplifier, the output of the HEMT can be adjusted according to the characteristics of the circuit to which it is connected.

  Moreover, also in heat dissipation, it has the same effect as 1st Embodiment. That is, since the driving of 8 or 16 HEMTs can be selected with 24 HEMTs, the area is larger than the chip size of only 8 or 16 HEMT patterns. For this reason, the amount of heat generated inside the FET is easily dispersed, and the heat dissipation is excellent.

  In the present embodiment, the first HEMT region, the second HEMT region, and the third HEMT region are arranged adjacent to each other. That is, one second HEMT region and one third HEMT region are provided between one certain first HEMT region and another one first HEMT region, and the first HEMT is provided. The areas are arranged apart from each other. Similarly, one third HEMT region and one first HEMT region are provided between one certain second HEMT region and another one second HEMT region. The HEMT regions are arranged apart from each other. Further, one first HEMT region and one second HEMT region are provided between one certain third HEMT region and another one third HEMT region, and the third HEMT is provided. The areas are arranged apart from each other. For this reason, the gate electrode 6A in one first HEMT region and the gate electrode 6A in the other second HEMT region are arranged apart from each other, and a heat source generated under the gate electrode 6A is generated in the semiconductor device. Distributed in. Also from this, this embodiment is excellent in heat dissipation.

  As a result, the effect of the present embodiment is that the driving of the HEMT in the semiconductor device can be selected, so that a plurality of outputs can be output from one layout pattern. Further, by fixing the chip size of the semiconductor device and disposing the HEMT gate electrodes 6 to be driven at an interval, the heat source for heat generation is dispersed, and heat dissipation is effective. Furthermore, since the present embodiment uses a HEMT structure, there is an effect of having characteristics of high speed and high mobility as compared with the FET structure of the first embodiment.

  Although the present embodiment has three drain electrode pads 3 and three gate electrode pads 5, the number of drain electrode pads 3 and gate electrode pads 5 is not limited to this. In this embodiment, the total number of HEMTs is 24, but the number of HEMTs is not limited to this.

  In FIG. 2, the through electrode 12 has a metal rod shape, but may have a hollow cylindrical shape. Further, although the source electrode 7 of the present embodiment is connected to the back electrode 10 through the through electrode 12, a source electrode pad may be formed on the semiconductor layer 1a.

(Third embodiment)
FIG. 4 is a diagram of the third embodiment. An active layer 2 is formed on a semiconductor layer 1 made of a semiconductor, and a plurality of drain electrodes 4, a plurality of gate electrodes 6 and a plurality of source electrodes 7 are connected to the active layer 2 to form a plurality of FETs. doing.

  The plurality of drain electrodes 4 constitute two drain bus lines 8 (8D and 8E in FIG. 4). In FIG. 4, four drain electrodes 4D are connected to the drain bus line 8D, and 16 drain electrodes 4E are connected to the drain bus line 8E. The drain electrode 4 is a general term for the drain electrodes 4D and 4E. The drain electrodes 4D and 4E are called drain finger electrodes. The drain electrodes 4D and 4E are provided on the semiconductor layer 1 substantially in parallel.

  The plurality of gate electrodes 6 constitute two gate bus lines 9 (9D and 9E in FIG. 4). Eight gate electrodes 6D are connected to the gate bus line 9D, and 32 gate electrodes 6E are connected to the gate bus line 9E. The gate electrode 6 is a general term for the gate electrodes 6D and 6E. The gate electrodes 6D and 6E are called gate finger electrodes. The gate electrodes 6D and 6E are provided in the semiconductor layer 1 substantially in parallel.

  All the source electrodes 7 are grounded. These source electrodes 7 are called source finger electrodes. Each source electrode 7 is provided on the semiconductor layer 1 substantially in parallel.

  In this embodiment, the drain bus line 8 and the gate bus line 9 each have a drain electrode pad 3 and a gate electrode pad 5 for applying a voltage. In the present embodiment, a drain electrode pad 3D and a drain electrode pad 3E are provided as shown in FIG. A drain bus line 8D is connected to the drain electrode pad 3D, and a drain bus line 8E is connected to the drain electrode pad 3E.

  In the present embodiment, a gate electrode pad 5D and a gate electrode pad 5E are provided as shown in FIG. The gate bus line 9D is connected to the gate electrode pad 5D, and the gate bus line 9E is connected to the gate electrode pad 5E.

  In the semiconductor device of this embodiment, four drain electrodes 4E are provided between one certain drain electrode 4D and another one drain electrode 4D.

  In the semiconductor device of the present embodiment, the gate electrode 6 is disposed in a pair with the gate electrode 6D, and the gate electrode 6E is disposed in a pair. Four pairs of gate electrodes 6E are provided between a certain pair of gate electrodes 6D and another pair of gate electrodes 6D.

  5 is a cross-sectional view taken along the line BB of the embodiment of the semiconductor device of FIG. The production of the semiconductor device of this embodiment is the same as that of the first embodiment. That is, the semiconductor layer 1 is stacked on the substrate 11, the active layer 2 is formed on the semiconductor layer 1, and the drain electrode 4, the gate electrode 6, and the source electrode 7 are disposed on the active layer 2. The configurations of the through electrode 12 and the back electrode 10 are the same as those in the first embodiment. For example, a compound semiconductor such as GaN is used for the semiconductor layer 1. Examples of the substrate 11 include Si, SiC, and sapphire.

  In FIG. 5, the gate electrode 6D is arranged on both sides of the drain electrode 4D. Further, the source electrode 7 is arranged adjacent to the outside. The drain electrode 4D is connected to the drain electrode pad 3D through the drain bus line 8D (see FIG. 4). The gate electrode 6D is connected to the gate electrode pad 5D through the gate bus line 9D (see FIG. 4). In this embodiment, a region in which two FETs that are driven by applying a voltage to the drain electrode pad 3D and the gate electrode pad 5D are provided between the source electrode 7 and the source electrode 7 (hereinafter referred to as a fourth FET region). Called).

  In FIG. 5, gate electrodes 6E are arranged on both sides of the drain electrode 4E. Further, the source electrode 7 is arranged adjacent to the outside. The drain electrode 4E is connected to the drain electrode pad 3E via the drain bus line 8E (see FIG. 4). The gate electrode 6E is connected to the gate electrode pad 5E through the gate bus line 9E (see FIG. 4). In the present embodiment, a region in which two FETs that are driven by applying a voltage to the drain electrode pad 3E and the gate electrode pad 5E are provided between the source electrode 7 and the source electrode 7 (hereinafter referred to as a fifth FET region). Called). Four fifth FET regions are arranged adjacent to each other between one fourth FET region and the other fourth EFT region.

  The semiconductor device of this embodiment has four of these fourth FET regions and 16 of fifth FET regions, and constitutes a total of 40 FETs. Thereby, it becomes possible to select the FET to operate by selecting the voltage application to the drain electrode pad 3D, the drain electrode pad 3E, the gate electrode pad 5D, and the gate electrode pad 5E. That is, when the semiconductor device of this embodiment is used as an amplifier, the output of the FET can be adjusted according to the characteristics of the connection destination circuit or the like. For example, when it is necessary to drive only 8 of the 40 FETs of this embodiment, it is possible to select the FET to be driven by applying a voltage only to the drain electrode pad 3D and the gate electrode pad 5D. . When 32 FET outputs are required, it is possible to select a FET to be driven by applying a voltage only to the drain electrode pad 3E and the gate electrode pad 5E.

  Further, the semiconductor device of this embodiment has a larger area than the chip size of the pattern of only eight FETs, like the semiconductor device of the first embodiment. For this reason, the amount of heat generated inside the FET is easily dispersed, and the heat dissipation is excellent. Furthermore, the chip size is larger than that of the semiconductor device of the first embodiment. When outputting the output of eight FETs, the semiconductor device of this embodiment is a distance from one pair of gate electrodes 6 to be driven to another pair of gate electrodes 6 as compared with the semiconductor device of the first embodiment. Is big.

  As a result, the effect of the present embodiment is to enable the selection of the driving of the FET in the semiconductor device, thereby making it possible to output two outputs from one layout pattern. In addition, since the chip size of the semiconductor device of the first embodiment is increased, the heat source for heat generation is more dispersed than in the first embodiment, which is effective in heat dissipation.

  In the present embodiment, the number of drain electrodes 4D connected to the drain electrode pad 3D is four, and the number of drain electrodes 4E connected to the drain electrode pad 3E is sixteen. It is not limited to. The number of gate electrodes 6D connected to the gate electrode pad 5D is eight, and the number of gate electrodes 6E connected to the gate electrode pad 5E is 32. However, the number of connections is limited to this. Not. In the present embodiment, the total number of FETs is 40, but the number of FETs is not limited to this.

  In FIG. 5, the through electrode 12 has a metal rod shape, but may have a hollow cylindrical shape. In addition, the source electrode 7 of the present embodiment is connected to the back electrode 10 through the through electrode 12, but a source electrode pad may be formed on the semiconductor layer 1.

(Fourth embodiment)
The plan view of the fourth embodiment is the same as that of the third embodiment, and the electrode arrangement is the same as that of FIG. FIG. 6 is a cross-sectional view of the semiconductor device of the fourth embodiment, and is a cross-sectional view corresponding to the portion BB in FIG. The present embodiment is a semiconductor device in which the semiconductor layer 1 is composed of two different layers of a first compound semiconductor layer 1a and a second compound semiconductor layer 1b. In this embodiment, the FET structure of the third embodiment is a HEMT. In the present embodiment, the first compound semiconductor layer 1a includes, for example, AlGaN containing group III elements Al and Ga and group V element N. The second compound grain semiconductor layer 1b includes, for example, GaN. The semiconductor device of this embodiment has a 2DEG layer as in the second embodiment.

  In the present embodiment, the arrangement of the electrodes and the arrangement of the electrode pads are the same as those of the semiconductor device of the third embodiment. For this reason, in the present embodiment, as shown in FIG. 6, two HEMTs that are driven by applying a voltage to the drain electrode pad 3D and the gate electrode pad 5D between the source electrode 7 and the source electrode 7 (hereinafter referred to as the HEMT) , Referred to as a fourth HEMT region). Similarly, a region in which two HEMTs that are driven by applying a voltage to the drain electrode pad 3E and the gate electrode pad 5E are provided between the source electrode 7 and the source electrode 7 (hereinafter referred to as a fifth HEMT region). Called).

  The semiconductor device of this embodiment has four such fourth HEMT regions and sixteen fifth HEMT regions, constituting a total of 40 HEMTs. Accordingly, it is possible to select an operating HEMT by selecting voltage application to the drain electrode pad 3D, the drain electrode pad 3E, the gate electrode pad 5D, and the gate electrode pad 5E. That is, when the semiconductor device of this embodiment is used as an amplifier, the output of the HEMT can be adjusted according to the characteristics of the connection destination circuit or the like. For example, when it is necessary to drive only 8 of the 40 HEMTs of this embodiment, the HEMT to be driven can be selected by applying a voltage only to the drain electrode pad 3D and the gate electrode pad 5D. . When 32 HEMT outputs are required, a voltage can be applied only to the drain electrode pad 3E and the gate electrode pad 5E to select the HEMT to be driven.

  In addition, the semiconductor device of this embodiment has a larger area than the chip size of the pattern of only eight HEMTs, like the semiconductor device of the second embodiment. For this reason, the amount of heat generated inside the HEMT is easily dispersed, and the heat dissipation is excellent. Furthermore, the chip size is larger than that of the semiconductor device of the first embodiment. In the case of outputting eight HEMTs, the semiconductor device of the present embodiment is a distance from one pair of gate electrodes 6 to be driven to another pair of gate electrodes 6 as compared with the semiconductor device of the second embodiment. Is big.

  As a result, the effect of this embodiment is that the HEMT drive in the semiconductor device can be selected, so that two outputs can be output from one layout pattern. In addition, since the chip size of the semiconductor device of the second embodiment is increased, the heat source for heat generation is more dispersed than in the second embodiment, which is effective in heat dissipation.

  As a result, the effect of this embodiment is that the HEMT drive in the semiconductor device can be selected, so that two outputs can be output from one layout pattern. In addition, since the chip size of the semiconductor device of the second embodiment is increased, the heat source for heat generation is more dispersed than in the second embodiment, which is effective in heat dissipation. Further, the use of the HEMT structure has an effect of having characteristics of high speed and high mobility as compared with the semiconductor device of the third embodiment.

  In the present embodiment, the number of drain electrodes 4D connected to the drain electrode pad 3D is four, and the number of drain electrodes 4E connected to the drain electrode pad 3E is sixteen. It is not limited to. The number of gate electrodes 6D connected to the gate electrode pad 5D is eight, and the number of gate electrodes 6E connected to the gate electrode pad 5E is 32. However, the number of connections is limited to this. Not. In this embodiment, the total number of HEMTs is 40, but the number of HEMTs is not limited to this.

  In FIG. 6, the through electrode 12 has a metal rod shape, but may have a hollow cylindrical shape. Further, although the source electrode 7 of the present embodiment is connected to the back electrode 10 through the through electrode 12, a source electrode pad may be formed on the semiconductor layer 1a.

  In the first to fourth embodiments, the drain electrode pad 4 and the gate electrode pad 6 are opened, and the FET or HEMT may be covered with a protective film made of an insulator for the other portions. The protective film is laminated by a CVD (Chemical Vapor Deposition) method or the like after disposing an electrode on the GaN layer.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1. Semiconductor layer,
1a ... the first compound semiconductor layer,
1b ... the second compound semiconductor layer,
2. Active layer,
3, 3A, 3B, 3C, 3D, 3E... Drain electrode pad,
4, 4A, 4B, 4C, 4D, 4E ... drain electrode,
5, 5A, 5B, 5C, 5D, 5E... Gate electrode pad,
6, 6A, 6B, 6C, 6D, 6E ... gate electrodes,
7. Source electrode,
8, 8A, 8B, 8C, 8D, 8E ... drain bus lines,
9, 9A, 9B, 9C, 9D, 9E ... gate bus lines,
10 ... Back electrode,
11 ... Substrate,
12 ... Through electrode.

Claims (7)

A semiconductor layer;
A first drain electrode electrically connected to the first drain bus line and provided in the semiconductor layer;
A second drain electrode electrically connected to the first drain bus line and provided in the semiconductor layer substantially parallel to the first drain electrode;
A third drain electrode that is electrically connected to a second drain bus line and is provided between the first drain electrode and the second drain electrode of the semiconductor layer;
A first gate electrode electrically connected to a first gate bus line and provided between the first drain electrode and the second drain electrode of the semiconductor layer;
A second gate electrode that is electrically connected to a second gate bus line and is provided between the first drain electrode and the second drain electrode of the semiconductor layer;
At least one source electrode provided between the first drain electrode and the second drain electrode of the semiconductor layer;
A semiconductor device comprising: At least one fourth drain electrode provided between the first drain electrode and the second drain electrode of the semiconductor layer;
At least one third gate electrode provided between the first drain electrode and the second drain electrode of the semiconductor layer;
The semiconductor device according to claim 1, comprising: The first gate electrode is provided between the source electrode and the first drain electrode;
The semiconductor device according to claim 1, wherein the second gate electrode is provided between the source electrode and the third drain electrode.   4. The drain electrode electrically connected to at least one of the first drain bus line and the second drain bus line is provided on the semiconductor layer at equal intervals. 5. The semiconductor device according to any one of the above. The source electrode is formed from the semiconductor layer toward the substrate and includes a through electrode connected to the back electrode.
The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein the semiconductor layer includes two or more compound semiconductor layers.   The semiconductor device according to claim 1, wherein the semiconductor layer is a nitride semiconductor.

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