JP2016103067A - Circuit unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit unit which easily reads data stored in a memory device even when an information processing circuit for controlling the memory device or a power supply circuit thereof fails.SOLUTION: A control unit 15 includes: a bus switch 31 for electrically or physically disconnecting a system bus 25a connected between RAMs 23a, 23b and a CPU 21 or the like; a multipolar connector 35 which is connected to a system bus or the like (control lines CS, WE, address buses A0-Am, and data buses D0-Dn) of the RAMs 23a, 23b on the side closer to the RAMs 23a, 23b than the bus switch 31, to enable external connection of them. When a CPU 21 or the like is disconnected from the system bus 25a by the bus switch 31, to connect another control unit in normal operation to the multipolar connector 35, the RAMs 23a, 23b are controlled by the other control unit.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a circuit unit used in a device mounted on a vehicle, and relates to a circuit unit having an information processing circuit for writing data to and reading data from a memory device.

  In general, a device unit controlled by a microcomputer or the like uses a circuit unit having an information processing circuit that reads and writes data from and to a memory device such as a memory IC. As a circuit unit used in a device mounted on a vehicle, for example, there is a “non-contact IC card reader / writer” disclosed in Patent Document 1 below. The IC card reader / writer is mounted near the boarding gate of the route bus and accesses a non-contact IC card possessed by the passenger. For example, by holding a non-contact IC card held by a passenger over the communication unit, data stored in the IC card is read or data is written to the IC card. In addition, information on the IC card of the passenger who has made such access may be stored in the memory IC as log data (access log).

JP 2006-4205 A

  By the way, various mechanical vibrations such as vibrations generated when the engine is driven and vibrations received from the road surface are input to the device mounted on the vehicle. Therefore, such vibration input may lead to failure of the equipment device. In the case of a failure, it is necessary to take out the data stored in the memory IC, for example, the above-mentioned passenger access log from the failure machine, but the failure part is a microcomputer that controls the memory IC, its power supply circuit, etc. In this case, it is not easy to read the stored data from the memory IC.

  For example, it is theoretically possible to remove a memory IC from a circuit board, attach it to another circuit board, and read it with a normal microcomputer, etc., but the memory IC is directly soldered and mounted on the circuit board. If so, the memory IC may be damaged during the removal from the circuit board. In the case of an in-vehicle device, since the vehicle is often in a driving state, the vibration input as described above always occurs during operation of the device device. For this reason, the configuration in which the sub board on which only the memory IC is mounted is attached to the circuit board through the connector, and the IC socket in which the memory IC can be easily removed is attached to the circuit board, causes the occurrence of contact failure due to vibration input. Considering, it is difficult to be adopted.

  The present invention has been made to solve the above-described problems, and can easily read out data stored in a memory device even when an information processing circuit that controls the memory device, a power supply circuit thereof, or the like fails. The purpose is to provide units.

  In order to achieve the above object, a circuit unit according to claim 1 of the present invention is used in an apparatus mounted on a vehicle and has an information processing circuit for writing and reading data to and from a memory device. A circuit unit, a bus disconnection unit for electrically or physically disconnecting an address bus and a data bus connected between the memory device and the information processing circuit, and the memory device side from the bus disconnection unit And a connector portion connected to the control line of the memory device, the address bus, and the data bus to enable external connection to all of the buses and the control line.

  In the invention of the circuit unit according to claim 1, a bus disconnection unit for electrically or physically disconnecting an address bus and a data bus connected between the memory device and the information processing circuit, and a memory than the bus disconnection unit And a connector portion connected to a control line, an address bus, and a data bus of the memory device on the device side to enable external connection to all these buses and control lines. As a result, the information processing circuit connected to the address bus and the data bus is separated from these buses by the bus disconnection unit. Therefore, by connecting another information processing circuit that operates normally to the connector unit, the memory device Control by this other information processing circuit becomes possible.

  A data read unit according to claim 2 of the claim is a data read unit for reading the data from the memory device of the circuit unit according to claim 1, wherein the data read unit is When the data is read out, the connector part of the data reading unit corresponding to the connector part is electrically connected to the connector part of the circuit unit. It is connected to.

  In the invention of the data read unit according to the second aspect, the data read unit has the same configuration as the circuit unit except that it does not include a memory device. By electrically connecting the connector portion of the data read unit to the connector portion of the circuit unit, the information processing circuit of the data read unit is connected to the address bus and the data bus of the circuit unit. As a result, the memory device of the circuit unit can be controlled by the information processing circuit of the data reading unit.

  In the present invention, even if an information processing circuit, its power supply circuit, or the like is out of order, data stored in a memory device can be easily read by another information processing circuit that operates normally.

  In the present invention, a data reading unit can be easily configured by removing a memory device (or not mounting a memory device) using a unit having the same configuration as that of a circuit unit without preparing a special one. Can do.

It is a front view which shows the example of the external appearance structure of the IC card reader / writer to which the circuit unit of this invention is applied. It is a block diagram which shows the example of a circuit structure of the IC card reader / writer of this embodiment. It is a circuit diagram which shows the example of a partial structure of the control unit which comprises the IC card reader / writer of this embodiment, and shows peripheral circuits, such as CPU, ROM and RAM. It is a circuit diagram which shows the structural example of another control unit which reads the data stored in RAM of a control unit, and is equivalent to the partial circuit diagram of the control unit shown in FIG. It is a block diagram which shows the example of a connection of the said control unit and another control unit of a data reading device in the case of reading data from the control unit of an IC card reader / writer. It is a circuit which shows the other structural example of a control unit, and is equivalent to the circuit diagram shown in FIG.

  Hereinafter, an embodiment in which a circuit unit of the present invention is applied to an IC card reader / writer will be described with reference to the drawings. First, the configuration of the IC card reader / writer 10 will be described with reference to FIGS. FIG. 1 is a front view showing an example of the external configuration of the IC card reader / writer 10. FIG. 2 is a block diagram showing an example of the circuit configuration of the IC card reader / writer 10.

  As shown in FIG. 1, the IC card reader / writer 10 includes a main body case 11 having a substantially rectangular box shape. A liquid crystal display portion 27a occupying almost half of the front case portion of the main body case 11 and a read / write portion 28 located substantially at the center of the remaining portion of the front portion are provided so as to be exposed to the outside. . The read / write unit 28 incorporates a communication antenna. In addition, an LED light emitting unit 27b is provided at the back of the center of the read / write unit 28 (downward in the direction perpendicular to the paper surface of FIG. 1).

  The liquid crystal display unit 27a, the LED light emitting unit 27b, and the read / write unit 28 function by being controlled by the control unit 15 accommodated in the main body case 11. That is, as shown in FIG. 2, the main body case 11 includes a control unit (hereinafter referred to as “CPU etc.”) 21, a ROM 22 and a RAM 23 including peripheral circuits such as a CPU and an address decoder, and an address bus connecting them. A control unit 15 including a data bus and control line (hereinafter referred to as “system bus etc.”) 25, an input / output interface 26, and a communication device 29 is accommodated, and the liquid crystal display unit 27a and the like are controlled by these units. Has been.

  Specifically, the IC card reader / writer 10 is provided in the vicinity of the entrance or exit of the route bus and accesses a non-contact IC card (hereinafter referred to as “IC card”) possessed by the passenger. That is, when the passenger holds the non-contact IC card over the read / write unit 28, the read / write unit 28 performs wireless communication with the IC card, and the read / write unit 28 reads the data stored in the IC card, The read / write unit 28 writes data to the IC card. Further, the result of such information processing is displayed as characters on the liquid crystal display unit 27a, or notified by the color of light emitted from the LED light emitting unit 27b.

  When the LED emits light, the LED light emitting unit 27b transmits the irradiation light through the surface of the read / write unit 28 (the gray colored portion shown in FIG. 1). Thus, the passenger visually recognizes the emission color and determines whether or not the IC card can be read. For example, when the emission color of the LED light emitting unit 27b is green, the passenger is notified that the reading of the IC card is completed, and when the emission color is red, the passenger is notified that the reading has failed. In this embodiment, as shown in FIG. 1, for example, the irradiation light of the LED is visible to the passenger around a pictogram portion composed of an ellipse, a figure representing a radio wave surrounded by the ellipse, and a picture of a hand holding the IC card. Transparent to possible.

  The IC card reader / writer 10 stores information on the IC card of the passenger who has made such access in the RAM 23 as, for example, access log data. The CPU 21 of the control unit 15 performs such processing and processing for reading and writing the above-described IC card. That is, as shown in FIG. 2, each of these processes is realized by loading a predetermined program stored in advance in the ROM 22 into the RAM 23 and executing it by the CPU 21.

  Here, in the control unit 15, the CPU 21 and the like, the ROM 22, the RAM 23 and their peripheral connections will be described with reference to FIG. FIG. 3 is a circuit diagram illustrating a partial configuration example of the control unit 15. In FIG. 3, there is a part that is different from the notation rule of the actual circuit diagram. For example, a CPU and an address decoder and other peripheral circuits connected to the CPU are collected in one frame (reference numeral 21). The CPU 21 may correspond to an “information processing circuit” described in the claims.

  As shown in FIG. 3, the ROM 22, RAM 23a, and RAM 23b are connected to the CPU 21 and the like 21 via system buses 25a and 25a 'and a control line 25b. The RAMs 23a and 23b are the RAMs 23 described so far. For example, the SRAMs correspond to these. The RAM 23 and the RAMs 23a and 23b may correspond to “memory devices” recited in the claims.

  That is, the ROM 22 and the RAMs 23a and 23b have, as system buses 25a and 25a ', an address bus (A0 to Am) composed of (m + 1) bits and a data bus (D0 to Dn) composed of (n + 1) bits. The control line 25b is connected. The system buses 25a and 25a 'are represented by one thick line in FIG. 3, but this indicates that a plurality of connection lines are gathered. In this embodiment, (m + 1) address buses and (n + 1) data buses are included.

  Similarly, the control line 25b is a group of a plurality of connection lines. The control line 25b is mainly composed of a chip select CS control line indicating that the device has been selected and a write enable WE control line indicating write permission. In addition to these, a control line for output enable OE indicating permission of data output of the memory may be included. In FIG. 3, the overline (upper bar) written in CS and WE represents that these are low active (negative logic).

  By connecting such system buses 25a, 25a ′ and control lines 25b to the ROM 22, RAMs 23a, 23b, from the ROMs 22 and RAMs 23a, 23b of the memory addresses specified by the address data output from the CPU 21 at a predetermined timing. It is possible to read data and write data to the RAMs 23a and 23b at the memory address specified by the address data. The ROM 22 and the RAMs 23 a and 23 b are supplied with appropriate driving voltages via a power supply line 24 from a power supply unit (not shown) housed in the main body case 11.

  Further, when the RAMs 23a and 23b are volatile memories such as SRAMs, the backup data is stored so that the stored data can be maintained without loss even when the drive voltage is not supplied from the power supply line 24. A power supply 41 is connected to the power supply line 24. The backup power supply 41 is provided in the control unit 15, and its output voltage is lower than the voltage supplied from the power supply line 24 in a normal state, and is higher than the voltage necessary for the RAMs 23a and 23b to hold data. Is set to The diode 43 connected in series to the backup power supply 41 serves to prevent a current from flowing from the power supply line 24 toward the backup power supply 41. Note that “Vdd” shown in FIG. 3 represents power terminals of the CPU 21, ROM 22, RAMs 23 a and 23 b, and “GND” represents these ground terminals.

  In this embodiment, a bus switch 31 is provided between the system bus 25a and the system bus 25a ', and a multipolar connector 35 is connected to the system bus 25a' and the control line 25b. That is, the bus switch 31 is interposed so that the CPU 21 and the RAMs 23a and 23b connected via the system buses 25a and 25a 'can be disconnected. Further, the control unit 15 is provided with a multipolar connector 35 having a number of terminals equal to or greater than the total number of bus lines of the system buses 25a and 25a 'and the number of control lines 25b. The multipolar connector 35 is also connected to the power supply line 24 and the ground GND. The bus switch 31 may correspond to a “bus cutting part” described in the claims. Further, the multipolar connector 35 may correspond to a “connector portion” described in the claims.

  The bus switch 31 is an aggregate of switches that can be individually turned on / off for each of the bus lines ((m + 1) address buses and (n + 1) data buses) constituting the system buses 25a and 25a '. For example, the MOS switches corresponding to the number of connection lines can be controlled from the ON state to the OFF state almost simultaneously from the outside. In the present embodiment, the control input of the bus switch 31 is connected to a pull-up resistor (not shown) connected to Vdd and the other end of the DIP switch 33 connected to the ground GND on one end.

  In normal times, the CPU 21 and the like, ROM 22, and RAMs 23a and 23b need to be connected by system buses 25a and 25a '. Therefore, in the bus switch 31, all the switches are normally kept in the on state at the normal time. For example, the normal ON state is maintained by fixing the control input of the bus switch 31 to the H level with a pull-up resistor. On the other hand, when the CPU 21 etc. breaks down or a power supply unit (not shown) connected to the power supply line 24 breaks down, that is, when there is an abnormality, the system between the CPU 21 etc. and the RAMs 23 a, 23 b The bus switch 31 disconnects the connection between the bus 25a and the system bus 25a ′. For example, when the dip switch 33 is turned on, the control input of the bus switch 31 is connected to the ground GND. As a result, the control input of the bus switch 31 is forcibly shifted to the L level, so that each switch of the bus switch 31 that has been on until then is switched off.

  The bus switch 31 may be a multi-pole dip switch (mechanical switch) having switch circuits equal to or more than the number of bus lines constituting the system buses 25a and 25a '. Further, instead of such a bus switch 31, for example, the system bus 25a and the system bus 25a 'may be physically disconnected. Specifically, when a cut or perforation is formed in the circuit board constituting the control unit 15 and the circuit board is bent along these lines, the wiring pattern of the system bus 25a or the system bus 25a ′ is physically changed. The control unit 15 may be configured to be disconnected. Further, the wiring pattern of the system bus 25a may be cut with a sharp blade such as a knife. In these cases, the “cut”, “perforation” and “wiring pattern that can be cut with a sharp knife such as a knife” instead of the bus switch 31 correspond to the “bus cutting portion” described in the claims. It is possible.

  3 indicate that the control line 25b and the power supply line 24 are disconnected as necessary. These connection lines are fewer in number than the system buses 25a and 25a '. Therefore, without providing the bus switch 31, the operator cuts the control line 25b and the power supply line 24 with a knife or the like as necessary. As a case where it is not necessary to cut off these connection lines, for example, as will be described later, another control unit connected to the multipolar connector 35 is not affected by such connection or is expected to be difficult to receive. A case (a corresponding terminal of the CPU 21 or the like maintains a high impedance) is assumed.

  Further, by configuring the circuit board itself of the control unit 15 so as to be divided into two along cuts and perforations, the system buses 25a and 25a ′, the control line 25b, and the power supply line 24 are physically cut off. Also good. Thereby, the RAMs 23 a and 23 b can be easily separated from the CPU 21 without providing the bus switch 31 and the dip switch 33.

  As described above, in the control unit 15 shown in FIG. 3, the CPU 21 is disconnected from the system bus 25a ′ connected to the RAMs 23a and 23b by the bus switch 31 and the like. By connecting to the pole connector 35, the RAM 23 can be controlled by this separate control unit. Here, the configuration of such “another control unit” will be described with reference to FIG. 4. FIG. 4 is a circuit diagram illustrating a configuration example of another control unit 55 that reads data stored in the RAMs 23a and 23b of the control unit 15.

  As shown in FIG. 4, another control unit 55 is configured in substantially the same manner as the control unit 15. That is, the same configuration as that of the control unit 15 is adopted except that the RAMs 23a and 23b are not mounted. Note that a rectangular frame indicated by a two-dot chain line in FIG. 4 shows a virtual image of the RAM 23a and RAM 23b mounted in the control unit 15, and the RAM 23a and 23b are mounted in another control unit 55. It is not.

  The CPU 21 of the control unit 15, ROM 22, power supply line 24, system buses 25 a and 25 a ′, control line 25 b, bus switch 31, dip switch 33, multipolar connector 35, backup power supply 41 and diode 43 shown in FIG. 4, the CPU 61 of the control unit 55, the ROM 62, the power supply line 64, the system buses 65a and 65a ′, the control line 65b, the bus switch 71, the dip switch 73, the multipolar connector 75, the backup power supply 81, respectively, shown in FIG. Correspondingly, the diode 83 is similarly configured. The bus switch 71 may correspond to a “bus cutting unit” described in the claims. The multipolar connector 75 may correspond to a “connector portion” described in the claims.

  Accordingly, as shown in FIG. 5, the multipolar connector 75 of another control unit 55 is electrically connected to the multipolar connector 35 of the control unit 15 via the connection cable 90, whereby another control unit 55. Are connected to the system bus 25a (address buses A0 to Am and data buses D0 to Dn) of the control unit 15. FIG. 5 is a block diagram showing a connection example between the control unit 15 and another control unit 55 of the data reading device 50 when data is read from the control unit 15 of the IC card reader / writer 10. .

  In the control unit 15 of the IC card reader / writer 10, since the DIP switch 33 is turned on, the bus switch 31 is shifted to the OFF state, and as described above, the CPU 21 is disconnected from the system bus 25a. Yes. Therefore, when the multipolar connector 75 is connected to the multipolar connector 35 of the control unit 15 via the connection cable 90, the RAMs 23 a and 23 b of the control unit 15 are controlled by the CPU 61 of another control unit 55. It becomes possible to do.

  That is, even if the CPU 21 or the like 21 of the control unit 15 breaks down or the power supply unit connected to the power supply line 24 breaks down, the data stored in the RAM 23 (RAM 23a, 23b) of the control unit 15 (for example, The access log data of the IC card that has accessed the IC card reader / writer 10) can be read out from another control unit 55 configured as described above.

  A communication device 69 similar to the communication device 29 mounted on the control unit 15 is also provided in another control unit 55. Therefore, for example, by connecting the keyboard 91 and the display 93 to another control unit 55 via the communication device 69, the other control unit 55 is operated by these input / output devices (keyboard 91 and display 93). It is also possible to do. The command input by the keyboard 91 and the output display such as the processing result on the display 93 are processed by a terminal control program stored in advance in the ROM 62, for example. This terminal control program is also stored in the ROM 22 of the control unit 15.

  Next, another configuration example of the control unit 15 will be described with reference to FIG. FIG. 6 shows a circuit representing another configuration example of the control unit 15. This circuit diagram corresponds to the circuit diagram shown in FIG. 3, and the same reference numerals are given to substantially the same components as those in FIG. 3, and the description thereof will be omitted.

  As shown in FIG. 6, the control unit 15 ′ is different from the control unit 15 shown in FIG. 3 in the bus switch 31. That is, the control unit 15 ′ includes a switch group 32 in which the switching target by the bus switch is extended to the control line 25 b and the power supply line 24. As a result, the system bus 25a is electrically disconnected by the bus switch 32a, the control line 25b is electrically disconnected by the control line switch 32b, and the power supply line 24 is electrically disconnected by the power supply line switch 32c. Therefore, as compared with the control unit 15, it is not necessary for an operator to cut the control line 25 b and the power supply line 24 with a knife or the like as necessary. It becomes easier. The bus switch 32a may correspond to a “bus cutting part” described in the claims.

  Note that, similarly to the bus switch 31, the switch group 32 is configured so that, for example, the MOS switches for the number of connection lines can be controlled from the on state to the off state almost simultaneously from the outside. In the present embodiment, the control input of the switch group 32 is connected to a pull-up resistor (not shown) connected to Vdd and the other end of the DIP switch 33 connected to the ground GND on one end. The switch group 32 is a multi-pole dip switch (mechanical switch) having switch circuits equal to or greater than the total number of bus lines, control lines 25b and power supply lines 24 constituting the system buses 25a and 25a ′. Switch) may be used. In other words, all of the system bus 25a, the control line 25b, and the power supply line 24 may be configured to be electrically disconnected by a multipolar dip switch.

  As described above, in the control unit 15 constituting the IC card reader / writer 10 of the present embodiment, the system bus 25a (address bus A0 to Am and data bus D0 to Dn) connected between the RAM 23 and the CPU 21 or the like. Is connected to the system bus 25 of the RAM 23 (control lines CS, WE, address buses A0 to Am and data buses D0 to Dn) on the RAM 23 side of the bus switch 31. And a multipolar connector 35 that enables external connection to all of them. As a result, the CPU 21 or the like 21 connected to the system bus 25a is disconnected from the system bus 25a by the bus switch 31, so that another control unit 55 that operates normally is connected to the multipolar connector 35 via the connection cable 90. Thus, the RAM 23 can be controlled by the other control unit 55. Therefore, even if the CPU 21 or its power supply unit is out of order, the data stored in the RAM 23 can be easily read out by another control unit 55 that operates normally.

  Such another control unit 55 has the same configuration as the control unit 15 except that the RAM 23 is not provided. By electrically connecting the multipolar connector 75 of another control unit 55 to the multipolar connector 35 of the control unit 15, the CPU 61 or the like 61 of the other control unit 55 can control the system bus 25a (address bus A0) of the control unit 15. To Am and data buses D0 to Dn). As a result, the RAM 23 of the control unit 15 can be controlled by the CPU 61 of another control unit 55. Therefore, another control unit 55 can be easily configured by removing the RAM 23 (or not mounting the RAM 23) using a unit having the same configuration as the control unit 15 without preparing a special one. Further, the data stored in the RAM 23 can be easily read out by the separate control unit 55 configured as described above.

  In the above-described embodiment, the case where an SRAM of a volatile memory is used as an example of the memory device has been described. However, in addition to a volatile memory that can hold data by a backup power source such as an SRAM, an EEPROM or a flash memory Such a non-volatile memory can be used as a memory device. In other words, any nonvolatile memory that can write and read data while mounted on a circuit board and can retain data even when the power is turned off can be used for a memory device. The present invention can be applied to such a circuit unit. In that case, the backup power supply 41 connected to the power supply line 24 becomes unnecessary. Further, even if a volatile memory such as a DRAM that cannot hold stored data only by a backup power supply is used as the above-described memory device as long as it is a type of volatile memory having an auxiliary circuit such as a refresh circuit. The present invention can be applied to a circuit unit having such a volatile memory.

  In the above-described embodiment, the circuit unit of the present invention has been described as an example applied to the control unit 15 of the IC card reader / writer 10. However, data is stored in a memory device used in an apparatus mounted on a vehicle. As long as it is a circuit unit having an information processing circuit for writing and reading data, it is not limited to an IC card reader / writer. For example, an information processing circuit that constitutes a fare box with an IC card reader / writer mounted on a route bus, a drive recorder that records driving operations and travel data, a vehicle information data logger that records various control data of the vehicle, etc. The present invention can also be applied to a circuit unit having the same.

10, 10 '... IC card reader / writer (device mounted on vehicle)
11 ... Main body case 15, 15 '... Control unit (circuit unit)
21, 61... CPU (information processing device)
22, 62 ... ROM
23, 23a, 23b ... RAM (memory device)
24, 64 ... power supply line 25, 65 ... system bus, etc. (address bus, data bus, control line)
25a, 65a ... system bus (address bus, data bus)
25b, 65b ... control line 26 ... input / output interface 27a ... liquid crystal display unit 27b ... LED light emitting unit 28 ... read / write unit 29, 69 ... communication device 31, 32a, 71 ... bus switch (bus disconnection unit)
33, 73 ... DIP switch 35, 75 ... Multi-pole connector (connector part)
50 ... Data reading device 55 ... Another control unit (data reading unit)
90 ... Connection cable 91 ... Keyboard 93 ... Display

Claims (2)

A circuit unit having an information processing circuit that is used in an apparatus mounted on a vehicle and writes / reads data to / from a memory device,
A bus disconnecting unit that electrically or physically disconnects an address bus and a data bus connected between the memory device and the information processing circuit;
A connector part connected to the control line of the memory device, the address bus and the data bus on the memory device side of the bus disconnection part and enabling external connection to all of these buses and control lines;
A circuit unit comprising: A data read unit for reading the data from the memory device of the circuit unit according to claim 1,
The data read unit has the same configuration as the circuit unit except that the memory device is not provided,
When reading the data, the data reading unit is characterized in that a connector portion of the data reading unit corresponding to the connector portion is electrically connected to the connector portion of the circuit unit.