JP2016082251A - Ccd image sensor and arrangement method of pixel group of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CCD image sensor that synchronizes a charge transfer timing with a subject moving timing.SOLUTION: A CCD image sensor has a pixel clutch containing two-dimensionally arranged pixels each of which performs time-delay integration of charges generated by photoelectric conversion and vertically transfers the charges by using a vertical transfer clock, and a TDI stage number setting circuit unit for dividing and setting a predetermined TDI stage number into two stage numbers on the basis of the vertical transfer clock and a selection signal representing the connection state to a transfer electrode in the pixel clutch. The pixel clutch contains first to third pixel clutch groups in which a predetermined natural number of pixel clutches are sequentially arranged in a column direction. The second pixel clutch group is disposed on the same line as the first pixel clutch group so as to be spaced from the first pixel clutch group by only a predetermined interval. The third pixel clutch group is disposed on a line adjacent to the first and second pixel clutch groups on a column corresponding to the gap. The TDI stage number setting circuit unit is disposed to be adjacent to at least each one end in the column direction of the first to third pixel clutch groups.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a TDI (Time Delay and Integration) type CCD (Charge Coupled Device) image sensor and a method for arranging a pixel group thereof.

  Many CCD image sensors have been developed in which a large number of photodetectors are arranged in an array on a semiconductor substrate and a signal charge readout circuit or output circuit is provided on the same substrate. In remote sensing, a CCD image sensor in which photodetectors are arranged in one row is mounted on a subject such as an artificial satellite, and the surface of the ground surface is made to coincide with the traveling direction of the satellite by making the direction perpendicular to the row direction of the photodetectors. A two-dimensional image is taken. However, it is desirable to reduce the pixel pitch as much as possible in order to improve the image resolution. However, there is a problem that the incident light quantity is reduced by the reduction in the area of the photodetector and the S / N ratio is deteriorated.

  Therefore, a TDI (Time Delay and Integration) CCD image sensor has been developed as a clever means for improving the S / N ratio. The TDI system uses an FFT (full frame transfer) CCD (Charge Coupled Devices), which is a two-dimensional CCD image sensor, and improves the S / N ratio by synchronizing the charge transfer timing with the movement timing of the subject. This is a readout method for a CCD image sensor. When this method is applied to remote sensing, TDI operation can be realized by matching the charge transfer in the vertical direction with the moving speed of the satellite. For example, if an M-stage TDI operation is performed with a vertical CCD, the accumulation time is effectively M times, so that the sensitivity is improved M times and the S / N ratio is improved to √M times.

  Since the sensitivity of the TDI type CCD image sensor changes in proportion to the number of TDI stages, it is desirable that the number of TDI stages can be arbitrarily switched according to the luminance of the subject. For example, Patent Document 1 discloses a TDI type CCD image sensor capable of switching the number of TDI stages to an arbitrary number of stages.

Japanese Patent No. 4968227

  However, the CCD image sensor disclosed in Patent Document 1 cannot synchronize the timing of charge transfer with the movement timing of the subject when the direction of movement of the subject such as an artificial satellite is opposite to the direction of charge transfer. There was a problem.

  Further, in the case of a CCD image sensor having a very large number of horizontal pixels, the length of the transfer electrode formed from the polysilicon thin film becomes very large, so that the wiring resistance between both ends of the transfer electrode becomes very large. . Accordingly, since the time constant of the wiring becomes large, there is a problem that the waveform of the drive clock is distorted and normal charge transfer cannot be performed.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a CCD image sensor and a method for arranging the pixel group thereof that can synchronize the timing of charge transfer with the movement timing of a subject without increasing the time constant of wiring. It is to provide.

The CCD image sensor according to the present invention is
A plurality of pixel groups in which a plurality of pixels for two-dimensionally arranging a plurality of pixels for performing vertical transfer using a plurality of vertical transfer clocks by time-delay integrating charges generated by performing photoelectric conversion;
Based on a plurality of selection signals indicating connection states between the plurality of vertical transfer clocks and a plurality of transfer electrodes in the plurality of pixel groups, a predetermined number of TDI stages is divided into a first stage number and a second stage number. A CCD image sensor having a TDI stage number setting circuit unit to be set,
The plurality of pixel groups include first, second, and third pixel group groups each having a predetermined natural number of pixel groups continuously arranged in the column direction,
The second pixel group group is arranged to be separated from the first pixel group group by a predetermined interval in the same row as the first pixel group group.
The third pixel group group is arranged in a row adjacent to the first pixel group group and the second pixel group group in a column corresponding to the interval,
The TDI stage number setting circuit section is disposed adjacent to at least one end in the column direction of the first pixel group, the second pixel group, and the third pixel group, respectively. And

  According to the image sensor of the present invention, forward reading and backward reading can be realized by two-stage horizontal transfer, so that the charge transfer timing can be synchronized with the movement timing of the subject. Therefore, it is possible to greatly improve the mobility capability for multipoint imaging in remote sensing.

  In addition, each pixel group is arranged by moving in the row direction so that a predetermined number of pixel groups are not continuously arranged in the column direction, and the TDI stage number setting circuit unit is arranged in an area vacated by the movement. Accordingly, since the wiring length between the TDI stage number setting circuit unit and the transfer electrode can be reduced, the waveform of the vertical transfer clock due to the time constant of the wiring between the TDI stage number setting circuit unit and the transfer electrode does not occur, Normal charge transfer can be performed.

1 is a pattern layout diagram of a CCD image sensor according to a first embodiment of the present invention. FIG. 2 is an element plan view of a CCD image sensor formed by the pattern layout method of FIG. 1. FIG. 3 is a block diagram showing components of a unit cell circuit 2-1 of the vertical shift register circuit 2 of FIG. FIG. 3 is a block diagram showing components of a unit cell circuit 3-1 of the line selection circuit 3 of FIG. FIG. 5 is a time axis waveform diagram showing changes in signal level with respect to time t of vertical transfer clocks φV1, φV2, φV3, and φV4 input to the transfer electrode 6 of FIG. FIG. 3 is a time axis waveform diagram showing changes in signal levels with respect to time t of a TDI transfer stage designation signal φTS and trigger clock signals φT1, φT2 inputted to the vertical shift register circuit 2 of FIG. It is a schematic diagram which shows the state of the vertical shift register circuit 2 in each time t1-t8 of FIG. It is a pattern layout figure of the CCD image sensor which concerns on Embodiment 2 of this invention. (A) is a schematic diagram showing a pattern layout diagram of the CCD image sensor of FIG. 8, (b) is a schematic diagram of output data of the CCD image sensor of (a).

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals, and description thereof is omitted.

  Embodiment 1 FIG.

  FIG. 1 is a pattern layout diagram of a TDI type CCD image sensor according to Embodiment 1 of the present invention. Here, the TDI method is a CCD image sensor reading method, in which an object moving at a constant speed is imaged by matching the moving direction and speed with the charge transfer direction and speed of the CCD image sensor. The number of vertical pixels when the object to be moved is repeatedly subjected to time-delay integration exposure by the number of vertical pixels of the CCD image sensor is referred to as the number of TDI stages. In the following description, the vertical direction refers to the vertical direction of the pixel group 41, and the horizontal direction refers to the horizontal direction of the pixel group 41. That is, the pixel group 41 includes a plurality of pixels arranged in a two-dimensional array, the column direction of the two-dimensional array is a vertical direction, and the row direction orthogonal to the column direction is a horizontal direction. It is.

  FIG. 1 shows a part of the pattern layout of the CCD image sensor. Here, the pattern layout of the CCD image sensor includes a pixel group 41, a TDI stage number setting circuit unit 42, first and second charge storage units 44, first and second horizontal transfer units 43, And the second output circuit unit 45 as a basic component.

  In FIG. 1, a pixel group 41 is configured by two-dimensionally arranging a plurality of pixels for time-delay integration of charges generated by photoelectric conversion and vertical transfer using a plurality of vertical transfer clocks. In addition, the TDI stage number setting circuit unit 42 has a predetermined TDI stage number based on a plurality of selection signals representing connection states between a plurality of vertical transfer clocks and a plurality of transfer electrodes 6 (described later) in the plurality of pixel groups 41. Is divided into the first stage number and the second stage number.

  The first charge accumulating unit 44 accumulates the vertically transferred charge by time delay integration by the first number of stages. The second charge storage unit 44 stores the vertically transferred charge by time delay integration by the second number of stages. The first horizontal transfer unit 43 horizontally transfers the charges accumulated in the first charge accumulation unit 44 to the output circuit unit 45. The second horizontal transfer unit 43 horizontally transfers the charges accumulated in the second charge accumulation unit 44 to the output circuit unit 45. Here, the first and second charge accumulation units 44 are disposed adjacent to both ends of each pixel group 41 in the row direction, and the first and second horizontal transfer units 43 include the first and second horizontal transfer units 43, respectively. The charge storage portions 44 are disposed adjacent to both ends in the row direction.

  In FIG. 1, after the pixel groups P11 to P13 and P15 to P17 are continuously arranged in the horizontal direction in the first row, the pixel group 41 having a predetermined natural number or more is not continuously arranged in the column direction. The pixel groups P24 and P28 are moved and arranged in the row. The TDI stage number setting circuit unit 42 is arranged adjacent to one end (or both ends) of the pixel group 41 in the column direction using the area vacated by this movement. That is, the plurality of pixel groups 41 include first, second, and third pixel group groups each having a predetermined natural number of pixel groups continuously arranged in the column direction, and the second pixel group group (pixel The groups P15 to P17) are arranged so as to be separated from the first pixel group (pixel groups P11 to P13) by a predetermined distance in the same row as the first pixel group (pixel groups P11 to P13). The third pixel group group (pixel group P24) is divided into the first pixel group group (pixel groups P11 to P13) and the second pixel group group (pixel groups P15 to P17) in the column corresponding to the interval. Arranged in adjacent rows. In addition, the TDI stage number setting circuit unit 42 is disposed adjacent to the left end in the column direction of the first pixel group group, the second pixel group group, and the third pixel group group (which may be at least one end). . In FIG. 1, the TDI stage number setting circuit unit 42 is disposed adjacent to one end in the column direction of the first pixel group group to the third pixel group group. A pixel group 41 having a natural number n rows and a natural number m columns is defined as a pixel group Pnm.

  Each of the predetermined natural numbers described above is the wiring resistance of the wiring connecting between the transfer electrode for vertically transferring the signal charge accumulated in each pixel 1 by time delay integration and the TDI stage number setting circuit unit 42. And is set based on the wiring capacity. Specifically, the above-mentioned predetermined natural number is obtained when the vertical transfer clock is supplied from the TDI stage number setting circuit unit 42 to the left and right ends of each transfer electrode, and the wiring between the TDI stage number setting circuit unit 42 and the transfer electrode is set. The vertical transfer clock waveform based on the time constant is set so as not to be rounded and normal charge transfer can be performed.

  With the configuration as described above, a pixel group for one row can be configured using the pixel groups P11 to P13 and P15 to P17 in the first row and the pixel groups P24 and P28 in the second row. Further, the chip position of the CCD image sensor can be further reduced by bringing the pixel groups P24 and P28 in the second row closer to the pixel groups P11 to P13 and P15 to P17 in the first row. Further, if the TDI stage number setting circuits 42 are formed at both ends in the column direction of the first pixel group group to the third pixel group group, the TDI stage number setting circuit unit 42 can be used for the first pixel group group to the third pixel group. Compared with the case where it is arranged adjacent to one end in the column direction of the group, the rounding of the waveform of the vertical transfer clock is less likely to occur.

  A CCD image sensor formed using the pattern layout method described above will be described below.

  FIG. 2 is an element plan view of a CCD image sensor formed by the pattern layout method of FIG. The CCD image sensor of FIG. 2 includes a CCD imaging unit 100 formed of a plurality of pixel groups 41, a plurality of transfer electrodes 6 for time-delay integrating and vertically transferring signal charges accumulated in each pixel 1, A vertical transfer clock connected to the horizontal CCD circuit 5 formed by the plurality of horizontal transfer units 43 and the plurality of transfer electrodes 6 and for vertically transferring the accumulated signal charges is input to the plurality of transfer electrodes 6 respectively. A plurality of select lines SLa, SLb, SLc, SLd, a charge storage circuit 4 formed from a plurality of charge storage circuit sections 44, and a TDI stage number setting circuit 8 formed from a plurality of TDI stage number setting circuit sections 42, And an output circuit 15 formed of a plurality of output circuit units 45. The TDI stage number setting circuit 8 includes a vertical shift register circuit 2 and a line selection circuit 3. Here, the number of TDI stages of the CCD image sensor is set to eight. The number of TDI stages of the CCD image sensor is set based on a TDI transfer stage designation signal φTS that is input to the vertical shift register circuit 2 and held as a plurality of selection signals.

  In FIG. 2, the signal charges that have been time-delay integrated are transferred in the vertical transfer direction (upward and downward in the figure) toward the two horizontal CCD circuits 5, and further in each horizontal CCD circuit 5 in the horizontal transfer direction (rightward in the figure). ) And output to the two output circuits 5 respectively. Each output circuit 5 converts the input signal charge integrated with time delay into an electric signal and outputs it. The vertical transfer direction is a TDI transfer direction of signal charges. For example, when a TDI type CCD image sensor is mounted on an artificial satellite, the TDI transfer direction coincides with the traveling direction of the artificial satellite. In the first embodiment, when the traveling direction of the artificial satellite coincides with the upward vertical transfer direction, the signal charge accumulated in the upward charge accumulation circuit 4 is converted into an electric signal by the output circuit 5. (This is referred to as “forward reading”). In addition, when the advancing direction of the artificial satellite matches the vertical transfer direction, the signal charge stored in the downward charge storage circuit 4 is converted into an electrical signal by the output circuit 5 and output ( This is referred to as “reverse reading”). Here, in the CCD image pickup unit 100 configured with eight pixels (eight stages) in the vertical transfer direction, the first stage, the second stage,... The pixel 1 adjacent to the charge storage circuit 4 in the upward direction is the eighth stage, and a total of eight stages from the first stage to the eighth stage are set as TDI transfer stages.

  In FIG. 2, the TDI transfer stage designation signal φTS includes a plurality of selection signals for the CCD image sensor, and the selection signals indicate the connection states of the vertical transfer clocks φV2 and φV4 in the line selection circuit 3 of the CCD image sensor. . Here, the selection signal determines the first stage number and the second stage number obtained by dividing the TDI stage number by two.

  Here, the number of unit cell circuits 2-1 to 2-8 is the same as the value of the number of vertical pixels (the number of stages) of the CCD image pickup unit 100 constituting the CCD image sensor. In the first embodiment, the vertical shift register circuit 2 includes eight unit cell circuits 2-1 to 2-8. Further, input pins 19a and 19b for inputting the respective trigger clock signals φT1 and φT2 are connected to the unit cell circuits 2-1 to 2-8 via metal wirings 18a and 18b, respectively. The unit cell circuit 2-1 is connected to an input pin 19c, which is an input terminal for inputting the TDI transfer stage designating signal φTS, via a metal wiring 18c, so that the unit cell circuit 2-m (2 ≦ natural number m). ≦ 8) is connected in series with the unit cell circuit 2- (m−1), respectively.

  The TDI stage number setting circuit 8 is composed of a plurality of unit cell circuits 2-1 to 2-8. The TDI stage number setting circuit 8 receives a selection signal indicating the connection state of the vertical transfer clocks φV2 and φV4 in the line selection circuit 3 and corresponds to the unit cell circuit 2- Connected to the vertical shift register circuit 2 held in 1 to 2-8 and the selection lines SLb and SLd, and connects a plurality of vertical transfer clocks φV2 and φV4 to predetermined selection lines based on a plurality of selection signals. And a line selection circuit 3. Here, the connection state of the vertical transfer clocks φV2 and φV4 in the line selection circuit 3 is a connection state in which the first stage number and the second stage number are set as described above, and the line selection circuit 3 receives a plurality of selection signals. Based on this, by controlling whether or not a predetermined pair of vertical transfer clocks among a plurality of vertical transfer clocks φV1 to φV4 are replaced with each other, control is performed so as to set the first stage number and the second stage number.

  The line selection circuit 3 includes unit cell circuits 3-1 to 3-8 made up of a selection MOS transistor group. Here, the number of unit cell circuits 3-1 to 3-8 is the same as the number of vertical pixels (the number of stages) of the CCD image pickup unit 100 constituting the CCD image sensor. Further, input pins 14b and 14d for inputting the vertical transfer clocks φV2 and φV4, respectively, are connected to the unit cell circuits 3-1 to 3-8 via metal wirings 13b and 13d, respectively.

  The CCD imaging unit 100 is configured by arranging 10 pixels in a horizontal transfer direction and 8 pixels in a vertical transfer direction in a two-dimensional array on the surface of a substrate (not shown) on which a CCD image sensor is formed. . Here, the pixel 1 is indicated by a region indicated by a thick broken frame in FIG. 1, and the region indicated by the thick frame is a boundary line schematically showing a boundary between the pixels 1.

  In each pixel 1 in FIG. 2, signal charges generated by photoelectric conversion are accumulated, and the accumulated signal charges are time-delay integrated by the transfer electrode 6 and vertically transferred. Here, a four-phase drive CCD image sensor is used for signal charge transfer, and a set of four transfer electrodes 6 is arranged on the pixel 1. Here, transfer electrodes 6a, 6b, 6c, 6d made of polysilicon are sequentially arranged, and a transfer channel (not shown) is formed thereunder, and the transfer channel has a conductivity type opposite to that of the substrate (not shown). It is electrically isolated by an isolation region 7 made of an impurity region. The transfer electrodes 6a and 6c are connected to the input pins 11a and 11c via selection lines SLa and SLc, which are metal wirings, respectively. On the other hand, the transfer electrodes 6b and 6d are connected to one of the input pins 14b and 14d via selection lines SLb and SLd which are metal wirings. The line selection circuit 3 determines which one is connected. That is, the transfer electrodes 6a, 6b, 6c, and 6d are connected to the selection lines SLa, SLb, SLc, and SLd, respectively, and four-phase vertical transfer clocks φV1 to φV4 are transferred to the four transfer electrodes 6a, 6b, 6c, and 6d. The signal charge is transferred in the vertical transfer direction.

  FIG. 3 is a block diagram showing components of the unit cell circuit 2-1 of the vertical shift register circuit 2 of FIG. In FIG. 3, the unit cell circuit 2-1 includes transmission gates 21a and 21b, which are NMOS transistors, and inverters 22a and 22b. The inverter 22b, the transmission gate 21b, the inverter 22a, and the transmission gate 21a. Are connected in series. Here, the drain terminal (not shown) of the transmission gate 21a is connected to the input pin 19c via the metal wiring 18c, and the source terminal (not shown) of the transmission gate 21a is the input terminal (not shown) of the inverter 22a. Connected). Further, the gate terminal (not shown) of the transmission gate 21a is connected to the input pin 19a through the metal wiring 18a.

  In FIG. 3, the output terminal (not shown) of the inverter 22a is connected to the drain terminal (not shown) of the transmission gate 21b, and the source terminal (not shown) of the transmission gate 21b is the input terminal (not shown) of the inverter 22b. (Not shown). A gate terminal (not shown) of the transmission gate 21b is connected to the input pin 19b through the metal wiring 18b. An output terminal (not shown) of the inverter 22b is connected to the unit cell circuit 3-1 of FIG. 1 is different from the unit cell circuit 2-1 in that the drain terminal of the transmission gate 21a is connected to the output terminal of the inverter 22b. Here, the vertical shift register circuit 2 receives the TDI transfer stage designation signal φTS from the input pin 19c, and advances the unit cell circuit step by step based on the trigger clock signals φT1 and φT2. That is, data of one clock pattern of the TDI transfer stage designation signal φTS input from the input pin 19c is held in the vertical shift register circuit 2.

  FIG. 4 is a block diagram showing components of the unit cell circuit 3-1 of the line selection circuit 3 of FIG. 4, the unit cell circuit 3-1 includes a transmission gate 34a composed of one NMOS transistor 32a and one PMOS transistor 33a, one NMOS transistor 32b, and one PMOS transistor 33b. A transmission gate 34b configured, a transmission gate 34c configured by one NMOS transistor 32c and a PMOS transistor 33c, a transmission configured by one NMOS transistor 32d and one PMOS transistor 33d. Gate 34d, inverter 31a having an output terminal connected to the gate terminal of transmission gate 34a and the gate terminal of transmission gate 34b, and the gate of transmission gate 34c. It constructed an inverter 31b for gate terminal and the output terminal of the terminal and the transmission gate 34d is connected.

  In FIG. 4, one end of the transmission gate 34a and the transmission gate 34b is connected to the selection line SLb connected to the transfer electrode 6b, and the other end of the transmission gate 34a is connected to the input pin 14b via the metal wiring 13b. The other end of the transmission gate 34b is connected to the input pin 14d through the metal wiring 13d. One end of the transmission gate 34c and the transmission gate 34d is connected to the selection line SLd connected to the transfer electrode 6d, and the other end of the transmission gate 34c is connected to the input pin 14d via the metal wiring 13d. The other end of the gate 34d is connected to the input pin 14b through the metal wiring 13b.

  The input gates of the NMOS transistors 32a and 32c of the transmission gates 34a and 34c, the input gate of the PMOS transistor 33b of the transmission gate 34b, and the input gate of the NMOS transistor 32c of the transmission gate 34c are connected to the above-described FIG. To the unit cell circuit 2-1. The input gate of the NMOS transistor 32a of the transmission gate 34a, the input gate of the PMOS transistor 33d of the transmission gate 34d, and the input terminals of the inverters 31a and 31b are connected to each other.

  The operation of the CCD image sensor configured as described above will be described below. In the following description, the signal levels of the vertical transfer clock φV1 to the vertical transfer clock φV4, the selection signal included in the TDI transfer stage designation signal φTS, and the trigger clock signals φT1 and φT2 are set to the high level or the low level. Note that these signal levels may be binary signals having first or second levels other than binary signals of high level and low level.

  FIG. 5 is a time axis waveform diagram showing changes in signal level with respect to time t of vertical transfer clocks φV1, φV2, φV3, and φV4 inputted to the transfer electrode 6 of FIG. That is, it is a timing chart of vertical transfer clocks φV1, φV2, φV3, and φV4 inputted to the four-phase driving CCD image sensor of FIG.

  In FIG. 5, vertical transfer clocks φV1 to φV4 are input to transfer electrodes 6a to 6d as drive clocks for the CCD image sensor. Here, the vertical transfer clock φV1 and the vertical transfer clock φV3, and the vertical transfer clock φV2 and the vertical transfer clock φV4 are in a phase relationship that is 180 degrees out of phase with each other, and each constitutes a pair. This will be described below.

  From time t1 to time t5, when the vertical transfer clock φV1, the vertical transfer clock φV2, the vertical transfer clock φV3, and the vertical transfer clock φV4 are sequentially input to the four transfer electrodes 6a, 6b, 6c, and 6d, The charge is transferred to the charge storage circuit 4 in the downward direction. In addition, when the vertical transfer clock φV1, the vertical transfer clock φV4, the vertical transfer clock φV3, and the vertical transfer clock φV2 are sequentially input to the four transfer electrodes 6a, 6b, 6c, and 6d from time t1 to time t5. The signal charge is transferred to the charge storage circuit 4 in the upward direction. That is, in the CCD image sensor, among the vertical transfer clocks φV1, φV2, φV3, and φV4 that are input to the four transfer electrodes 6a, 6b, 6c, and 6d, for example, the vertical transfer clock φV2 and the vertical transfer clock φV4 are replaced. The direction of vertical transfer of signal charge is reversed. Therefore, it is possible to control the first stage number and the second stage number obtained by dividing the TDI stage number by two.

  The operation of the unit cell circuit 2-1 of the vertical shift register circuit 2 of FIG. 3 will be described.

  When the trigger clock signal φT1 is set to the high level, the transmission gate 21a is turned on and the output of the previous stage is input to the inverter 22a, and the output of the inverter 22a becomes the inverted output of the previous stage. When the unit cell circuit 2-1 is in the first stage, the TDI transfer stage designation signal φTS input to the input pin 19c is input to the inverter 22a instead of the output of the previous stage, and the output of the inverter 22a is the TDI transfer stage designation signal. φTS inverted output. Next, when the trigger clock signal φT1 is set to the low level, the transmission gate 21a is turned off, and the input and output of the inverter 22a are held as they are. Next, when the trigger clock signal φT2 input to the input pin 19b is set to the high level, the transmission gate 22b is turned on, the output of the inverter 22a is input to the inverter 22b, and the output of the inverter 22b becomes the inverted output of the inverter 22a. This output is transmitted to the unit cell circuit 3-1 of the line selection circuit 3 as an output signal from the unit cell circuit 2-1. Next, when the trigger clock signal φT2 is set to the low level, the transmission gate 21b is turned off, and the input and output of the inverter 22b are held as they are. Further, when the trigger clock signal φT1 is set to the high level, the series of operations so far are repeated. The operations of the unit cell circuits 2-2 to 2-8 of the vertical shift register circuit 2 are the same as those of the unit cell circuit 2-1 described above.

  As described above, in the vertical shift register circuit 2, the clock pulses of the TDI transfer stage designation signal φTS input from the input pin 19c are sequentially transmitted to the next stage one by one, and each unit cell circuit 2-1 to 2 is transmitted. The output signal from −8 is transmitted to the unit cell circuits 3-1 to 3-4 of the line selection circuit 3, respectively.

  Next, the operation of the unit cell circuit 3-1 of the line selection circuit 3 in FIG. 4 will be described.

  When the signal level of the output signal from the unit cell circuit 2-1 is high, the transmission gate 34a is turned on, the input pin 14b is connected to the selection line SLb, and the vertical transfer clock φV2 is input to the transfer electrode 6b. When the signal level of the output signal from the unit cell circuit 2-1 is low, the transmission gate 34b is turned on, the input pin 14d is connected to the selection line SLb, and the vertical transfer clock φV4 is input to the transfer electrode 6b. The

  When the signal level of the output signal from the unit cell circuit 2-1 is high, the transmission gate 34c is turned on, the input pin 14d is connected to the selection line SLd, and the vertical transfer clock φV4 is input to the transfer electrode 6d. When the signal level of the output signal from the unit cell circuit 2-1 is low, the transmission gate 34d is turned on, the input pin 14b is connected to the selection line SLd, and the vertical transfer clock φV2 is input to the transfer electrode 6d. The

  As described above, the unit cell circuits 3-1 to 3-8 of the line selection circuit 3 are vertically input to the transfer electrodes (6b, 6d) based on the signal level of the output signal from the unit cell circuit 2-1. Control is performed so that the transfer clocks (φV2, φV4) are switched. That is, the line selection circuit 3 determines the number of first stages and the number of second stages by determining whether or not to replace a predetermined pair of vertical transfer clocks among a plurality of vertical transfer clocks based on each selection signal. Control to do.

  FIG. 6 is a time axis waveform diagram showing changes in signal level with respect to time t of the TDI transfer stage designation signal φTS and the trigger clock signals φT1 and φT2 input to the vertical shift register circuit 2 of FIG. It is a schematic diagram which shows the state of the vertical shift register circuit 2 in each time t1-t8 of FIG. Here, the input TDI transfer stage designation signal φTS is a clock pulse indicating an input clock to the CCD image sensor, and FIG. 7 shows the output signal of the vertical shift register circuit 2 at time t1 to t8 in time series. Shown for each.

  6 and 7, the shift register circuit 4 is initialized at time t0. Next, at time t1, the trigger clock signals φT1 and φT2 are sequentially set to the high level while the TDI transfer stage specifying signal φTS is kept at the low level. As a result, at time t1, the signal level of the output signal from the unit cell circuit 4-1 is set to a low level. At time t2, the trigger clock signals φT1 and φT2 are sequentially set to the high level while the TDI transfer stage designation signal φTS is kept at the low level. As a result, at time t2, the signal level of the output signal from the unit cell circuit 2-1 is set to a low level, the signal level held by the unit cell circuit 2-1 advances by one step, and the unit cell circuit 2-2 The signal level of the output signal is low. At time t3, the trigger clock signals φT1 and φT2 are sequentially set to the high level while the TDI transfer stage designation signal φTS is kept at the low level. As a result, at time t3, the signal level of the output signal from the unit cell circuit 4-1 is set to a low level, the signal level held by the unit cell circuit 2-1 and the signal held by the unit cell circuit 2-2. The level low level advances by one stage, the signal level of the output signal from the unit cell circuit 2-2 becomes low level, and the signal level of the output signal from the unit cell circuit 2-3 becomes low level. The same applies to the following, and at time t8, the TDI transfer stage designation signal φTS input to the vertical shift register circuit 2 of FIG. 2 is schematically represented. In the present embodiment, the TDI transfer stage designating signal φTS controls the number of forward reading stages (first stage number) to 3 (TDI transfer stage designating signal φTS is the number of backward reading stages (second stage number). ) Is controlled to 5 stages.). Here, signal levels transmitted to the unit cell circuits 3-1 to 3-8 of the line selection circuit 3 of the CCD image sensor are illustrated. This will be briefly described below.

  When all the signals of one clock pattern of the TDI transfer stage designation signal φTS are prepared in the vertical shift register circuit 2, the signals are simultaneously given to the line selection circuit 3 of the CCD image sensor. As a result, the first stage number and the second stage number of the CCD image sensor are determined, and the imaging mode is entered.

  According to the CCD image sensor according to the above-described embodiment, forward reading and backward reading can be realized by two-stage horizontal transfer, so that the charge transfer timing can be synchronized with the movement timing of the subject. Therefore, it is possible to greatly improve the mobility capability for multipoint imaging in remote sensing.

  In addition, each pixel group is arranged by moving in the row direction so that a predetermined number of pixel groups are not continuously arranged in the column direction, and the TDI stage number setting circuit unit is arranged in an area vacated by the movement. Accordingly, since the wiring length between the TDI stage number setting circuit unit 42 and the transfer electrode can be reduced, the waveform of the vertical transfer clock due to the time constant of the wiring between the TDI stage number setting circuit unit 42 and the transfer electrode can be generated. Therefore, normal charge transfer can be performed.

  In the present embodiment described above, the number of TDI stages is set to eight. However, the present invention is not limited to this, and the number of TDI stages of the CCD image sensor may be set to an arbitrary value. Even in this case, the same effect as the present embodiment can be obtained.

Embodiment 2. FIG.
FIG. 8 is a pattern layout diagram of the CCD image sensor according to the second embodiment of the present invention. In FIG. 8, compared with the pattern layout diagram of the CCD image sensor of FIG. 1, the plurality of pixel groups 41 includes fourth, fifth and fifth pixel groups each having a predetermined natural number of pixel groups arranged continuously in the column direction. It further includes 6 pixel group groups. Here, the first pattern layout 30 includes pixel groups P11 to P13, P15 to P17, P24, and P28, and the second pattern layout 40 includes pixel groups P22, P26, P31, P33 to P35, and P37. . The first pattern layout 30 is the same as that of the CCD image sensor according to the first embodiment.

  In FIG. 8, the pixel group P11 corresponds to the pixel group P31, the pixel group P12 corresponds to the pixel group P22, the pixel group P13 corresponds to the pixel group P33, the pixel group P24 corresponds to the pixel group P34, and the pixel group P15 corresponds to the pixel group P35, the pixel group P16 corresponds to the pixel group P26, and the pixel group P17 corresponds to the pixel group P37. Here, each pixel group of the first to third pixel group groups is ½ pixel pitch in the column direction with respect to each pixel group of the fourth to sixth pixel group groups corresponding to each pixel group. It is arranged by shifting only.

  In FIG. 8, in the third row, after the pixel groups P31, P33 to P35, and P37 are arranged in the horizontal direction, the second row is arranged so that the pixel groups 41 of a predetermined natural number or more are not continuously arranged in the column direction. The pixel groups P22 and P26 are moved and arranged. The TDI stage number setting circuit unit 42 is arranged adjacent to one end (or both ends) of the pixel group 41 in the column direction using the area vacated by this movement. That is, the fifth pixel group (pixel groups P33 to P35) is adjacent to the third pixel group (pixel group P24), and is the fourth in the same row as the fourth pixel group (pixel group P31). The pixel group group (pixel group P31) is arranged so as to be separated by a predetermined distance. The sixth pixel group group (pixel group P22) is arranged in the same row as the third pixel group group (pixel group P24) in the column corresponding to the interval. In addition, the TDI stage number setting circuit unit 42 is disposed adjacent to (at least one end of) the column direction left ends of the fourth pixel group group, the fifth pixel group group, and the sixth pixel group group. . In FIG. 8, the TDI stage number setting circuit unit 42 is disposed adjacent to one end in the column direction of the fourth pixel group group to the sixth pixel group group. A pixel group 41 having a natural number n rows and a natural number m columns is defined as a pixel group Pnm.

  It should be noted that the chip size of the CCD image sensor can be made smaller by making the arrangement position of the pixel group 41 in the third row closer to the pixel group 41 in the second row. Further, if the TDI stage number setting circuits 42 are formed at both ends in the column direction of the first pixel group group to the third pixel group group, the TDI stage number setting circuit unit 42 can be used for the first pixel group group to the third pixel group. Compared with the case where the group is arranged adjacent to one end in the column direction, the rounding of the waveform of the vertical transfer clock is less likely to occur.

  FIG. 9A is a schematic diagram of a pattern layout of the CCD image sensor of FIG. 8, and FIG. 9B is a schematic diagram of output data of the CCD image sensor of FIG. 9A. 9A and 9B show the operation of the oversampling function using a pixel group when the number of TDI stages is one and the number of horizontal pixels is four.

  For example, the pixels 301 of the first pattern layout 30 are arranged at a ½ pixel pitch from the pixels 401 of the second pattern layout 40 in the column direction. Data 501 to 508 are obtained by combining the output data of the two pattern layouts 30 and 40. For example, the data 501 employs data of the pixel 301 of the first pattern layout 30. As the data 502, the data of the pixel 401 of the second pattern layout 40 is adopted. The horizontal pitch between the data 501 and the data 502 is set to ½ of the pixel pitch of the first pattern layout 30 and the second pattern layout 40 (for example, the pixel 301 and the pixel 302). Similarly, data from the first pattern layout 30 and the second pattern layout 40 are sequentially used. In this way, the output of the two pattern layouts 30 and 40 shifted by ½ pixel pitch can realize a resolution equal to or lower than the pixel pitch, and can improve the resolution (oversampling function).

  Note that the above-described operation of the oversampling function is merely an example, and it is possible to improve the resolution by performing interpolation calculation on output data of adjacent pixels or by combining various data.

  If the pattern layout according to the above embodiment is used, the output signals from the two CCD image sensors shifted by 1/2 pixel pitch are used as compared with the first embodiment, so that the resolution below the pixel pitch can be realized. (Oversampling function) can be realized.

  As described above in detail, according to the CCD image sensor according to the present invention, forward reading and backward reading can be realized by two-stage horizontal transfer, so that the charge transfer timing is synchronized with the movement timing of the subject. Can do. Therefore, it is possible to greatly improve the mobility capability for multi-point imaging by remote sensing.

  1 pixel, 2 vertical shift register circuit, 2-1 to 2-8 unit cell circuit, 3 line selection circuit, 3-1 to 3-8 unit cell circuit, 4 charge storage circuit, 5 horizontal CCD circuit, 6, 6a, 6b, 6c, 6d transfer electrode, 7 isolation region, 15 output circuit, 22a, 22b, 31a, 31b inverter, 21a, 21b transmission gate, 32a, 32b, 32c, 32d NMOS transistor, 33a, 33b, 33c, 33d PMOS transistor , 34a, 34b, 34c, 34d Transmission gate, 41 pixel group, 42 TDI stage number setting circuit section, 43 horizontal transfer section, 44 charge storage circuit section, 45 output circuit section, 100 CCD imaging section.

Claims (7)

A plurality of pixel groups in which a plurality of pixels for two-dimensionally arranging a plurality of pixels for performing vertical transfer using a plurality of vertical transfer clocks by time-delay integrating charges generated by performing photoelectric conversion;
Based on a plurality of selection signals indicating connection states between the plurality of vertical transfer clocks and a plurality of transfer electrodes in the plurality of pixel groups, a predetermined number of TDI stages is divided into a first stage number and a second stage number. A CCD image sensor having a TDI stage number setting circuit unit to be set,
The plurality of pixel groups include first, second, and third pixel group groups each having a predetermined natural number of pixel groups continuously arranged in the column direction,
The second pixel group group is arranged to be separated from the first pixel group group by a predetermined interval in the same row as the first pixel group group.
The third pixel group group is arranged in a row adjacent to the first pixel group group and the second pixel group group in a column corresponding to the interval,
The TDI stage number setting circuit section is disposed adjacent to at least one end in the column direction of the first pixel group, the second pixel group, and the third pixel group, respectively. CCD image sensor. The plurality of pixel groups further include fourth, fifth, and sixth pixel group groups each having a predetermined natural number of pixel groups continuously arranged in the column direction,
The fifth pixel group group is adjacent to the third pixel group group, and is arranged to be separated from the fourth pixel group group by a predetermined interval in the same row as the fourth pixel group group. And
The sixth pixel group group is arranged in the same row as the third pixel group group in a column corresponding to the interval,
The pixel groups of the first to third pixel group groups are each ½ pixel pitch in the column direction with respect to the pixel groups of the fourth to sixth pixel group groups corresponding to the pixel groups. The CCD image sensor according to claim 1, wherein the CCD image sensor is shifted and arranged. A plurality of selection lines respectively connected to the transfer electrodes;
The TDI stage number setting circuit section is
A line selection circuit that is connected to each of the selection lines and that connects the vertical transfer clocks to the predetermined selection lines based on the plurality of selection signals;
A vertical shift register circuit configured by a plurality of unit cell circuits and holding the plurality of selection signals representing connection states of the vertical transfer clocks in the line selection circuit in the corresponding unit cell circuits. The CCD image sensor according to claim 1 or 2. The connection state of each vertical transfer clock in the line selection circuit is a connection state for setting the first stage number and the second stage number,
The line selection circuit determines whether to replace a predetermined pair of vertical transfer clocks among the plurality of vertical transfer clocks based on the plurality of selection signals, thereby determining the first stage number and the second stage. The CCD image sensor according to claim 1, wherein the number of stages is controlled to be set. A first charge accumulator for accumulating the vertically transferred charge by time delay integration for the first stage number; and a second charge for accumulating the vertically transferred charge by time delay integration for the second stage number. An accumulation unit, a first horizontal transfer unit that horizontally transfers charges accumulated in the first charge accumulation unit, and a second horizontal transfer unit that horizontally transfers charges accumulated in the second charge accumulation unit And further comprising
The first and second charge storage units are respectively disposed adjacent to both ends of each pixel group in the row direction,
The first and second horizontal transfer units are respectively disposed adjacent to one ends of the first and second charge storage units in the row direction, respectively. The CCD image sensor according to any one of the above. A plurality of pixel groups in which a plurality of pixels for two-dimensionally arranging a plurality of pixels for performing vertical transfer using a plurality of vertical transfer clocks by time-delay integrating charges generated by performing photoelectric conversion;
Based on a plurality of selection signals indicating connection states between the plurality of vertical transfer clocks and a plurality of transfer electrodes in the plurality of pixel groups, a predetermined number of TDI stages is divided into a first stage number and a second stage number. A method for arranging a pixel group of a CCD image sensor having a TDI stage number setting circuit unit to be set,
The plurality of pixel groups include first, second, and third pixel group groups each having a predetermined natural number of pixel groups continuously arranged in the column direction,
The above method
Disposing the second pixel group group so as to be separated from the first pixel group group by a predetermined distance in the same row as the first pixel group group;
Disposing the third pixel group group in a row adjacent to the first pixel group group and the second pixel group group in a column corresponding to the interval;
Disposing the TDI stage number setting circuit section adjacent to at least one end in the column direction of the first pixel group group, the second pixel group group, and the third pixel group group, respectively. A method of arranging a pixel group of a CCD image sensor characterized by the above. The plurality of pixel groups further include fourth, fifth, and sixth pixel group groups each having a predetermined natural number of pixel groups continuously arranged in the column direction,
The above method
The fifth pixel group group is arranged adjacent to the third pixel group group and separated from the fourth pixel group group by a predetermined distance in the same row as the fourth pixel group group. Steps,
Disposing the sixth pixel group group in the same row as the third pixel group group in a column corresponding to the interval;
The first to third pixel groups corresponding to the first to third pixel group groups are shifted by a ½ pixel pitch in the column direction with respect to the pixel groups of the fourth to sixth pixel group groups. 7. The method of arranging a pixel group of a CCD image sensor according to claim 6, further comprising the step of arranging each pixel group of a third pixel group group.

Images