JP6270693B2 - CCD image sensor and driving method thereof - Google Patents

Description

  The present invention relates to a TDI (Time Delay and Integration) type CCD (Charge Coupled Device) image sensor and a driving method thereof.

  Many CCD image sensors have been developed in which a large number of photodetectors are arranged in an array on a semiconductor substrate and a signal charge readout circuit or output circuit is provided on the same substrate. In remote sensing, a CCD image sensor in which photodetectors are arranged in one row is mounted on a moving body such as an artificial satellite, and the direction perpendicular to the row direction of the photodetectors is made to coincide with the traveling direction of the satellite. Take a two-dimensional image of the ground surface. However, it is desirable to reduce the pixel pitch as much as possible in order to improve the image resolution. However, there is a problem that the incident light quantity is reduced by the reduction in the area of the photodetector and the S / N ratio is deteriorated.

  A TDI type image sensor has been developed as a clever means for improving the S / N ratio. The TDI system uses an FFT (full frame transfer) CCD, which is a two-dimensional image sensor, and synchronizes the timing of charge transfer with the movement timing of the subject image projected on the detector surface, thereby increasing the S / N ratio. This is a readout method for a CCD image sensor to be improved. In the case of remote sensing, TDI operation can be realized by adjusting the charge transfer in the vertical direction to the moving speed of the satellite. When the M-stage TDI operation is performed with the vertical CCD, the accumulation time is effectively M times, so that the sensitivity is improved M times and the S / N ratio is improved to √M times.

  When the detector sensitivity is increased by the TDI operation, there is a problem that the signal charge exceeds the saturation capacity of the pixel when a high-brightness object is imaged and the dynamic range is insufficient. Since the saturation capacity decreases with the pixel area, this problem becomes more pronounced when the pixel size is reduced in order to improve the image resolution. As one method for solving this, for example, a method described in Patent Document 1 has been proposed. In Patent Document 1, the pixel region is divided into a plurality of stages, and the saturation capacity of the pixel is changed stepwise for each stage, whereby a “knee characteristic” (here) The “knee characteristic” is a sensitivity characteristic in which the slope of the graph is different at a certain point between the case where the incident light intensity is low and the case where the incident light intensity is high. By this method, it is possible to perform imaging with high sensitivity for a low-luminance subject and low sensitivity for a high-luminance subject, and the dynamic range of the CCD image sensor is expanded as a whole.

Japanese Patent No. 4393715

  However, the CCD image sensor disclosed in Patent Document 1 has a problem that the “knee characteristic” in the input / output characteristics of the CCD image sensor cannot be adjusted.

  An object of the present invention is to solve the above problems and provide a CCD image sensor capable of adjusting the “knee characteristics” in the input / output characteristics of the CCD image sensor according to the imaging scene and a driving method thereof.

The CCD image sensor according to the present invention is
A CCD image sensor comprising a plurality of pixel groups in which a plurality of pixels for two-dimensionally arranging a plurality of pixels for time-delay integration of charges generated by photoelectric conversion and vertically transferring using a plurality of vertical transfer clocks. ,
A plurality of transfer electrodes for vertically transferring the signal charge accumulated in each pixel by time delay integration;
Provided for each of the pixels, and a means for discharging charges generated exceeding the saturation charge amount of the pixels;
A horizontal transfer section for horizontally transferring the signal charge integrated with the time delay;
A plurality of selection lines respectively connected to the transfer electrodes;
A first line selection circuit for connecting a plurality of first vertical transfer clocks to a predetermined corresponding one of the plurality of selection lines;
Corresponding to a plurality of first selection signals, each of which is composed of a plurality of unit cell circuits, and represents a connection state of each of the first vertical transfer clocks in the first line selection circuit. A first vertical shift register circuit held in the unit cell circuit,
The first line connection state of the in the selection circuits each first vertical transfer clock, Ri whether the connection status der selectively switches the saturation charge amount of each pixel,
The first line selection circuit selects and outputs one of the plurality of first vertical transfer clocks based on the plurality of first selection signals, whereby the saturated charge of each pixel is output. Control is performed so that the amount is selectively switched in units of rows .

  According to the CCD image sensor of the present invention, the saturation charge amount of each pixel in the CCD image sensor can be selectively switched in units of rows, so that the “knee characteristics” in the input / output characteristics of the CCD image sensor can be used in the imaging scene. It is possible to adjust accordingly.

1 is a top view of a TDI type CCD image sensor according to a first embodiment of the present invention. FIG. It is an element top view of the CCD image sensor of FIG. FIG. 3 is a block diagram showing components of a unit cell circuit 30-1 of the vertical shift register circuit 30 of FIG. FIG. 3 is a block diagram showing components of a unit cell circuit 25-1 of the line selection circuit 25 of FIG. FIG. 3 is a top view of the pixel 1 in FIG. 2. It is a longitudinal cross-sectional view of the pixel 1 when it cut | disconnects along A-A 'of FIG. 5A. FIG. 5 is a time axis waveform diagram showing changes in signal level with respect to time t of vertical transfer clocks φV1, φV2x, φV2y, and φV3 inputted to the transfer electrode 6 of FIG. FIG. 6B is a potential diagram showing a transfer operation of three-phase driving at each time t in FIG. 6A. FIG. 6B is a potential diagram showing a transfer operation of three-phase driving at each time t in FIG. 6A. FIG. 2 is a schematic diagram for explaining the operation of the pixel saturation control circuit 50 of FIG. 1. FIG. 3 is a time axis waveform diagram showing changes in signal level with respect to time t of a saturation charge amount control signal φSS and trigger clock signals φS1, φS2 input to the vertical shift register circuit 30 of FIG. FIG. 9 is a schematic diagram illustrating a state of the vertical shift register circuit 30 at times t1 to t6 in FIG. 8. It is a graph which shows the change of the signal charge amount accumulate | stored in each pixel 1 with respect to the pixel number of the conventional CCD image sensor in the case where incident light intensity is small and medium. FIG. 10B is a graph showing a change in the amount of output charge with respect to the incident light intensity P in FIG. 10A. 2 is a graph showing changes in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor of FIG. 1 when the incident light intensity is low and medium. 2 is a graph showing changes in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor of FIG. 1 when the incident light intensity is high. 12 is a graph showing changes in the amount of output charge with respect to incident light intensity P in FIGS. 11A and 11B. FIG. 6 is a top view of a TDI type CCD image sensor according to a second embodiment of the present invention. It is an element top view of the CCD image sensor of FIG. It is a block diagram which shows the component of the unit cell circuit 20-1 of the vertical shift register circuit 20 of FIG. It is a block diagram which shows the component of the unit cell circuit 15-1 of the line selection circuit 15 of FIG. FIG. 5 is a time axis waveform diagram showing changes in signal level with respect to time t of vertical transfer clocks φV1, φV2, φV3, and φV4 input to the transfer electrode 6 of FIG. FIG. 14 is a time axis waveform diagram showing changes in signal levels with respect to time t of a TDI transfer stage designation signal φTS and trigger clock signals φT1, φT2 inputted to the vertical shift register circuit 20 of FIG. FIG. 18 is a schematic diagram illustrating a state of the vertical shift register circuit 20 at times t1 to t8 in FIG. 17. It is a time-axis waveform diagram which shows the change of the signal level with respect to time t of the vertical transfer clocks φV1, φV2, φV3x, V3y and φV4 inputted to the transfer electrode 6 of FIG. FIG. 19B is a potential diagram showing a four-phase drive transfer operation at each time t in FIG. 19A. FIG. 19B is a potential diagram showing a four-phase drive transfer operation at each time t in FIG. 19A. It is the schematic for demonstrating operation | movement of the pixel saturation control circuit 50 of FIG. It is the schematic for demonstrating operation | movement of the TDI stage number setting circuit 60 of FIG. It is a graph which shows the change of the signal charge amount accumulate | stored in each pixel 1 with respect to the pixel number of the conventional CCD image sensor in the case where incident light intensity is small and medium. It is a graph which shows the change of the output charge amount with respect to the incident light intensity P in FIG. 22A. 2 is a graph showing changes in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor of FIG. 1 when the incident light intensity is low (graph I) and medium (graph II). 3 is a graph showing changes in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor in FIG. 1 when the incident light intensity is high (graph III). It is a graph which shows the change of the amount of output charges with respect to the incident light intensity P in FIG. 23A and FIG. 23B. It is an element top view of the CCD image sensor which concerns on Embodiment 3 of this invention. FIG. 25 is a block diagram showing components of a unit cell circuit 25A-1 of the line selection circuit 25A of FIG. FIG. 25 is a time axis waveform diagram showing changes in signal level with respect to time t of vertical transfer clocks φV1x, φV2, φV3x, and φV4 input to the transfer electrode 6 of FIG. FIG. 26B is a potential diagram showing a four-phase drive transfer operation at each time t in FIG. 26A. FIG. 25 is a time axis waveform diagram showing a change in signal level with respect to time t of vertical transfer clocks φV1y, φV2, φV3y, and φV4 input to the transfer electrode 6 of FIG. FIG. 27B is a potential diagram showing a transfer operation of four-phase driving at each time t in FIG. 27A. FIG. 25 is a schematic diagram for explaining the operation of the pixel saturation control circuit 50A of FIG. 24. It is an element top view of the CCD image sensor which concerns on Embodiment 4 of this invention. 30 is a graph showing changes in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor in FIG. 29 when the incident light intensity is low (graph I) and medium (graph II). 30 is a graph showing a change in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor in FIG. 29 when the incident light intensity is high (graph III). It is a graph which shows the change of the amount of output charges with respect to the incident light intensity P in FIG. 30A and 30B. Signal charges accumulated in each pixel 1 corresponding to the pixel number of the CCD image sensor in FIG. 29 when the incident light intensity is low (graph I) and medium (graph II) according to the fifth embodiment of the present invention. It is a graph which shows the change of quantity. FIG. 30 is a graph showing a change in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor in FIG. 29 when the incident light intensity is slightly high (graph III) according to Embodiment 5 of the present invention. . 30 is a graph showing a change in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor in FIG. 29 when the incident light intensity is high (graph IV) according to the fifth embodiment of the present invention. It is a graph which shows the change of the amount of output charges with respect to the incident light intensity P in FIG. 31A-FIG. 31C.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals, and description thereof is omitted.

Embodiment 1 FIG.
FIG. 1 is a top view of a TDI type CCD image sensor according to Embodiment 1 of the present invention. In FIG. 1, the detailed circuit is omitted, and the entire image of the CCD image sensor is shown. Here, the TDI method is a CCD image sensor reading method, in which an object moving at a constant speed is imaged by matching the moving direction and speed with the charge transfer direction and speed of the CCD image sensor. The number of vertical pixels when a moving object is repeatedly subjected to time-delay integrated exposure by the number of vertical pixels of the CCD image sensor is referred to as a TDI stage number (TDI transfer integration stage number). In the following description, the vertical direction refers to the vertical direction of the pixel group 100, and the horizontal direction refers to the horizontal direction of the pixel group 100. That is, the pixel group 100 includes a plurality of pixels 1 arranged in a two-dimensional array, the column direction of the two-dimensional array is a vertical direction, and the row direction orthogonal to the column direction is horizontal. Direction. In FIG. 1, the number of TDI stages is set to 100.

  In FIG. 1, a CCD image sensor includes a pixel group 100 having a plurality of pixels 1 arranged in a two-dimensional array, and pixel saturation control for controlling to selectively switch the saturation charge amount of each pixel 1 in units of rows. A circuit 50; a charge accumulator 3 that accumulates charges vertically transferred by time-delay integration by the number of stages; a horizontal CCD circuit 2 that is a horizontal transfer unit that horizontally transfers signal charges accumulated in the charge accumulator 3; And an output circuit 5. Here, the time-integrated signal charge is transferred in the vertical direction (downward in the drawing) toward the horizontal CCD circuit 2, and further transferred in the horizontal direction (rightward in the drawing) by the horizontal CCD circuit 2 for output. Read from the amplifier 5. Further, the pixel saturation control circuit 50 is formed on the same substrate as the pixel group 100, and the pixel saturation control circuit 50 and the pixel 1 are connected to each other by the wiring 8 for each row.

  In the present embodiment, each pixel 1 having pixel numbers 1 to S (1 ≦ natural number S ≦ 100) is set to the saturation charge amount Q1, and each pixel 1 having pixel numbers (S + 1) to 100 is set to the saturation charge amount Q2 (real number). Q1> real number Q2). That is, with the pixel 1 in the pixel row S as a boundary, the saturation charge amount of each pixel 1 is switched from the saturation charge amount Q2 to the saturation charge amount Q1 and becomes large.

  FIG. 2 is an element plan view of the CCD image sensor of FIG. The CCD image sensor of FIG. 2 includes a pixel group 100 formed of a plurality of pixels 1, a plurality of transfer electrodes 6 for vertically transferring signal charges accumulated in each pixel 1 by time delay integration, and a horizontal CCD. A plurality of selection lines SLa, SLb connected to the circuit 2 and the plurality of transfer electrodes 6 and for inputting vertical transfer clocks φV1 to φV3 for vertically transferring the accumulated signal charges to the plurality of transfer electrodes 6, respectively. , SLc, a charge storage section 3, a charge discharge drain section 4 for discharging unnecessary signal charges, a pixel saturation control circuit 50, and an output amplifier 5.

  2, the configuration and operation of the pixel saturation control circuit 50 will be described below. Here, the amplitude voltage of the vertical transfer clock φV2 input to the transfer electrode 6b of each pixel 1 is made smaller than the amplitude voltage of the vertical transfer clocks φV1 and φV3 input to the other transfer electrodes 6a and 6c. The saturation charge amount of 1 is changed. In the vertical transfer clock φV2, a vertical transfer clock having the same amplitude voltage as that of the vertical transfer clocks φV1 and φV3 is defined as a vertical transfer clock φV2x, and has an amplitude voltage smaller than that of the vertical transfer clocks φV1 and φV3. The vertical transfer clock is assumed to be vertical transfer clock φV2x. In order to simplify the description, the description will be made assuming that the number of TDI stages of the CCD image sensor is eight.

  The pixel saturation control circuit 50 in FIG. 2 includes a vertical shift register circuit 30 and a line selection circuit 25. Here, the vertical shift register circuit 30 holds a plurality of selection signals representing connection states of the vertical transfer clocks in the line selection circuit 25 in the corresponding unit cell circuits 30-1 to 30-8. Note that the saturation charge amount of each pixel 1 is selectively switched in units of rows based on the saturation charge amount control signal φSS input to the vertical shift register circuit 30 and held as a plurality of selection signals. That is, the line selection circuit 25 determines the saturation charge amount of each pixel 1 based on a plurality of selection signals indicating the connection state between the vertical transfer clock having the first amplitude voltage or the second amplitude voltage and the plurality of transfer electrodes. Is selectively switched line by line.

  In FIG. 2, the signal charge obtained by time delay integration is transferred toward the horizontal CCD circuit 2 in the vertical transfer direction (downward in the drawing), and further transferred in the horizontal CCD circuit 2 in the horizontal transfer direction (rightward in the drawing). And output to the output circuit 5. The output circuit 5 converts the input signal charges obtained by time delay integration into electrical signals and outputs them. The vertical transfer direction is a TDI transfer direction of signal charges. For example, when a TDI type CCD image sensor is mounted on an artificial satellite, the TDI transfer direction coincides with the traveling direction of the artificial satellite. Here, in the pixel group 100 composed of eight pixels (eight stages) in the vertical transfer direction, the first stage, the second stage,... The pixel 1 adjacent to the drain / drain unit 4 is set as the eighth stage, and a total of eight stages from the first stage to the eighth stage are set as TDI transfer stages.

  In FIG. 2, the saturation charge amount control signal φSS includes a plurality of selection signals for the CCD image sensor, and the selection signals represent the connection states of the vertical transfer clocks φV2x and φV2y in the line selection circuit 25 of the CCD image sensor. . Here, each selection signal selectively switches the saturation charge amount of each pixel 1 in units of rows.

  Here, the number of unit cell circuits 25-1 to 25-8 is the same as the value of the number of vertical pixels (the number of stages) of the pixel group 100 constituting the CCD image sensor. In the first embodiment, the vertical shift register circuit 30 includes eight unit cell circuits 30-1 to 30-8. Further, input pins 29a and 29b for inputting the respective trigger clock signals φS1 and φS2 are connected to the unit cell circuits 30-1 to 30-8 via metal wirings 28a and 28b, respectively. The unit cell circuit 30-1 is connected to an input pin 29c, which is an input terminal for inputting the saturation charge amount control signal φSS, via the metal wiring 28c, so that the unit cell circuit 30-m (2 ≦ natural number m). ≦ 8) is connected in series with the unit cell circuit 30- (m−1).

  The pixel saturation control circuit 50 is composed of a plurality of unit cell circuits 25-1 to 25-8, and a unit cell circuit 30- corresponding to a selection signal indicating a connection state of the vertical transfer clocks φV2x, φV2y in the line selection circuit 5 is provided. 1 to 30-8, which are connected to the vertical shift register circuit 30 and each of the selection lines SLb and SLd, and based on a plurality of selection signals, a plurality of vertical transfer clocks φV2x and φV2y are predetermined among the plurality of selection lines. And a line selection circuit 25 connected to one corresponding selection line.

  The vertical shift register circuit 30 includes eight unit cell circuits 30-1 to 30-8. Further, input pins 29a and 29b for inputting the respective trigger clock signals φS1 and φS2 are connected to the unit cell circuits 30-1 to 30-8 via metal wirings 28a and 28b, respectively. The unit cell circuit 30-1 is connected to an input pin 29c, which is an input terminal for inputting the saturation charge amount control signal φSS, via the metal wiring 28c, so that the unit cell circuit 30-m (2 ≦ natural number m). ≦ 8) is connected in series with the unit cell circuit 30- (m−1).

  The line selection circuit 25 includes unit cell circuits 25-1 to 25-8 made up of a selection MOS transistor group. Here, the number of unit cell circuits 25-1 to 25-8 is the same as the number of vertical pixels (the number of stages) of the pixel group 100 constituting the CCD image sensor. Further, input pins 24x and 24y for inputting the vertical transfer clocks φV2x and φV2y are connected to the unit cell circuits 25-1 to 25-8 via metal wirings 23x and 23y, respectively. The connection state of the vertical transfer clocks φV2x and φV2y in the line selection circuit 25 is a connection state indicating whether or not to selectively switch the saturation charge amount of each pixel 1, and the line selection circuit 25 includes a plurality of selection signals. Based on the above, by selecting and outputting one of the plurality of vertical transfer clocks φV2x, φV2y, the saturation charge amount of each pixel 1 is controlled to be selectively switched in units of rows.

  The pixel group 100 is configured by arranging 10 pixels in a horizontal transfer direction and 8 pixels in a vertical transfer direction in a two-dimensional array on the surface of a substrate (not shown) on which a CCD image sensor is formed. Here, the pixel 1 is indicated by a region indicated by a solid thick frame in FIG. 2, and the region indicated by the thick frame is a boundary line schematically showing a boundary between the pixels 1.

  In each pixel 1 in FIG. 2, signal charges generated by photoelectric conversion are accumulated, and the accumulated signal charges are time-delay integrated by the transfer electrode 6 and vertically transferred. Here, a three-phase drive CCD image sensor is used for signal charge transfer, and a set of three transfer electrodes 6 is arranged on the pixel 1. Here, transfer electrodes 6a, 6b, 6c made of polysilicon are sequentially arranged, and a transfer channel (not shown) is formed thereunder, and the transfer channel is an impurity region having a conductivity type opposite to that of the substrate (not shown). It is electrically separated by an overflow drain 7 as a separation region comprising The transfer electrodes 6a and 6c are connected to input pins 11a and 11c via selection lines SLa and SLc, respectively, which are metal wirings. On the other hand, the transfer electrode 6b is connected to one of the input pins 24x and 24y via a selection line SLb which is a metal wiring. The line selection circuit 25 determines which one is connected. That is, the transfer electrodes 6a, 6b, and 6c are connected to the selection lines SLa, SLb, and SLc, respectively, and any one of the three-phase vertical transfer clocks φV1, φV2 (φV2x or φV2y), φV3 is the three transfer electrodes 6a. , 6b and 6c, respectively, to transfer the signal charges in the vertical transfer direction.

  FIG. 3 is a block diagram showing components of the unit cell circuit 30-1 of the vertical shift register circuit 30 of FIG. In FIG. 3, the unit cell circuit 30-1 includes NMOS transmission gates 31a and 31b and inverters 32a and 32b. The inverter 32b, the transmission gate 31b, the inverter 32a, and the transmission gate 31a. Are connected in series. Here, the drain terminal of the transmission gate 31a is connected to the input pin 29c via the metal wiring 28c, and the source terminal of the transmission gate 31a is connected to the input terminal of the inverter 32a. The gate terminal of the transmission gate 31a is connected to the input pin 29a through the metal wiring 28a.

  In FIG. 3, the output terminal of the inverter 32a is connected to the drain terminal of the transmission gate 31b, and the source terminal of the transmission gate 31b is connected to the input terminal of the inverter 32b. The gate terminal of the transmission gate 31b is connected to the input pin 29b through the metal wiring 28b. The output terminal of the inverter 32b is connected to the unit cell circuit 25-1 of FIG. 2 differs from the unit cell circuit 30-1 in that the drain terminal of the transmission gate 31a is connected to the output terminal of the inverter 32b. Here, the vertical shift register circuit 30 receives the saturation charge amount control signal φSS from the input pin 29c, and advances the unit cell circuit step by step based on the trigger clock signals φS1 and φS2. That is, the data of one clock pattern of the saturation charge amount control signal φSS input from the input pin 29c is held in the vertical shift register circuit 30.

  FIG. 4 is a block diagram showing components of the unit cell circuit 25-1 of the line selection circuit 25 of FIG. In FIG. 4, the unit cell circuit 25-1 includes a transmission gate 29a composed of one NMOS transistor 27a and one PMOS transistor 28a, one NMOS transistor 27b and one PMOS transistor 28b. The transmission gate 29b is configured, and an inverter 35a whose output terminal is connected to the gate terminal of the PMOS transistor 28a and the gate terminal of the NMOS transistor 27b.

  In FIG. 4, one end of the transmission gate 29a and the transmission gate 29b is connected to the selection line SLb connected to the transfer electrode 6b, and the other end of the transmission gate 29a is connected to the input pin 24x via the metal wiring 23x. The other end of the transmission gate 29b is connected to the input pin 24y through the metal wiring 23y.

  The input gate of the NMOS transistor 27a of the transmission gate 29a and the input gate of the PMOS transistor 28b of the transmission gate 29b are connected to the unit cell circuit 2-1 of FIG. The input gate of the NMOS transistor 27a of the transmission gate 29a, the input gate of the PMOS transistor 28b of the transmission gate 29b, and the input terminal of the inverter 35a are connected to each other.

  5A is a top view of the pixel 1 in FIG. 2, and FIG. 5B is a vertical cross-sectional view of the pixel 1 when cut along A-A ′ in FIG. 5A. In FIG. 5A, the transfer electrode 6 of the pixel 1 is composed of a set of three transfer electrodes 6a, 6b, and 6c. Further, a horizontal overflow drain 7 is formed adjacent to each pixel 1. Here, unnecessary signal charges saturated in each pixel 1 are discharged from the charge discharging unit 4 to the outside via the overflow drain 7. 5B, a cross-sectional view of the lateral overflow drain 7 is shown. Here, the lateral overflow drain 7 includes an overflow drain region 72, a P-type impurity region 73, a high-concentration P-type impurity region 74, an overflow gate 71, and the like. It is composed of

  5B, a vertical CCD transfer channel 55 is formed on the surface side of a P-type silicon substrate 52, and a transfer electrode 6b made of polysilicon or the like is formed with a gate oxide film 54 interposed therebetween. An insulating film 53 made of an oxide film or the like is formed on the surface side of the element. An overflow drain region 72 composed of a high-concentration N-type impurity region is formed adjacent to the transfer channel 55, and a P-type impurity region 73 that determines an overflow threshold is formed between the transfer channel 55 and the overflow drain region 72. . Further, a high concentration P-type impurity region 74 for pixel separation is formed on the opposite side of the overflow drain region 72 from the P-type impurity region 73. Further, an overflow gate 71 made of polysilicon or the like is formed above the P-type impurity region 73 with the gate oxide film 54 interposed therebetween.

  Here, the overflow gate 71 is given a constant bias potential during imaging, and the saturation charge amount (storage capacitance) of the pixel 1 is determined by the potential value of the P-type impurity region 73 and the voltage applied to the overflow gate 71. . When light enters the pixel 1, the signal charge photoelectrically converted in the P-type silicon substrate is accumulated in the potential well of the transfer channel 55, but when the signal charge amount increases and exceeds the saturation charge amount of the pixel 1, saturation occurs. The signal charge amount exceeding the charge amount flows into the overflow drain region 72 through the potential barrier of the P-type impurity region 73 and is discharged from the charge discharging unit 4.

  The operation of the CCD image sensor configured as described above will be described below. In the following description, the signal levels of the vertical transfer clocks φV1 to φV3, the selection signal included in the saturation charge amount control signal φSS, and the trigger clock signals φS1 and φS2 are set to a high level or a low level. Note that these signal levels may be binary signals having first or second levels other than binary signals of high level and low level.

  The operation of the unit cell circuit 30-1 of the vertical shift register circuit 30 in FIG. 3 will be described.

  In FIG. 3, when the trigger clock signal φS1 is set to the high level, the transmission gate 31a is turned on and the output of the previous stage is input to the inverter 32a, and the output of the inverter 32a becomes the inverted output of the previous stage. When the unit cell circuit 30-1 is in the first stage, the saturation charge amount control signal φSS input to the input pin 29c is input to the inverter 32a instead of the output of the previous stage, and the output of the inverter 32a is the saturation charge amount control signal. φSS inverted output. Next, when the trigger clock signal φS1 is set to the low level, the transmission gate 31a is turned off, and the input and output of the inverter 32a are held as they are. Next, when the trigger clock signal φS2 input to the input pin 29b is set to the high level, the transmission gate 32b is turned on, the output of the inverter 32a is input to the inverter 32b, and the output of the inverter 32b becomes the inverted output of the inverter 32a. This output is transmitted to the unit cell circuit 25-1 of the line selection circuit 25 as an output signal from the unit cell circuit 30-1. Next, when the trigger clock signal φS2 is set to the low level, the transmission gate 31b is turned off, and the input and output of the inverter 32b are held as they are. Further, when the trigger clock signal φS1 is set to the high level, the series of operations so far are repeated. The operations of the unit cell circuits 30-2 to 30-8 of the vertical shift register circuit 30 are the same as those of the unit cell circuit 30-1.

  As described above, in the vertical shift register circuit 30, the clock pulses of the saturation charge amount control signal φSS input from the input pin 29c are sequentially transmitted to the next stage one by one, and each unit cell circuit 30-1 to 30-30. As an output signal from -8, it is transmitted to the unit cell circuits 25-1 to 25-8 of the line selection circuit 25, respectively.

  Next, the operation of the unit cell circuit 25-1 of the line selection circuit 25 in FIG. 4 will be described.

  In FIG. 4, when the signal level of the output signal from the unit cell circuit 30-1 in FIG. 3 is high, the transmission gate 29a is turned on, the input pin 24x is connected to the selection line SLb, and is vertically transferred to the transfer electrode 6b. The clock φV2x is input. When the signal level of the output signal from the unit cell circuit 30-1 is low, the transmission gate 29b is turned on, the input pin 24y is connected to the selection line SLb, and the vertical transfer clock φV2y is input to the transfer electrode 6b. The

  As described above, the unit cell circuits 25-1 to 25-8 of the line selection circuit 25 perform vertical input to the transfer electrode 6b based on the signal levels of the output signals from the unit cell circuits 30-1 to 30-8. Control is performed so that the transfer clocks (φV2x, φV2y) are switched.

  As shown in FIG. 2, in the CCD image sensor described above, among the plurality of vertical transfer clocks, the transfer electrodes for the vertical transfer clock φV1 and the vertical transfer clock φV3 are transferred via the input pins 11a and 11c and the selection lines SLa and SLc. Connected to 6a and 6c, respectively. On the other hand, the vertical transfer clocks φV2x and φV2y are connected to the transfer electrode 6b via the pixel saturation control circuit 50 and the selection line SLb. That is, the selection line SLb connected to the transfer electrode 6b is connected to one of the input terminals 24x and 24y of the vertical transfer clocks φV2x and φV2y. Here, the pixel saturation control circuit 50 determines the connection state between the selection line SLb and the input terminals 24x and 24y based on the saturation charge amount control signal φSS.

  In the above-described TDI linear image sensor, the saturation charge amount of the pixel 1 can be reduced by selectively switching the amplitude voltage of the vertical transfer clock φV2y to the vertical transfer clock φV2x having a smaller amplitude voltage than the vertical transfer clock φV2y. The operation will be described below.

  6A is a time axis waveform diagram showing changes in signal level with respect to time t of vertical transfer clocks φV1, φV2x, φV2y, and φV3 inputted to the transfer electrode 6 of FIG. 3 is a timing chart of vertical transfer clocks φV1, φV2x, φV2y, and φV3 input to the three-phase driving CCD image sensor of FIG.

  6B and 6C are potential diagrams showing the transfer operation of the three-phase drive at each time t in FIG. 6A. That is, FIGS. 6B and 6C schematically show the distribution pattern of the potential well of the transfer channel at times t1 to t7. Here, FIG. 6B shows a case where the vertical transfer clock φV2x having the same amplitude voltage as the vertical transfer clock φV1 and the vertical transfer clock φV3 is selected as an input signal to the selection line SLb, and FIG. 6C shows the selection. The case where the vertical transfer clock φV2y having an amplitude voltage smaller than the vertical transfer clock φV1 and the vertical transfer clock φV3 is selected as the input signal to the line SLb is shown. A dotted line shown in the potential diagram indicates a threshold level Vth at which charges are discharged to the horizontal overflow drain 7 when the pixel 1 is saturated.

  As shown in FIG. 6A, charge generated by photoelectric conversion is time-delay integrated and vertically transferred using a plurality of vertical transfer clocks φV1, φV2x, φV2y, and φV3, respectively. At this time, as shown in FIGS. 6B and 6C, the potential well formed in the transfer channel moves to the right in the drawing with time. The saturation charge amount of the pixel 1 is determined by the minimum value of the well capacity during the time t1 to t7. Therefore, in the case of FIG. 6B, the maximum accumulated charge amount at time t2, t4, or t6 is given. On the other hand, in the case of FIG. 6C, compared to FIG. 6B, the potential well formed in the transfer channel by the vertical transfer clock φV2y becomes shallower, so the saturation charge amount of the pixel 1 is determined by the maximum accumulated charge amount at time t4. Is done. Note that the saturation charge amount of the pixel 1 increases / decreases in accordance with the amplitude voltage of the vertical transfer clock, and the saturation charge amount at the amplitude voltage of the vertical transfer clock φV2y decreases by setting the amplitude voltage of the vertical transfer clock φV2y small. Become.

  FIG. 7 is a schematic diagram for explaining the operation of the pixel saturation control circuit 50 of FIG. FIG. 7 shows an example in which the pixel saturation control circuit 50 selectively switches the saturation charge amount of each pixel 1 in units of rows, and the saturation charge amount Q1 of the pixel 1 of the pixel numbers 1 to 5 is the pixel numbers 6 to 8. The case where the saturation charge amount Q2 of the pixel 1 is larger is shown.

  FIG. 8 is a time axis waveform diagram showing changes in signal level with respect to time t of the saturation charge amount control signal φSS and trigger clock signals φS1 and φS2 input to the vertical shift register circuit 30 of FIG. FIG. 9 is a schematic diagram showing the state of the vertical shift register circuit 30 at times t1 to t6 in FIG. Here, the input saturation charge amount control signal φSS is a clock pulse in which input clocks to the CCD image sensor are coupled in series. FIG. 9 shows the output of the vertical shift register circuit 30 at each time t1 to t6. The signal is shown for each time series.

  8 and 9, the vertical shift register circuit 30 is initialized at time t0. Next, at time t1, the trigger clock signals φS1 and φS2 are sequentially set to the high level while the saturation charge amount control signal φSS is kept at the high level. As a result, at time t1, the signal level of the output signal from the unit cell circuit 30-1 is set to a high level. At time t2, the trigger clock signals φS1 and φS2 are sequentially set to the high level while the saturation charge amount control signal φSS is kept at the high level. As a result, at time t2, the signal level of the output signal from the unit cell circuit 30-1 is set to a high level, and the high level signal level held by the unit cell circuit 30-1 advances by one stage, so that the unit cell circuit 30-2 The signal level of the output signal from becomes a high level. At time t3, the trigger clock signals φS1 and φS2 are sequentially set to the high level while the saturation charge amount control signal φSS is kept at the high level. As a result, at time t3, the signal level of the output signal from the unit cell circuit 30-1 is set to the high level, and the high level signal level held by the unit cell circuit 30-1 and the unit cell circuit 4-2 hold. The high level signal level advances by one stage, the signal level of the output signal from the unit cell circuit 30-2 becomes high level, and the signal level of the output signal from the unit cell circuit 30-3 becomes high level. The same applies hereinafter.

  When all the signals of one clock pattern of the saturation charge amount control signal φSS are prepared in the vertical shift register circuit 30, the signals are simultaneously output to the line selection circuit 25.

  With the above-described configuration, it is possible to control the saturation charge amount of each pixel 1 to be selectively switched in units of rows by using three clock patterns of the trigger clock signals φS1 and φS2 and the saturation charge amount control signal φSS. .

  According to the CCD image sensor described above, since the saturation charge amount of each pixel 1 can be selectively switched in units of rows by the pixel saturation control circuit 50, the “knee characteristic” of the input / output characteristics of the CCD image sensor is controlled. It becomes possible. The operation will be described below.

  FIG. 10A is a graph showing changes in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the conventional CCD image sensor when the incident light intensity is low and medium. FIG. 10B is a graph showing a change in the amount of output charge with respect to the incident light intensity P in FIG. 10A. Here, the amount of signal charge that is vertically transferred increases in proportion to the number of TDI stages, and the saturation charge amount of each pixel 1 is constant in the entire region of the pixel group 100.

  In FIG. 10A, in a general TDI type CCD image sensor, the change in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number when uniform light is incident on the entire region of the pixel group 100 and the TDI operation is performed. The signal charge accumulated in each pixel 1 is vertically transferred by time delay integration from the pixel 1 of the pixel number 100 to the pixel of the pixel number 1 toward the lower side of the drawing. Here, the change in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number when the incident light intensity P is large (graph II) and when the incident light intensity P is small (graph I) is shown. When the light intensity P is high (graph II), the signal charge amount Q accumulated in the pixel number n reaches the saturation charge amount Q1 and overflows.

  FIG. 10B shows a change in the output charge amount with respect to the incident light intensity P when the TDI operation is performed with uniform light incident on the entire region of the pixel group 100. Here, the output charge amount corresponds to the signal charge amount Q accumulated in the pixel number 1 in FIG. 10A. Further, when the saturation charge amount of each pixel 1 is constant in the entire region of the pixel group 100, the “knee characteristic” does not appear in the input / output characteristics as shown in FIG. 10B.

  FIG. 11A is a graph showing changes in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor in FIG. 1 when the incident light intensity is low and medium. FIG. 11B is a graph showing the change in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor in FIG. 1 when the incident light intensity is high. FIG. 11C is a graph showing changes in the amount of output charge with respect to the incident light intensity P in FIGS. 11A and 11B. Here, the pixel saturation control circuit 50 sets the saturation charge amount Q2 for each pixel 1 of pixel numbers 100 to (S + 1), and the saturation charge for each pixel 1 of pixel numbers S to 1. The quantity is set to Q1 (Q2 <Q1).

  As shown in FIG. 11A, when the incident light intensity is small (graph I), the accumulated signal charge amount does not reach the saturation charge amount Q1 of each pixel 1, but the incident light intensity is medium (graph II). ), The signal charge amount Q accumulated in the pixel numbers 100 to S1 becomes equal to or greater than the saturation charge amount Q2 and overflow occurs. Thereafter, since the signal charge amount Q accumulated in the pixel numbers S to 1 does not reach the saturation charge amount Q1, no overflow occurs.

  As shown in FIG. 11B, when the incident light intensity is still higher (graph III), the signal charge amount Q accumulated in the pixel numbers 100 to S1 becomes equal to or greater than the saturation charge amount Q2 and overflow occurs. Thereafter, the signal charge amount Q accumulated in the pixel numbers S to 1 reaches the saturation charge amount Q1 and overflows.

  As shown in FIG. 11C, the output charge amount of the CCD image sensor of FIG. 1 has a bending point at the incident light intensity P1, overflows above the incident light intensity P2, and the output charge amount becomes almost constant. That is, by providing a bending point, it is possible to obtain “knee characteristics” in the input / output characteristics of the CCD image sensor. Here, the incident light intensity 0 to P1 is set as a small incident light intensity (corresponding to the graph I in FIG. 11A), and the incident light intensity P1 to P2 is set as a medium incident light intensity (corresponding to the graph II in FIG. 11A). The incident light intensities P2 to P3 are set to a large incident light intensity (corresponding to the graph III in FIG. 11B). Further, the gradient from the incident light intensity 0 to P1 is proportional to the total number of stages of TDI transfer (100 stages in this embodiment), and the gradient from the incident light intensity P1 to P2 is set to the saturation charge amount Q1. It is proportional to the number of stages of 1 (S in this embodiment). The values of the saturation charge amounts Q1 and Q2 can be changed by the amplitude voltage with respect to the time t of the vertical transfer clocks φV1, φV2x, φV2y, and φV3. When the pixel number S and the saturation charge amounts Q1 and Q2 are changed, the inclination of the graph and the position of the bending point can be changed in the “knee characteristics” shown in FIG. 11C.

  According to the CCD image sensor according to the above embodiment, the saturation charge amount of each pixel 1 can be selectively switched in units of rows, so that “knee characteristics” can be obtained in the input / output characteristics of the CCD image sensor. Further, since the saturation charge amount of each pixel 1 can be changed to an arbitrary value, the slope of the graph and the position of the bending point in the “knee characteristics” can be adjusted.

Embodiment 2. FIG.
In Embodiment 1, the saturation charge amount of each pixel 1 is controlled to be selectively switched with the pixel 1 in a predetermined pixel row as a boundary. On the other hand, the present embodiment further includes a TDI stage number setting circuit 60 for setting the number of TDI stages, and performs control so as to obtain “knee characteristics” as input / output characteristics even at low luminance incidence. It is characterized by that. Here, the amplitude voltage of the vertical transfer clock φV3 input to the transfer electrode 6c of each pixel 1 is made smaller than the amplitude voltage of the vertical transfer clocks φV1, φV2, and φV4 input to the other transfer electrodes 6a, 6b, and 6d. As a result, the saturation charge amount of each pixel 1 is changed. In the vertical transfer clock φV3, a vertical transfer clock having the same amplitude voltage as the vertical transfer clocks φV1, φV2, and φV4 is defined as a vertical transfer clock φV3x, which is smaller than the amplitude voltages of the vertical transfer clocks φV1, φV2, and φV4. A vertical transfer clock having an amplitude voltage is defined as a vertical transfer clock φV3y. In order to simplify the description, the description will be made assuming that the number of TDI stages of the CCD image sensor is eight.

  FIG. 12 is a top view of a TDI type CCD image sensor according to Embodiment 2 of the present invention. 12 is characterized by further comprising a TDI stage number setting circuit 60 connected to the pixel 1 by each wiring 8 for each row as compared with the CCD image sensor of FIG. Here, the TDI stage number setting circuit 60 sets the number of integration stages to be vertically transferred by time delay integration. In FIG. 12, pixels 1 from pixel number M to pixel number 1 are vertically transferred. Further, the pixels 1 to the pixel numbers M to (S + 1) are set to the saturation charge amount Q2, and the pixels 1 to the pixel numbers 1 to S are set to the saturation charge amount Q1 (real number Q1> real number Q2). Is done. Here, the number of TDI stages of the CCD image sensor is set based on a TDI transfer stage designation signal φTS that is input to a vertical shift register circuit 20 described later and held as a plurality of selection signals.

  FIG. 13 is an element plan view of the CCD image sensor of FIG. The CCD image sensor of FIG. 13 is a four-phase drive CCD image sensor compared to the three-phase drive CCD image sensor of FIG. 2, and a set of four transfer electrodes 6 are arranged on each pixel 1. Is different. Here, transfer electrodes 6a to 6d made of polysilicon are sequentially arranged, and a transfer channel (not shown) is formed thereunder, and the transfer channel is made of an impurity region having a conductivity type opposite to that of the substrate (not shown). It is electrically separated by an overflow drain 7 as a separation region. The transfer electrodes 6a, 6b, and 6d are connected to the input pins 14a, 14b, and 14d via selection lines SLa, SLb, and SLd, which are metal wirings, respectively. On the other hand, the transfer electrode 6c is connected to one of the input pins 24x and 24y via a selection line SLc that is a metal wiring. The line selection circuit 25 determines which one is connected. That is, the transfer electrodes 6a to 6d are connected to the selection lines SLa to SLd, respectively, and any one of the four-phase vertical transfer clocks φV1 to φV4 is input to the four transfer electrodes 6a, 6b, 6c, and 6d. The signal charge is transferred in the vertical transfer direction.

  In FIG. 13, the line selection circuit 15 includes unit cell circuits 15-1 to 15-8 each including a selection MOS transistor group. Here, the number of unit cell circuits 15-1 to 15-8 is the same as the number of vertical pixels (the number of stages) of the pixel group 100. Further, input pins 14b and 14d for inputting the vertical transfer clocks φV2 and φV4 are connected to the unit cell circuits 15-1 to 15-8 via metal wirings 13b and 13d, respectively.

  The vertical shift register circuit 20 includes eight unit cell circuits 20-1 to 20-8. Further, input pins 19a and 19b for inputting the respective trigger clock signals φT1 and φT2 are connected to the unit cell circuits 20-1 to 20-8 via metal wirings 18a and 18b, respectively. The unit cell circuit 20-1 is connected to an input pin 19c, which is an input terminal for inputting the TDI transfer stage designation signal φTS, via a metal wiring 18c, so that the unit cell circuit 20-m (2 ≦ natural number m). ≦ 12) is connected in series with the unit cell circuit 20- (m−1).

  The TDI stage number setting circuit 60 is composed of a plurality of unit cell circuits 20-1 to 20-8, and a unit cell circuit 15- corresponding to a selection signal indicating the connection state of the vertical transfer clocks φV2, φV4 in the line selection circuit 15 is provided. The vertical shift register circuit 20 held at 1 to 15-8 and each of the selection lines SLb and SLd are connected to the plurality of vertical transfer clocks φV2 and φV4 as a predetermined corresponding one of the plurality of selection lines. And a line selection circuit 15 to be connected. Here, the connection state of the vertical transfer clocks φV2 and φV4 in the line selection circuit 15 is a connection state indicating whether or not the signal charge is vertically transferred to the horizontal CCD circuit 2, and the line selection circuit 15 is based on the selection signal. Thus, by selecting whether or not a predetermined pair of vertical transfer clocks among the plurality of vertical transfer clocks φV1 to φV4 are replaced with each other, it is controlled to select whether or not the signal charge is vertically transferred to the horizontal CCD circuit 2. . That is, the line selection circuit 15 controls the number of stages of time delay integration of the CCD image sensor based on each selection signal.

  FIG. 14 is a block diagram showing components of the unit cell circuit 20-1 of the vertical shift register circuit 20 of FIG. In FIG. 14, the unit cell circuit 20-1 includes NMOS transmission gates 21a and 21b and inverters 22a and 22b. The inverter 22b, the transmission gate 21b, the inverter 22a, and the transmission gate 21a. Are connected in series. Here, the drain terminal of the transmission gate 21a is connected to the input pin 19c via the metal wiring 18c, and the source terminal of the transmission gate 21a is connected to the input terminal of the inverter 22a. The gate terminal of the transmission gate 21a is connected to the input pin 19a through the metal wiring 18a.

  In FIG. 14, the output terminal of the inverter 22a is connected to the drain terminal of the transmission gate 21b, and the source terminal of the transmission gate 21b is connected to the input terminal of the inverter 22b. The gate terminal of the transmission gate 21b is connected to the input pin 19b through the metal wiring 18b. The output terminal of the inverter 22b is connected to the unit cell circuit 15-1 of FIG. The unit cell circuits 20-2 to 20-8 in FIG. 14 are different from the unit cell circuit 20-1 in that the drain terminal of the transmission gate 21a is connected to the output terminal of the inverter 22b. Here, the vertical shift register circuit 20 receives the TDI transfer stage designation signal φTS from the input pin 19c, and advances the unit cell circuit step by step based on the trigger clock signals φT1 and φT2. That is, the data of one clock pattern of the TDI transfer stage designation signal φTS input from the input pin 19c is held in the vertical shift register circuit 20.

  FIG. 15 is a block diagram showing components of the unit cell circuit 15-1 of the line selection circuit 15 of FIG. In FIG. 15, a unit cell circuit 15-1 includes a transmission gate 23a composed of one NMOS transistor 18a and one PMOS transistor 19a, one NMOS transistor 18b and one PMOS transistor 19b. A transmission gate 23b configured, a transmission gate 23c configured by one NMOS transistor 18c and a PMOS transistor 19c, a transmission configured by one NMOS transistor 18d and one PMOS transistor 19d. Gate 23d, inverter 17a having an output terminal connected to the gate terminal of transmission gate 23a and the gate terminal of transmission gate 23b, and transmission gate 23c Constructed and an inverter 17b which output terminal to the gate terminal of the over preparative terminal a transmission gate 23d is connected.

  In FIG. 15, one end of transmission gate 23a and transmission gate 23b is connected to selection line SLb connected to transfer electrode 6b, and the other end of transmission gate 23a is connected to input pin 14b via metal wiring 13b. The other end of the transmission gate 23b is connected to the input pin 14d through the metal wiring 13d. One end of the transmission gate 23c and the transmission gate 23d is connected to the selection line SLd connected to the transfer electrode 6d, and the other end of the transmission gate 23c is connected to the input pin 14d via the metal wiring 13d. The other end of the gate 23d is connected to the input pin 14b through the metal wiring 13b.

  The input gates of the NMOS transistors 18a and 18c of the transmission gates 23a and 23c, the input gate of the PMOS transistor 19b of the transmission gate 23b, and the input gate of the NMOS transistor 18c of the transmission gate 23c are connected to the above-described FIG. To the unit cell circuit 20-1. The input gate of the NMOS transistor 18a of the transmission gate 23a, the input gate of the PMOS transistor 19d of the transmission gate 23d, and the input terminals of the inverters 17a and 17b are connected to each other.

  The operation of the CCD image sensor configured as described above will be described below. In the following description, the signal levels of the vertical transfer clock φV1 to the vertical transfer clock φV4, the selection signal included in the saturation charge amount control signal φSS, and the trigger clock signals φS1 and φS2 are set to a high level or a low level. The signal levels of the selection signal and the trigger clock signals φT1 and φT2 included in the TDI transfer stage designation signal φTS are set to a high level or a low level. Note that these signal levels may be binary signals having first or second levels other than binary signals of high level and low level.

  FIG. 16 is a time axis waveform diagram showing changes in signal level with respect to time t of vertical transfer clocks φV1, φV2, φV3, and φV4 inputted to the transfer electrode 6 of FIG. That is, it is a timing chart of vertical transfer clocks φV1, φV2, φV3, and φV4 inputted to the four-phase driving CCD image sensor of FIG.

  In FIG. 16, vertical transfer clocks [phi] V1 to [phi] V4 are input to the transfer electrodes 6a to 6d as drive clocks for the CCD image sensor. Here, the vertical transfer clock φV1 and the vertical transfer clock φV3 (φV3x or φV3y), and the vertical transfer clock φV2 and the vertical transfer clock φV4 are in a phase relationship that is 180 degrees out of phase with each other. To do. This will be described below.

  From time t1 to time t5, the vertical transfer clock φV1, the vertical transfer clock φV2, the vertical transfer clock φV3 (φV3x or φV3y), and the vertical transfer clock φV4 are sequentially input to the four transfer electrodes 6a, 6b, 6c, and 6d. In this case, the signal charge is transferred in the direction of the charge storage unit 3 (vertical transfer direction). Also, from time t1 to time t5, the vertical transfer clock φV1, the vertical transfer clock φV4, the vertical transfer clock φV3 (φV3x or φV3y), and the vertical transfer clock φV2 are sequentially applied to the four transfer electrodes 6a, 6b, 6c, and 6d. In the case of input, the signal charge is transferred in the direction of the charge discharge drain portion 4 (reverse vertical transfer direction). That is, in the CCD image sensor, among the vertical transfer clocks φV1, φV2, φV3 (φV3x or φV3y), φV4 input to the four transfer electrodes 6a, 6b, 6c, 6d, for example, the vertical transfer clock φV2 and the vertical transfer clock φV4 Is reversed to reverse the direction of vertical transfer of signal charges.

  An operation of the unit cell circuit 20-1 of the vertical shift register circuit 20 of FIG. 13 will be described.

  In FIG. 13, when the trigger clock signal φT1 is set to the high level, the transmission gate 21a is turned on and the output of the previous stage is input to the inverter 22a, and the output of the inverter 22a becomes the inverted output of the previous stage. When the unit cell circuit 2-1 is in the first stage, the TDI transfer stage designation signal φTS input to the input pin 19c is input to the inverter 22a instead of the output of the previous stage, and the output of the inverter 22a is the TDI transfer stage designation signal. φTS inverted output. Next, when the trigger clock signal φT1 is set to the low level, the transmission gate 21a is turned off, and the input and output of the inverter 22a are held as they are. Next, when the trigger clock signal φT2 input to the input pin 19b is set to the high level, the transmission gate 22b is turned on, the output of the inverter 22a is input to the inverter 22b, and the output of the inverter 22b becomes the inverted output of the inverter 22a. This output is transmitted to the unit cell circuit 15-1 of the line selection circuit 15 as an output signal from the unit cell circuit 2-1. Next, when the trigger clock signal φT2 is set to the low level, the transmission gate 21b is turned off, and the input and output of the inverter 22b are held as they are. Further, when the trigger clock signal φT1 is set to the high level, the series of operations so far are repeated. The operations of the unit cell circuits 20-2 to 20-8 of the vertical shift register circuit 20 are the same as those of the unit cell circuit 20-1.

  As described above, in the vertical shift register circuit 20, the clock pulses of the TDI transfer stage designation signal φTS input from the input pin 19c are sequentially transmitted to the next stage one by one, and each unit cell circuit 20-1 to 20-20. The output signal from −8 is transmitted to the unit cell circuits 15-1 to 15-8 of the line selection circuit 15, respectively.

  Next, the operation of the unit cell circuit 15-1 of the line selection circuit 15 in FIG. 15 will be described.

  In FIG. 15, when the signal level of the output signal from the unit cell circuit 20-1 is high, the transmission gate 23a is turned on, the input pin 14b is connected to the selection line SLb, and the vertical transfer clock φV2 is applied to the transfer electrode 6b. Entered. When the signal level of the output signal from the unit cell circuit 20-1 is low, the transmission gate 23b is turned on, the input pin 14d is connected to the selection line SLb, and the vertical transfer clock φV4 is input to the transfer electrode 6b. The

  When the signal level of the output signal from the unit cell circuit 20-1 is high, the transmission gate 23c is turned on, the input pin 14d is connected to the selection line SLd, and the vertical transfer clock φV4 is input to the transfer electrode 6d. When the signal level of the output signal from the unit cell circuit 20-1 is low, the transmission gate 23d is turned on, the input pin 14b is connected to the selection line SLd, and the vertical transfer clock φV2 is input to the transfer electrode 6d. The

  As described above, the unit cell circuits 15-1 to 15-8 of the line selection circuit 15 are vertically input to the transfer electrodes (6b, 6d) based on the signal level of the output signal from the unit cell circuit 20-1. Control is performed so that the transfer clocks (φV2, φV4) are switched. That is, the line selection circuit 5 inputs the vertical transfer clock φV2 to the selection line SLd and inputs the vertical transfer clock φV2 to the selection line SLb based on each selection signal, and sends the signal charge to the horizontal CCD circuit 2 in the direction. Is controlled to transfer vertically in the opposite direction.

  FIG. 17 is a time axis waveform diagram showing signal level changes with respect to time t of the TDI transfer stage designation signal φTS and trigger clock signals φT1 and φT2 input to the vertical shift register circuit 20 of FIG. FIG. 18 is a schematic diagram illustrating a state of the vertical shift register circuit 20 at times t1 to t8 in FIG. 17. Here, the input TDI transfer stage designation signal φTS is a clock pulse indicating the input clock to the CCD image sensor, and FIG. 17 shows the output signal of the vertical shift register circuit 2 at time t1 to t8 in time series. Shown for each.

  17 and 18, the vertical shift register circuit 20 is initialized at time t0. Next, at time t1, the trigger clock signals φT1 and φT2 are sequentially set to the high level while the TDI transfer stage designation signal φTS is kept at the high level. As a result, at time t1, the signal level of the output signal from the unit cell circuit 20-1 is set to a high level. At time t2, the trigger clock signals φT1 and φT2 are sequentially set to the high level while the TDI transfer stage designation signal φTS is kept at the high level. As a result, at time t2, the signal level of the output signal from the unit cell circuit 20-1 is set to the high level, the signal level held by the unit cell circuit 20-1 advances by one step, and the unit cell circuit 20-2 The signal level of the output signal is high. At time t3, the trigger clock signals φT1 and φT2 are sequentially set to the high level while the TDI transfer stage specifying signal φTS is kept at the high level. As a result, at time t3, the signal level of the output signal from the unit cell circuit 20-1 is set to a high level, and the signal level held by the unit cell circuit 20-1 and the signal level held by the unit cell circuit 20-2 are set. The signal level of the output signal from the unit cell circuit 20-2 goes high, and the signal level of the output signal from the unit cell circuit 20-3 goes high. The same applies to the following, and at time t8, the TDI transfer stage designation signal φTS input to the vertical shift register circuit 20 of FIG. 13 is schematically represented. In the present embodiment, the TDI transfer stage designation signal φTS controls the number of TDI stages to five. Here, the signal levels transmitted to the unit cell circuits 15-1 to 15-8 of the line selection circuit 15 of the CCD image sensor are shown. This will be briefly described below.

  When all the signals of one clock pattern of the TDI transfer stage designation signal φTS are prepared in the vertical shift register circuit 20, the signals are simultaneously given to the line selection circuit 15 of the CCD image sensor. Thereby, the setting of the number of TDI stages of each CCD image sensor is completed, and the mode shifts to the imaging mode.

  FIG. 19A is a time axis waveform diagram showing changes in signal level with respect to time t of vertical transfer clocks φV1, φV2, φV3x, V3y, and φV4 inputted to the transfer electrode 6 of FIG. That is, it is a timing chart of the vertical transfer clocks φV1, φV2, φV3x, V3y, and φV4 input to the four-phase driving CCD image sensor of FIG.

  19B and 19C are potential diagrams showing the transfer operation of the four-phase drive at each time t in FIG. 19A. That is, FIG. 19B and FIG. 19C schematically show the distribution pattern of the potential well of the transfer channel at times t1 to t9. Here, FIG. 19B shows a case where the vertical transfer clock φV3x having the same amplitude voltage as the vertical transfer clocks φV1, φV2, and φV4 is selected as an input signal to the selection line SLc, and FIG. 19C shows the selection. A case where the vertical transfer clock φV3y having an amplitude voltage smaller than the vertical transfer clocks φV1, φV2, and φV4 is selected as an input signal to the line SLc is shown. A dotted line shown in the potential diagram indicates a threshold level Vth at which charges are discharged to the horizontal overflow drain 7 when the pixel 1 is saturated.

  As shown in FIG. 19A, charges generated by photoelectric conversion are time-delay integrated and vertically transferred using a plurality of vertical transfer clocks φV1, φV2, φV3x, V3y, and φV4, respectively. At this time, as shown in FIGS. 19B and 19C, the potential well formed in the transfer channel moves to the right in the drawing with time. The saturation charge amount of the pixel 1 is determined by the minimum value of the well capacity during the time t1 to t9. Accordingly, in the case of FIG. 19B, the maximum accumulated charge amount at time t2, t4, t6, or t8 is given. On the other hand, in the case of FIG. 19C, since the potential well formed in the transfer channel by the vertical transfer clock φV3y becomes shallower than in FIG. 19B, the saturation charge amount of the pixel 1 is the maximum accumulated charge amount at time t6 or t8. Determined by The saturation charge amount of the pixel 1 increases / decreases in accordance with the amplitude voltage of the vertical transfer clock, and the saturation charge amount at the amplitude voltage of the vertical transfer clock φV3y decreases by the amount that the amplitude voltage of the vertical transfer clock φV3x is set small. Become.

  FIG. 20 is a schematic diagram for explaining the operation of the pixel saturation control circuit 50 of FIG. FIG. 20 shows an example in which the pixel saturation control circuit 50 selectively switches the saturation charge amount of each pixel 1 in units of rows. For a TDI type CCD image sensor in which the number of TDI stages is 8 in all stages, The case where the saturation charge amount Q1 of each pixel 1 with pixel numbers 1 to 5 is larger than the saturation charge amount Q2 of each pixel 1 with pixel numbers 6 to 8 is shown.

  FIG. 21 is a schematic diagram for explaining the operation of the TDI stage number setting circuit 60 of FIG. FIG. 21 shows an example of setting the integration stage number at the time of imaging by the TDI stage number setting circuit 60. The TDI transfer integration stage number is set for a TDI type CCD image sensor having 8 TDI stages in all. The case of setting to 5 levels is shown.

  FIG. 22A is a graph showing the change in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the conventional CCD image sensor when the incident light intensity is low and medium. 22B is a graph showing a change in the amount of output charge with respect to the incident light intensity P in FIG. 22A. Here, the amount of signal charge that is vertically transferred increases in proportion to the number of TDI stages, and the saturation charge amount of each pixel 1 is constant in the entire region of the pixel group 100.

  In FIG. 22A, in a general TDI type CCD image sensor, a change in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number when uniform light is incident on the entire region of the pixel group 100 and the TDI operation is performed. The signal charges accumulated in each pixel 1 are vertically transferred by time delay integration from the pixel 1 of the pixel number M to the pixel of the pixel number 1 toward the lower side of the drawing. Here, the change in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number when the incident light intensity P is large (graph II) and when the incident light intensity P is small (graph I) is shown. When the light intensity P is high (graph II), the signal charge amount Q accumulated in the pixel number n reaches the saturation charge amount Q1 and overflows.

  FIG. 22B shows the change in the amount of output charge with respect to the incident light intensity P when the TDI operation is performed with uniform light incident on the entire region of the pixel group 100. Here, the output charge amount corresponds to the signal charge amount Q accumulated in the pixel number 1 in FIG. 22A. Further, when the saturation charge amount of each pixel 1 is constant in the entire region of the pixel group 100, the “knee characteristic” does not appear in the input / output characteristics as shown in FIG. 22B.

  FIG. 23A is a graph showing a change in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor in FIG. 1 when the incident light intensity is low (graph I) and medium (graph II). It is. FIG. 23B is a graph showing a change in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor in FIG. 1 when the incident light intensity is high (graph III). FIG. 23C is a graph showing changes in the amount of output charge with respect to the incident light intensity P in FIGS. 23A and 23B. Here, the pixel saturation control circuit 50 sets the saturation charge amount Q2 for each pixel 1 of pixel numbers 100 to (S + 1), and the saturation charge for each pixel 1 of pixel numbers S to 1. Set to the quantity Q1 (Q2 <Q1). The TDI stage number setting circuit 60 controls the number of stages of time delay integration of the CCD image sensor. That is, the TDI stage number setting circuit 60 performs control so that the signal charge amount accumulated in each pixel 1 of the pixel numbers M to 1 is vertically transferred to the horizontal CCD circuit 2.

  As shown in FIG. 23A, when the incident light intensity is small (graph I), the accumulated signal charge amount does not reach the saturation charge amount Q1 of each pixel 1 and does not overflow, but the incident light intensity is medium ( In the graph II), the signal charge amount Q accumulated up to pixel numbers M to (S + 1) exceeds the saturation charge amount Q2 and overflows. Thereafter, the signal charge amount Q accumulated in the pixel numbers S to 1 does not reach the saturation charge amount Q1 and does not overflow.

  As shown in FIG. 23B, when the incident light intensity is higher (graph III), the signal charge amount Q accumulated from the pixel number M becomes equal to or greater than the saturation charge amount Q2 and overflow occurs. Thereafter, the signal charge amount Q accumulated from the pixel number S reaches the saturation charge amount Q1 and overflows.

  As shown in FIG. 23C, the output charge amount of the CCD image sensor of FIG. 1 has a bending point at the incident light intensity P1, overflows above the incident light intensity P2, and the output charge amount becomes almost constant. That is, by providing a bending point, it is possible to obtain “knee characteristics” in the input / output characteristics of the CCD image sensor. Here, the incident light intensity 0 to P1 is set as a small incident light intensity (corresponding to the graph I in FIG. 23A), and the incident light intensity P1 to P2 is set as a medium incident light intensity (corresponding to the graph II in FIG. 23A). The incident light intensity P2 to P3 is set to a large incident light intensity (corresponding to the graph III in FIG. 23B). The slope from incident light intensity 0 to P1 is proportional to the number of TDI stages (M stage in the present embodiment), and the slope from incident light intensity P1 to P2 is the number of stages of pixel 1 set to the saturation charge amount Q1. In this embodiment, it is proportional to S. The values of the saturation charge amounts Q1 and Q2 can be changed by the amplitude voltage with respect to the time t of the vertical transfer clocks φV1, φV2x, φV2y, and φV3. When the pixel number S and the saturation charge amounts Q1 and Q2 are changed, the inclination of the graph and the position of the bending point can be changed in the “knee characteristics” shown in FIG. 11C.

  According to the CCD image sensor according to the above embodiment, the same effects as those of the first embodiment can be obtained. Furthermore, since the number of TDI stages (number of TDI transfer integration stages) can be further changed as compared with the first embodiment, the adjustment range of the “knee characteristics” of the input / output characteristics at the time of low-luminance incidence can be further expanded. It becomes.

Embodiment 3 FIG.
In the second embodiment described above, the amplitude voltage of the vertical transfer clock φV3 input to the transfer electrode 6c of each pixel 1 is changed to the amplitude of the vertical transfer clocks φV1, φV2, and φV4 input to the other transfer electrodes 6a, 6b, and 6d. The saturation charge amount of each pixel 1 was selectively switched in units of rows by making it smaller than the voltage. On the other hand, in this embodiment, the clock widths of the vertical transfer clock φV1 input to the transfer electrode 6a of each pixel 1 and the vertical transfer clock φV3 input to the transfer electrode 6c of each pixel 1 are set to the width of each pixel 1. The saturation charge amount of each pixel 1 is selectively selected in units of rows by making it smaller than the clock width of the vertical transfer clock φV2 input to the transfer electrode 6b and the vertical transfer clock φV4 input to the transfer electrode 6d of each pixel 1. It is characterized by switching. Here, in the vertical transfer clocks φV1 and φV3, vertical transfer clocks having the same clock width as the vertical transfer clocks φV2 and φV4 are defined as vertical transfer clocks φV1x and φV3x, respectively, and from the clock widths of the vertical transfer clocks φV2 and φV4 Are vertical transfer clocks φV1y and φV3y, respectively.

  FIG. 24 is an element plan view of the CCD image sensor according to Embodiment 3 of the present invention. Compared with the CCD image sensor of FIG. 13, the CCD image sensor of FIG. 24 includes a pixel saturation control circuit 50A instead of the pixel saturation control circuit 50, and instead of inputting the vertical transfer clock φV1 from the input pin 14a to the selection line SLa. Further, the output signal from the pixel saturation control circuit 50A is inputted to the selection line SLa as the vertical transfer clock φV1.

  Compared with the pixel saturation control circuit 50 of FIG. 13, the pixel saturation control circuit 50A includes unit cell circuits 25A-1 to 25A-8 instead of the line selection circuit 25 including the unit cell circuits 25-1 to 25-8. A line selection circuit 25A is provided. Here, the line selection circuit 25A determines the saturation charge of each pixel 1 based on a plurality of selection signals indicating connection states between a vertical transfer clock having the first clock width or the second clock width and a plurality of transfer electrodes. Selectively switch quantities by line.

  FIG. 25 is a block diagram showing components of the unit cell circuit 25A-1 of the line selection circuit 25A of FIG. In FIG. 25, the unit cell circuit 25A-1 includes a transmission gate 44a composed of one NMOS transistor 42a and one PMOS transistor 43a, one NMOS transistor 42b and one PMOS transistor 43b. A transmission gate 44b configured, a transmission gate 44c configured by one NMOS transistor 42c and one PMOS transistor 43c, a transmission configured by one NMOS transistor 42d and one PMOS transistor 43d. The gate 41d, the inverter 41a whose output terminal is connected to the gate terminal of the PMOS transistor 43a and the gate terminal of the NMOS transistor 42b, and the gate terminal of the PMOS transistor 43c Constructed and an inverter 41b which output terminal to the gate terminal of the 42d NMOS transistor is connected.

  In FIG. 25, one end of the transmission gate 44a and the transmission gate 44b is connected to the selection line SLa connected to the transfer electrode 6a, and the other end of the transmission gate 44a is connected to the input pin 42x via the metal wiring 41x. The other end of the transmission gate 44b is connected to the input pin 42y through the metal wiring 41y. Further, one end of the transmission gate 44c and the transmission gate 44d is connected to the selection line SLc connected to the transfer electrode 6c, and the other end of the transmission gate 44c is connected to the input pin 44x via the metal wiring 43x. The other end of the gate 44d is connected to the input pin 44y through the metal wiring 43y.

  The input gates of the NMOS transistors 42a and 42c of the transmission gates 44a and 44c and the input gate of the PMOS transistor 43d of the transmission gate 44d are connected to the unit cell circuit 30-1 of FIG. The input gate of the NMOS transistor 42a of the transmission gate 44a, the input gate of the PMOS transistor 43d of the transmission gate 44d, and the input terminals of the inverters 41a and 41b are connected to each other.

  The operation of the CCD image sensor configured as described above will be described below. In the following description, the signal levels of the vertical transfer clock φV1 to the vertical transfer clock φV4, the selection signal included in the TDI transfer stage designation signal φTS, and the trigger clock signals φT1 and φT2 are set to the high level or the low level. Note that these signal levels may be binary signals having first or second levels other than binary signals of high level and low level.

  The operation of the unit cell circuit 25A-1 of the line selection circuit 25A of FIG. 25 will be described.

  When the signal level of the output signal from the unit cell circuit 30-1 is high, the transmission gate 44a is turned on, the input pin 42x is connected to the selection line SLa, and the vertical transfer clock φV1x is input to the transfer electrode 6a. When the signal level of the output signal from the unit cell circuit 30-1 is low, the transmission gate 44b is turned on, the input pin 42y is connected to the selection line SLa, and the vertical transfer clock φV1y is input to the transfer electrode 6a. The

  When the signal level of the output signal from the unit cell circuit 30-1 is high, the transmission gate 44c is turned on, the input pin 44x is connected to the selection line SLc, and the vertical transfer clock φV3x is input to the transfer electrode 6c. When the signal level of the output signal from the unit cell circuit 30-1 is low, the transmission gate 44d is turned on, the input pin 44y is connected to the selection line SLc, and the vertical transfer clock φV3y is input to the transfer electrode 6c. The

  As described above, the unit cell circuits 25A-1 to 25A-8 of the line selection circuit 25A are input to the transfer electrodes (6a, 6c) based on the signal level of the output signal from the unit cell circuit 30-1. Control is made so that the clock width of the vertical transfer clocks (φV1, φV3) is the same as or smaller than the clock width of the vertical transfer clocks (φV2, φV4) input to the other transfer electrodes (6b, 6d).

  26A is a time axis waveform diagram showing changes in signal level with respect to time t of vertical transfer clocks φV1x, φV2, φV3x, and φV4 input to the transfer electrode 6 of FIG. That is, it is a timing chart of vertical transfer clocks φV1x, φV2, φV3x, and φV4 inputted to the four-phase driving CCD image sensor of FIG. Here, the clock widths of the four vertical transfer clocks φV1x, φV2, φV3x, and φV4 are all the same.

  FIG. 26B is a potential diagram showing the transfer operation of the four-phase drive at each time t in FIG. 26A. That is, FIG. 26B schematically shows the pattern of the potential well distribution of the transfer channel at times t1 to t9. As shown in FIG. 26B, the charges generated by the photoelectric conversion are time-delay integrated and vertically transferred using a plurality of vertical transfer clocks φV1x, φV2, φV3x, and φV4, respectively. At this time, the potential well formed in the transfer channel moves to the right in the drawing with time. The saturation charge amount of the pixel 1 is determined by the minimum value of the well capacity during the time t1 to t9. Accordingly, since the width of the potential well formed under the transfer gate at time t2, t4, t6, or t8 is from three gates to two gates, the saturation charge amount of the pixel 1 is the maximum accumulation of two gates. It is given by the amount of charge.

  FIG. 27A is a time axis waveform diagram showing changes in signal level with respect to time t of vertical transfer clocks φV1y, φV2, φV3y, and φV4 inputted to the transfer electrode 6 of FIG. That is, it is a timing chart of vertical transfer clocks φV1y, φV2, φV3y, and φV4 input to the four-phase driving CCD image sensor of FIG. Here, the clock widths of the vertical transfer clocks φV1y and φV3y are smaller than the clock widths of the vertical transfer clocks φV2 and φV4.

  FIG. 27B is a potential diagram showing the transfer operation of the four-phase drive at each time t in FIG. 27A. That is, FIG. 27B schematically shows the distribution pattern of the potential well of the transfer channel at times t1 to t9. In FIG. 27B, compared with FIG. 26B, the clock widths of the vertical transfer clocks φV1y and φV3y are smaller than the clock widths of the vertical transfer clocks φV2 and φV4, so one potential well is formed below the transfer gate at time t5. Only the width of minutes. Therefore, the saturation charge amount of the pixel 1 is given by the maximum accumulated charge amount for one gate. That is, the saturation charge amount when driving with the clock pattern shown in FIG. 26A is different from the saturation charge amount when driving with the clock pattern shown in FIG. 27A.

  FIG. 28 is a schematic diagram for explaining the operation of the pixel saturation control circuit 50A of FIG. FIG. 28 shows an example in which the pixel saturation control circuit 50A selectively switches the saturation charge amount of each pixel 1 in units of rows. For a TDI type CCD image sensor in which the number of TDI stages is 8 in all stages, The case where the saturation charge amount Q1 of each pixel 1 with pixel numbers 1 to 5 is larger than the saturation charge amount Q2 of each pixel 1 with pixel numbers 6 to 8 is shown.

  According to the CCD image sensor according to the above embodiment, the same effect as that of the CCD image sensor according to the embodiment 2 can be obtained.

Embodiment 4 FIG.
In the second embodiment described above, the saturation charge amount of each pixel 1 is selectively switched with the pixel 1 in the pixel row S as a boundary. On the other hand, this embodiment is characterized in that only the saturation charge amount of the pixel 1 in at least one pixel row is changed. In order to simplify the description, the number of TDI stages of the CCD image sensor is set to eight.

  FIG. 29 is an element plan view of a CCD image sensor according to Embodiment 4 of the present invention. Compared with the CCD image sensor of FIG. 24, the CCD image sensor of FIG. 29 has an input pin instead of the output signals from the pixel saturation control circuit 50A being input to the selection lines SLa and SLc as the vertical transfer clocks φV1 and φV3, respectively. The vertical transfer clocks φV1 and φV3 are input to the selection lines SLa and SLc via 11a and 11c (or 45x to 45z), respectively. Here, the vertical transfer clock φV3z is input to the transfer electrode 6c of the pixel 1 with the pixel number 2 through the input pin 45z, and the transfer electrode 6c of the pixel 1 with the pixel number 3 is input to the transfer electrode 6c in the vertical direction through the input pin 45y. The transfer clock φV3y is input, and the vertical transfer clock φV3x is input to the transfer electrode 6c of the pixel 1 with the pixel number 4 through the input pin 45x.

  The CCD image sensor configured as described above performs the same operation as the CCD image sensor according to the second embodiment described above. Here, the amplitude voltage of only one of the vertical transfer clocks φV3x, φV3y, φV3z is made smaller than the amplitude voltage of the vertical transfer clocks φV1, φV2, φV4, and the other two are the vertical transfer clocks φV1, φV2. , ΦV4 and the same amplitude voltage. When a vertical transfer clock having the same amplitude voltage as the vertical transfer clocks φV1, φV2, and φV4 is input, the saturation charge amount Q2 is set, and a vertical transfer clock smaller than the amplitude voltages of the vertical transfer clocks φV1, φV2, and φV4 is set. When input, the saturation charge amount Q1 (Q1> Q2) is set. Further, the number of TDI stages is set to M stages.

  FIG. 30A is a graph showing a change in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor in FIG. 29 when the incident light intensity is low (graph I) and medium (graph II). It is. FIG. 30B is a graph showing a change in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor in FIG. 29 when the incident light intensity is high (graph III). FIG. 30C is a graph showing a change in the amount of output charge with respect to the incident light intensity P in FIGS. 30A and 30B.

  As shown in FIGS. 30A to 30B, the amplitude voltage of the vertical transfer clock φV3 applied to the row corresponding to the pixel number S is reduced, and the saturation charge amount Q2 is set to the pixel 1 of the pixel number S.

  As shown in FIG. 30A, when the incident light intensity is low (graph I), the accumulated signal charge amount does not reach the saturation charge amount Q1 of each pixel 1 and does not overflow, but the incident light intensity is medium ( In the graph II), during the TDI transfer between the pixel numbers M to (S + 1), the accumulated signal charge amount Q does not overflow if the saturation charge amount Q1 or less, and the saturation charge amount Q1 or more. If it overflows. Next, when the TDI transfer is performed to the pixel 1 with the pixel number S, the accumulated signal charge amount Q exceeds the saturation charge amount Q2 and overflows, and the accumulated signal charge amount Q once exceeds the value of the saturation charge amount Q2. Become. Thereafter, the signal charge amount Q accumulated in the pixel numbers S to 1 does not reach the saturation charge amount Q1 and does not overflow.

  As shown in FIG. 30B, when the incident light intensity is even higher (graph III), the signal charge amount Q accumulated from the pixel number M overflows at the pixel 1 of the pixel number S and once reaches the value of the saturation charge amount Q2. It becomes. Thereafter, the signal charge amount Q accumulated in the pixel numbers S to 1 reaches the saturation charge amount Q1 and overflows.

  As shown in FIG. 30C, the output charge amount of the CCD image sensor of FIG. 29 has a bending point at the incident light intensity P1, overflows above the incident light intensity P2, and the output charge amount becomes almost constant. That is, by providing a bending point, it is possible to obtain “knee characteristics” in the input / output characteristics of the CCD image sensor. Here, the incident light intensity 0 to P1 is set as a small incident light intensity (corresponding to the graph I in FIG. 30A), and the incident light intensity P1 to P2 is set as a medium incident light intensity (corresponding to the graph II in FIG. 30A). The incident light intensity P2 to P3 is set to a large incident light intensity (corresponding to the graph III in FIG. 30B). The slope from incident light intensity 0 to P1 is proportional to the number of TDI stages (M stage in the present embodiment), and the slope from incident light intensity P1 to P2 is the number of stages of pixel 1 set to the saturation charge amount Q1. In this embodiment, it is proportional to S.

  According to the CCD image sensor according to the above embodiment, the same effects as those of the second embodiment can be obtained. Furthermore, compared with the second embodiment, the circuit for setting the number of TDI stages can be omitted, so that the circuit scale can be reduced.

Embodiment 5. FIG.
In the above-described fourth embodiment, the amplitude voltage of one of the vertical transfer clocks φV3x, φV3y, φV3z input from the input pins 45x, 45y, 45z is made smaller than the amplitude voltage of the vertical transfer clocks φV1, φV2, φV4. The remaining two amplitude voltages are the same as the amplitude voltages of the vertical transfer clocks φV1, φV2, and φV4.

  On the other hand, in the present embodiment, in the CCD image sensor of FIG. 29, one of the vertical transfer clocks φV3x, φV3y, and φV3z input from the input pins 45x, 45y, and 45z is converted into the vertical transfer clock φV1. , ΦV2 and φV4 are set to an amplitude voltage V10 smaller than the amplitude voltage, and another amplitude voltage is set to an amplitude voltage V20 smaller than the amplitude voltage V10. Here, the vertical transfer clock of the amplitude voltage V10 is input to the transfer electrode 6c of the pixel 1 of the pixel number S2, and the vertical transfer clock of the amplitude voltage V20 is input to the transfer electrode 6c of the pixel 1 of the pixel number S3. The The pixel 1 with the pixel number S2 is set to the saturation charge amount Q2, the pixel 1 with the pixel number S3 is set to the saturation charge amount Q3, and the other pixels 1 have the saturation charge amount Q1 (Q1> Q2> Q3). Is set.

  FIG. 31A shows accumulation in each pixel 1 for the pixel number of the CCD image sensor of FIG. 29 when the incident light intensity is small (graph I) and medium (graph II) according to the fifth embodiment of the present invention. It is a graph which shows the change of the signal charge amount made. FIG. 31B shows the change in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor in FIG. 29 when the incident light intensity is slightly high (graph III) according to Embodiment 5 of the present invention. It is a graph to show. FIG. 31C shows a change in the amount of signal charge accumulated in each pixel 1 with respect to the pixel number of the CCD image sensor in FIG. 29 when the incident light intensity is high (graph IV) according to Embodiment 5 of the present invention. It is a graph. FIG. 31D is a graph showing a change in the amount of output charge with respect to the incident light intensity P in FIGS. 31A to 31C.

  As shown in FIG. 31A, when the incident light intensity is small (graph I), the accumulated signal charge amount does not reach the saturation charge amount Q1 of each pixel 1 and does not overflow, but the incident light intensity is medium ( In the graph II), during the TDI transfer between the pixel numbers M to (S3 + 1), the accumulated signal charge amount Q does not overflow if the saturation charge amount Q1 is less than or equal to the saturation charge amount Q1 or more. If it overflows. Next, when TDI transfer is performed to the pixel 1 with the pixel number S3, the accumulated signal charge amount Q overflows beyond the saturated charge amount Q3, and the accumulated signal charge amount Q is temporarily set to the value of the saturated charge amount Q3. Become. Thereafter, the signal charge amount Q accumulated in the pixel numbers S3 to 1 does not reach the saturation charge amount Q1 and does not overflow.

  As shown in FIG. 31B, when the incident light intensity is slightly high (graph III), the signal charge amount Q accumulated from the pixel number M overflows at the pixel 1 of the pixel number S3 and once reaches the value of the saturation charge amount Q3. It becomes. Thereafter, the signal charge amount Q accumulated in the pixel numbers S3 to (S2 + 1) reaches the saturation charge amount Q2, overflows, and temporarily becomes the value of the saturation charge amount Q2. Thereafter, the signal charge amount Q accumulated in the pixel numbers S2 to 1 does not reach the saturation charge amount Q1 and does not overflow.

  As shown in FIG. 31C, when the incident light intensity is high (graph IV), the signal charge amount Q accumulated from the pixel number M overflows at the pixel 1 of the pixel number S3 and once reaches the value of the saturation charge amount Q3. Become. Thereafter, the signal charge amount Q accumulated in the pixel numbers S3 to (S2 + 1) reaches the saturation charge amount Q2, overflows, and temporarily becomes the value of the saturation charge amount Q2. Thereafter, the signal charge amount Q accumulated in the pixel numbers S2 to 1 reaches the saturation charge amount Q1 and overflows.

  As shown in FIG. 31D, the output charge amount of the CCD image sensor in FIG. 29 has a bending point at the incident light intensities P1 and P2, and overflows at the incident light intensity P3 or more, and the output charge amount becomes almost constant. That is, by providing a bending point, it is possible to obtain “knee characteristics” in the input / output characteristics of the CCD image sensor. Here, the incident light intensity from 0 to P1 is set as a small incident light intensity (corresponding to the graph I in FIG. 31A), and the incident light intensity from P1 to P2 is set as a medium incident light intensity (corresponding to the graph II in FIG. 31A). The incident light intensities P2 to P3 are set to be slightly higher (corresponding to the graph III in FIG. 31B), and the incident light intensities P3 to P4 are set to be higher (corresponding to the graph IV in FIG. 31C). . Further, the slope from incident light intensity 0 to P1 is proportional to the number of TDI stages (M stage in the present embodiment), and the slope from incident light intensity P1 to P2 is the number of stages of pixel 1 set to the saturation charge amount Q3. (S3 in this embodiment) and the slope from incident light intensity P2 to P3 is proportional to the number of stages of pixels 1 (S2 in this embodiment) set to the saturation charge amount Q2.

  According to the CCD image sensor according to the above embodiment, the same effect as in the fourth embodiment can be obtained. Furthermore, as compared with the fourth embodiment, the number of bending points of the “knee characteristics” of the CCD image sensor increases, so that smoother input / output characteristics can be obtained.

  In the fifth embodiment described above, the case where the amplitude voltage of the vertical transfer clock φV3 is set in three stages has been described, but the present invention is not limited to this. For example, by setting four or more steps, the input / output characteristics of the CCD image sensor can be controlled more smoothly.

  In the above-described embodiment, the case of three-phase driving and four-phase driving has been described, but the present invention is not limited to this. For example, the present invention can be applied even when the number of phases is other than that.

  In the embodiment described above, the saturation charge amount is changed by changing the amplitude voltage and clock width of the clock, but the present invention is not limited to this. For example, the saturation charge amount may be changed by changing the clock delay, rise time, fall time, or the like. Even in this case, the same effect as the present embodiment can be obtained.

  In the present embodiment described above, the number of TDI stages is set to eight. However, the present invention is not limited to this, and the number of TDI stages of the CCD image sensor may be set to an arbitrary value. Even in this case, the same effect as the present embodiment can be obtained.

  As described above in detail, according to the CCD image sensor of the present invention, the saturation charge amount of each pixel can be selectively switched in units of rows, so that the “knee characteristics” in the input / output characteristics of the CCD image sensor can be reduced. It is possible to adjust according to the imaging scene.

  1 pixel, 2 horizontal CCD circuit, 3 charge storage section, 4 charge discharge drain section, 5 output circuit, 6, 6a, 6b, 6c, 6d transfer electrode, 7 overflow drain, 15 line selection circuit, 15-1 to 15- 8 unit cell circuit, 18a to 18d, 42a to 42d NMOS transistor, 19a to 19d, 43a to 43d PMOS transistor, 20 vertical shift register circuit, 20-1 to 20-8 unit cell circuit, 23a to 23d, 44a to 44d Transmission Gate, 25, 25A line selection circuit, 25-1 to 25-8, 25A-1 to 25A-8 unit cell circuit, 30 vertical shift register circuit, 30-1 to 30-8 unit cell circuit, 21a, 21b, 31a 31b Transmission gates 17a, 17b, 22a, 22b, 32a, 32b 35a, 41a, 41b inverter, 50, 50A pixel saturation control circuit, 52 P-type silicon substrate, 53 insulating film, 54 gate oxide film, 55 transfer channel, 60 TDI stage number setting circuit, 71 overflow gate, 72 overflow drain region, 73 P-type impurity region, 74 high-concentration P-type impurity region, 100 pixel group.

Claims (7)

A CCD image sensor comprising a plurality of pixel groups in which a plurality of pixels for two-dimensionally arranging a plurality of pixels for time-delay integration of charges generated by photoelectric conversion and vertically transferring using a plurality of vertical transfer clocks. ,
A plurality of transfer electrodes for vertically transferring the signal charge accumulated in each pixel by time delay integration;
Provided for each of the pixels, and a means for discharging charges generated exceeding the saturation charge amount of the pixels;
A horizontal transfer section for horizontally transferring the signal charge integrated with the time delay;
A plurality of selection lines respectively connected to the transfer electrodes;
A first line selection circuit for connecting a plurality of first vertical transfer clocks to a predetermined corresponding one of the plurality of selection lines;
Corresponding to a plurality of first selection signals, each of which is composed of a plurality of unit cell circuits, and represents a connection state of each of the first vertical transfer clocks in the first line selection circuit. A first vertical shift register circuit held in the unit cell circuit,
The first line connection state of the in the selection circuits each first vertical transfer clock, Ri whether the connection status der selectively switches the saturation charge amount of each pixel,
The first line selection circuit selects and outputs one of the plurality of first vertical transfer clocks based on the plurality of first selection signals, whereby the saturated charge of each pixel is output. A CCD image sensor , wherein the amount is controlled to be selectively switched in units of rows . Each of the first selection signals is a binary signal having a first or second level,
The first line selection circuit, CCD image sensor according to claim 1, wherein the switch based on the respective first selection signal, selectively the saturation charge amount of the pixel of each pixel row. A second line selection circuit for connecting a plurality of second vertical transfer clocks to a predetermined corresponding one of the plurality of selection lines;
Corresponding to a plurality of second selection signals, each of which is composed of a plurality of unit cell circuits, and represents a connection state of each of the second vertical transfer clocks in the second line selection circuit. A second vertical shift register circuit held in the unit cell circuit for
The connection state of each of the second vertical transfer clocks in the second line selection circuit is a connection state of whether or not to vertically transfer the signal charge to the horizontal transfer unit,
The second line selection circuit determines whether or not to replace a predetermined pair of vertical transfer clocks among the plurality of second vertical transfer clocks based on the second selection signals. 3. The CCD image sensor according to claim 1, wherein the selection of whether or not the charge is vertically transferred to the horizontal transfer unit is controlled. 4. The CCD image sensor according to claim 3 , wherein the second line selection circuit controls the number of stages of time delay integration of the CCD image sensor based on the second selection signals. A method for driving a CCD image sensor comprising a plurality of pixel groups in which a plurality of pixels are two-dimensionally arranged for time-delay integration of charges generated by photoelectric conversion and vertical transfer using a plurality of vertical transfer clocks, respectively. Because
The CCD image sensor
A plurality of transfer electrodes for vertically transferring the signal charge accumulated in each pixel by time delay integration;
Provided for each of the pixels, and a means for discharging charges generated exceeding the saturation charge amount of the pixels;
A horizontal transfer section for horizontally transferring the signal charge integrated with the time delay;
A plurality of selection lines respectively connected to the transfer electrodes,
A step of line selection circuit, connected to a predetermined one corresponding select line of the plurality of selection lines,
Vertical shift register circuit, a step of holding the unit cell circuits corresponding to the plurality of selection signals indicating the connection state of each vertical transfer clocks in the line selection circuit,
The line selection circuit selectively switching the saturation charge amount of each pixel in units of rows based on a plurality of selection signals indicating connection states between the plurality of vertical transfer clocks and the plurality of transfer electrodes. See
By the switching operation of the line selection circuit, the saturation charge amount of pixels in at least one row of the plurality of pixels is set smaller than the saturation charge amount of the remaining pixels.
A method for driving a CCD image sensor. The plurality of vertical transfer clocks have a first amplitude voltage or a second amplitude voltage,
The line selection circuit has a saturation charge amount of each pixel based on a plurality of selection signals representing connection states between the vertical transfer clock having the first amplitude voltage or the second amplitude voltage and the plurality of transfer electrodes. 6. The method of driving a CCD image sensor according to claim 5 , wherein the switching is selectively performed in units of rows. The plurality of vertical transfer clocks have a first clock width or a second clock width,
The line selection circuit has a saturation charge amount of each pixel based on a plurality of selection signals representing connection states between a vertical transfer clock having the first clock width or the second clock width and the plurality of transfer electrodes. 6. The method of driving a CCD image sensor according to claim 5 , wherein the switching is selectively performed in units of rows.

Images