JP2016081397A - Design verification support device and design verification support method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate debugging of coverage, and to enable increase in verification efficiency.SOLUTION: A design verification support device comprises an information control unit that displays waveform information 100 on a logic simulation result of a logic circuit description in which a coverage extraction description indicative of presence or absence of occurrence of a prescribed event of a verification object circuit is added, a signal name of the waveform information 100 and a signal value thereof on a display device, extract a cover point name 101 indicative of the presence or absence of the prescribed event of the object circuit, an obtainable value 102 by the cover point and non-obtainable value 103 from the waveform information 100, and display cover group waveform information generated by associating a time and the cover point with the obtainable value and the non-obtainable value at the same time axis as with the waveform information 100 on the display device.SELECTED DRAWING: Figure 1A

Description

  The present invention relates to a design verification support apparatus and a design verification support method that support debugging of logic simulation results.

  In LSI development, a description method called a register transfer level (RTL) is used based on design specifications, and logic of a circuit is expressed by combining logical expressions. In order to verify whether or not the logic circuit designed in the RTL can realize the function and operation as specified, a logic simulation is executed using a computer. Also, functions and operations are extracted from the specifications of the target LSI as verification items, and a verification item table is created. The created verification item table is applied to the logic simulation to verify whether the function or operation is realized. At this time, it is confirmed that the completeness of verification, that is, there is no verification omission.

  For example, coverage is used as a measure of the completeness of verification. The coverage is an index indicating whether or not a certain condition, operation, or state has occurred, and includes a cover point name, a value that can be taken by each cover point (bins value), a value that cannot be taken (illegal_bins value), and the like. By using the coverage, it is possible to confirm whether an expected condition, operation, or state has occurred in the verification target, or whether an unexpected condition, operation, or state has not occurred. The coverage of the completeness of verification is acquired by the following procedure, for example.

1. In order to input the verification item to the logic simulator, the verification item is described using a cover group description of the System Verilog language.
2. Above 1. The logic simulation is executed with the description of.
3. 2. The coverage is obtained with the coverage analysis tool using the simulation result of.

  Based on the acquired coverage, the above 1. Debugging may be performed such as confirmation of time and signal value when a verification item described in a cover group is covered, confirmation of a condition where a verification item that should not be covered is covered, and the like. At this time, the above 3. In the coverage analysis tool used in, the cover time and signal value are not displayed. Therefore, when checking the cover time and signal value, a waveform viewer is used.

  The function of generating a waveform as a logical simulation result is realized by various companies that provide an EDA (Electronic Design Automation) tool as a waveform database. In addition, the waveform display (signal name and signal value) function is also realized by various companies that provide verification support tools as waveform viewers.

  For example, as a verification support technique, there is a technique for setting an identification number for identifying a difference in the execution contents of a simulation, and associating the identification number of the simulation for verifying the specified condition with the flag indicating the verified condition in the coverage information. is there. Also, items that verify the occurrence of events during operation simulation and items that verify occurrence violations using information that defines the circuit operation based on the signal of the circuit to be verified and the control file that describes the restrictions on the circuit operation There is a technique for generating and storing an associated item table. There is also a technique for measuring coverage related to a combination of a plurality of test inputs given in time series (for example, refer to Patent Documents 1 to 3 below).

JP 2010-267209 A JP 2013-206033 A JP 2003-345855 A

  However, according to the conventional technique, coverage (cover point name, possible value of each cover point, and impossible value) cannot be displayed on the waveform viewer. In addition, the time when the cross coverage that is a combination of a plurality of cover points is filled cannot be easily found on the waveform. As described above, conventionally, since the signal name and the information in the cover group cannot be displayed in association with the signal waveform on the waveform viewer, it is necessary to check the operation of the waveform viewer and the coverage analysis tool. As a result, coverage cannot be debugged easily when a cover group is used, and verification efficiency cannot be improved.

  In one aspect, an object of the present invention is to easily perform coverage debugging and improve verification efficiency.

  In one proposal, the waveform information of the logic simulation result of the logic circuit description with the description for coverage extraction indicating whether or not a predetermined event has occurred in the verification target circuit, and the signal name and signal value of the waveform information are displayed. A cover point that is displayed on a device and indicates the presence or absence of a predetermined event in the target circuit, and a value that can be taken and a value that cannot be taken are extracted from the waveform information, and a time, the cover point, and the value that can be taken And an information control unit that displays on the display device the cover group waveform information generated by combining the incapable values with the same time axis as the waveform information.

  According to one embodiment, coverage debugging can be easily performed, and verification efficiency can be improved.

FIG. 1A is a diagram (part 1) illustrating a display output example of the design verification support apparatus according to the embodiment. FIG. 1B is a second diagram illustrating a display output example of the design verification support apparatus according to the embodiment. FIG. 2 is a block diagram of a functional configuration example of the design verification support apparatus according to the embodiment. FIG. 3 is a diagram illustrating a description example of a verification target. FIG. 4 is a diagram illustrating a description example of a cover group. FIG. 5 is a chart showing an example in which the result of the coverage analysis tool is reflected in the cross coverage table. FIG. 6 is a diagram illustrating a waveform display example of the logic simulation result. FIG. 7 is a diagram illustrating an example of cover group information. FIG. 8A is a diagram (part 1) illustrating the generation of cover group waveform information. FIG. 8B is a diagram (part 2) illustrating generation of cover group waveform information. FIG. 9 is a flowchart illustrating an example of a confirmation process for a covered verification item. FIG. 10 is a diagram for explaining generation of item table information. FIG. 11 is a chart showing the display state of the item table. FIG. 12 is a diagram (part 1) for explaining the cooperative display of the waveform information and the item table. FIG. 13 is a diagram (part 2) illustrating the cooperative display of the waveform information and the item table. FIG. 14 is a flowchart illustrating an example of confirmation processing for a covered verification item. FIG. 15 is a block diagram of a hardware configuration example of the design verification support apparatus according to the embodiment. FIG. 16 is a flowchart showing the processing contents of cover group waveform information generation. FIG. 17 is a flowchart showing the processing contents of the cover group waveform display control. FIG. 18 is a flowchart showing the processing contents of item table information generation. FIG. 19 is a flowchart showing the processing contents of the item table display control.

  Exemplary embodiments of a design verification support apparatus and a conversion method according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Display example of design verification support device)
FIG. 1A and FIG. 1B are diagrams illustrating display output examples of the design verification support apparatus according to the embodiment. As shown in FIG. 1A, the design verification support apparatus according to the embodiment includes: On the same time axis as the waveform information (signal waveform) 100 of the existing logic simulation execution result, the cover point name 101 which is information in the cover group is included and displayed.

  In addition, as shown in FIG. Waveform information 100; The item table 110 can be displayed on the same screen. B. The location where the cross coverage part of the item table 110 is buried can be confirmed on the waveform information 100.

  As shown in FIG. 1A, an existing signal name (clk, addr) and waveform information 100 of signal values are displayed. In this embodiment, a cover point name (address ADDR in the example of FIG. 1) 101 used in a cover group (cover group) and values (bins values) 102 that each cover point can take are further displayed. In addition, a value (illegal_bins value) 103 that each cover point cannot take is displayed.

  The value (illegal_bins value) 103 that each cover point cannot take is highlighted (highlighted) by changing the display color. Furthermore, the number of occurrences 104 of the value (illegal_bins value) that each cover point cannot take is displayed. This highlighting makes it possible to easily check the occurrence time of a value that cannot be taken by the cover point.

  In addition to the display of the waveform information 100 as shown in FIG. 1B (1), an item table 110 corresponding to the displayed waveform information 100 is displayed (cooperation between waveform and item table). The waveform information 100 displays the contents of FIG. 1A. The item table 110 displays the number of times the cross coverage part is filled. For example, in the item table 110 shown in FIG. 1B (2), the number of times the cross-coverage part is filled at all times T0 of the waveform in FIG. 1B (1) is displayed.

  In addition, the item table 110 shown in FIG. 1B (3) is a value when the predetermined (time) range T1 of FIG. 1B (1) is specified on the waveform information 100, and the value of the item table is changed by changing the time range. Changes from FIG. 1B (2).

(Functional configuration example of design verification support device)
FIG. 2 is a block diagram of a functional configuration example of the design verification support apparatus according to the embodiment. The design verification support apparatus 200 includes a cover group information acquisition unit 201, cover group information (storage unit) 202, display operation input unit 203, display operation input information (storage unit) 204, cover group information control unit 205, ,including.

  The design verification support apparatus 200 according to the embodiment displays not only the waveform information 100 of the logic simulation result but also the coverage displayed by the existing coverage analysis tool and the waveform information displayed by the waveform viewer. In addition, it has a function of displaying the coverage and the waveform information in cooperation with each other.

  Components other than the cover group information control unit 205, which are a cover group information acquisition unit 201, a cover group information (storage unit) 202, a display operation input unit 203, and a display operation input information (storage unit) 204, are existing logic simulators. This corresponds to the function provided by.

  In the embodiment, a cover group information control unit 205 is further provided. The cover group information control unit 205 includes a cover group waveform information generation unit 211, a cover group waveform information (storage unit) 212, a cover group waveform display control unit 213, an item table information generation unit 214, and item table information (storage). Part) 215, item table display control part 216, and linkage information (storage part) 217. The waveform information 100 and the item table 110 shown in FIGS. 1A and 1B correspond to the display contents of the cover group waveform information 212 and the item table information 215.

  A source code 222 in a language such as SystemVerilog used for verification of the target LSI is input to the cover group information acquisition unit 201. The cover group information acquisition unit 201 acquires cover group information based on the source code 222 and stores the cover group information 202 in the storage unit.

  The cover group information control unit 205 generates cover group waveform information 212 and item table information 215 based on the waveform information 221 of the verification target circuit and the cover group information 202 stored in the storage unit. Then, the cover group information control unit 205 displays and outputs the cover group waveform information 212 (waveform information 100) and the item table information 215 (item table 110) in cooperation with each other. For example, the cover group waveform display control unit 213 and the item table display control unit 216 have both the waveform information 100 and the item table 110 on the same screen on the single display 232 (for example, arranged vertically as shown in FIG. 1B). The display signal to be displayed is output.

  The cover group waveform information generation unit 211 generates cover group waveform information 212 based on the waveform information 221 (the waveform information 100 described above) and the cover group information 202 stored in the storage unit, and the cover group waveform information is stored in the storage unit. Information 212 is stored.

  The item table information generation unit 214 generates an item table based on the waveform information 221 that is the execution result of the logic simulation and the cover group information stored in the storage unit 202, and stores the item table information 215 in the storage unit. . The item table information 215 includes the time of coverage acquisition timing in the cover group and the signal value at the coverage acquisition timing of the signal corresponding to each cover point. Then, a value (bins value) 102 that each cover point can take and a value (illegal_bins value) 103 that cannot be taken are generated.

  The cover group waveform display control unit 213 performs display control for displaying the cover group waveform information 212 stored in the storage unit as the waveform information 100 on the display 232 or the like. The item table display control unit 216 performs display control for displaying the item table information 215 stored in the storage unit on the display 232 or the like as the item table 110.

  Display operation input of the display operation unit 231 such as a keyboard and a mouse is input to the display operation input unit 203 and stored as display operation input information 204 in the storage unit as display operation input information for the design verification support apparatus 200. From the display operation unit 231, selection of a coverage item, designation of a cover group name to be displayed, designation of a period range (start time, end time, etc.), and the like are input.

  The cover group waveform display control unit 213 and the item table display control unit 216 follow the display operation input information indicated by the display operation input information 204 stored in the storage unit, and cover group waveform information 212 (waveform information 100) and items Display control for displaying and outputting the table information 215 (item table 110) is performed.

  In this display control, the cover group waveform display control unit 213 and the item table display control unit 216 store, in the storage unit, linkage information 217 that links display contents of the cover group waveform information 212 and the item table information 215. Then, the cover group waveform display control unit 213 and the item table display control unit 216 display the cover group waveform information 212 and the display contents of the item table information 215 (item table 110) on the same screen based on the cooperation information 217. Display them in cooperation with each other.

  In the configuration shown in FIG. 2, different information (cover group information 202 to linkage information 217) is stored in a plurality of storage units. However, a plurality of pieces of information are stored by dividing an area of one storage unit. It is good also as composition to do.

(Existing debug example)
A debugging example based on an existing logic simulation will be briefly described with reference to FIGS.

  FIG. 3 is a diagram illustrating a description example of a verification target. FIG. 3 shows an example of a source code 300 of an existing verification logic circuit description for RTL. Based on the addr and cmd described in the third and fourth lines, the waveforms of addr and cmd are displayed.

  FIG. 4 is a diagram illustrating a description example of a cover group. Here, the meaning of each term is described. “Coverage acquisition timing” is a timing at which coverage is acquired. In the example of FIG. 4, “@ (positioned clk)” on the seventh line corresponds to “coverage acquisition timing”. The “cover point name” is a name of one item representing a certain condition, operation, and state. In the example of FIG. 4, ADDR and CMD described before “: coverpoint” on the 8th and 15th lines correspond to the “cover point name”.

  The “bins value” is a value that each cover point can take. In the example of FIG. 4, the description between bins and = in the 9th to 11th lines and the 16th to 18th lines corresponds to the “bins value”. “Illegal_bins value” is a value that each cover point cannot take. In the example of FIG. 4, the description between illegal_bins and = in the 12th and 19th lines corresponds to the “illegal_bins value”.

  The “cross name” is a name of a cross coverage obtained by combining a plurality of cover points. In the example of FIG. 4, CRS_ADDR_CMD before “: cross” on the 23rd line corresponds to “cross name”. “Cross coverage” is coverage of a combination of values of a plurality of cover points.

As an example, coverage acquisition / debugging is performed according to the following procedure.
1. Identify verification items. This process is performed manually. For example, a) to c) are listed as verification items below.
a) The address (signal addr) has changed to all possible address values.
b) The command (signal cmd) has changed to all possible command values.
c) The command and address take all possible combinations.

2. Next, using the cover group description of SystemVerilog, the above 1. The verification items extracted in (1) are added to the logic circuit description to be verified as descriptions that can be input to the logic simulator. This process is performed by manual operation by hand or setting input using a spreadsheet application. Lines 7 to 26 in FIG. 4 are descriptions added.

3. Next, the description shown in FIG. 4 is input to the logic simulator, and a logic simulation is executed.
4). The simulation result is input to a coverage analysis tool to obtain coverage. The information obtained by the coverage analysis tool is only the number of times each bins value and illegal_bins value for the cover point name in the cover group description added in FIG. 4 is covered.

  FIG. 5 is a chart showing an example in which the result of the coverage analysis tool is reflected in the cross coverage table. From the result display of FIG. 5, when the combination (cross) value of the ADDR bins value and the CMD bins value is 1 or more, it can be determined that the combination (cross) has occurred. When the combination (cross) value of the ADDR bins value and the CMD bins value is 0, it can be determined that the combination (cross) has not occurred. However, in the existing technology, it is not known from FIG. 5 when the combination occurs (time). In addition, when the bins value includes a plurality of signal values (for example, addr1_5), it is not known which signal value (3'b001 to 3'b101) causes the combination (cross).

5. Thereafter, a waveform is displayed for debugging, and the generation time and signal value of the combination are confirmed. FIG. 6 is a diagram illustrating a waveform display example of the logic simulation result. The waveform viewer of the existing technology can display the signal name (CLK, addr, cmd) and its value (signal value).

  As described above, when the existing technology is used, the coverage is displayed by the coverage analysis tool and the waveform is simultaneously displayed by the waveform viewer. However, at present, debugging was performed by observing both the displayed coverage and waveform, and it took time and effort to debug.

  The covered verification items are debugged manually. The confirmation process will be briefly described. First, the cover point name and bins value of the covered verification item are extracted from the result of the coverage analysis tool (process 1). Thereafter, a signal name corresponding to the cover point name is acquired from the logic circuit description (processing 2). Next, the waveform viewer displays the waveform corresponding to the signal name (processing 3). In the case of cross coverage, processing 1 and the following are performed for all cover points (processing 4).

  Next, a signal value corresponding to the bins value is acquired from the logic circuit description (process 5). Next, a part where the signal values match is searched on the waveform viewer, and it is confirmed whether it is as intended (process 6). In the case of cross coverage, a part where all signal values match is searched to check whether it is as intended (process 7). If the confirmation is not completed, the process 2 and subsequent steps are executed again, and if the confirmation is completed, the process 8 is performed.

  In process 8, it is confirmed whether or not all the verification items have been confirmed (process 8). If all the verification items have not been confirmed, the process 1 and the subsequent steps are executed again. If all the verification items have been confirmed, the above confirmation process is terminated.

In such an existing technology, it took time to debug for the following reasons.
Cause 1: The waveform viewer cannot display the cover point name / bins (illegal_bins) name. The waveform is displayed with the signal name and its signal value, and the coverage is displayed with the cover point name / bins name.
Cause 2: It is not possible to easily find where the cross coverage is buried on the waveform.

In addition, it took time to find cross coverage in the following cases.
When there are many cover points that make up the cross coverage.
When there are many kinds of values (bins) that each cover point can take (for example, addr0 to addr7 in FIG. 5).
When one bins value of the cover point is composed of a plurality of signal values (for example, 3′b001 to 3′b101 of addr1_5 in FIG. 5).

  As described above, the existing technology cannot display the coverage (cover point name, possible value bins value of each cover point and impossible value illegal_bins value) on the waveform viewer. Also, the time when the cross coverage is filled cannot be easily found on the waveform. In general, coverage is information focusing on the presence / absence (including the number of times) of an event indicating whether or not the event has occurred.

(A. Processing contents for displaying both information in the cover group and waveform information)
The design verification support apparatus 200 according to the embodiment includes: In order to display the information in the cover group on the same time axis as the waveform information of the existing logic simulation result, the presence / absence of the event (including the number of times) and the time are managed.

  Specifically, first, change information (time and signal value) is extracted for each cover point name based on the waveform data, and a “signal value” is a value (bins value) 102 that each cover point can take, and Waveform data replaced with a value (illegal_bins value) 103 that each cover point cannot take is generated.

  Next, based on the waveform data generated above, the number of occurrences of a value (illegal_bins value) 103 that each cover point cannot take is counted, and the result (counter value) is a value (illegal_bins) that each cover point cannot take. Value) In association with the unique name for each 103, the above 1. It is added to the waveform data generated in.

  As a result, as shown in FIG. 1A, the information 101, 102, and 103 in the cover group can be displayed on the same time axis as the existing waveform information 100.

  FIG. 7 is a diagram illustrating an example of cover group information. FIG. 7A shows an example of the source code 222 such as SystemVerilog. In FIG. 7A, the above-described coverage and cross coverage are described.

  FIG. 7B shows cover group information (syntax tree) stored in the storage unit of the cover group information 202 based on the source code 222 of FIG. For example, an example is shown in which the cover points are ADDR and CMD, the signal names and values (bins value and illegal_bins value) of these cover points, and the cross coverage is ADDR and CMD.

  Then, the cover group waveform information generation unit 211 performs the following processing A1. -A5. Are executed sequentially. First, A1. By the user operation, the cover point ADDR (cover_point_identifier) 701 shown in FIG. 7B is taken out as a waveform display target. A2. A signal name addr 702 corresponding to ADDR 701 is taken out.

  8A and 8B are diagrams for explaining generation of cover group waveform information. The description of the upper end portion of FIG. 8B is connected to the description of the lower end portion of FIG. The cover group waveform information generation unit 211 generates cover group waveform information 212 based on the waveform information 221 and the cover group information 202.

  As shown in FIGS. 8A and 8B, the waveform information 221 includes a time when the signal changes (change time), a signal name, and a value after the change (signal value). Then, the cover group waveform information generation unit 211 next performs A3. From the waveform information 221, the signal name of the waveform information 221 and the signal change information of addr (change time and signal value) are extracted, and the extracted cover group waveform information 212a is generated.

  Next, the cover group waveform information generation unit 211 performs A4. The signal value of the extracted cover group waveform information 212a is replaced with bins_identifier / or illegal_bins_identifier to generate the replaced cover group waveform information 212b. For example, the signal value 3'b000 at the change time 100 is replaced with bins_identifier addr0 corresponding to FIG. Also, the signal value 3'b111 at the change time 800 is replaced with illegal_bins_identifier addr7.

  Next, A5. Of the replaced cover group waveform information 212b, the cover group waveform information 212c is generated using only the time when the possible value bins_identifier / or the impossible value illegal_bins_identifier changes. For example, information of change times 300 to 600 in which bins_identifier is not changed in the replaced cover group waveform information 212b is deleted. The generated cover group waveform information 212c is stored in the cover group waveform information (storage unit) 212 together with the cover point name (ADDR).

  The cover group waveform information 212 generated in this way includes the presence / absence (change) of the event and the change time. By using the cover group waveform information 212, the number of data necessary for display can be reduced, the processing efficiency can be improved, and the display processing of the cover point (address ADDR) 101 can be easily performed.

  Thereafter, the cover group waveform display control unit 213 performs A6. The cover group waveform information 212 is displayed together with the waveform information 100. At this time, the cover group waveform display control unit 213, as shown in FIG. 1A, covers a cover point name (address ADDR) 101 used in the cover group (cover group) and values (bins values) 102 that each cover point can take. Is displayed. In addition, illegal_bins (addr7) is highlighted to make it easy to visually recognize the value (illegal_bins value) 103 that the cover point cannot take.

  Further, the cover group waveform information generation unit 211 performs A7. Of the extracted waveform information 202a, a counter signal is created for each _bins_identifier of illegal_bins. Then, the cover group waveform information generation unit 211 displays the number of occurrences 104 of the value (illegal_bins value) that each cover point cannot take on the same screen as the waveform display. As a result, it becomes easier to find the time of the value (illegal_bins value) 103 that the cover point cannot take, and debugging can be performed efficiently.

  FIG. 9 is a flowchart illustrating an example of a confirmation process for a covered verification item. A. Performed by the design verification support apparatus 200 described above. An example of the debugging process performed manually based on the information in the cover group and the display of the waveform information is shown.

  First, A. mentioned above. From the result of displaying the information in the cover group and the waveform information on the same time axis, the cover point name and bins value of the covered verification item are extracted (step S901). Next, the waveform (value is a bins value) for the cover point name is displayed on the waveform viewer of the design verification support apparatus 200 (step S902). Next, a part where the bins values match on the waveform viewer is searched (step S903). This processing can use the function of the waveform viewer.

  Next, in the case of cross coverage, it is confirmed whether or not all cover points have been confirmed (step S904). If the confirmation of all cover points has not been completed (step S904: No), the process returns to step S902. If the confirmation of all cover points has been completed (step S904: Yes), the process proceeds to step S905. In step S905, if all the verification items have not been confirmed (step S905: No), the process returns to step S901, and if all the verification items have been confirmed (step S905: Yes), the above processing ends. To do.

(B. Contents of processing that can confirm on the waveform where the cross-coverage part is buried)
Next, cooperative display of waveforms and item tables performed by the design verification support apparatus 200 of this embodiment will be described. The processing contents of displaying the waveform information 100 shown in FIG. 1B and displaying the item table 110 corresponding to the waveform on the same screen (cooperation between the waveform and the item table) will be described.

  For the item table 110, the design verification support apparatus 200 displays the number of times that the cross coverage portion is filled in the waveform information 100. As described above, for example, when all the times T0 of the waveform information 100 in FIG. 1B (1) are designated, the number of times the cross coverage portion is filled is displayed as shown in FIG. 1B (2). Furthermore, when the predetermined range T1 is designated on the waveform in the selected state as shown in FIG. 1B (2), the value output to the item table 110 is FIG. 1B (3).

  FIG. 10 is a diagram for explaining generation of item table information. The item table information generation unit 214 generates item table information 215 based on the waveform information 221 and the cover group information 202. The waveform information 221 shown in FIG. 10 is the same as that in FIGS. 8A and 8B. As shown in FIG. 7, the cover group information 202 includes coverage acquisition timing and cover point information (cover point name, signal name, bins value and corresponding signal value, illegal_bins value and corresponding signal value).

The item table information generating unit 214 is configured to display the B.B. For linked display of waveforms and item tables, the following processing B1. -B2. Are executed sequentially.
B1. The signal name and the signal value for the cover point name at the coverage acquisition timing are extracted.
In this example, as the coverage acquisition timing, the signal name and the signal value for the cover point name when the clock is “possed” are extracted. However, if there is no signal change at the coverage acquisition timing, the signal value at the signal change time closest to the coverage acquisition timing is extracted.

  Specifically, coverage acquisition timing, cover point name, signal name, bins value and corresponding signal value, illegal_bins value and corresponding signal value) are extracted from the cover group information 202. A signal value corresponding to the signal name at the coverage acquisition timing is extracted from the waveform information 221 (extraction information 221a).

  For example, in FIG. 7, the coverage acquisition timing is 1′b1 (rise) of clk. Since the signal value of clk is 1'b1 (rising) at the change time 100, it is determined as the coverage acquisition timing, and the signal value of the signal corresponding to the cover point name is extracted.

  However, for a signal having no signal change at the same time as the coverage acquisition timing, the signal value at the change time immediately before the coverage acquisition timing is set as the signal value at the coverage acquisition timing. For example, in the extraction information 221a, the signal addr is changed at the coverage acquisition timing 200, but the signal cmd is not changed. Therefore, the signal value of the signal cmd is the signal value 2′b00 at the change time 100. Complement.

B2. Next, for the extracted information 221a, the item table information 215 is generated by replacing the signal name with the cover point name and the signal value with the bins value or the illegal_bins value.

  Thereby, the item table information generation unit 214 can manage the cover point state (ADDR, CMD) of the cross coverage as a pair for each coverage acquisition timing as the item table information 215. The item table information generation unit 214 stores the item table information 215 in the storage unit. The item table display control unit 216 reads the item table information 215 from the storage unit, and displays and outputs the item table 110 on the display 232 or the like.

  FIG. 11 is a chart showing the display state of the item table. Thereafter, the item table display control unit 216 sequentially searches (scans) the item table information 215, counts the points where the bins value of the cover point or the illegal_bins value crosses, and corresponds to the item table 110 shown in FIG. Count values are sequentially set in the square portion (cross information of verification items). The example of FIG. 11 shows a state in which a count value is set in the case of coverage acquisition time.

  Here, the relationship between the display items of the item table 110 and the cover group information 202 will be described. Display item names to be displayed on the vertical and horizontal axes of the item table 110 are displayed and set using existing technology. For example, ADDR is displayed and set based on cover_cross-list_of_coverpoints-ADDR of the cover group information 202 of the syntax tree shown in FIG. The CMD of the item table 110 is displayed and set based on cover_cross-list_of_coverpoints-CMD of the cover group information 202.

  Also, the ADDR addr0 of the item table 110 is set based on bins_or_empty-bin_identifier-addr0 of the cover group information 202. The value 3'b000 of ADDR addr0 in the item table 110 is set based on open_range_list-3'b000 corresponding to addr0.

  Also, UNKNOWN of CMD is displayed and set based on bin_identifier-UNKNOWN belonging to cover_point_identifier-CMD. The value 2'b11 of the CMD UNKNOWN is displayed and set based on the open_range_list-2'b11 corresponding to the UNKNOWN.

(Linkage between waveform information and item table)
12 and 13 are diagrams for explaining the cooperative display of the waveform information and the item table. The cooperative display of the waveform information 100 (cover group waveform information 212) and the item table 110 (item table information 215) will be described.

  First, the cooperative display of the coverage state according to the section will be described with reference to FIG. FIG. 12 (1) is item table information 215, and FIG. 12 (2) is an item table 110 corresponding to all times T0 (see FIG. 1B). FIG. 12 (3) is an item table 110 corresponding to a predetermined (time) range T1 (see FIG. 1B).

  By operating the display operation unit 231 and inputting the start time and end time of an arbitrary period to be confirmed as coverage, the coverage state corresponding to the input arbitrary period can be displayed as the item table 110. This arbitrary period is not a logic simulation execution period. When the period is different, the value of the square (cross information) in the item table 110 changes to a value corresponding to the period as shown in FIGS. 12 (2) and 12 (3).

  This cooperation display control is performed by the cover group waveform display control unit 213 and the item table display control unit 216 accessing the storage unit of the cooperation information 217. The linkage information 217 includes, for example, the coverage display target time (start time and end time) displayed as the item table 110, the cover point name, the time of coverage acquisition timing when the coverage is counted (marking instruction time), and the like.

  If there is a marking instruction time in the linkage information 217, the cover group waveform display control unit 213 starts and ends a marker of the start time and the end time (corresponding to the instruction time on the waveform information 100 (the start time and end of T0 or T1 in FIG. 1B). (Time) is displayed in a line.

  Also, if the item table coverage display target time is set in the display operation input information 204, the cover group waveform display control unit 213 sets the start time and end time of this item table coverage display target time in the linkage information 217. Save (corresponding to part period T1).

  If the start time and end time (corresponding to a partial period T1) of the item table coverage display target time are set in the linkage information 217, the item table display control unit 216 starts the start time of the item table coverage display target time. The coverage up to the end time is counted and displayed as the item table 110. On the other hand, if the start time and end time (corresponding to T1) of the item table coverage display target time are not set in the linkage information 217, the coverage of all times (corresponding to all times T0) is counted and displayed as the item table 110. To do.

  Next, the cooperative display of the cover group waveform display and the item table display will be described with reference to FIG. FIG. 13 (1) is item table information 215. FIG. 13B is an item table 110 displayed by the item table display control unit 216 based on the item table information 215. FIG. 13 (3) shows the waveform information 100 displayed by the cover group waveform display control unit 213 based on the cover group waveform information 212. FIG. 13 (2) and FIG. 13 (3) are states displayed on the same screen 232.

  In this state, when the user operates the display operation unit 231 to select a predetermined square (cross information of the covered verification item) 110a in the item table 110, the item table display control unit 216 sets the corresponding coverage acquisition timing. The item table information 215 is searched. In the example of FIG. 13 (2), the value of the square 110a is 2, indicating that there are two corresponding coverage acquisitions.

  The item table display control unit 216 stores the cover point name corresponding to the square selected by the user in the cooperation information 217 as the waveform display instruction cover point. Further, the coverage acquisition timing including the cover point name corresponding to the square selected by the user and the bins value or the illegal_bins value is extracted from the item table information 215 and stored in the linkage information 217 as the marking instruction time.

  In FIG. 13, the cover point names ADDR and CMD are stored in the cooperation information 217 as waveform display instruction cover points. Furthermore, the coverage acquisition timing (200 and 1000) when the bins value of the cover point name ADDR is addr1_5 and the bins value of the cover point name CMD is READ (215a and 215b) is extracted and linked as the marking instruction time Stored in information 217.

  The cover group waveform display control unit 213 searches the cover group waveform information 212 for a waveform display instruction cover point stored in the cooperation information 217, and displays the found cover point name, bins value, and illegal_bins value in a waveform. Further, the cover group waveform display control unit 213 displays a marker based on the marking instruction time stored in the cooperation information 217. In FIG. 13 (3), ta and tb are examples.

  Accordingly, when the time when the cross coverage is filled (occurred) on the item table 110 is selected, the time when the selected cross coverage is filled can be clearly indicated by displaying the marker on the waveform information 100.

  FIG. 14 is a flowchart illustrating an example of confirmation processing for a covered verification item. B. Performed by the design verification support apparatus 200 described above. An example of the debugging process which checks manually the state by which the location where the cross coverage part of the item table | surface 110 was buried was displayed on the waveform is shown.

  First, one of the covered verification items in the displayed coverage item table 110 is selected (step S1401). As a result, the design verification support apparatus 200 displays the cover group name of the cover point corresponding to the selected verification item and its bins value on the display 232. A marker is displayed at the displayed cover time.

  The user only has to confirm information (time etc.) of this marker part (step S1402). Thereafter, it is confirmed whether or not all the verification items have been confirmed. If not completed (step S1403: No), the process returns to step S1402, and if completed (step S1403: Yes), the confirmation process is terminated.

(Example of hardware configuration of design verification support device)
FIG. 15 is a block diagram of a hardware configuration example of the design verification support apparatus according to the embodiment. In FIG. 15, the design verification support apparatus 1500 includes a CPU (Central Processing Unit) 1501, a RAM (Random Access Memory) 1502, and an HDD (Hard Disk Drive) 1503. The design verification support apparatus 1500 includes a graphic processing apparatus 1504, an input interface 1505, and a communication interface 1506. Each unit 1501 to 1506 is connected by a bus 1507.

  Here, the CPU 1501 governs overall control of the design verification support apparatus 1500. The RAM 1502 is used as a work area for the CPU 1501. The HDD 1503 controls the reading / writing of data according to the control of the CPU 1501 and stores the data written by the control. Examples of the HDD 1503 include a magnetic disk and an optical disk.

  The communication interface 1506 is connected to a network NETWORK such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line 1508, and is connected to other devices via this network. A communication interface 1506 controls an internal interface with the network and controls data input / output from an external device. As the communication interface 1506, for example, a modem or a LAN adapter can be employed.

  The input interface 1505 is an interface that is connected to a keyboard, a mouse, a touch panel, and the like, and inputs various data by a user operation. The input interface 1505 can also capture images and moving images from the camera. The input interface 1505 can also capture audio from a microphone. The graphic processing device 1504 is an interface that outputs data in accordance with an instruction from the CPU 1501. The graphic processing device 1504 is connected to a display, for example, and outputs data to the display.

  Through the input interface 1505 or the communication interface 1506, the waveform information 221, the source code 222, and the display operation input information 204 for design verification support are input. Then, the CPU 1501 processes the input information to generate various types of information (cover group information 202, cover group waveform information 212, item table information 215, linkage information 217, etc.) and store them in the HDD 1503. Using the information stored in the HDD 1503, display data for displaying the waveform information 100 and the item table 110 in cooperation with each other is output to the graphic processing device 1504.

  The processing of the cover group information acquisition unit 201, the display operation input unit 203, and the cover group information control unit 205 is coded in a program stored in a storage device such as the RAM 1502 and the HDD 1503 that can be accessed by the CPU 1501 shown in FIG. Yes. Then, the CPU 1501 reads the program from the storage device and executes the process coded in the program. Accordingly, the processing of each functional unit illustrated in FIG. 2 is realized, and the processing result (for example, each information (cover group information 202 to cooperation information 217) illustrated in FIG. 2) is stored in a storage device such as the RAM 1502 or the HDD 1503. Is done.

(Example of processing performed by the cover group information control unit)
Hereinafter, processing examples of the functional units of the cover group waveform information generation unit 211, the item table information generation unit 214, the cover group waveform display control unit 213, and the item table display control unit 216 included in the cover group information control unit 205 described above will be described. To do.

  FIG. 16 is a flowchart showing the processing contents of cover group waveform information generation. A generation process of the cover group waveform information 212 performed by the cover group waveform information generation unit 211 will be described. First, if there is a cover point in the cover group information 202 that has not yet generated the cover group waveform information 212 (step S1601: Yes), the cover group waveform information generation unit 211 performs the processing from step S1602 onward. On the other hand, if all cover group waveform information has been created (step S1601: No), the process ends.

  In step S1602, the cover group waveform information generation unit 211 extracts from the cover group information 202 a signal name corresponding to one of the cover point names for which the cover group waveform information 212 has not yet been generated (step S1602).

  Next, the cover group waveform information generation unit 211 extracts change information (change time and changed signal value) of the extracted signal from the waveform information 221 (step S1603). Then, the extracted signal value is replaced with the corresponding bins value or illegal_bins value (step S1604).

  Next, the cover group waveform information generation unit 211 has information that the bins value and the illegal_bins value are not changed even when the change times are different (the change time and the bins value and the illegal_bins value after the change) with the larger change time. Is discarded (step S1605).

  Next, if there is an illegal_bins value for which counter signal information has not been generated yet (step S1606: Yes), the cover group waveform information generation unit 211 proceeds to step S1607, otherwise (step S1606: No), step S1601. Return to.

  In step S1607, a counter signal name is generated for one of the illegal_bins values for which counter signal information has not yet been generated, and the change information (change time and count value) is stored (step S1607). Return.

  FIG. 17 is a flowchart showing the processing contents of the cover group waveform display control. The contents of display control of the cover group waveform information 212 performed by the cover group waveform display control unit 213 will be described.

  First, the cover group waveform display control unit 213 determines whether there is a cover point instructed to display a waveform in the display operation input information 204 based on the operation of the display operation unit 231 or the linkage information 217 (step S1701). If there is no cover point instructed to display the waveform (step S1701: No), the process proceeds to step S1708. If there is a cover point for which waveform display is instructed (step S1701: Yes), a waveform display instruction cover point is searched from the cover group waveform information 212 (step S1702).

  Next, the cover group waveform display control unit 213 determines whether the waveform of the cover point found by the search has already been displayed (step S1703). If the waveform has been displayed (step S1703: YES), the process proceeds to step S1708. If the waveform is not displayed (step S1703: No), the cover group waveform display control unit 213 displays the waveform of the found cover point (step S1704).

  Next, the cover group waveform display control unit 213 determines whether the displayed cover point includes an illegal_bins value (step S1705). When the cover point does not include the illegal_bins value (step S1705: NO), the process proceeds to step S1708. When the cover point includes the illegal_bins value (step S1705: YES), the cover group waveform display control unit 213 highlights (highlights) the illegal_bins value on the waveform (step S1706).

  Next, the cover group waveform display control unit 213 displays a waveform of the counter signal corresponding to the highlighted illegal_bins value (step S1707).

  Next, the cover group waveform display control unit 213 determines whether there is a marking instruction time in the cooperation information 217 (step S1708). If there is no marking instruction time (step S1708: No), the process proceeds to step S1710. If there is a marking instruction time (step S1708: Yes), a marker is displayed on the waveform at the marking instruction time of the cooperation information 217 (step S1709).

  Next, the cover group waveform display control unit 213 determines whether there is an item table coverage display target time in the display operation input information 204 (step S1710). If there is no item table coverage display target time (step S1710: No), the process proceeds to step S1712. If the item table coverage display target time is present (step S1710: Yes), the cover group waveform display control unit 213 stores the item table coverage display target time (start time and end time) in the linkage information 217 (step S1711).

  Then, the cover group waveform display control unit 213 determines whether the waveform display is completed (step S1712). If not completed (step S1712: No), the process returns to step S1701, and if completed (step S1712: Yes), the above process ends.

  FIG. 18 is a flowchart showing the processing contents of item table information generation. A process for generating the item table information 215 performed by the item table information generation unit 214 will be described. First, the item table information generation unit 214 determines whether there is a cover group that has not yet generated the item table information 215 in the cover group information 202 (step S1801). If there is no cover group for which item table information 215 has not been generated (step S1801: No), the process ends.

  On the other hand, if there is a cover group for which item table information 215 has not been generated (step S1801: Yes), information corresponding to one cover group for which item table information 215 has not yet been generated is extracted from cover group information 202 (step S1801: Yes). S1802).

  Information extracted at this time is a coverage acquisition timing (coverage_event), a cover point name, a corresponding signal name, bins value, and illegal_bins value.

  Next, the item table information generation unit 214 extracts predetermined information from the waveform information 221 based on the extracted information, and stores it as item table information 215 (step S1803). Information extracted at this time is the time of coverage acquisition timing and the signal value at the coverage acquisition timing of the signal corresponding to each cover point. If the signal does not change at the time of coverage acquisition timing, the signal value at the change time immediately before is complemented.

  Next, the item table information generation unit 214 replaces the stored signal value with a bins value or an illegal_bins value (step S1804), and returns to step S1801.

  FIG. 19 is a flowchart showing the processing contents of the item table display control. The control contents of the item table cover group waveform display performed by the item table display control unit 216 will be described. First, the item table display control unit 216 determines whether there is a cover group instructed to display the item table in the display operation input information 204 (step S1901). If there is no cover group instructed to display the item table (step S1901: NO), the process proceeds to step S1908. If there is a cover group instructed to display the item table (step S1901: Yes), the item table display control unit 216 searches the item table information 215 for the cover group instructed to display (step S1902).

  Next, the item table display control unit 216 determines whether the found cover group is already displayed as the item table 110 (step S1903). If already displayed (step S1903: Yes), the process proceeds to step S1908. If not displayed (step S1903: No), the item table display control unit 216 displays the cover point name, bins value, and illegal_bins value of the found cover group in the item table 110 (step S1904).

  Next, the item table display control unit 216 determines whether there is an item table coverage display target time (start time and end time) in the cooperation information 217 (step S1905). If there is no item table coverage display target time (step S1905: No), the process proceeds to step S1907. If the item table coverage display target time is present (step S1905: Yes), the item table display control unit 216 counts the coverage within the item table coverage display target time from the item table information 215 and displays it in the item table 110 (step S1905). S1906), the process proceeds to step S1908. In step S1907, the coverage of all times is counted from the item table information 215, displayed on the item table 110 (step S1907), and the process proceeds to step S1908.

  In step S1908, the item table display control unit 216 determines whether there is a waveform display instruction for the specific coverage of the item table 110 being displayed in the display operation input information 204 (step S1908). If there is no waveform display instruction (step S1908: No), the process proceeds to step S1910. If there is a waveform display instruction (step S1908: Yes), the item table display control unit 216 stores predetermined information as linkage information 217 for the coverage instructed to display the waveform (step S1909).

  At this time, the information to be stored is the cover point name and the time of coverage acquisition timing (marking instruction time) counting the coverage.

  Thereafter, it is determined whether the display of the item table 110 has been completed (step S1910). If not completed (step S1910: No), the process returns to step S1901, and if completed (step S1910: Yes), The process ends.

  According to the embodiment described above, it is possible to display the cover point and the cover group waveform information including the values that the cover point can and cannot take together with the waveform information (signal waveform) of the existing simulation result. Debugging such as confirmation of time and signal values when verification items described in a cover group are covered, confirmation of conditions that cover verification items that should not be covered, etc. can be performed easily and efficiently. .

  The cover group waveform information can be easily generated by extracting from the input waveform information. At this time, the signal value of the signal is replaced with a value that each cover point can and cannot take, and only the time when the value that can be taken and the value that cannot be taken is changed to generate cover group waveform information. The number of necessary data can be reduced, the processing efficiency can be improved, and the cover point display processing can be easily performed.

  In addition, the number of occurrences of values that cover points cannot take is counted and displayed as the name of values that cover points cannot take, making it easy to understand the occurrences and occurrences of values that cover points cannot take. . In addition, it becomes possible to easily check the generation time of a value that cannot be covered by the highlighting.

  Further, by displaying and outputting the cover group waveform information and the verification item table, it becomes possible to efficiently perform debugging work using the cover group waveform information and the verification item table. Then, by changing the count value of the verification item table corresponding to the time range specified on the screen displaying the cover group waveform information, the display content of the cover group waveform information and the display content of the verification item table can be linked. Can be debugged efficiently.

  Also, the verification item table makes it easy to change the cross-coverage cover points at each coverage acquisition timing by replacing the signal name and signal value of the coverage acquisition timing with the values that each cover point can and cannot take based on the waveform information. It becomes possible to manage. Further, when the signal value does not change at the time of coverage acquisition timing at the time of replacement, it can be complemented using the signal value at the immediately previous change time.

  In addition, by selecting a crosspoint on the displayed verification item table, the corresponding time can be displayed as a marker on the waveform information, and the time of the crosspoint on the waveform information can be easily confirmed by operation on the verification item table. It becomes like this.

  Therefore, based on the acquired coverage, debugging such as confirmation of the time and signal value when the verification item described in the cover group is covered, confirmation of the condition that covered the verification item that should not be covered, etc. is easy. Will be able to do. At this time, since the cover group waveform information and the verification item table can be displayed on the same screen, the debugging work using the existing coverage analysis tool and waveform viewer can be eliminated, and the screen checking work at the time of debugging can be done easily. It is possible to improve verification efficiency and verification quality.

  In the above embodiment, the example in which the waveform information 100 and the item table 110 are displayed on the same screen of the single display 232 has been described. Not limited to this, the waveform information 100 and the item table 110 are linked to each other. Therefore, the waveform information 100 and the item table 110 may be displayed on different screens of the single display 232. Further, the waveform information 100 and the item table 110 can be displayed in cooperation with each other on the screens of different displays 232.

  The design verification support method described in the present embodiment can be realized by executing a waveform data conversion program prepared in advance on a computer such as a personal computer or a workstation. The waveform data conversion program is recorded on a computer-readable recording medium such as a magnetic disk, an optical disk, or a USB (Universal Serial Bus) flash memory, and is executed by being read from the recording medium by the computer. Further, the waveform data conversion program may be distributed via a network such as the Internet.

  The following additional notes are disclosed with respect to the embodiment described above.

(Supplementary Note 1) Display device for displaying waveform information of logic simulation result of logic circuit description to which description for coverage extraction indicating presence / absence of predetermined event occurrence in verification target circuit is added, signal name and signal value of the waveform information Displayed on the
A cover point indicating the presence / absence of a predetermined event in the target circuit, a value that the cover point can take and a value that cannot be taken are extracted from the waveform information, and a time, the cover point, the value that can be taken, and a value that cannot be taken An information control unit for displaying the cover group waveform information generated by linking to the display device on the same time axis as the waveform information,
A design verification support apparatus characterized by comprising:

(Appendix 2) The information control unit
Based on the waveform information, extracting a signal name corresponding to each cover point name of the cover point, a changed signal value and a change time of the signal corresponding to the signal name, and generating the cover group waveform information The design verification support apparatus according to Supplementary Note 1, which is a feature.

(Supplementary Note 3) The information control unit
For each cover point name of the waveform information, the signal value and the change time at which the signal has changed are extracted, and the signal value of the signal is replaced with the possible value and the impossible value of each cover point. Produces
3. The design verification support apparatus according to appendix 2, wherein the cover group waveform information is generated leaving only the time when the possible value and the impossible value of the replaced waveform information are changed.

(Supplementary Note 4) The information control unit
The number of occurrences of the value that cannot be taken by the cover point is counted, and the counter value is associated with a unique name for each value that cannot be taken by each cover point and added to the replaced waveform information. 3. The design verification support apparatus according to 3.

(Supplementary Note 5) The information control unit
The design verification support apparatus according to any one of appendices 1 to 4, wherein a value that cannot be taken by the cover point is highlighted on the display apparatus.

(Appendix 6) The information control unit
The cover table waveform information and item table information in which a cross point count value of a verification item table in which a plurality of the cover points indicating the verification items of the target circuit are combined are displayed on the display device. The design verification support apparatus according to any one of appendices 1 to 5, characterized in that:

(Appendix 7) The information control unit
7. The design verification support apparatus according to appendix 6, wherein the count value of the verification item table is changed corresponding to a time range specified on the display apparatus that displays the cover group waveform information.

(Appendix 8) The information control unit
When creating the verification item table, based on the waveform information, extract the signal name and signal value when the clock rises,
Extracting the time of coverage acquisition timing from the waveform information and the signal value at the coverage acquisition timing of the signal corresponding to each cover point,
The design verification support apparatus according to appendix 6 or 7, wherein the item table information is generated by replacing the signal value with the possible value and the impossible value of each cover point.

(Supplementary note 9) The information control unit
9. The design verification support apparatus according to appendix 8, wherein when the signal does not change at the time of the coverage acquisition timing at the time of replacement, the signal is complemented by using the signal value at the immediately previous change time.

(Supplementary Note 10) The information control unit
When an arbitrary cross point on the verification item table displayed on the display device is selected, a time at which the corresponding coverage is filled is searched from the item table information, and the corresponding time is displayed on the waveform information on the display device. The design verification support apparatus according to appendix 8 or 9, wherein a marker is displayed on the display.

(Supplementary Note 11) The information control unit
The information at the time of data change for one of the cover group waveform information or the other item table information to be displayed and output on the display device is held as linkage information, referring to the linkage information at the time of data change of either one of the information, The design verification support apparatus according to any one of appendices 6 to 10, wherein the design verification support apparatus is used for changing data of the other information.

(Supplementary Note 12) The information control unit
The design verification support apparatus according to any one of appendices 6 to 11, wherein a display signal for displaying the cover group waveform information and the verification item table on the same screen of the display apparatus is output.

(Supplementary note 13)
Processing for displaying on the display device the waveform information of the logic simulation result of the logic circuit description to which a description for coverage extraction indicating whether or not a predetermined event has occurred in the verification target circuit is added, and the signal name and signal value of the waveform information When,
A cover point indicating the presence / absence of a predetermined event in the target circuit, a value that the cover point can take and a value that cannot be taken are extracted from the waveform information, and a time, the cover point, the value that can be taken, and a value that cannot be taken Processing to display the cover group waveform information generated by linking to the display device on the same time axis as the waveform information;
A design verification support method characterized by executing

(Supplementary note 14) Item table information in which the cover group waveform information is associated with count values of cross points of a verification item table in which a plurality of the cover points indicating verification items of the target circuit are combined with each other. Processing to display and output to
The design verification support method according to supplementary note 13, further comprising:

(Supplementary Note 15) Display device for displaying waveform information of logic simulation result of logic circuit description to which description for coverage extraction indicating presence / absence of predetermined event occurrence in verification target circuit is added, signal name and signal value of the waveform information Displayed on the
A cover point indicating the presence / absence of a predetermined event in the target circuit, a value that the cover point can take and a value that cannot be taken are extracted from the waveform information, and a time, the cover point, the value that can be taken, and a value that cannot be taken And display the cover group waveform information generated by linking to the display device on the same time axis as the waveform information,
A design verification support program characterized by causing a computer to execute processing.

(Supplementary Note 16) Item table information in which the cover group waveform information is associated with count values of cross points of a verification item table in which a plurality of the cover points indicating the verification items of the target circuit are combined with each other. Processing to display and output to
The design verification support program according to appendix 15, wherein the program is executed by a computer.

100, 221 Waveform information 110 Item table 200, 1500 Design verification support device 201 Cover group information acquisition unit 202 Cover group information 203 Display operation input unit 204 Display operation input information 205 Cover group information control unit 211 Cover group waveform information generation unit 212 Cover Group waveform information 213 Cover group waveform display control unit 214 Item table information generation unit 215 Item table information 216 Item table display control unit 217 Cooperation information 222 Source code 231 Display operation unit 232 Display (display device)
1501 CPU
1502 RAM
1503 HDD
1504 Graphic processing device 1505 Input interface 1506 Communication interface 1507 Bus 1508 Communication line

Claims (13)

Display on the display device the waveform information of the logic simulation result of the logic circuit description to which the description for coverage extraction indicating the presence or absence of the predetermined event occurrence of the verification target circuit is added, the signal name and the signal value of the waveform information,
A cover point indicating the presence / absence of a predetermined event in the target circuit, a value that the cover point can take and a value that cannot be taken are extracted from the waveform information, and a time, the cover point, the value that can be taken, and a value that cannot be taken An information control unit for displaying the cover group waveform information generated by linking to the display device on the same time axis as the waveform information,
A design verification support apparatus characterized by comprising: The information control unit
Based on the waveform information, extracting a signal name corresponding to each cover point name of the cover point, a changed signal value and a change time of the signal corresponding to the signal name, and generating the cover group waveform information The design verification support apparatus according to claim 1, wherein The information control unit
For each cover point name of the waveform information, the signal value and the change time at which the signal has changed are extracted, and the signal value of the signal is replaced with the possible value and the impossible value of each cover point. Produces
3. The design verification support apparatus according to claim 2, wherein the cover group waveform information is generated by leaving only the time when the possible value and the impossible value of the replaced waveform information are changed. . The information control unit
The number of occurrences of a value that cannot be taken by the cover point is counted, and a counter value is associated with a unique name for each value that cannot be taken by each cover point and added to the replaced waveform information. Item 4. The design verification support apparatus according to Item 3. The information control unit
The design verification support apparatus according to claim 1, wherein a value that cannot be taken by the cover point is highlighted on the display device. The information control unit
The cover table waveform information and item table information in which a cross point count value of a verification item table in which a plurality of the cover points indicating the verification items of the target circuit are combined are displayed on the display device. The design verification support apparatus according to any one of claims 1 to 5, wherein The information control unit
The design verification support apparatus according to claim 6, wherein the count value of the verification item table is changed in correspondence with a time range designated on the display device displaying the cover group waveform information. The information control unit
When creating the verification item table, based on the waveform information, extract the signal name and signal value when the clock rises,
Extracting the time of coverage acquisition timing from the waveform information and the signal value at the coverage acquisition timing of the signal corresponding to each cover point,
8. The design verification support apparatus according to claim 6, wherein the item table information is generated by replacing the signal value with the possible value and the impossible value of each cover point. The information control unit
9. The design verification support apparatus according to claim 8, wherein when the signal does not change at the time of the coverage acquisition timing at the time of the replacement, the design verification support apparatus is complemented by using a signal value at the immediately previous change time. The information control unit
When an arbitrary cross point on the verification item table displayed on the display device is selected, a time at which the corresponding coverage is filled is searched from the item table information, and the corresponding time is displayed on the waveform information on the display device. 10. The design verification support apparatus according to claim 8, wherein a marker is displayed on the display. The information control unit
The information at the time of data change for one of the cover group waveform information or the other item table information to be displayed and output on the display device is held as linkage information, referring to the linkage information at the time of data change of either one of the information, The design verification support apparatus according to claim 6, wherein the design verification support apparatus is used to change data of the other information. Computer
Processing for displaying on the display device the waveform information of the logic simulation result of the logic circuit description to which a description for coverage extraction indicating whether or not a predetermined event has occurred in the verification target circuit is added, and the signal name and signal value of the waveform information When,
A cover point indicating the presence / absence of a predetermined event in the target circuit, a value that the cover point can take and a value that cannot be taken are extracted from the waveform information, and a time, the cover point, the value that can be taken, and a value that cannot be taken Processing to display the cover group waveform information generated by linking to the display device on the same time axis as the waveform information;
A design verification support method characterized by executing The cover table waveform information and item table information in which a cross point count value of a verification item table in which a plurality of the cover points indicating the verification items of the target circuit are combined are displayed on the display device. processing,
The design verification support method according to claim 12, further comprising:

Images